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@@ -1327,32 +1327,39 @@ QDF_STATUS ol_download_firmware(struct ol_context *ol_ctx)
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(uint8_t *) &address, 4, ol_ctx);
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}
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- if (ini_cfg->enable_uart_print) {
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- switch (target_version) {
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- case AR6004_VERSION_REV1_3:
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- param = 11;
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- break;
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- case AR6320_REV1_VERSION:
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- case AR6320_REV2_VERSION:
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- case AR6320_REV3_VERSION:
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- case AR6320_REV3_2_VERSION:
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- case QCA9379_REV1_VERSION:
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- case AR6320_REV4_VERSION:
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- case AR6320_DEV_VERSION:
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- if (hif_get_bus_type(scn) == QDF_BUS_TYPE_SDIO)
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- param = 19;
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- else
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- param = 6;
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+ switch (target_version) {
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+ case AR6004_VERSION_REV1_3:
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+ param = 11;
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+ break;
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+ case AR6320_REV1_VERSION:
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+ case AR6320_REV2_VERSION:
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+ case AR6320_REV3_VERSION:
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+ case AR6320_REV3_2_VERSION:
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+ case QCA9377_REV1_1_VERSION:
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+ case QCA9379_REV1_VERSION:
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+ case AR6320_REV4_VERSION:
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+ case AR6320_DEV_VERSION:
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+ /*
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+ * In sdio interface chip, both sdio_data2 and uart_tx pin
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+ * will use GPIO6. It is set by fw rom code, which will cause
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+ * sdio CRC error when there is sdio transaction.
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+ * Override uart tx pin to avoid side effect to sdio pin.
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+ */
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+ if (hif_get_bus_type(scn) == QDF_BUS_TYPE_SDIO)
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+ param = 19;
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+ else
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+ param = 6;
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+ break;
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+ default:
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+ /* Configure GPIO AR9888 UART */
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+ param = 7;
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+ }
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- break;
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- default:
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- /* Configure GPIO AR9888 UART */
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- param = 7;
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- }
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+ bmi_write_memory(hif_hia_item_address(target_type,
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+ offsetof(struct host_interest_s, hi_dbg_uart_txpin)),
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+ (uint8_t *)¶m, 4, ol_ctx);
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- bmi_write_memory(hif_hia_item_address(target_type,
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- offsetof(struct host_interest_s, hi_dbg_uart_txpin)),
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- (uint8_t *)¶m, 4, ol_ctx);
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+ if (ini_cfg->enable_uart_print) {
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param = 1;
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bmi_write_memory(hif_hia_item_address(target_type,
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offsetof(struct host_interest_s, hi_serial_enable)),
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