qcacmn: Separate GetFrameControl API's for LI chipsets

For 802.11 Fragmented frames, currently there is a
generic GetFrameControl API from RX TLV for all Li
Chipsets. As the offset for frame control in RX TLV
is different for QCN9000 and QCA8074V2, reading the
frame control with generic API gives wrong frame
control value. The Offset is different as the size
of RX_MSDU_START struct is 8DWORDS in QCA8074v2 while
it is 9DWORDS in QCA9000. In the reo reinject path
the destination queue descriptor address read from ring
descriptor address is Invalid

Fix is Separating out the GetFrameControl API from
generic API to Chip specific API. Also fix the reading
of queue descriptor address.

CRs-Fixed: 3280809
change-Id: Ifc5eca31b9b7e70c84ca455d56a58c27601cd51d
This commit is contained in:
Kenvish Butani
2022-08-29 07:34:05 -07:00
committed by Madan Koyyalamudi
parent 1a5b0d838e
commit a16d867018
12 changed files with 133 additions and 21 deletions

View File

@@ -228,24 +228,6 @@ static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf)
return msdu_len;
}
/**
* hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field
*
* @nbuf: Network buffer
* Returns: rx more fragment bit
*
*/
static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t frame_ctrl = 0;
frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
return frame_ctrl;
}
/**
* hal_rx_get_proto_params_li() - Get l4 proto values from TLV
* @buf: rx tlv address
@@ -1204,8 +1186,6 @@ void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li;
hal_soc->ops->hal_rx_tlv_msdu_len_get =
hal_rx_msdu_start_msdu_len_get_li;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_frame_ctrl_field_li;
hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li;
hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li;

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@@ -2635,4 +2635,22 @@ hal_rx_fst_get_fse_size_li(void)
return 0;
}
#endif /* WLAN_SUPPORT_RX_FISA */
/**
* hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field
*
* @nbuf: Network buffer
* Returns: rx more fragment bit
*
*/
static uint16_t hal_rx_get_frame_ctrl_field_li(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t frame_ctrl = 0;
frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
return frame_ctrl;
}
#endif /* _HAL_LI_GENERIC_API_H_ */

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@@ -1345,6 +1345,8 @@ uint8_t hal_get_tlv_hdr_size_li(void)
uint64_t hal_rx_get_qdesc_addr_li(uint8_t *dst_ring_desc, uint8_t *buf)
{
return *(uint64_t *)dst_ring_desc +
uint8_t *dst_qdesc_addr = dst_ring_desc +
REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET;
return *(uint64_t *)dst_qdesc_addr;
}

View File

@@ -915,6 +915,24 @@ static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf)
return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
}
/**
* hal_rx_get_mpdu_frame_control_field_5018(): Function to
* retrieve frame control field
*
* @nbuf: Network buffer
* Returns: value of frame control field
*/
static uint16_t hal_rx_get_mpdu_frame_control_field_5018(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t frame_ctrl = 0;
frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
return frame_ctrl;
}
/*
* hal_rx_mpdu_get_addr1_5018(): API to check get address1 of the mpdu
*
@@ -1786,6 +1804,8 @@ static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_5018;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_mpdu_frame_control_field_5018;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018;

View File

@@ -1167,6 +1167,8 @@ static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6290;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_frame_ctrl_field_li;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290;

View File

@@ -1234,6 +1234,8 @@ static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6390;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6390;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_frame_ctrl_field_li;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6390;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6390;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6390;

View File

@@ -1853,6 +1853,8 @@ static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6490;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6490;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_frame_ctrl_field_li;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6490;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6490;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6490;

View File

@@ -1989,6 +1989,8 @@ static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6750;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6750;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_frame_ctrl_field_li;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6750;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6750;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6750;

View File

@@ -414,6 +414,25 @@ static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf)
return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
}
/**
* hal_rx_get_mpdu_frame_control_field_8074v1(): Function to
* retrieve frame control field
*
* @nbuf: Network buffer
* Returns: value of frame control field
*
*/
static uint16_t hal_rx_get_mpdu_frame_control_field_8074v1(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t frame_ctrl = 0;
frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
return frame_ctrl;
}
/*
* hal_rx_mpdu_get_addr1_8074v1(): API to check get address1 of the mpdu
*
@@ -1331,6 +1350,8 @@ static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_8074v1;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_mpdu_frame_control_field_8074v1;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1;

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@@ -400,6 +400,25 @@ static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf)
return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
}
/**
* hal_rx_get_mpdu_frame_control_field_8074v2(): Function to
* retrieve frame control field
*
* @nbuf: Network buffer
* Returns: value of frame control field
*
*/
static uint16_t hal_rx_get_mpdu_frame_control_field_8074v2(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t frame_ctrl = 0;
frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
return frame_ctrl;
}
/*
* hal_rx_mpdu_get_addr1_8074v2(): API to check get address1 of the mpdu
*
@@ -1328,6 +1347,8 @@ static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_8074v2;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_mpdu_frame_control_field_8074v2;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2;

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@@ -877,6 +877,25 @@ static uint8_t hal_rx_get_mpdu_frame_control_valid_6122(uint8_t *buf)
return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
}
/**
* hal_rx_get_mpdu_frame_control_field_6122(): Function to
* retrieve frame control field
*
* @nbuf: Network buffer
* Returns: value of frame control field
*
*/
static uint16_t hal_rx_get_mpdu_frame_control_field_6122(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t frame_ctrl = 0;
frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
return frame_ctrl;
}
/*
* hal_rx_mpdu_get_addr1_6122(): API to check get address1 of the mpdu
*
@@ -1837,6 +1856,8 @@ static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6122;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6122;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_mpdu_frame_control_field_6122;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6122;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6122;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6122;

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@@ -922,6 +922,25 @@ static uint8_t hal_rx_get_mpdu_frame_control_valid_9000(uint8_t *buf)
return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
}
/**
* hal_rx_get_mpdu_frame_control_field_9000(): Function
* to retrieve frame control field
*
* @nbuf: Network buffer
* Returns: value of frame control field
*
*/
static uint16_t hal_rx_get_mpdu_frame_control_field_9000(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
uint16_t frame_ctrl = 0;
frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
return frame_ctrl;
}
/*
* hal_rx_mpdu_get_addr1_9000(): API to check get address1 of the mpdu
*
@@ -1881,6 +1900,8 @@ static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_9000;
hal_soc->ops->hal_rx_get_frame_ctrl_field =
hal_rx_get_mpdu_frame_control_field_9000;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000;