Config: enable techpack display driver compilation for lahaina
This change enables display drivers code compilation for lahaina target and current location of header files is replacing the header files in usr/include/drm directory before installing display specific header files. This change ensures both the drm and msm_drv header files are exported to user mode clients. Change-Id: If6fc347598b902e670b7206dbcb82fe0740b3984 Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org> Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org> Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This commit is contained in:
Narendra Muppalla
573
include/uapi/display/drm/msm_drm_pp.h
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573
include/uapi/display/drm/msm_drm_pp.h
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@@ -0,0 +1,573 @@
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _MSM_DRM_PP_H_
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#define _MSM_DRM_PP_H_
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#include <linux/types.h>
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/**
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* struct drm_msm_pcc_coeff - PCC coefficient structure for each color
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* component.
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* @c: constant coefficient.
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* @r: red coefficient.
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* @g: green coefficient.
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* @b: blue coefficient.
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* @rg: red green coefficient.
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* @gb: green blue coefficient.
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* @rb: red blue coefficient.
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* @rgb: red blue green coefficient.
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*/
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struct drm_msm_pcc_coeff {
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__u32 c;
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__u32 r;
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__u32 g;
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__u32 b;
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__u32 rg;
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__u32 gb;
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__u32 rb;
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__u32 rgb;
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};
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/**
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* struct drm_msm_pcc - pcc feature structure
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* @flags: for customizing operations
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* @r: red coefficients.
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* @g: green coefficients.
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* @b: blue coefficients.
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* @r_rr: second order coefficients
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* @r_gg: second order coefficients
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* @r_bb: second order coefficients
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* @g_rr: second order coefficients
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* @g_gg: second order coefficients
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* @g_bb: second order coefficients
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* @b_rr: second order coefficients
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* @b_gg: second order coefficients
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* @b_bb: second order coefficients
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*/
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#define DRM_MSM_PCC3
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struct drm_msm_pcc {
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__u64 flags;
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struct drm_msm_pcc_coeff r;
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struct drm_msm_pcc_coeff g;
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struct drm_msm_pcc_coeff b;
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__u32 r_rr;
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__u32 r_gg;
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__u32 r_bb;
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__u32 g_rr;
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__u32 g_gg;
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__u32 g_bb;
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__u32 b_rr;
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__u32 b_gg;
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__u32 b_bb;
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};
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/* struct drm_msm_pa_vlut - picture adjustment vLUT structure
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* flags: for customizing vlut operation
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* val: vLUT values
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*/
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#define PA_VLUT_SIZE 256
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struct drm_msm_pa_vlut {
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__u64 flags;
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__u32 val[PA_VLUT_SIZE];
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};
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#define PA_HSIC_HUE_ENABLE (1 << 0)
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#define PA_HSIC_SAT_ENABLE (1 << 1)
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#define PA_HSIC_VAL_ENABLE (1 << 2)
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#define PA_HSIC_CONT_ENABLE (1 << 3)
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/**
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* struct drm_msm_pa_hsic - pa hsic feature structure
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* @flags: flags for the feature customization, values can be:
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* - PA_HSIC_HUE_ENABLE: Enable hue adjustment
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* - PA_HSIC_SAT_ENABLE: Enable saturation adjustment
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* - PA_HSIC_VAL_ENABLE: Enable value adjustment
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* - PA_HSIC_CONT_ENABLE: Enable contrast adjustment
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*
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* @hue: hue setting
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* @saturation: saturation setting
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* @value: value setting
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* @contrast: contrast setting
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*/
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#define DRM_MSM_PA_HSIC
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struct drm_msm_pa_hsic {
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__u64 flags;
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__u32 hue;
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__u32 saturation;
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__u32 value;
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__u32 contrast;
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};
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#define MEMCOL_PROT_HUE (1 << 0)
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#define MEMCOL_PROT_SAT (1 << 1)
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#define MEMCOL_PROT_VAL (1 << 2)
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#define MEMCOL_PROT_CONT (1 << 3)
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#define MEMCOL_PROT_SIXZONE (1 << 4)
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#define MEMCOL_PROT_BLEND (1 << 5)
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/* struct drm_msm_memcol - Memory color feature structure.
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* Skin, sky, foliage features are supported.
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* @prot_flags: Bit mask for enabling protection feature.
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* @color_adjust_p0: Adjustment curve.
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* @color_adjust_p1: Adjustment curve.
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* @color_adjust_p2: Adjustment curve.
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* @blend_gain: Blend gain weightage from othe PA features.
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* @sat_hold: Saturation hold value.
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* @val_hold: Value hold info.
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* @hue_region: Hue qualifier.
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* @sat_region: Saturation qualifier.
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* @val_region: Value qualifier.
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*/
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#define DRM_MSM_MEMCOL
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struct drm_msm_memcol {
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__u64 prot_flags;
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__u32 color_adjust_p0;
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__u32 color_adjust_p1;
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__u32 color_adjust_p2;
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__u32 blend_gain;
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__u32 sat_hold;
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__u32 val_hold;
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__u32 hue_region;
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__u32 sat_region;
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__u32 val_region;
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};
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#define DRM_MSM_SIXZONE
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#define SIXZONE_LUT_SIZE 384
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#define SIXZONE_HUE_ENABLE (1 << 0)
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#define SIXZONE_SAT_ENABLE (1 << 1)
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#define SIXZONE_VAL_ENABLE (1 << 2)
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/* struct drm_msm_sixzone_curve - Sixzone HSV adjustment curve structure.
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* @p0: Hue adjustment.
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* @p1: Saturation/Value adjustment.
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*/
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struct drm_msm_sixzone_curve {
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__u32 p1;
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__u32 p0;
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};
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/* struct drm_msm_sixzone - Sixzone feature structure.
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* @flags: for feature customization, values can be:
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* - SIXZONE_HUE_ENABLE: Enable hue adjustment
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* - SIXZONE_SAT_ENABLE: Enable saturation adjustment
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* - SIXZONE_VAL_ENABLE: Enable value adjustment
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* @threshold: threshold qualifier.
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* @adjust_p0: Adjustment curve.
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* @adjust_p1: Adjustment curve.
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* @sat_hold: Saturation hold info.
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* @val_hold: Value hold info.
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* @curve: HSV adjustment curve lut.
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*/
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struct drm_msm_sixzone {
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__u64 flags;
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__u32 threshold;
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__u32 adjust_p0;
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__u32 adjust_p1;
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__u32 sat_hold;
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__u32 val_hold;
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struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE];
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};
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#define GAMUT_3D_MODE_17 1
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#define GAMUT_3D_MODE_5 2
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#define GAMUT_3D_MODE_13 3
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#define GAMUT_3D_MODE17_TBL_SZ 1229
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#define GAMUT_3D_MODE5_TBL_SZ 32
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#define GAMUT_3D_MODE13_TBL_SZ 550
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#define GAMUT_3D_SCALE_OFF_SZ 16
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#define GAMUT_3D_SCALEB_OFF_SZ 12
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#define GAMUT_3D_TBL_NUM 4
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#define GAMUT_3D_SCALE_OFF_TBL_NUM 3
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#define GAMUT_3D_MAP_EN (1 << 0)
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/**
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* struct drm_msm_3d_col - 3d gamut color component structure
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* @c0: Holds c0 value
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* @c2_c1: Holds c2/c1 values
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*/
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struct drm_msm_3d_col {
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__u32 c2_c1;
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__u32 c0;
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};
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/**
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* struct drm_msm_3d_gamut - 3d gamut feature structure
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* @flags: flags for the feature values are:
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* 0 - no map
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* GAMUT_3D_MAP_EN - enable map
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* @mode: lut mode can take following values:
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* - GAMUT_3D_MODE_17
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* - GAMUT_3D_MODE_5
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* - GAMUT_3D_MODE_13
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* @scale_off: Scale offset table
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* @col: Color component tables
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*/
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struct drm_msm_3d_gamut {
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__u64 flags;
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__u32 mode;
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__u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];
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struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ];
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};
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#define PGC_TBL_LEN 512
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#define PGC_8B_ROUND (1 << 0)
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/**
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* struct drm_msm_pgc_lut - pgc lut feature structure
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* @flags: flags for the featue values can be:
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* - PGC_8B_ROUND
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* @c0: color0 component lut
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* @c1: color1 component lut
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* @c2: color2 component lut
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*/
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struct drm_msm_pgc_lut {
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__u64 flags;
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__u32 c0[PGC_TBL_LEN];
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__u32 c1[PGC_TBL_LEN];
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__u32 c2[PGC_TBL_LEN];
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};
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#define IGC_TBL_LEN 256
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#define IGC_DITHER_ENABLE (1 << 0)
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/**
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* struct drm_msm_igc_lut - igc lut feature structure
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* @flags: flags for the feature customization, values can be:
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* - IGC_DITHER_ENABLE: Enable dither functionality
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* @c0: color0 component lut
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* @c1: color1 component lut
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* @c2: color2 component lut
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* @strength: dither strength, considered valid when IGC_DITHER_ENABLE
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* is set in flags. Strength value based on source bit width.
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* @c0_last: color0 lut_last component
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* @c1_last: color1 lut_last component
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* @c2_last: color2 lut_last component
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*/
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struct drm_msm_igc_lut {
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__u64 flags;
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__u32 c0[IGC_TBL_LEN];
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__u32 c1[IGC_TBL_LEN];
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__u32 c2[IGC_TBL_LEN];
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__u32 strength;
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__u32 c0_last;
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__u32 c1_last;
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__u32 c2_last;
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};
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#define LAST_LUT 2
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#define HIST_V_SIZE 256
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/**
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* struct drm_msm_hist - histogram feature structure
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* @flags: for customizing operations
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* @data: histogram data
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*/
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struct drm_msm_hist {
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__u64 flags;
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__u32 data[HIST_V_SIZE];
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};
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#define AD4_LUT_GRP0_SIZE 33
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#define AD4_LUT_GRP1_SIZE 32
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/*
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* struct drm_msm_ad4_init - ad4 init structure set by user-space client.
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* Init param values can change based on tuning
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* hence it is passed by user-space clients.
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*/
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struct drm_msm_ad4_init {
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__u32 init_param_001[AD4_LUT_GRP0_SIZE];
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__u32 init_param_002[AD4_LUT_GRP0_SIZE];
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__u32 init_param_003[AD4_LUT_GRP0_SIZE];
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__u32 init_param_004[AD4_LUT_GRP0_SIZE];
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__u32 init_param_005[AD4_LUT_GRP1_SIZE];
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__u32 init_param_006[AD4_LUT_GRP1_SIZE];
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__u32 init_param_007[AD4_LUT_GRP0_SIZE];
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__u32 init_param_008[AD4_LUT_GRP0_SIZE];
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__u32 init_param_009;
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__u32 init_param_010;
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__u32 init_param_011;
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__u32 init_param_012;
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__u32 init_param_013;
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__u32 init_param_014;
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__u32 init_param_015;
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__u32 init_param_016;
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__u32 init_param_017;
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__u32 init_param_018;
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__u32 init_param_019;
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__u32 init_param_020;
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__u32 init_param_021;
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__u32 init_param_022;
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__u32 init_param_023;
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__u32 init_param_024;
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__u32 init_param_025;
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__u32 init_param_026;
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__u32 init_param_027;
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__u32 init_param_028;
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__u32 init_param_029;
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__u32 init_param_030;
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__u32 init_param_031;
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__u32 init_param_032;
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__u32 init_param_033;
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__u32 init_param_034;
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__u32 init_param_035;
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__u32 init_param_036;
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__u32 init_param_037;
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__u32 init_param_038;
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__u32 init_param_039;
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__u32 init_param_040;
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__u32 init_param_041;
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__u32 init_param_042;
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__u32 init_param_043;
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__u32 init_param_044;
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__u32 init_param_045;
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__u32 init_param_046;
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__u32 init_param_047;
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__u32 init_param_048;
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__u32 init_param_049;
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__u32 init_param_050;
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__u32 init_param_051;
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__u32 init_param_052;
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__u32 init_param_053;
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__u32 init_param_054;
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__u32 init_param_055;
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__u32 init_param_056;
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__u32 init_param_057;
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__u32 init_param_058;
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__u32 init_param_059;
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__u32 init_param_060;
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__u32 init_param_061;
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__u32 init_param_062;
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__u32 init_param_063;
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__u32 init_param_064;
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__u32 init_param_065;
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__u32 init_param_066;
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__u32 init_param_067;
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__u32 init_param_068;
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__u32 init_param_069;
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__u32 init_param_070;
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__u32 init_param_071;
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__u32 init_param_072;
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__u32 init_param_073;
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__u32 init_param_074;
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__u32 init_param_075;
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};
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/*
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* struct drm_msm_ad4_cfg - ad4 config structure set by user-space client.
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* Config param values can vary based on tuning,
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* hence it is passed by user-space clients.
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*/
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struct drm_msm_ad4_cfg {
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__u32 cfg_param_001;
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__u32 cfg_param_002;
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__u32 cfg_param_003;
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__u32 cfg_param_004;
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__u32 cfg_param_005;
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__u32 cfg_param_006;
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__u32 cfg_param_007;
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__u32 cfg_param_008;
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__u32 cfg_param_009;
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__u32 cfg_param_010;
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__u32 cfg_param_011;
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__u32 cfg_param_012;
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__u32 cfg_param_013;
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__u32 cfg_param_014;
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__u32 cfg_param_015;
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__u32 cfg_param_016;
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__u32 cfg_param_017;
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__u32 cfg_param_018;
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__u32 cfg_param_019;
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__u32 cfg_param_020;
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__u32 cfg_param_021;
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__u32 cfg_param_022;
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__u32 cfg_param_023;
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__u32 cfg_param_024;
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__u32 cfg_param_025;
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__u32 cfg_param_026;
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__u32 cfg_param_027;
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__u32 cfg_param_028;
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__u32 cfg_param_029;
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__u32 cfg_param_030;
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__u32 cfg_param_031;
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__u32 cfg_param_032;
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__u32 cfg_param_033;
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__u32 cfg_param_034;
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__u32 cfg_param_035;
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__u32 cfg_param_036;
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__u32 cfg_param_037;
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__u32 cfg_param_038;
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__u32 cfg_param_039;
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__u32 cfg_param_040;
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__u32 cfg_param_041;
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__u32 cfg_param_042;
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__u32 cfg_param_043;
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__u32 cfg_param_044;
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__u32 cfg_param_045;
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__u32 cfg_param_046;
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__u32 cfg_param_047;
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__u32 cfg_param_048;
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__u32 cfg_param_049;
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__u32 cfg_param_050;
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__u32 cfg_param_051;
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__u32 cfg_param_052;
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__u32 cfg_param_053;
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};
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#define DITHER_MATRIX_SZ 16
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/**
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* struct drm_msm_dither - dither feature structure
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* @flags: for customizing operations
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* @temporal_en: temperal dither enable
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* @c0_bitdepth: c0 component bit depth
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* @c1_bitdepth: c1 component bit depth
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* @c2_bitdepth: c2 component bit depth
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* @c3_bitdepth: c2 component bit depth
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* @matrix: dither strength matrix
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*/
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struct drm_msm_dither {
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__u64 flags;
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__u32 temporal_en;
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__u32 c0_bitdepth;
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__u32 c1_bitdepth;
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__u32 c2_bitdepth;
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__u32 c3_bitdepth;
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__u32 matrix[DITHER_MATRIX_SZ];
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};
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/**
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* struct drm_msm_pa_dither - dspp dither feature structure
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* @flags: for customizing operations
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* @strength: dither strength
|
||||
* @offset_en: offset enable bit
|
||||
* @matrix: dither data matrix
|
||||
*/
|
||||
#define DRM_MSM_PA_DITHER
|
||||
struct drm_msm_pa_dither {
|
||||
__u64 flags;
|
||||
__u32 strength;
|
||||
__u32 offset_en;
|
||||
__u32 matrix[DITHER_MATRIX_SZ];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_ad4_roi_cfg - ad4 roi params config set
|
||||
* by user-space client.
|
||||
* @h_x - hotizontal direction start
|
||||
* @h_y - hotizontal direction end
|
||||
* @v_x - vertical direction start
|
||||
* @v_y - vertical direction end
|
||||
* @factor_in - the alpha value for inside roi region
|
||||
* @factor_out - the alpha value for outside roi region
|
||||
*/
|
||||
#define DRM_MSM_AD4_ROI
|
||||
struct drm_msm_ad4_roi_cfg {
|
||||
__u32 h_x;
|
||||
__u32 h_y;
|
||||
__u32 v_x;
|
||||
__u32 v_y;
|
||||
__u32 factor_in;
|
||||
__u32 factor_out;
|
||||
};
|
||||
|
||||
#define LTM_FEATURE_DEF 1
|
||||
#define LTM_DATA_SIZE_0 32
|
||||
#define LTM_DATA_SIZE_1 128
|
||||
#define LTM_DATA_SIZE_2 256
|
||||
#define LTM_DATA_SIZE_3 33
|
||||
#define LTM_BUFFER_SIZE 5
|
||||
#define LTM_GUARD_BYTES 255
|
||||
#define LTM_BLOCK_SIZE 2
|
||||
|
||||
#define LTM_STATS_SAT (1 << 1)
|
||||
#define LTM_STATS_MERGE_SAT (1 << 2)
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_stats_data - LTM stats data structure
|
||||
*/
|
||||
struct drm_msm_ltm_stats_data {
|
||||
__u32 stats_01[LTM_DATA_SIZE_0][LTM_DATA_SIZE_1];
|
||||
__u32 stats_02[LTM_DATA_SIZE_2];
|
||||
__u32 stats_03[LTM_DATA_SIZE_0];
|
||||
__u32 stats_04[LTM_DATA_SIZE_0];
|
||||
__u32 stats_05[LTM_DATA_SIZE_0];
|
||||
__u32 status_flag;
|
||||
__u32 display_h;
|
||||
__u32 display_v;
|
||||
__u32 init_h[LTM_BLOCK_SIZE];
|
||||
__u32 init_v;
|
||||
__u32 inc_h;
|
||||
__u32 inc_v;
|
||||
__u32 portrait_en;
|
||||
__u32 merge_en;
|
||||
__u32 cfg_param_01;
|
||||
__u32 cfg_param_02;
|
||||
__u32 cfg_param_03;
|
||||
__u32 cfg_param_04;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_init_param - LTM init param structure
|
||||
*/
|
||||
struct drm_msm_ltm_init_param {
|
||||
__u32 init_param_01;
|
||||
__u32 init_param_02;
|
||||
__u32 init_param_03;
|
||||
__u32 init_param_04;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_cfg_param - LTM config param structure
|
||||
*/
|
||||
struct drm_msm_ltm_cfg_param {
|
||||
__u32 cfg_param_01;
|
||||
__u32 cfg_param_02;
|
||||
__u32 cfg_param_03;
|
||||
__u32 cfg_param_04;
|
||||
__u32 cfg_param_05;
|
||||
__u32 cfg_param_06;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_data - LTM data structure
|
||||
*/
|
||||
struct drm_msm_ltm_data {
|
||||
__u32 data[LTM_DATA_SIZE_0][LTM_DATA_SIZE_3];
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_buffers_crtl - LTM buffer control structure.
|
||||
* This struct will be used to init and
|
||||
* de-init the LTM buffers in driver.
|
||||
* @num_of_buffers: valid number of buffers used
|
||||
* @fds: fd array to for all the valid buffers
|
||||
*/
|
||||
struct drm_msm_ltm_buffers_ctrl {
|
||||
__u32 num_of_buffers;
|
||||
__u32 fds[LTM_BUFFER_SIZE];
|
||||
};
|
||||
|
||||
/*
|
||||
* struct drm_msm_ltm_buffer - LTM buffer structure.
|
||||
* This struct will be passed from driver to user
|
||||
* space for LTM stats data notification.
|
||||
* @fd: fd assicated with the buffer that has LTM stats data
|
||||
* @offset: offset from base address that used for alignment
|
||||
* @status status flag for error indication
|
||||
*/
|
||||
struct drm_msm_ltm_buffer {
|
||||
__u32 fd;
|
||||
__u32 offset;
|
||||
__u32 status;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_msm_ad4_manual_str_cfg - ad4 manual strength config set
|
||||
* by user-space client.
|
||||
* @in_str - strength for inside roi region
|
||||
* @out_str - strength for outside roi region
|
||||
*/
|
||||
#define DRM_MSM_AD4_MANUAL_STRENGTH
|
||||
struct drm_msm_ad4_manual_str_cfg {
|
||||
__u32 in_str;
|
||||
__u32 out_str;
|
||||
};
|
||||
#endif /* _MSM_DRM_PP_H_ */
|
||||
Reference in New Issue
Block a user