asoc: Update SWR Port Types for Kalama chipset
Add PBR, CPS port types and port parameters for WSA Update RX and TX port types to include full list of ports Change-Id: I5b69ee777addebcf4167dccd4ce4ab0af31b754d Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
This commit is contained in:
Matthew Rice
@@ -37,6 +37,7 @@
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static int swr_master_channel_map[] = {
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ZERO,
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SWRM_TX_PCM_OUT,
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SWRM_TX1_CH1,
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SWRM_TX1_CH2,
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SWRM_TX1_CH3,
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@@ -49,7 +50,7 @@ static int swr_master_channel_map[] = {
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SWRM_TX3_CH2,
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SWRM_TX3_CH3,
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SWRM_TX3_CH4,
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SWRM_PCM_IN,
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SWRM_TX_PCM_IN,
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};
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/*
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@@ -364,10 +365,10 @@ err_port_map:
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}
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static const char * const tx_master_port_text[] = {
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"ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
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"SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
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"SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
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"SWRM_PCM_IN",
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"ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
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"SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
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"SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
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"SWRM_TX3_CH4", "SWRM_PCM_IN",
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};
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static const struct soc_enum tx_master_port_enum =
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@@ -2886,10 +2886,10 @@ static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
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}
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const char * const tx_master_ch_text[] = {
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"ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4",
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"SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4",
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"SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4",
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"SWRM_PCM_IN",
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"ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
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"SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
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"SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
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"SWRM_TX3_CH4", "SWRM_PCM_IN",
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};
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const struct soc_enum tx_master_ch_enum =
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@@ -46,6 +46,7 @@ static const struct swr_slave_ch_map swr_slv_tx_ch_idx[] = {
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static int swr_master_ch_map[] = {
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ZERO,
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SWRM_TX_PCM_OUT,
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SWRM_TX1_CH1,
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SWRM_TX1_CH2,
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SWRM_TX1_CH3,
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@@ -58,7 +59,7 @@ static int swr_master_ch_map[] = {
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SWRM_TX3_CH2,
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SWRM_TX3_CH3,
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SWRM_TX3_CH4,
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SWRM_PCM_IN,
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SWRM_TX_PCM_IN,
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};
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#if IS_ENABLED(CONFIG_SND_SOC_WCD938X)
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@@ -17,33 +17,50 @@
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*/
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static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
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{7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
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{15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{7, 1, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR1 */
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{31, 3, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP1 */
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{63, 5, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB1 */
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{7, 2, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR2 */
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{31, 4, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP2 */
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{63, 21, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB2 */
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{399, 0, 0, 8, 0, 9, 0, 0, 0xFF, 0x00, 0x01}, /* PBR */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
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{15, 6, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS1 */
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{15, 13, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS2 */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
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{799, 0, 0, 15, 15, 25, 0, 0, 0xFF, 0x01, 0x01}, /* CPS */
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};
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static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
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{3, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{31, 2, 3, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
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{63, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{3, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
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{15, 3, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
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{3, 1, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR1 */
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{31, 3, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP1 */
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{63, 5, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB1 */
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{3, 2, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR2 */
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{31, 4, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP2 */
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{63, 21, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB2 */
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{399, 0, 0, 8, 0, 9, 0, 0, 0xFF, 0x00, 0x01}, /* PBR */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
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{15, 6, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS1 */
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{15, 13, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS2 */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
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{799, 0, 0, 15, 15, 25, 0, 0, 0xFF, 0x01, 0x01}, /* CPS */
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};
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static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00},
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02},
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x02},
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{7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00},
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00},
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02}, /* HPH_CLH */
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x02}, /* HPH_CMP */
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{7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00}, /* LO/AUX */
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00}, /* DSD */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HIFI */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
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};
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/* Headset + PCM Haptics */
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@@ -54,6 +71,13 @@ static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */
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{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
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{0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HIFI */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
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};
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/* Headset(44.1K) + PCM Haptics */
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@@ -64,6 +88,12 @@ static struct port_params rx_frame_params_44p1KHz[SWR_MSTR_PORT_LEN] = {
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0, 0x00, 0x00}, /* LO/AUX */
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{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
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{0x1FF, 0, 0, 0x8, 0x8, 0x0F, 0, 0, 0, 0x00, 0x01}, /* PCM_OUT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HIFI */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
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};
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static struct swr_mstr_port_map sm_port_map[] = {
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@@ -1439,15 +1439,16 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, int w
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static int msm_int_wsa_init(struct snd_soc_pcm_runtime *rtd)
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{
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u8 spkleft_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3};
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u8 spkright_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3};
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u8 spkleft_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3, 4, 5};
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u8 spkright_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3, 4, 5};
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u8 spkleft_port_types[WSA884X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
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SPKR_L_BOOST, SPKR_L_VI};
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SPKR_L_BOOST, PBR, SPKR_L_VI, CPS};
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u8 spkright_port_types[WSA884X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
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SPKR_R_BOOST, SPKR_R_VI};
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SPKR_R_BOOST, PBR, SPKR_R_VI, CPS};
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unsigned int ch_rate[WSA884X_MAX_SWR_PORTS] = {SWR_CLK_RATE_2P4MHZ, SWR_CLK_RATE_0P6MHZ,
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SWR_CLK_RATE_0P3MHZ, SWR_CLK_RATE_1P2MHZ};
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unsigned int ch_mask[WSA884X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
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SWR_CLK_RATE_0P3MHZ, SWR_CLK_RATE_48KHZ,
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SWR_CLK_RATE_1P2MHZ, SWR_CLK_RATE_24KHZ};
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unsigned int ch_mask[WSA884X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3, 0x3, 0x3};
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struct snd_soc_component *component = NULL;
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@@ -28,48 +28,60 @@
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#define SPKR_L 1
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#define SPKR_L_COMP 2
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#define SPKR_L_BOOST 3
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#define SPKR_L_VI 4
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#define SPKR_R 5
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#define SPKR_R_COMP 6
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#define SPKR_R_BOOST 7
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#define SPKR_R_VI 8
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#define HPH_L 9
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#define HPH_R 10
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#define COMP_L 11
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#define COMP_R 12
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#define CLSH 13
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#define LO 14
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#define DSD_L 15
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#define DSD_R 16
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#define MBHC 17
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#define ADC1 18
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#define ADC2 19
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#define ADC3 20
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#define ADC4 21
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#define DMIC0 22
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#define DMIC1 23
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#define DMIC2 24
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#define DMIC3 25
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#define DMIC4 26
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#define DMIC5 27
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#define DMIC6 28
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#define DMIC7 29
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#define DMIC8 30
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#define DMIC9 31
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#define DMIC10 32
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#define PCM_OUT1 33
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#define SWRM_TX1_CH1 34
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#define SWRM_TX1_CH2 35
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#define SWRM_TX1_CH3 36
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#define SWRM_TX1_CH4 37
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#define SWRM_TX2_CH1 38
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#define SWRM_TX2_CH2 39
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#define SWRM_TX2_CH3 40
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#define SWRM_TX2_CH4 41
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#define SWRM_TX3_CH1 42
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#define SWRM_TX3_CH2 43
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#define SWRM_TX3_CH3 44
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#define SWRM_TX3_CH4 45
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#define SWRM_PCM_IN 46
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#define SPKR_R 4
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#define SPKR_R_COMP 5
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#define SPKR_R_BOOST 6
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#define PBR 7
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#define SPKR_HAPT 8
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#define OCPM 9
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#define SPKR_L_VI 10
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#define SPKR_R_VI 11
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#define SPKR_IPCM 12
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#define CPS 13
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#define HPH_L 14
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#define HPH_R 15
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#define COMP_L 16
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#define COMP_R 17
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#define CLSH 18
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#define LO 19
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#define DSD_L 20
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#define DSD_R 21
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#define PCM_OUT1 22
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#define GPPO 23
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#define HAPT 24
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#define HIFI 25
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#define HPTH 26
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#define CMPT 27
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#define IPCM 28
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#define MBHC 29
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#define ADC1 30
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#define ADC2 31
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#define ADC3 32
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#define ADC4 33
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#define DMIC0 34
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#define DMIC1 35
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#define DMIC2 36
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#define DMIC3 37
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#define DMIC4 38
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#define DMIC5 39
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#define DMIC6 40
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#define DMIC7 41
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#define DMIC8 42
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#define DMIC9 43
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#define DMIC10 44
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#define SWRM_TX_PCM_OUT 45
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#define SWRM_TX1_CH1 46
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#define SWRM_TX1_CH2 47
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#define SWRM_TX1_CH3 48
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#define SWRM_TX1_CH4 49
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#define SWRM_TX2_CH1 50
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#define SWRM_TX2_CH2 51
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#define SWRM_TX2_CH3 52
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#define SWRM_TX2_CH4 53
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#define SWRM_TX3_CH1 54
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#define SWRM_TX3_CH2 55
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#define SWRM_TX3_CH3 56
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#define SWRM_TX3_CH4 57
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#define SWRM_TX_PCM_IN 58
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#endif /* __AUDIO_CODEC_PORT_TYPES_H */
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _LINUX_SOUNDWIRE_H
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@@ -19,6 +19,8 @@ enum {
|
||||
SWR_UC_MAX,
|
||||
};
|
||||
|
||||
#define SWR_CLK_RATE_24KHZ 24000
|
||||
#define SWR_CLK_RATE_48KHZ 48000
|
||||
#define SWR_CLK_RATE_0P3MHZ 300000
|
||||
#define SWR_CLK_RATE_0P6MHZ 600000
|
||||
#define SWR_CLK_RATE_1P2MHZ 1200000
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2015, 2017-2020 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2015, 2017-2021 The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_SWR_COMMON_H
|
||||
@@ -36,6 +36,6 @@ struct swr_mstr_port_map {
|
||||
struct port_params *swr_port_params;
|
||||
};
|
||||
|
||||
#define SWR_MSTR_PORT_LEN 8 /* Number of master ports */
|
||||
#define SWR_MSTR_PORT_LEN 13 /* Number of master ports */
|
||||
|
||||
#endif /* _LINUX_SWR_COMMON_H */
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
#define SWR_MSTR_MAX_REG_ADDR 0x6B160A8
|
||||
#define SWR_MSTR_MAX_REG_ADDR 0x60A8
|
||||
#define SWR_MSTR_START_REG_ADDR 0x00
|
||||
#define SWR_MSTR_MAX_BUF_LEN 32
|
||||
#define BYTES_PER_LINE 12
|
||||
@@ -32,7 +32,7 @@
|
||||
|
||||
#define SWR_WCD_NAME "swr-wcd"
|
||||
|
||||
#define SWR_MSTR_PORT_LEN 8 /* Number of master ports */
|
||||
#define SWR_MSTR_PORT_LEN 13 /* Number of master ports */
|
||||
|
||||
#define SWRM_VERSION_1_0 0x01010000
|
||||
#define SWRM_VERSION_1_2 0x01030000
|
||||
|
||||
Reference in New Issue
Block a user