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asoc: Update SWR Port Types for Kalama chipset

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Add PBR, CPS port types and port parameters for WSA
Update RX and TX port types to include full list of ports

Change-Id: I5b69ee777addebcf4167dccd4ce4ab0af31b754d
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
This commit is contained in:
Matthew Rice
2021-11-30 14:01:38 -08:00
parent 2dacb122a3
commit a0a83d7e42
9 changed files with 144 additions and 97 deletions
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11
asoc/codecs/swr-dmic.c
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@@ -37,6 +37,7 @@
static int swr_master_channel_map[] = { static int swr_master_channel_map[] = {
ZERO, ZERO,
SWRM_TX_PCM_OUT,
SWRM_TX1_CH1, SWRM_TX1_CH1,
SWRM_TX1_CH2, SWRM_TX1_CH2,
SWRM_TX1_CH3, SWRM_TX1_CH3,
@@ -49,7 +50,7 @@ static int swr_master_channel_map[] = {
SWRM_TX3_CH2, SWRM_TX3_CH2,
SWRM_TX3_CH3, SWRM_TX3_CH3,
SWRM_TX3_CH4, SWRM_TX3_CH4,
SWRM_PCM_IN, SWRM_TX_PCM_IN,
}; };
/* /*
@@ -364,10 +365,10 @@ err_port_map:
} }
static const char * const tx_master_port_text[] = { static const char * const tx_master_port_text[] = {
"ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4", "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
"SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4", "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
"SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4", "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
"SWRM_PCM_IN", "SWRM_TX3_CH4", "SWRM_PCM_IN",
}; };
static const struct soc_enum tx_master_port_enum = static const struct soc_enum tx_master_port_enum =

8
asoc/codecs/wcd938x/wcd938x.c
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@@ -2886,10 +2886,10 @@ static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
} }
const char * const tx_master_ch_text[] = { const char * const tx_master_ch_text[] = {
"ZERO", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3", "SWRM_TX1_CH4", "ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
"SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3", "SWRM_TX2_CH4", "SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
"SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3", "SWRM_TX3_CH4", "SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
"SWRM_PCM_IN", "SWRM_TX3_CH4", "SWRM_PCM_IN",
}; };
const struct soc_enum tx_master_ch_enum = const struct soc_enum tx_master_ch_enum =

3
asoc/codecs/wcd938x/wcd938x.h
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@@ -46,6 +46,7 @@ static const struct swr_slave_ch_map swr_slv_tx_ch_idx[] = {
static int swr_master_ch_map[] = { static int swr_master_ch_map[] = {
ZERO, ZERO,
SWRM_TX_PCM_OUT,
SWRM_TX1_CH1, SWRM_TX1_CH1,
SWRM_TX1_CH2, SWRM_TX1_CH2,
SWRM_TX1_CH3, SWRM_TX1_CH3,
@@ -58,7 +59,7 @@ static int swr_master_ch_map[] = {
SWRM_TX3_CH2, SWRM_TX3_CH2,
SWRM_TX3_CH3, SWRM_TX3_CH3,
SWRM_TX3_CH4, SWRM_TX3_CH4,
SWRM_PCM_IN, SWRM_TX_PCM_IN,
}; };
#if IS_ENABLED(CONFIG_SND_SOC_WCD938X) #if IS_ENABLED(CONFIG_SND_SOC_WCD938X)

72
asoc/kalama-port-config.h
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@@ -17,33 +17,50 @@
*/ */
static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = { static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
{7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {7, 1, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR1 */
{31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {31, 3, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP1 */
{63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {63, 5, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB1 */
{7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {7, 2, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR2 */
{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {31, 4, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP2 */
{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {63, 21, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB2 */
{15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {399, 0, 0, 8, 0, 9, 0, 0, 0xFF, 0x00, 0x01}, /* PBR */
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
{15, 6, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS1 */
{15, 13, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS2 */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
{799, 0, 0, 15, 15, 25, 0, 0, 0xFF, 0x01, 0x01}, /* CPS */
}; };
static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = { static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
{3, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {3, 1, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR1 */
{31, 2, 3, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {31, 3, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP1 */
{63, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {63, 5, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB1 */
{3, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {3, 2, 0, 0, 0, 1, 0, 0, 0xFF, 0x00, 0x00}, /* SPKR2 */
{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {31, 4, 7, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* CMP2 */
{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00}, {63, 21, 31, 0, 0, 1, 1, 0, 0xFF, 0x00, 0x00}, /* SB2 */
{15, 3, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {399, 0, 0, 8, 0, 9, 0, 0, 0xFF, 0x00, 0x01}, /* PBR */
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, /* HAPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01}, /* OCPM */
{15, 6, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS1 */
{15, 13, 0, 0, 15, 1, 1, 0, 0xFF, 0x01, 0x00}, /* IVS2 */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x01}, /* ICPM */
{799, 0, 0, 15, 15, 25, 0, 0, 0xFF, 0x01, 0x01}, /* CPS */
}; };
static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, /* HPH/EAR */
{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02}, /* HPH_CLH */
{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x02}, {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0, 0x00, 0x02}, /* HPH_CMP */
{7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00}, {7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0, 0x00, 0x00}, /* LO/AUX */
{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00}, {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0, 0x00, 0x00}, /* DSD */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HIFI */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
}; };
/* Headset + PCM Haptics */ /* Headset + PCM Haptics */
@@ -54,6 +71,13 @@ static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */ {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* LO/AUX */
{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */ {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
{0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */ {0x18F, 0, 0, 0x8, 0x8, 0x0F, 0x00, 0, 0, 0x00, 0x01}, /* PCM_OUT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HIFI */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
}; };
/* Headset(44.1K) + PCM Haptics */ /* Headset(44.1K) + PCM Haptics */
@@ -64,6 +88,12 @@ static struct port_params rx_frame_params_44p1KHz[SWR_MSTR_PORT_LEN] = {
{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0, 0x00, 0x00}, /* LO/AUX */ {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0, 0x00, 0x00}, /* LO/AUX */
{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */ {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0, 0x00, 0x00}, /* DSD */
{0x1FF, 0, 0, 0x8, 0x8, 0x0F, 0, 0, 0, 0x00, 0x01}, /* PCM_OUT */ {0x1FF, 0, 0, 0x8, 0x8, 0x0F, 0, 0, 0, 0x00, 0x01}, /* PCM_OUT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* GPPO */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HAPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HIFI */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* HPHT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
}; };
static struct swr_mstr_port_map sm_port_map[] = { static struct swr_mstr_port_map sm_port_map[] = {

13
asoc/kalama.c
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@@ -1439,15 +1439,16 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, int w
static int msm_int_wsa_init(struct snd_soc_pcm_runtime *rtd) static int msm_int_wsa_init(struct snd_soc_pcm_runtime *rtd)
{ {
u8 spkleft_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3}; u8 spkleft_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3, 4, 5};
u8 spkright_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3}; u8 spkright_ports[WSA884X_MAX_SWR_PORTS] = {0, 1, 2, 3, 4, 5};
u8 spkleft_port_types[WSA884X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP, u8 spkleft_port_types[WSA884X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
SPKR_L_BOOST, SPKR_L_VI}; SPKR_L_BOOST, PBR, SPKR_L_VI, CPS};
u8 spkright_port_types[WSA884X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP, u8 spkright_port_types[WSA884X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
SPKR_R_BOOST, SPKR_R_VI}; SPKR_R_BOOST, PBR, SPKR_R_VI, CPS};
unsigned int ch_rate[WSA884X_MAX_SWR_PORTS] = {SWR_CLK_RATE_2P4MHZ, SWR_CLK_RATE_0P6MHZ, unsigned int ch_rate[WSA884X_MAX_SWR_PORTS] = {SWR_CLK_RATE_2P4MHZ, SWR_CLK_RATE_0P6MHZ,
SWR_CLK_RATE_0P3MHZ, SWR_CLK_RATE_1P2MHZ}; SWR_CLK_RATE_0P3MHZ, SWR_CLK_RATE_48KHZ,
unsigned int ch_mask[WSA884X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3}; SWR_CLK_RATE_1P2MHZ, SWR_CLK_RATE_24KHZ};
unsigned int ch_mask[WSA884X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3, 0x3, 0x3};
struct snd_soc_component *component = NULL; struct snd_soc_component *component = NULL;

98
include/bindings/audio-codec-port-types.h
View File

@@ -28,48 +28,60 @@
#define SPKR_L 1 #define SPKR_L 1
#define SPKR_L_COMP 2 #define SPKR_L_COMP 2
#define SPKR_L_BOOST 3 #define SPKR_L_BOOST 3
#define SPKR_L_VI 4 #define SPKR_R 4
#define SPKR_R 5 #define SPKR_R_COMP 5
#define SPKR_R_COMP 6 #define SPKR_R_BOOST 6
#define SPKR_R_BOOST 7 #define PBR 7
#define SPKR_R_VI 8 #define SPKR_HAPT 8
#define HPH_L 9 #define OCPM 9
#define HPH_R 10 #define SPKR_L_VI 10
#define COMP_L 11 #define SPKR_R_VI 11
#define COMP_R 12 #define SPKR_IPCM 12
#define CLSH 13 #define CPS 13
#define LO 14 #define HPH_L 14
#define DSD_L 15 #define HPH_R 15
#define DSD_R 16 #define COMP_L 16
#define MBHC 17 #define COMP_R 17
#define ADC1 18 #define CLSH 18
#define ADC2 19 #define LO 19
#define ADC3 20 #define DSD_L 20
#define ADC4 21 #define DSD_R 21
#define DMIC0 22 #define PCM_OUT1 22
#define DMIC1 23 #define GPPO 23
#define DMIC2 24 #define HAPT 24
#define DMIC3 25 #define HIFI 25
#define DMIC4 26 #define HPTH 26
#define DMIC5 27 #define CMPT 27
#define DMIC6 28 #define IPCM 28
#define DMIC7 29 #define MBHC 29
#define DMIC8 30 #define ADC1 30
#define DMIC9 31 #define ADC2 31
#define DMIC10 32 #define ADC3 32
#define PCM_OUT1 33 #define ADC4 33
#define SWRM_TX1_CH1 34 #define DMIC0 34
#define SWRM_TX1_CH2 35 #define DMIC1 35
#define SWRM_TX1_CH3 36 #define DMIC2 36
#define SWRM_TX1_CH4 37 #define DMIC3 37
#define SWRM_TX2_CH1 38 #define DMIC4 38
#define SWRM_TX2_CH2 39 #define DMIC5 39
#define SWRM_TX2_CH3 40 #define DMIC6 40
#define SWRM_TX2_CH4 41 #define DMIC7 41
#define SWRM_TX3_CH1 42 #define DMIC8 42
#define SWRM_TX3_CH2 43 #define DMIC9 43
#define SWRM_TX3_CH3 44 #define DMIC10 44
#define SWRM_TX3_CH4 45 #define SWRM_TX_PCM_OUT 45
#define SWRM_PCM_IN 46 #define SWRM_TX1_CH1 46
#define SWRM_TX1_CH2 47
#define SWRM_TX1_CH3 48
#define SWRM_TX1_CH4 49
#define SWRM_TX2_CH1 50
#define SWRM_TX2_CH2 51
#define SWRM_TX2_CH3 52
#define SWRM_TX2_CH4 53
#define SWRM_TX3_CH1 54
#define SWRM_TX3_CH2 55
#define SWRM_TX3_CH3 56
#define SWRM_TX3_CH4 57
#define SWRM_TX_PCM_IN 58
#endif /* __AUDIO_CODEC_PORT_TYPES_H */ #endif /* __AUDIO_CODEC_PORT_TYPES_H */

4
include/soc/soundwire.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/ */
#ifndef _LINUX_SOUNDWIRE_H #ifndef _LINUX_SOUNDWIRE_H
@@ -19,6 +19,8 @@ enum {
SWR_UC_MAX, SWR_UC_MAX,
}; };
#define SWR_CLK_RATE_24KHZ 24000
#define SWR_CLK_RATE_48KHZ 48000
#define SWR_CLK_RATE_0P3MHZ 300000 #define SWR_CLK_RATE_0P3MHZ 300000
#define SWR_CLK_RATE_0P6MHZ 600000 #define SWR_CLK_RATE_0P6MHZ 600000
#define SWR_CLK_RATE_1P2MHZ 1200000 #define SWR_CLK_RATE_1P2MHZ 1200000

4
include/soc/swr-common.h
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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2015, 2017-2020 The Linux Foundation. All rights reserved. * Copyright (c) 2015, 2017-2021 The Linux Foundation. All rights reserved.
*/ */
#ifndef _LINUX_SWR_COMMON_H #ifndef _LINUX_SWR_COMMON_H
@@ -36,6 +36,6 @@ struct swr_mstr_port_map {
struct port_params *swr_port_params; struct port_params *swr_port_params;
}; };
#define SWR_MSTR_PORT_LEN 8 /* Number of master ports */ #define SWR_MSTR_PORT_LEN 13 /* Number of master ports */
#endif /* _LINUX_SWR_COMMON_H */ #endif /* _LINUX_SWR_COMMON_H */

4
soc/swr-mstr-ctrl.h
View File

@@ -15,7 +15,7 @@
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#define SWR_MSTR_MAX_REG_ADDR 0x6B160A8 #define SWR_MSTR_MAX_REG_ADDR 0x60A8
#define SWR_MSTR_START_REG_ADDR 0x00 #define SWR_MSTR_START_REG_ADDR 0x00
#define SWR_MSTR_MAX_BUF_LEN 32 #define SWR_MSTR_MAX_BUF_LEN 32
#define BYTES_PER_LINE 12 #define BYTES_PER_LINE 12
@@ -32,7 +32,7 @@
#define SWR_WCD_NAME "swr-wcd" #define SWR_WCD_NAME "swr-wcd"
#define SWR_MSTR_PORT_LEN 8 /* Number of master ports */ #define SWR_MSTR_PORT_LEN 13 /* Number of master ports */
#define SWRM_VERSION_1_0 0x01010000 #define SWRM_VERSION_1_0 0x01010000
#define SWRM_VERSION_1_2 0x01030000 #define SWRM_VERSION_1_2 0x01030000