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@@ -197,13 +197,39 @@ static int32_t cam_cci_lock_queue(struct cci_device *cci_dev,
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enum cci_i2c_master_t master,
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enum cci_i2c_master_t master,
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enum cci_i2c_queue_t queue, uint32_t en)
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enum cci_i2c_queue_t queue, uint32_t en)
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{
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{
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- uint32_t val;
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+ int32_t rc = 0;
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+ uint32_t val = 0;
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+ uint32_t read_val = 0;
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+ struct cam_hw_soc_info *soc_info =
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+ &cci_dev->soc_info;
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+ void __iomem *base =
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+ soc_info->reg_map[0].mem_base;
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+ uint32_t reg_offset =
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+ master * 0x200 + queue * 0x100;
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if (queue != PRIORITY_QUEUE)
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if (queue != PRIORITY_QUEUE)
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- return 0;
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+ goto end;
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+
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+ read_val = cam_io_r_mb(base +
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+ CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset);
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val = en ? CCI_I2C_LOCK_CMD : CCI_I2C_UNLOCK_CMD;
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val = en ? CCI_I2C_LOCK_CMD : CCI_I2C_UNLOCK_CMD;
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- return cam_cci_write_i2c_queue(cci_dev, val, master, queue);
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+ rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue);
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+
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+ if (rc) {
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+ CAM_ERR(CAM_CCI,
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+ "CCI%d_I2C_M%d_Q%d Failed to write i2c data:0x%x rc:%d",
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+ cci_dev->soc_info.index, master, queue, val, rc);
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+ goto end;
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+ }
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+
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+ read_val++;
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+
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+ cam_io_w_mb(read_val, base +
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+ CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset);
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+
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+end:
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+ return rc;
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}
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}
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@@ -356,7 +382,6 @@ static int32_t cam_cci_wait_report_cmd(struct cci_device *cci_dev,
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uint32_t reg_val = 1 << ((master * 2) + queue);
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uint32_t reg_val = 1 << ((master * 2) + queue);
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- cam_cci_load_report_cmd(cci_dev, master, queue);
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spin_lock_irqsave(
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spin_lock_irqsave(
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&cci_dev->cci_master_info[master].lock_q[queue], flags);
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&cci_dev->cci_master_info[master].lock_q[queue], flags);
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atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1);
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atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1);
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@@ -380,6 +405,7 @@ static int32_t cam_cci_transfer_end(struct cci_device *cci_dev,
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if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 0) {
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if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 0) {
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spin_unlock_irqrestore(
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spin_unlock_irqrestore(
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&cci_dev->cci_master_info[master].lock_q[queue], flags);
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&cci_dev->cci_master_info[master].lock_q[queue], flags);
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+ cam_cci_load_report_cmd(cci_dev, master, queue);
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rc = cam_cci_lock_queue(cci_dev, master, queue, 0);
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rc = cam_cci_lock_queue(cci_dev, master, queue, 0);
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if (rc < 0) {
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if (rc < 0) {
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CAM_ERR(CAM_CCI,
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CAM_ERR(CAM_CCI,
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@@ -407,6 +433,7 @@ static int32_t cam_cci_transfer_end(struct cci_device *cci_dev,
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cci_dev->soc_info.index, master, queue, rc);
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cci_dev->soc_info.index, master, queue, rc);
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return rc;
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return rc;
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}
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}
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+ cam_cci_load_report_cmd(cci_dev, master, queue);
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rc = cam_cci_lock_queue(cci_dev, master, queue, 0);
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rc = cam_cci_lock_queue(cci_dev, master, queue, 0);
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if (rc < 0) {
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if (rc < 0) {
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CAM_ERR(CAM_CCI,
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CAM_ERR(CAM_CCI,
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@@ -498,6 +525,7 @@ static int32_t cam_cci_process_full_q(struct cci_device *cci_dev,
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spin_unlock_irqrestore(
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spin_unlock_irqrestore(
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&cci_dev->cci_master_info[master].lock_q[queue], flags);
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&cci_dev->cci_master_info[master].lock_q[queue], flags);
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CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d is set to 0", cci_dev->soc_info.index, master, queue);
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CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d is set to 0", cci_dev->soc_info.index, master, queue);
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+ cam_cci_load_report_cmd(cci_dev, master, queue);
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rc = cam_cci_wait_report_cmd(cci_dev, master, queue);
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rc = cam_cci_wait_report_cmd(cci_dev, master, queue);
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if (rc < 0) {
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if (rc < 0) {
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CAM_ERR(CAM_CCI,
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CAM_ERR(CAM_CCI,
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