asoc: codecs: Update rouleur watchdog interrupt sequence
Update PDM watchdog interrupt sequence for rouleur codec. Add HPH PA gain registers in regmap and update defaults. Update mic bias register bits and rouleur version for ADIE RTC to work. Change-Id: I1bbb41efcdd9a0a8b38fcd4beadbd5d639a4b858 Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
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e7efdae360
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9f50810d7f
@@ -88,7 +88,7 @@ static struct wcd_mbhc_register
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WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
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WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
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ROULEUR_ANA_MBHC_RESULT_3, 0xFF, 0, 0),
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ROULEUR_ANA_MBHC_RESULT_3, 0xFF, 0, 0),
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WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
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WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
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ROULEUR_ANA_MICBIAS_MICB_1_2_EN, 0x04, 2, 0),
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ROULEUR_ANA_MICBIAS_MICB_1_2_EN, 0x06, 1, 0),
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WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
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WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
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SND_SOC_NOPM, 0x00, 0, 0),
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SND_SOC_NOPM, 0x00, 0, 0),
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WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
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WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",
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@@ -45,6 +45,8 @@ static const struct reg_default rouleur_defaults[] = {
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{ ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x2B },
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{ ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x2B },
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{ ROULEUR_ANA_HPHPA_PA_STATUS, 0x00 },
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{ ROULEUR_ANA_HPHPA_PA_STATUS, 0x00 },
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{ ROULEUR_ANA_HPHPA_FSM_CLK, 0x12 },
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{ ROULEUR_ANA_HPHPA_FSM_CLK, 0x12 },
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{ ROULEUR_ANA_HPHPA_L_GAIN, 0x00 },
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{ ROULEUR_ANA_HPHPA_R_GAIN, 0x00 },
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{ ROULEUR_SWR_HPHPA_HD2, 0x1B },
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{ ROULEUR_SWR_HPHPA_HD2, 0x1B },
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{ ROULEUR_ANA_HPHPA_SPARE_CTL, 0x02 },
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{ ROULEUR_ANA_HPHPA_SPARE_CTL, 0x02 },
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{ ROULEUR_ANA_SURGE_EN, 0x38 },
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{ ROULEUR_ANA_SURGE_EN, 0x38 },
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@@ -40,6 +40,8 @@ const u8 rouleur_reg_access_analog[ROULEUR_REG(
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_CNP_CTL_2)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_CNP_CTL_2)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_PA_STATUS)] = RD_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_PA_STATUS)] = RD_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_FSM_CLK)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_FSM_CLK)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_L_GAIN)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_R_GAIN)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_SPARE_CTL)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_HPHPA_SPARE_CTL)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_SWR_HPHPA_HD2)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_SWR_HPHPA_HD2)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_SURGE_EN)] = RD_WR_REG,
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[ROULEUR_REG(ROULEUR_ANA_SURGE_EN)] = RD_WR_REG,
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@@ -475,14 +475,8 @@ static int rouleur_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
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0x04, 0x04);
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0x04, 0x04);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x01, 0x01);
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x01, 0x01);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x03);
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break;
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break;
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case SND_SOC_DAPM_POST_PMD:
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case SND_SOC_DAPM_POST_PMD:
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x00);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
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0x01, 0x00);
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0x01, 0x00);
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@@ -546,14 +540,8 @@ static int rouleur_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
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0x08, 0x08);
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0x08, 0x08);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x02);
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x02);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL1,
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0x03, 0x03);
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break;
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break;
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case SND_SOC_DAPM_POST_PMD:
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case SND_SOC_DAPM_POST_PMD:
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL1,
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0x03, 0x00);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x00);
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x00);
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break;
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break;
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@@ -582,18 +570,12 @@ static int rouleur_codec_ear_lo_dac_event(struct snd_soc_dapm_widget *w,
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
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0x01, 0x01);
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0x01, 0x01);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x03);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL,
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ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL,
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0x04, 0x04);
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0x04, 0x04);
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break;
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break;
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case SND_SOC_DAPM_POST_PMD:
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case SND_SOC_DAPM_POST_PMD:
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x00);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
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ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
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0x01, 0x00);
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0x01, 0x00);
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@@ -622,14 +604,11 @@ static int rouleur_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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rouleur->rx_swr_dev->dev_num,
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rouleur->rx_swr_dev->dev_num,
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true);
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true);
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_HPHPA_CNP_CTL_2,
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0x40, 0x40);
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set_bit(HPH_PA_DELAY, &rouleur->status_mask);
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set_bit(HPH_PA_DELAY, &rouleur->status_mask);
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/* TODO: WHY SECOND TIME */
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usleep_range(5000, 5100);
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ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
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snd_soc_component_update_bits(component,
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rouleur->rx_swr_dev->dev_num,
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ROULEUR_DIG_SWR_PDM_WD_CTL1,
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true);
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0x03, 0x03);
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break;
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break;
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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/*
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/*
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@@ -676,8 +655,8 @@ static int rouleur_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
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WCD_EVENT_POST_HPHR_PA_OFF,
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WCD_EVENT_POST_HPHR_PA_OFF,
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&rouleur->mbhc->wcd_mbhc);
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&rouleur->mbhc->wcd_mbhc);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_HPHPA_CNP_CTL_2,
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ROULEUR_DIG_SWR_PDM_WD_CTL1,
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0x40, 0x00);
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0x03, 0x00);
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break;
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break;
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};
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};
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return ret;
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return ret;
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@@ -700,10 +679,11 @@ static int rouleur_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
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ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
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ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
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rouleur->rx_swr_dev->dev_num,
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rouleur->rx_swr_dev->dev_num,
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true);
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true);
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_HPHPA_CNP_CTL_2,
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0x80, 0x80);
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set_bit(HPH_PA_DELAY, &rouleur->status_mask);
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set_bit(HPH_PA_DELAY, &rouleur->status_mask);
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usleep_range(5000, 5100);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x03);
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break;
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break;
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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/*
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/*
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@@ -748,8 +728,8 @@ static int rouleur_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
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WCD_EVENT_POST_HPHL_PA_OFF,
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WCD_EVENT_POST_HPHL_PA_OFF,
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&rouleur->mbhc->wcd_mbhc);
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&rouleur->mbhc->wcd_mbhc);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_HPHPA_CNP_CTL_2,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x80, 0x00);
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0x03, 0x00);
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break;
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break;
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};
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};
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@@ -773,10 +753,10 @@ static int rouleur_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
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ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
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ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
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rouleur->rx_swr_dev->dev_num,
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rouleur->rx_swr_dev->dev_num,
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true);
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true);
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_COMBOPA_CTL,
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0x80, 0x80);
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usleep_range(5000, 5100);
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usleep_range(5000, 5100);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x03);
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break;
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break;
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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if (rouleur->update_wcd_event)
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if (rouleur->update_wcd_event)
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@@ -795,10 +775,10 @@ static int rouleur_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
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(WCD_RX1 << 0x10 | 0x1));
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(WCD_RX1 << 0x10 | 0x1));
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break;
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break;
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case SND_SOC_DAPM_POST_PMD:
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case SND_SOC_DAPM_POST_PMD:
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_COMBOPA_CTL,
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0x80, 0x00);
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usleep_range(5000, 5100);
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usleep_range(5000, 5100);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x00);
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};
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};
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return ret;
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return ret;
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}
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}
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@@ -823,10 +803,10 @@ static int rouleur_codec_enable_lo_pa(struct snd_soc_dapm_widget *w,
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_COMBOPA_CTL,
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ROULEUR_ANA_COMBOPA_CTL,
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0x40, 0x40);
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0x40, 0x40);
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_COMBOPA_CTL,
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0x80, 0x80);
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usleep_range(5000, 5100);
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usleep_range(5000, 5100);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x03);
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break;
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break;
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMU:
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if (rouleur->update_wcd_event)
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if (rouleur->update_wcd_event)
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@@ -845,13 +825,13 @@ static int rouleur_codec_enable_lo_pa(struct snd_soc_dapm_widget *w,
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(WCD_RX1 << 0x10 | 0x1));
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(WCD_RX1 << 0x10 | 0x1));
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break;
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break;
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case SND_SOC_DAPM_POST_PMD:
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case SND_SOC_DAPM_POST_PMD:
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_COMBOPA_CTL,
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0x80, 0x00);
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snd_soc_component_update_bits(component,
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snd_soc_component_update_bits(component,
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ROULEUR_ANA_COMBOPA_CTL,
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ROULEUR_ANA_COMBOPA_CTL,
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0x40, 0x00);
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0x40, 0x00);
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usleep_range(5000, 5100);
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usleep_range(5000, 5100);
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snd_soc_component_update_bits(component,
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ROULEUR_DIG_SWR_PDM_WD_CTL0,
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0x03, 0x00);
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};
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};
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return ret;
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return ret;
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}
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}
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@@ -1552,6 +1532,9 @@ static int rouleur_codec_enable_pa_vpos(struct snd_soc_dapm_widget *w,
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break;
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break;
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case SND_SOC_DAPM_POST_PMD:
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case SND_SOC_DAPM_POST_PMD:
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set_bit(ALLOW_VPOS_DISABLE, &rouleur->status_mask);
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set_bit(ALLOW_VPOS_DISABLE, &rouleur->status_mask);
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ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
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rouleur->rx_swr_dev->dev_num,
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false);
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break;
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break;
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}
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}
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return 0;
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return 0;
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@@ -1822,7 +1805,7 @@ static ssize_t rouleur_version_read(struct snd_info_entry *entry,
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switch (priv->version) {
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switch (priv->version) {
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case ROULEUR_VERSION_1_0:
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case ROULEUR_VERSION_1_0:
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len = snprintf(buffer, sizeof(buffer), "rouleur_1_0\n");
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len = snprintf(buffer, sizeof(buffer), "ROULEUR_1_0\n");
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break;
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break;
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default:
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default:
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len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
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len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
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