asoc: codecs: Update rouleur watchdog interrupt sequence

Update PDM watchdog interrupt sequence for rouleur
codec. Add HPH PA gain registers in regmap and update
defaults. Update mic bias register bits and rouleur
version for ADIE RTC to work.

Change-Id: I1bbb41efcdd9a0a8b38fcd4beadbd5d639a4b858
Signed-off-by: Aditya Bavanari <abavanar@codeaurora.org>
This commit is contained in:
Aditya Bavanari
2020-04-10 16:38:29 +05:30
committed by Gerrit - the friendly Code Review server
parent e7efdae360
commit 9f50810d7f
4 changed files with 33 additions and 46 deletions

View File

@@ -88,7 +88,7 @@ static struct wcd_mbhc_register
WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT", WCD_MBHC_REGISTER("WCD_MBHC_ELECT_RESULT",
ROULEUR_ANA_MBHC_RESULT_3, 0xFF, 0, 0), ROULEUR_ANA_MBHC_RESULT_3, 0xFF, 0, 0),
WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL", WCD_MBHC_REGISTER("WCD_MBHC_MICB_CTRL",
ROULEUR_ANA_MICBIAS_MICB_1_2_EN, 0x04, 2, 0), ROULEUR_ANA_MICBIAS_MICB_1_2_EN, 0x06, 1, 0),
WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME", WCD_MBHC_REGISTER("WCD_MBHC_HPH_CNP_WG_TIME",
SND_SOC_NOPM, 0x00, 0, 0), SND_SOC_NOPM, 0x00, 0, 0),
WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN", WCD_MBHC_REGISTER("WCD_MBHC_HPHR_PA_EN",

View File

@@ -45,6 +45,8 @@ static const struct reg_default rouleur_defaults[] = {
{ ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x2B }, { ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x2B },
{ ROULEUR_ANA_HPHPA_PA_STATUS, 0x00 }, { ROULEUR_ANA_HPHPA_PA_STATUS, 0x00 },
{ ROULEUR_ANA_HPHPA_FSM_CLK, 0x12 }, { ROULEUR_ANA_HPHPA_FSM_CLK, 0x12 },
{ ROULEUR_ANA_HPHPA_L_GAIN, 0x00 },
{ ROULEUR_ANA_HPHPA_R_GAIN, 0x00 },
{ ROULEUR_SWR_HPHPA_HD2, 0x1B }, { ROULEUR_SWR_HPHPA_HD2, 0x1B },
{ ROULEUR_ANA_HPHPA_SPARE_CTL, 0x02 }, { ROULEUR_ANA_HPHPA_SPARE_CTL, 0x02 },
{ ROULEUR_ANA_SURGE_EN, 0x38 }, { ROULEUR_ANA_SURGE_EN, 0x38 },

View File

@@ -40,6 +40,8 @@ const u8 rouleur_reg_access_analog[ROULEUR_REG(
[ROULEUR_REG(ROULEUR_ANA_HPHPA_CNP_CTL_2)] = RD_WR_REG, [ROULEUR_REG(ROULEUR_ANA_HPHPA_CNP_CTL_2)] = RD_WR_REG,
[ROULEUR_REG(ROULEUR_ANA_HPHPA_PA_STATUS)] = RD_REG, [ROULEUR_REG(ROULEUR_ANA_HPHPA_PA_STATUS)] = RD_REG,
[ROULEUR_REG(ROULEUR_ANA_HPHPA_FSM_CLK)] = RD_WR_REG, [ROULEUR_REG(ROULEUR_ANA_HPHPA_FSM_CLK)] = RD_WR_REG,
[ROULEUR_REG(ROULEUR_ANA_HPHPA_L_GAIN)] = RD_WR_REG,
[ROULEUR_REG(ROULEUR_ANA_HPHPA_R_GAIN)] = RD_WR_REG,
[ROULEUR_REG(ROULEUR_ANA_HPHPA_SPARE_CTL)] = RD_WR_REG, [ROULEUR_REG(ROULEUR_ANA_HPHPA_SPARE_CTL)] = RD_WR_REG,
[ROULEUR_REG(ROULEUR_SWR_HPHPA_HD2)] = RD_WR_REG, [ROULEUR_REG(ROULEUR_SWR_HPHPA_HD2)] = RD_WR_REG,
[ROULEUR_REG(ROULEUR_ANA_SURGE_EN)] = RD_WR_REG, [ROULEUR_REG(ROULEUR_ANA_SURGE_EN)] = RD_WR_REG,

View File

@@ -475,14 +475,8 @@ static int rouleur_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
0x04, 0x04); 0x04, 0x04);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x01, 0x01); ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x01, 0x01);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x03);
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
0x01, 0x00); 0x01, 0x00);
@@ -546,14 +540,8 @@ static int rouleur_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
0x08, 0x08); 0x08, 0x08);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x02); ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x02);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL1,
0x03, 0x03);
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL1,
0x03, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x00); ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, 0x02, 0x00);
break; break;
@@ -582,18 +570,12 @@ static int rouleur_codec_ear_lo_dac_event(struct snd_soc_dapm_widget *w,
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
0x01, 0x01); 0x01, 0x01);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x03);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL, ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL,
0x04, 0x04); 0x04, 0x04);
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_CDC_RX_CLK_CTL, ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,
0x01, 0x00); 0x01, 0x00);
@@ -622,14 +604,11 @@ static int rouleur_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
rouleur->rx_swr_dev->dev_num, rouleur->rx_swr_dev->dev_num,
true); true);
snd_soc_component_update_bits(component,
ROULEUR_ANA_HPHPA_CNP_CTL_2,
0x40, 0x40);
set_bit(HPH_PA_DELAY, &rouleur->status_mask); set_bit(HPH_PA_DELAY, &rouleur->status_mask);
/* TODO: WHY SECOND TIME */ usleep_range(5000, 5100);
ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev, snd_soc_component_update_bits(component,
rouleur->rx_swr_dev->dev_num, ROULEUR_DIG_SWR_PDM_WD_CTL1,
true); 0x03, 0x03);
break; break;
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
/* /*
@@ -676,8 +655,8 @@ static int rouleur_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
WCD_EVENT_POST_HPHR_PA_OFF, WCD_EVENT_POST_HPHR_PA_OFF,
&rouleur->mbhc->wcd_mbhc); &rouleur->mbhc->wcd_mbhc);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_ANA_HPHPA_CNP_CTL_2, ROULEUR_DIG_SWR_PDM_WD_CTL1,
0x40, 0x00); 0x03, 0x00);
break; break;
}; };
return ret; return ret;
@@ -700,10 +679,11 @@ static int rouleur_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev, ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
rouleur->rx_swr_dev->dev_num, rouleur->rx_swr_dev->dev_num,
true); true);
snd_soc_component_update_bits(component,
ROULEUR_ANA_HPHPA_CNP_CTL_2,
0x80, 0x80);
set_bit(HPH_PA_DELAY, &rouleur->status_mask); set_bit(HPH_PA_DELAY, &rouleur->status_mask);
usleep_range(5000, 5100);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x03);
break; break;
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
/* /*
@@ -748,8 +728,8 @@ static int rouleur_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
WCD_EVENT_POST_HPHL_PA_OFF, WCD_EVENT_POST_HPHL_PA_OFF,
&rouleur->mbhc->wcd_mbhc); &rouleur->mbhc->wcd_mbhc);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_ANA_HPHPA_CNP_CTL_2, ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x80, 0x00); 0x03, 0x00);
break; break;
}; };
@@ -773,10 +753,10 @@ static int rouleur_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev, ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
rouleur->rx_swr_dev->dev_num, rouleur->rx_swr_dev->dev_num,
true); true);
snd_soc_component_update_bits(component,
ROULEUR_ANA_COMBOPA_CTL,
0x80, 0x80);
usleep_range(5000, 5100); usleep_range(5000, 5100);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x03);
break; break;
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
if (rouleur->update_wcd_event) if (rouleur->update_wcd_event)
@@ -795,10 +775,10 @@ static int rouleur_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
(WCD_RX1 << 0x10 | 0x1)); (WCD_RX1 << 0x10 | 0x1));
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
ROULEUR_ANA_COMBOPA_CTL,
0x80, 0x00);
usleep_range(5000, 5100); usleep_range(5000, 5100);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x00);
}; };
return ret; return ret;
} }
@@ -823,10 +803,10 @@ static int rouleur_codec_enable_lo_pa(struct snd_soc_dapm_widget *w,
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_ANA_COMBOPA_CTL, ROULEUR_ANA_COMBOPA_CTL,
0x40, 0x40); 0x40, 0x40);
snd_soc_component_update_bits(component,
ROULEUR_ANA_COMBOPA_CTL,
0x80, 0x80);
usleep_range(5000, 5100); usleep_range(5000, 5100);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x03);
break; break;
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
if (rouleur->update_wcd_event) if (rouleur->update_wcd_event)
@@ -845,13 +825,13 @@ static int rouleur_codec_enable_lo_pa(struct snd_soc_dapm_widget *w,
(WCD_RX1 << 0x10 | 0x1)); (WCD_RX1 << 0x10 | 0x1));
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
ROULEUR_ANA_COMBOPA_CTL,
0x80, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
ROULEUR_ANA_COMBOPA_CTL, ROULEUR_ANA_COMBOPA_CTL,
0x40, 0x00); 0x40, 0x00);
usleep_range(5000, 5100); usleep_range(5000, 5100);
snd_soc_component_update_bits(component,
ROULEUR_DIG_SWR_PDM_WD_CTL0,
0x03, 0x00);
}; };
return ret; return ret;
} }
@@ -1552,6 +1532,9 @@ static int rouleur_codec_enable_pa_vpos(struct snd_soc_dapm_widget *w,
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
set_bit(ALLOW_VPOS_DISABLE, &rouleur->status_mask); set_bit(ALLOW_VPOS_DISABLE, &rouleur->status_mask);
ret = swr_slvdev_datapath_control(rouleur->rx_swr_dev,
rouleur->rx_swr_dev->dev_num,
false);
break; break;
} }
return 0; return 0;
@@ -1822,7 +1805,7 @@ static ssize_t rouleur_version_read(struct snd_info_entry *entry,
switch (priv->version) { switch (priv->version) {
case ROULEUR_VERSION_1_0: case ROULEUR_VERSION_1_0:
len = snprintf(buffer, sizeof(buffer), "rouleur_1_0\n"); len = snprintf(buffer, sizeof(buffer), "ROULEUR_1_0\n");
break; break;
default: default:
len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");