Jelajahi Sumber

disp: msm: fix WD timer load value calculation

Fix the Watchdog timer load value calculation with jitter feature.
Change the long term jitter value check to have jitter < 10.

Change-Id: If834e16d3b8fad5009642e479f529fa5b7cf2d17
Signed-off-by: Veera Sundaram Sankaran <[email protected]>
Veera Sundaram Sankaran 3 tahun lalu
induk
melakukan
9f41310155
2 mengubah file dengan 3 tambahan dan 6 penghapusan
  1. 2 2
      msm/dsi/dsi_panel.c
  2. 1 4
      msm/sde/sde_hw_intf.c

+ 2 - 2
msm/dsi/dsi_panel.c

@@ -2210,7 +2210,7 @@ static int dsi_panel_parse_wd_jitter_config(struct dsi_display_mode_priv_info *p
 	struct msm_display_wd_jitter_config *wd_jitter = &priv_info->wd_jitter;
 	u32 ltj[DEFAULT_PANEL_JITTER_ARRAY_SIZE] = {0, 1};
 	u32 ltj_time = 0;
-	const u32 min_ltj = 10;
+	const u32 max_ltj = 10;
 
 	if (!(utils->read_bool(utils->data, "qcom,dsi-wd-jitter-enable"))) {
 		priv_info->panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR;
@@ -2221,7 +2221,7 @@ static int dsi_panel_parse_wd_jitter_config(struct dsi_display_mode_priv_info *p
 	rc = utils->read_u32_array(utils->data, "qcom,dsi-wd-ltj-max-jitter", ltj,
 			DEFAULT_PANEL_JITTER_ARRAY_SIZE);
 	rc |= utils->read_u32(utils->data, "qcom,dsi-wd-ltj-time-sec", &ltj_time);
-	if (rc || !ltj[1] || !ltj_time || (ltj[0] / ltj[1] < min_ltj)) {
+	if (rc || !ltj[1] || !ltj_time || (ltj[0] / ltj[1] >= max_ltj)) {
 		DSI_DEBUG("No valid long term jitter defined\n");
 		priv_info->panel_jitter_numer = DEFAULT_PANEL_JITTER_NUMERATOR;
 		priv_info->panel_jitter_denom = DEFAULT_PANEL_JITTER_DENOMINATOR;

+ 1 - 4
msm/sde/sde_hw_intf.c

@@ -501,13 +501,10 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf, u32 frame_r
 	c = &intf->hw;
 
 	reg = CALCULATE_WD_LOAD_VALUE(frame_rate);
-	if (intf->cap->features & BIT(SDE_INTF_WD_JITTER))
-		reg *= MDP_TICK_COUNT;
-
 	SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, reg);
 
 	SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */
-	reg |= BIT(8); /* enable heartbeat timer */
+	reg = BIT(8); /* enable heartbeat timer */
 	reg |= BIT(0); /* enable WD timer */
 	reg |= BIT(1); /* select default 16 clock ticks */
 	SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL2, reg);