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disp: msm: sde: reset dsc mux config in encoder disable

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During display encoder disable, reset the dsc control
mux configuration during null commit to ensure dsc hw
blocks are cleanly freed up.

Change-Id: I02e2f074450e4d7b49dc8fec14777f380786c63e
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This commit is contained in:
Prabhanjan Kandula
2021-10-05 19:40:20 -07:00
parent 7db951ec69
commit 9e988121fc
1 changed files with 12 additions and 0 deletions
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12
msm/sde/sde_encoder.c
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@@ -3172,6 +3172,7 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
struct sde_encoder_virt *sde_enc;
struct sde_hw_ctl *ctl = phys_enc->hw_ctl;
struct sde_ctl_flush_cfg cfg;
struct sde_hw_dsc *hw_dsc = NULL;
int i;
ctl->ops.reset(ctl);
@@ -3226,6 +3227,17 @@ void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
phys_enc->hw_pp->merge_3d ?
phys_enc->hw_pp->merge_3d->idx : 0);
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
hw_dsc = sde_enc->hw_dsc[i];
if (hw_dsc && hw_dsc->ops.bind_pingpong_blk) {
hw_dsc->ops.bind_pingpong_blk(hw_dsc, false, PINGPONG_MAX);
if (ctl->ops.update_bitmask)
ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_DSC, hw_dsc->idx, true);
}
}
sde_crtc_disable_cp_features(sde_enc->base.crtc);
ctl->ops.get_pending_flush(ctl, &cfg);
SDE_EVT32(DRMID(phys_enc->parent), cfg.pending_flush_mask);