qcacmn: HIF layer changes for QCN9100 bringup

Initial changes made for bring up of
QCN9100 in HIF layer

Change-Id: I60c5f7e8d5456e6f2bfda8f99d873a30ca979ada

hif/inc/hif.h

@@ -68,6 +68,7 @@ typedef void *hif_handle_t;
 #define HIF_TYPE_QCA6490 22
 #define HIF_TYPE_QCA6750 23
 #define HIF_TYPE_QCA5018 24
+#define HIF_TYPE_QCN9100 25
 
 #define DMA_COHERENT_MASK_DEFAULT   37
 

hif/inc/hostdef.h

@@ -46,4 +46,5 @@ extern struct hostdef_s *QCA8074V2_HOSTDEF;
 extern struct hostdef_s *QCA6018_HOSTDEF;
 extern struct hostdef_s *QCA5018_HOSTDEF;
 extern struct hostdef_s *QCN9000_HOSTDEF;
+extern struct hostdef_s *QCN9100_HOSTDEF;
 #endif

hif/inc/target_type.h

@@ -66,6 +66,9 @@ extern "C" {
 #define TARGET_TYPE_QCA5018   29
 #endif
 
+#ifndef TARGET_TYPE_QCN9100
+#define TARGET_TYPE_QCN9100   30
+#endif
 
 #ifdef __cplusplus
 }

hif/inc/targetdef.h

@@ -46,6 +46,7 @@ extern struct targetdef_s *QCA8074V2_TARGETDEF;
 extern struct targetdef_s *QCA6018_TARGETDEF;
 extern struct targetdef_s *QCA5018_TARGETDEF;
 extern struct targetdef_s *QCN9000_TARGETDEF;
+extern struct targetdef_s *QCN9100_TARGETDEF;
 
 extern struct ce_reg_def *AR6002_CE_TARGETdef;
 extern struct ce_reg_def *AR6003_CE_TARGETdef;
@@ -68,6 +69,7 @@ extern struct ce_reg_def *QCA8074V2_CE_TARGETDEF;
 extern struct ce_reg_def *QCA6018_CE_TARGETDEF;
 extern struct ce_reg_def *QCA5018_CE_TARGETDEF;
 extern struct ce_reg_def *QCN9000_CE_TARGETDEF;
+extern struct ce_reg_def *QCN9100_CE_TARGETDEF;
 
 
 #endif

hif/src/ath_procfs.c

@@ -87,6 +87,7 @@ static ssize_t ath_procfs_diag_read(struct file *file, char __user *buf,
 	     (tgt_info->target_type == TARGET_TYPE_QCA8074) ||
 	     (tgt_info->target_type == TARGET_TYPE_QCA8074V2) ||
 	     (tgt_info->target_type == TARGET_TYPE_QCN9000) ||
+	     (tgt_info->target_type == TARGET_TYPE_QCN9100) ||
 	     (tgt_info->target_type == TARGET_TYPE_QCA5018) ||
 	     (tgt_info->target_type == TARGET_TYPE_QCA6018) ||
 	     (tgt_info->target_type == TARGET_TYPE_QCN7605))) ||
@@ -170,6 +171,7 @@ static ssize_t ath_procfs_diag_write(struct file *file,
 	      (tgt_info->target_type == TARGET_TYPE_QCA8074) ||
 	      (tgt_info->target_type == TARGET_TYPE_QCA8074V2) ||
 	      (tgt_info->target_type == TARGET_TYPE_QCN9000) ||
+	      (tgt_info->target_type == TARGET_TYPE_QCN9100) ||
 	      (tgt_info->target_type == TARGET_TYPE_QCA5018) ||
 	      (tgt_info->target_type == TARGET_TYPE_QCA6018) ||
 	      (tgt_info->target_type == TARGET_TYPE_QCN7605))) ||

hif/src/ce/ce_assignment.h

@@ -931,6 +931,57 @@ static struct CE_pipe_config target_ce_config_wlan_adrastea[] = {
 	{ /* CE11 */ 11, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
 };
 
+#define QCN_9100_CE_COUNT 6
+static struct CE_attr host_ce_config_wlan_qcn9100[] = {
+	/* host->target HTC control and raw streams */
+	{/*CE0*/ (EPPING_CE_FLAGS_POLL), 0, 16, 2048, 0, NULL,},
+	/* target->host HTT + HTC control */
+	{/*CE1*/ (EPPING_CE_FLAGS_POLL), 0, 0,  2048,
+		512, NULL,},
+	/* target->host WMI */
+	{/*CE2*/ (EPPING_CE_FLAGS_POLL), 0, 0,  2048,
+		128, NULL,},
+	/* host->target WMI */
+	{/*CE3*/ (EPPING_CE_FLAGS_POLL), 0, 32, 2048, 0, NULL,},
+	/* host->target HTT */
+	{/*CE4*/ (EPPING_CE_FLAGS_POLL), 0,
+		CE_HTT_H2T_MSG_SRC_NENTRIES, 256, 0, NULL,},
+	/* target -> host PKTLOG */
+	{/*CE5*/ (EPPING_CE_FLAGS_POLL), 0, 0, 2048,
+		512, NULL,},
+	/* Target autonomous HIF_memcpy */
+	{/*CE6*/ EPPING_CE_FLAGS_POLL, 0, 0, 0, 0, NULL,},
+	/* host->target WMI (mac1) */
+	{/*CE7*/ EPPING_CE_FLAGS_POLL, 0, 0, 0, 0, NULL,},
+	/* Reserved for target */
+	{/*CE8*/ EPPING_CE_FLAGS_POLL, 0, 0, 0, 0, NULL,},
+	/* CE 9, 10, 11 belong to CoreBsp & MHI driver */
+};
+
+static struct CE_pipe_config target_ce_config_wlan_qcn9100[] = {
+	/* host->target HTC control and raw streams */
+	{ /* CE0 */ 0, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
+	/* target->host HTT */
+	{ /* CE1 */ 1, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
+	/* target->host WMI  + HTC control */
+	{ /* CE2 */ 2, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
+	/* host->target WMI */
+	{ /* CE3 */ 3, PIPEDIR_OUT, 32, 2048, CE_ATTR_FLAGS, 0,},
+	/* host->target HTT */
+	{ /* CE4 */ 4, PIPEDIR_OUT, 256, 256,
+		(CE_ATTR_FLAGS | CE_ATTR_DISABLE_INTR), 0,},
+	/* Target -> host PKTLOG */
+	{ /* CE5 */ 5, PIPEDIR_IN,  32, 2048, CE_ATTR_FLAGS, 0,},
+	/* Reserved for target autonomous HIF_memcpy */
+	{ /* CE6 */ 6, PIPEDIR_INOUT, 32, 16384, CE_ATTR_FLAGS, 0,},
+	/* CE7 used only by Host */
+	{ /* CE7 */ 7, PIPEDIR_OUT, 32, 2048,
+		8192, 0,},
+	/* Reserved for target */
+	{ /* CE8 */ 8, PIPEDIR_INOUT, 32, 16384, CE_ATTR_FLAGS, 0,},
+	/* CE 9, 10, 11 belong to CoreBsp & MHI driver */
+};
+
 #define QCA_5018_CE_COUNT 6
 static struct CE_attr host_ce_config_wlan_qca5018[] = {
 	/* host->target HTC control and raw streams */

hif/src/ce/ce_main.c

@@ -912,6 +912,7 @@ static void hif_select_service_to_pipe_map(struct hif_softc *scn,
 				sizeof(target_service_to_ce_map_qcn9000);
 			break;
 		case TARGET_TYPE_QCA5018:
+		case TARGET_TYPE_QCN9100:
 			*tgt_svc_map_to_use =
 				target_service_to_ce_map_qca5018;
 			*sz_tgt_svc_map_to_use =
@@ -1128,6 +1129,7 @@ bool ce_srng_based(struct hif_softc *scn)
 	case TARGET_TYPE_QCA6750:
 	case TARGET_TYPE_QCA6018:
 	case TARGET_TYPE_QCN9000:
+	case TARGET_TYPE_QCN9100:
 	case TARGET_TYPE_QCA5018:
 		return true;
 	default:
@@ -3271,6 +3273,13 @@ void hif_ce_prepare_config(struct hif_softc *scn)
 		scn->ce_count = QCN_9000_CE_COUNT;
 		scn->disable_wake_irq = 1;
 		break;
+	case TARGET_TYPE_QCN9100:
+		hif_state->host_ce_config = host_ce_config_wlan_qcn9100;
+		hif_state->target_ce_config = target_ce_config_wlan_qcn9100;
+		hif_state->target_ce_config_sz =
+					sizeof(target_ce_config_wlan_qcn9100);
+		scn->ce_count = QCN_9100_CE_COUNT;
+		break;
 	case TARGET_TYPE_QCA5018:
 		hif_state->host_ce_config = host_ce_config_wlan_qca5018;
 		hif_state->target_ce_config = target_ce_config_wlan_qca5018;

hif/src/hif_main.c

@@ -1155,6 +1155,12 @@ int hif_get_device_type(uint32_t device_id,
 		HIF_INFO(" *********** QCN9000 *************\n");
 		break;
 
+	case QCN9100_DEVICE_ID:
+		*hif_type = HIF_TYPE_QCN9100;
+		*target_type = TARGET_TYPE_QCN9100;
+		HIF_INFO(" *********** QCN9100 *************\n");
+		break;
+
 	case QCN7605_DEVICE_ID:
 	case QCN7605_COMPOSITE:
 	case QCN7605_STANDALONE:

hif/src/hif_main.h

@@ -89,6 +89,7 @@
 #define QCA6290_EMULATION_DEVICE_ID (0xabcd)
 #define QCA6290_DEVICE_ID (0x1100)
 #define QCN9000_DEVICE_ID (0x1104)
+#define QCN9100_DEVICE_ID (0xFFFB)
 #define QCA6390_EMULATION_DEVICE_ID (0x0108)
 #define QCA6390_DEVICE_ID (0x1101)
 /* TODO: change IDs for HastingsPrime */

hif/src/pcie/if_pci.c

@@ -1729,6 +1729,7 @@ int hif_pci_bus_configure(struct hif_softc *hif_sc)
 	if (((hif_sc->target_info.target_type == TARGET_TYPE_QCA8074) ||
 	     (hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2) ||
 	     (hif_sc->target_info.target_type == TARGET_TYPE_QCA5018) ||
+	     (hif_sc->target_info.target_type == TARGET_TYPE_QCN9100) ||
 	     (hif_sc->target_info.target_type == TARGET_TYPE_QCA6018)) &&
 	    (hif_sc->bus_type == QDF_BUS_TYPE_AHB)) {
 		hif_sc->per_ce_irq = true;
@@ -1750,6 +1751,7 @@ int hif_pci_bus_configure(struct hif_softc *hif_sc)
 	if (((hif_sc->target_info.target_type == TARGET_TYPE_QCA8074) ||
 	     (hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2) ||
 	     (hif_sc->target_info.target_type == TARGET_TYPE_QCA5018) ||
+	     (hif_sc->target_info.target_type == TARGET_TYPE_QCN9100) ||
 	     (hif_sc->target_info.target_type == TARGET_TYPE_QCA6018)) &&
 	    (hif_sc->bus_type == QDF_BUS_TYPE_PCI))
 		HIF_INFO_MED("%s: Skip irq config for PCI based 8074 target",

hif/src/qcn9100def.c

@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "qdf_module.h"
+
+#if defined(QCN9100_HEADERS_DEF)
+
+#undef UMAC
+#define WLAN_HEADERS 1
+
+#include "wcss_version.h"
+#include "wcss_seq_hwiobase.h"
+#include "wfss_ce_reg_seq_hwioreg.h"
+
+#define MISSING 0
+
+#define SOC_RESET_CONTROL_OFFSET MISSING
+#define GPIO_PIN0_OFFSET                        MISSING
+#define GPIO_PIN1_OFFSET                        MISSING
+#define GPIO_PIN0_CONFIG_MASK                   MISSING
+#define GPIO_PIN1_CONFIG_MASK                   MISSING
+#define LOCAL_SCRATCH_OFFSET 0x18
+#define GPIO_PIN10_OFFSET MISSING
+#define GPIO_PIN11_OFFSET MISSING
+#define GPIO_PIN12_OFFSET MISSING
+#define GPIO_PIN13_OFFSET MISSING
+#define MBOX_BASE_ADDRESS MISSING
+#define INT_STATUS_ENABLE_ERROR_LSB MISSING
+#define INT_STATUS_ENABLE_ERROR_MASK MISSING
+#define INT_STATUS_ENABLE_CPU_LSB MISSING
+#define INT_STATUS_ENABLE_CPU_MASK MISSING
+#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
+#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
+#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
+#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
+#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
+#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
+#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
+#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
+#define INT_STATUS_ENABLE_ADDRESS MISSING
+#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
+#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
+#define HOST_INT_STATUS_ADDRESS MISSING
+#define CPU_INT_STATUS_ADDRESS MISSING
+#define ERROR_INT_STATUS_ADDRESS MISSING
+#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
+#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
+#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
+#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
+#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
+#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
+#define COUNT_DEC_ADDRESS MISSING
+#define HOST_INT_STATUS_CPU_MASK MISSING
+#define HOST_INT_STATUS_CPU_LSB MISSING
+#define HOST_INT_STATUS_ERROR_MASK MISSING
+#define HOST_INT_STATUS_ERROR_LSB MISSING
+#define HOST_INT_STATUS_COUNTER_MASK MISSING
+#define HOST_INT_STATUS_COUNTER_LSB MISSING
+#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
+#define WINDOW_DATA_ADDRESS MISSING
+#define WINDOW_READ_ADDR_ADDRESS MISSING
+#define WINDOW_WRITE_ADDR_ADDRESS MISSING
+/* GPIO Register */
+#define GPIO_ENABLE_W1TS_LOW_ADDRESS            MISSING
+#define GPIO_PIN0_CONFIG_LSB                    MISSING
+#define GPIO_PIN0_PAD_PULL_LSB                  MISSING
+#define GPIO_PIN0_PAD_PULL_MASK                 MISSING
+/* SI reg */
+#define SI_CONFIG_ERR_INT_MASK                  MISSING
+#define SI_CONFIG_ERR_INT_LSB                   MISSING
+
+#define RTC_SOC_BASE_ADDRESS MISSING
+#define RTC_WMAC_BASE_ADDRESS MISSING
+#define SOC_CORE_BASE_ADDRESS MISSING
+#define WLAN_MAC_BASE_ADDRESS MISSING
+#define GPIO_BASE_ADDRESS MISSING
+#define ANALOG_INTF_BASE_ADDRESS MISSING
+#define CE0_BASE_ADDRESS MISSING
+#define CE1_BASE_ADDRESS MISSING
+#define CE_COUNT 12
+#define CE_WRAPPER_BASE_ADDRESS MISSING
+#define SI_BASE_ADDRESS MISSING
+#define DRAM_BASE_ADDRESS MISSING
+
+#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
+#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
+#define CLOCK_CONTROL_OFFSET MISSING
+#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
+#define RESET_CONTROL_SI0_RST_MASK MISSING
+#define WLAN_RESET_CONTROL_OFFSET MISSING
+#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
+#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
+#define CPU_CLOCK_OFFSET MISSING
+
+#define CPU_CLOCK_STANDARD_LSB MISSING
+#define CPU_CLOCK_STANDARD_MASK MISSING
+#define LPO_CAL_ENABLE_LSB MISSING
+#define LPO_CAL_ENABLE_MASK MISSING
+#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
+
+#define SOC_CHIP_ID_ADDRESS	  MISSING
+#define SOC_CHIP_ID_REVISION_MASK MISSING
+#define SOC_CHIP_ID_REVISION_LSB  MISSING
+#define SOC_CHIP_ID_REVISION_MSB  MISSING
+
+#define FW_IND_EVENT_PENDING MISSING
+#define FW_IND_INITIALIZED MISSING
+
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
+#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB  MISSING
+#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB  MISSING
+
+#define SR_WR_INDEX_ADDRESS MISSING
+#define DST_WATERMARK_ADDRESS MISSING
+
+#define DST_WR_INDEX_ADDRESS MISSING
+#define SRC_WATERMARK_ADDRESS MISSING
+#define SRC_WATERMARK_LOW_MASK MISSING
+#define SRC_WATERMARK_HIGH_MASK MISSING
+#define DST_WATERMARK_LOW_MASK MISSING
+#define DST_WATERMARK_HIGH_MASK MISSING
+#define CURRENT_SRRI_ADDRESS MISSING
+#define CURRENT_DRRI_ADDRESS MISSING
+#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
+#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
+#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
+#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
+#define HOST_IS_ADDRESS MISSING
+#define MISC_IS_ADDRESS MISSING
+#define HOST_IS_COPY_COMPLETE_MASK MISSING
+#define CE_WRAPPER_BASE_ADDRESS MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
+#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
+#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
+#undef WFSS_CE_COMMON_REG_REG_BASE
+#define WFSS_CE_COMMON_REG_REG_BASE 0x1B80000
+
+#define HOST_IE_ADDRESS \
+	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET)
+#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
+#define HOST_IE_ADDRESS_2 \
+	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET)
+#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
+#define HOST_IE_ADDRESS_3 \
+	HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
+		SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET)
+#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
+
+#define HOST_CE_ADDRESS SOC_WFSS_CE_REG_BASE
+
+#define HOST_IE_COPY_COMPLETE_MASK MISSING
+#define SR_BA_ADDRESS MISSING
+#define SR_BA_ADDRESS_HIGH MISSING
+#define SR_SIZE_ADDRESS MISSING
+#define CE_CTRL1_ADDRESS MISSING
+#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
+#define DR_BA_ADDRESS MISSING
+#define DR_BA_ADDRESS_HIGH MISSING
+#define DR_SIZE_ADDRESS MISSING
+#define CE_CMD_REGISTER MISSING
+#define CE_MSI_ADDRESS MISSING
+#define CE_MSI_ADDRESS_HIGH MISSING
+#define CE_MSI_DATA MISSING
+#define CE_MSI_ENABLE_BIT MISSING
+#define MISC_IE_ADDRESS MISSING
+#define MISC_IS_AXI_ERR_MASK MISSING
+#define MISC_IS_DST_ADDR_ERR_MASK MISSING
+#define MISC_IS_SRC_LEN_ERR_MASK MISSING
+#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
+#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
+#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
+#define SRC_WATERMARK_LOW_LSB MISSING
+#define SRC_WATERMARK_HIGH_LSB MISSING
+#define DST_WATERMARK_LOW_LSB MISSING
+#define DST_WATERMARK_HIGH_LSB MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
+#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
+#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
+#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
+#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
+#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
+#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
+#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
+#define CE_WRAPPER_DEBUG_OFFSET MISSING
+#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
+#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
+#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
+#define CE_DEBUG_OFFSET MISSING
+#define CE_DEBUG_SEL_MSB MISSING
+#define CE_DEBUG_SEL_LSB MISSING
+#define CE_DEBUG_SEL_MASK MISSING
+#define CE0_BASE_ADDRESS MISSING
+#define CE1_BASE_ADDRESS MISSING
+#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
+#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
+
+#define QCN9100_BOARD_DATA_SZ MISSING
+#define QCN9100_BOARD_EXT_DATA_SZ MISSING
+
+#define MY_TARGET_DEF QCN9100_TARGETDEF
+#define MY_HOST_DEF QCN9100_HOSTDEF
+#define MY_CEREG_DEF QCN9100_CE_TARGETDEF
+#define MY_TARGET_BOARD_DATA_SZ QCN9100_BOARD_DATA_SZ
+#define MY_TARGET_BOARD_EXT_DATA_SZ QCN9100_BOARD_EXT_DATA_SZ
+#include "targetdef.h"
+#include "hostdef.h"
+qdf_export_symbol(QCN9100_CE_TARGETDEF);
+#else
+#include "common_drv.h"
+#include "targetdef.h"
+#include "hostdef.h"
+struct targetdef_s *QCN9100_TARGETDEF;
+struct hostdef_s *QCN9100_HOSTDEF;
+#endif /*QCN9100_HEADERS_DEF */
+qdf_export_symbol(QCN9100_TARGETDEF);
+qdf_export_symbol(QCN9100_HOSTDEF);

hif/src/regtable.c

@@ -134,6 +134,14 @@ void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
 		break;
 #endif
 
+#if defined(QCN9100_HEADERS_DEF)
+	case TARGET_TYPE_QCN9100:
+		scn->targetdef = QCN9100_TARGETDEF;
+		scn->target_ce_def = QCN9100_CE_TARGETDEF;
+		HIF_TRACE("%s: TARGET_TYPE_QCN9100", __func__);
+		break;
+#endif
+
 #if defined(QCA5018_HEADERS_DEF)
 	case TARGET_TYPE_QCA5018:
 		scn->targetdef = QCA5018_TARGETDEF;
@@ -258,6 +266,11 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
 		scn->hostdef = QCN9000_HOSTDEF;
 		break;
 #endif
+#if defined(QCN9100_HEADERS_DEF)
+	case HIF_TYPE_QCN9100:
+		scn->hostdef = QCN9100_HOSTDEF;
+		break;
+#endif
 #if defined(QCA5018_HEADERS_DEF)
 	case HIF_TYPE_QCA5018:
 		scn->hostdef = QCA5018_HOSTDEF;

hif/src/snoc/if_ahb.c

@@ -257,6 +257,18 @@ end:
 	return ret;
 }
 
+static void hif_ahb_get_soc_info_pld(struct hif_pci_softc *sc,
+				     struct device *dev)
+{
+	struct pld_soc_info info;
+	int ret = 0;
+
+	ret = pld_get_soc_info(dev, &info);
+	sc->mem = info.v_addr;
+	sc->ce_sc.ol_sc.mem    = info.v_addr;
+	sc->ce_sc.ol_sc.mem_pa = info.p_addr;
+}
+
 int hif_ahb_configure_irq(struct hif_pci_softc *sc)
 {
 	int ret = 0;
@@ -490,6 +502,7 @@ void hif_ahb_disable_bus(struct hif_softc *scn)
 		if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
 		    (tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
 		    (tgt_info->target_type != TARGET_TYPE_QCA5018) &&
+		    (tgt_info->target_type != TARGET_TYPE_QCN9100) &&
 		    (tgt_info->target_type != TARGET_TYPE_QCA6018)) {
 			hif_ahb_clk_enable_disable(&pdev->dev, 0);
 
@@ -553,18 +566,46 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
 		return QDF_STATUS_E_FAILURE;
 	}
 
-	status = pfrm_platform_get_resource(&pdev->dev,
-					    (struct qdf_pfm_hndl *)pdev,
-					    &vmres,
-					    IORESOURCE_MEM, 0);
-	if (QDF_IS_STATUS_ERROR(status)) {
-		HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__);
-		return status;
-	}
-	memres = (struct resource *)vmres;
-	if (!memres) {
-		HIF_INFO("%s: Failed to get IORESOURCE_MEM\n", __func__);
-		return QDF_STATUS_E_IO;
+	if (target_type == TARGET_TYPE_QCN9100) {
+		hif_ahb_get_soc_info_pld(sc, dev);
+	} else {
+		status = pfrm_platform_get_resource(&pdev->dev,
+						    (struct qdf_pfm_hndl *)pdev,
+						    &vmres,
+						    IORESOURCE_MEM, 0);
+		if (QDF_IS_STATUS_ERROR(status)) {
+			HIF_INFO("%s: Failed to get IORESOURCE_MEM\n",
+				 __func__);
+			return status;
+		}
+		memres = (struct resource *)vmres;
+		if (!memres) {
+			HIF_INFO("%s: Failed to get IORESOURCE_MEM\n",
+				 __func__);
+			return QDF_STATUS_E_IO;
+		}
+
+		/* Arrange for access to Target SoC registers. */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
+		status = pfrm_devm_ioremap_resource(
+					dev,
+					(struct qdf_vbus_resource *)memres,
+					&mem);
+#else
+		status = pfrm_devm_request_and_ioremap(
+					dev,
+					(struct qdf_vbus_resource *)memres,
+					&mem);
+#endif
+		if (QDF_IS_STATUS_ERROR(status)) {
+			HIF_INFO("ath: ioremap error\n");
+			ret = PTR_ERR(mem);
+			goto err_cleanup1;
+		}
+
+		sc->mem = mem;
+		ol_sc->mem = mem;
+		ol_sc->mem_pa = memres->start;
 	}
 
 	ret = pfrm_dma_set_mask(dev, 32);
@@ -581,31 +622,10 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
 #endif
 	if (ret) {
 		HIF_ERROR("%s: failed to set dma mask error = %d",
-				__func__, ret);
+			  __func__, ret);
 		return QDF_STATUS_E_IO;
 	}
 
-	/* Arrange for access to Target SoC registers. */
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
-	status = pfrm_devm_ioremap_resource(dev,
-					    (struct qdf_vbus_resource *)memres,
-					    &mem);
-#else
-	status = pfrm_devm_request_and_ioremap(
-					dev,
-					(struct qdf_vbus_resource *)memres,
-					&mem);
-#endif
-	if (QDF_IS_STATUS_ERROR(status)) {
-		HIF_INFO("ath: ioremap error\n");
-		status = QDF_STATUS_E_IO;
-		goto err_cleanup1;
-	}
-
-	sc->mem = mem;
-	ol_sc->mem = mem;
-	ol_sc->mem_pa = memres->start;
-
 	tgt_info = hif_get_target_info_handle((struct hif_opaque_softc *)ol_sc);
 
 	tgt_info->target_type = target_type;
@@ -629,6 +649,7 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
 	if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
 			(tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
 			(tgt_info->target_type != TARGET_TYPE_QCA5018) &&
+			(tgt_info->target_type != TARGET_TYPE_QCN9100) &&
 			(tgt_info->target_type != TARGET_TYPE_QCA6018)) {
 		if (hif_ahb_enable_radio(sc, pdev, id) != 0) {
 			HIF_INFO("error in enabling soc\n");
@@ -647,6 +668,7 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
 err_target_sync:
 	if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
 	    (tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
+	    (tgt_info->target_type != TARGET_TYPE_QCN9100) &&
 	    (tgt_info->target_type != TARGET_TYPE_QCA5018) &&
 	    (tgt_info->target_type != TARGET_TYPE_QCA6018)) {
 		HIF_INFO("Error: Disabling target\n");