From 9dd2955dc9093d72394ceffb94287056f8aeb47b Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Fri, 19 Nov 2021 14:30:19 +0530 Subject: [PATCH] msm: camera: cpas: Add support for Parrot Camera Parrot has different version of CPAS which requires camnoc interface changes and CPAS version change. This change adds the same. CRs-Fixed: 3081144 Change-Id: Icf39e12d3af8518471b093c860888df05af279b7 Signed-off-by: Alok Pandey --- Android.mk | 9 + Kbuild | 4 + config/{netrani.mk => parrot.mk} | 0 drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 18 + drivers/cam_cpas/cpas_top/cam_cpastop_hw.h | 9 + drivers/cam_cpas/cpas_top/cpastop_v640_200.h | 566 ++++++++++++++++++ drivers/cam_cpas/include/cam_cpas_api.h | 3 + .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 3 +- 8 files changed, 611 insertions(+), 1 deletion(-) rename config/{netrani.mk => parrot.mk} (100%) create mode 100644 drivers/cam_cpas/cpas_top/cpastop_v640_200.h diff --git a/Android.mk b/Android.mk index 090b7607e9..afbd981bfb 100644 --- a/Android.mk +++ b/Android.mk @@ -15,6 +15,10 @@ ifeq ($(TARGET_BOARD_PLATFORM), taro) KBUILD_OPTIONS += KBUILD_EXTRA_SYMBOLS=$(shell pwd)/$(call intermediates-dir-for,DLKM,mmrm-module-symvers)/Module.symvers endif +ifeq ($(TARGET_BOARD_PLATFORM), parrot) + KBUILD_OPTIONS += KBUILD_EXTRA_SYMBOLS=$(shell pwd)/$(call intermediates-dir-for,DLKM,mmrm-module-symvers)/Module.symvers +endif + # Clear shell environment variables from previous android module during build include $(CLEAR_VARS) # For incremental compilation support. @@ -38,6 +42,11 @@ ifeq ($(TARGET_BOARD_PLATFORM), taro) LOCAL_ADDITIONAL_DEPENDENCIES := $(call intermediates-dir-for,DLKM,mmrm-module-symvers)/Module.symvers endif +ifeq ($(TARGET_BOARD_PLATFORM), parrot) + LOCAL_REQUIRED_MODULES := mmrm-module-symvers + LOCAL_ADDITIONAL_DEPENDENCIES := $(call intermediates-dir-for,DLKM,mmrm-module-symvers)/Module.symvers +endif + ifeq ($(TARGET_BOARD_PLATFORM), lahaina) # Include Kernel DLKM Android.mk target to place generated .ko file in image include $(DLKM_DIR)/AndroidKernelModule.mk diff --git a/Kbuild b/Kbuild index ba430332c6..10f9613059 100644 --- a/Kbuild +++ b/Kbuild @@ -46,6 +46,10 @@ ifeq ($(CONFIG_ARCH_CAPE), y) include $(CAMERA_KERNEL_ROOT)/config/cape.mk endif +ifeq ($(CONFIG_ARCH_PARROT), y) +include $(CAMERA_KERNEL_ROOT)/config/parrot.mk +endif + # List of all camera-kernel headers cam_include_dirs := $(shell dirname `find $(CAMERA_KERNEL_ROOT) -name '*.h'` | uniq) diff --git a/config/netrani.mk b/config/parrot.mk similarity index 100% rename from config/netrani.mk rename to config/parrot.mk diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index fcf9f255e3..200f35f48b 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -34,6 +34,7 @@ #include "cpastop_v680_110.h" #include "cpastop_v165_100.h" #include "cpastop_v780_100.h" +#include "cpastop_v640_200.h" #include "cam_req_mgr_workq.h" #include "cam_common_util.h" @@ -164,6 +165,15 @@ static const uint32_t cam_cpas_hw_version_map 0, 0, }, + /* for camera_640 */ + { + 0, + 0, + 0, + 0, + 0, + CAM_CPAS_TITAN_640_V200, + }, }; static int cam_cpas_translate_camera_cpas_version_id( @@ -222,6 +232,9 @@ static int cam_cpas_translate_camera_cpas_version_id( case CAM_CPAS_CAMERA_VERSION_780: *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_780; break; + case CAM_CPAS_CAMERA_VERSION_640: + *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_640; + break; default: CAM_ERR(CAM_CPAS, "Invalid cam version %u", @@ -971,6 +984,11 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, camnoc_info = &cam780_cpas100_camnoc_info; qchannel_info = &cam780_cpas100_qchannel_info; break; + case CAM_CPAS_TITAN_640_V200: + camnoc_info = &cam640_cpas200_camnoc_info; + qchannel_info = &cam640_cpas200_qchannel_info; + break; + default: CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d", hw_caps->camera_version.major, diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h index 0dd6bf3401..56667d8d41 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -188,10 +188,19 @@ enum cam_camnoc_port_type { CAM_CAMNOC_JPEG, CAM_CAMNOC_FD, CAM_CAMNOC_ICP, + CAM_CAMNOC_TFE_BAYER_STATS, + CAM_CAMNOC_TFE_BAYER_STATS_1, + CAM_CAMNOC_TFE_BAYER_STATS_2, + CAM_CAMNOC_TFE_RAW, + CAM_CAMNOC_TFE_RAW_1, + CAM_CAMNOC_TFE_RAW_2, CAM_CAMNOC_TFE, CAM_CAMNOC_TFE_1, CAM_CAMNOC_TFE_2, CAM_CAMNOC_OPE, + CAM_CAMNOC_OPE_BPS_WR, + CAM_CAMNOC_OPE_BPS_CDM_RD, + CAM_CAMNOC_CRE, CAM_CAMNOC_IFE01234_RDI_WRITE, CAM_CAMNOC_IFE01_NRDI_WRITE, CAM_CAMNOC_IFE2_NRDI_WRITE, diff --git a/drivers/cam_cpas/cpas_top/cpastop_v640_200.h b/drivers/cam_cpas/cpas_top/cpastop_v640_200.h new file mode 100644 index 0000000000..fe2cc55317 --- /dev/null +++ b/drivers/cam_cpas/cpas_top/cpastop_v640_200.h @@ -0,0 +1,566 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V640_200_H_ +#define _CPASTOP_V640_200_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v640_200_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6840, /* CAM_NOC_SBM_FAULTINEN0_LOW */ + .value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6848, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x6880, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x5 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v640_200_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = false, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6608, /* CAM_NOC_ERL_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6610, /* CAM_NOC_ERL_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x6618, /* CAM_NOC_ERL_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5DA0, /* WR_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5D90, /* WR_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5D98, /* WR_NIU_ENCERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5F20, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */ + .value = 0xFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5F10, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5F18, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = false, + .sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6888, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6890, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v640_200_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_TFE_BAYER_STATS, + .port_name = "TFE_BAYER", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5830, /*PRIORITYLUT_LOW */ + .value = 0x55554433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5834, /* PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5838, /* URGENCY_LOW */ + .value = 0x00000030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5840, /* DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5848, /* SAFELUT_LOW */ + .value = 0x0000000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4208, /* QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4220, /* QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4224, /* QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x5820, /* UBWC_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_RAW, + .port_name = "TFE_RDI_RAW", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A30, /* PRIORITYLUT_LOW */ + .value = 0x55554433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A34, /* PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A38, /* URGENCY_LOW */ + .value = 0x00000003, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A40, /* DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A48, /* SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4408, /* QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4420, /* QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4424, /* QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x5A20, /* STATS_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_WR, + .port_name = "OPE_BPS_WR", + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C30, /* PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C34, /* PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C38, /* URGENCY_LOW */ + .value = 0x00000030, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C40, /* DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5C48, /* SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4608, /* QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4620, /* QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4624, /* QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x5C20, /* MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_OPE_BPS_CDM_RD, + .port_name = "OPE_BPS_CDM_RD", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E30, /* IPE_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E34, /* IPE_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E38, /* IPE_WR_URGENCY_LOW */ + .value = 0x30, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E40, /* IPE_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E48, /* IPE_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4808, /* IPE_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4820, /* IPE_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4824, /* IPE_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_CRE, + .port_name = "CRE_RD_WR", + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6030, /* BPS_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6034, /* BPS_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6038, /* BPS_WR_URGENCY_LOW */ + .value = 0x03, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6040, /* BPS_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6048, /* BPS_WR_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4A08, /* BPS_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4A20, /* BPS_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4A24, /* BPS_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + .maxwr_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ, + .masked_value = 0, + .offset = 0x6020, /* BPS_WR_MAXWR_LOW */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_ICP, + .port_name = "ICP", + .enable = true, + .flag_out_set0_low = { + .enable = false, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x6888, + .value = 0x100000, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4008, /* ICP_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4020, /* ICP_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4024, /* ICP_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam640_cpas200_err_logger_offsets = { + .mainctrl = 0x6608, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x6610, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x6620, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x6624, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x6628, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x662c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x6630, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x6634, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x6638, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x663c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam640_cpas200_errata_wa_list = { +}; + +static struct cam_camnoc_info cam640_cpas200_camnoc_info = { + .specific = &cam_cpas_v640_200_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v640_200_camnoc_specific), + .irq_sbm = &cam_cpas_v640_200_irq_sbm, + .irq_err = &cam_cpas_v640_200_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v640_200_irq_err), + .err_logger = &cam640_cpas200_err_logger_offsets, + .errata_wa_list = &cam640_cpas200_errata_wa_list, +}; + +static struct cam_cpas_camnoc_qchannel cam640_cpas200_qchannel_info = { + .qchannel_ctrl = 0x5C, + .qchannel_status = 0x60, +}; +#endif /* _CPASTOP_V640_200_H_ */ + diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index 079ef9e865..bf06894a22 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -73,6 +73,7 @@ enum cam_cpas_camera_version { CAM_CPAS_CAMERA_VERSION_680 = 0x00060800, CAM_CPAS_CAMERA_VERSION_165 = 0x00010605, CAM_CPAS_CAMERA_VERSION_780 = 0x00070800, + CAM_CPAS_CAMERA_VERSION_640 = 0x00060400, CAM_CPAS_CAMERA_VERSION_MAX }; @@ -107,6 +108,7 @@ enum cam_cpas_camera_version_map_id { CAM_CPAS_CAMERA_VERSION_ID_680 = 0x9, CAM_CPAS_CAMERA_VERSION_ID_165 = 0xA, CAM_CPAS_CAMERA_VERSION_ID_780 = 0xB, + CAM_CPAS_CAMERA_VERSION_ID_640 = 0xC, CAM_CPAS_CAMERA_VERSION_ID_MAX }; @@ -149,6 +151,7 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_680_V100 = 0x680100, CAM_CPAS_TITAN_680_V110 = 0x680110, CAM_CPAS_TITAN_780_V100 = 0x780100, + CAM_CPAS_TITAN_640_V200 = 0x640200, CAM_CPAS_TITAN_MAX }; diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 021c010824..80161a90d6 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -6547,7 +6547,8 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, (camera_hw_version == CAM_CPAS_TITAN_570_V200) || (camera_hw_version == CAM_CPAS_TITAN_680_V100) || (camera_hw_version == CAM_CPAS_TITAN_680_V110) || - (camera_hw_version == CAM_CPAS_TITAN_780_V100)) { + (camera_hw_version == CAM_CPAS_TITAN_780_V100) || + (camera_hw_version == CAM_CPAS_TITAN_640_V200)) { if (cam_caps & CPAS_TITAN_IPE0_CAP_BIT) icp_hw_mgr.ipe0_enable = true; if (cam_caps & CPAS_BPS_BIT)