Merge "msm: camera: csiphy: Move AON Camera select control" into camera-kernel.lnx.5.0

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -44,6 +44,7 @@ struct g_csiphy_data {
 	void __iomem *base_address;
 	uint8_t is_3phase;
 	uint32_t cpas_handle;
+	struct cam_csiphy_aon_sel_params_t *aon_sel_param;
 };
 
 static struct g_csiphy_data g_phy_data[MAX_CSIPHY] = {{0, 0}};
@@ -1117,6 +1118,7 @@ int cam_csiphy_util_update_aon_ops(
 {
 	uint32_t aon_config = 0;
 	uint32_t cpas_hdl = 0;
+	struct cam_csiphy_aon_sel_params_t *aon_sel_params;
 	int rc = 0;
 
 	if (phy_idx > MAX_CSIPHY) {
@@ -1124,7 +1126,13 @@ int cam_csiphy_util_update_aon_ops(
 		return -ENODEV;
 	}
 
+	if (g_phy_data[phy_idx].aon_sel_param == NULL) {
+		CAM_ERR(CAM_CSIPHY, "AON select parameters are null");
+		return -EINVAL;
+	}
+
 	cpas_hdl = g_phy_data[phy_idx].cpas_handle;
+	aon_sel_params = g_phy_data[phy_idx].aon_sel_param;
 
 	CAM_DBG(CAM_CSIPHY, "PHY idx: %d", phy_idx);
 	rc = cam_csiphy_cpas_ops(cpas_hdl, true);
@@ -1139,23 +1147,25 @@ int cam_csiphy_util_update_aon_ops(
 	}
 
 	cam_cpas_reg_read(cpas_hdl, CAM_CPAS_REG_CPASTOP,
-		CAM_CSIPHY_CPAS_AON_SEL_ADDR, true,	&aon_config);
+		aon_sel_params->aon_cam_sel_offset,
+		true, &aon_config);
 
 	if (get_access) {
-		aon_config &= ~(CAM_CSIPHY_CPAS_MAIN_CAM_SEL |
-			CAM_CSIPHY_CPAS_MCLK_SEL);
+		aon_config &= ~(aon_sel_params->cam_sel_mask |
+			aon_sel_params->mclk_sel_mask);
 		CAM_DBG(CAM_CSIPHY,
 			"Selecting MainCamera over AON Camera");
 	} else if (!get_access) {
-		aon_config |= (CAM_CSIPHY_CPAS_MAIN_CAM_SEL |
-			CAM_CSIPHY_CPAS_MCLK_SEL);
+		aon_config |= (aon_sel_params->cam_sel_mask |
+			aon_sel_params->mclk_sel_mask);
 		CAM_DBG(CAM_CSIPHY,
 			"Releasing MainCamera to AON Camera");
 	}
 
 	CAM_DBG(CAM_CSIPHY, "value of aon_config = %u", aon_config);
 	if (cam_cpas_reg_write(cpas_hdl, CAM_CPAS_REG_CPASTOP,
-		CAM_CSIPHY_CPAS_AON_SEL_ADDR, true, aon_config)) {
+		aon_sel_params->aon_cam_sel_offset,
+		true, aon_config)) {
 		CAM_ERR(CAM_CSIPHY,
 				"CPAS AON sel register write failed");
 	}
@@ -1692,4 +1702,6 @@ void cam_csiphy_register_baseaddress(struct csiphy_device *csiphy_dev)
 		csiphy_dev->soc_info.reg_map[0].mem_base;
 	g_phy_data[csiphy_dev->soc_info.index].cpas_handle =
 		csiphy_dev->cpas_handle;
+	g_phy_data[csiphy_dev->soc_info.index].aon_sel_param =
+		csiphy_dev->ctrl_reg->csiphy_reg.aon_sel_params;
 }

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -64,16 +64,24 @@
 #define DPHY_LANE_3    BIT(6)
 #define DPHY_CLK_LN    BIT(7)
 
-#define CAM_CSIPHY_CPAS_AON_SEL_ADDR    0x001E0
-#define CAM_CSIPHY_CPAS_MAIN_CAM_SEL    BIT(0)
-#define CAM_CSIPHY_CPAS_MCLK_SEL        BIT(8)
-
 enum cam_csiphy_state {
 	CAM_CSIPHY_INIT,
 	CAM_CSIPHY_ACQUIRE,
 	CAM_CSIPHY_START,
 };
 
+/**
+ * struct cam_csiphy_aon_sel_params_t
+ * @aon_cam_sel_offset : AON Cam Select Register offset in cpas top
+ * @cam_sel_mask       : Camera select mask.
+ * @mclk_sel_mask      : MCLK select mask.
+ */
+struct cam_csiphy_aon_sel_params_t {
+	uint32_t aon_cam_sel_offset;
+	uint32_t cam_sel_mask;
+	uint32_t mclk_sel_mask;
+};
+
 /**
  * struct csiphy_reg_parms_t
  * @mipi_csiphy_glbl_irq_cmd_addr: CSIPhy irq addr
@@ -97,6 +105,7 @@ enum cam_csiphy_state {
  * @csiphy_cpas_cp_3ph_offset: cp register 3ph offset
  * @csiphy_2ph_clock_lane: clock lane in 2ph
  * @csiphy_2ph_combo_ck_ln: clk lane in combo 2ph
+ * @aon_sel_params: aon selection parameters
  */
 struct csiphy_reg_parms_t {
 /*MIPI CSI PHY registers*/
@@ -120,6 +129,7 @@ struct csiphy_reg_parms_t {
 	uint32_t csiphy_2ph_clock_lane;
 	uint32_t csiphy_2ph_combo_ck_ln;
 	uint32_t prgm_cmn_reg_across_csiphy;
+	struct cam_csiphy_aon_sel_params_t *aon_sel_params;
 };
 
 /**

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_1_0_HWREG_H_
@@ -17,6 +17,7 @@ struct csiphy_reg_parms_t csiphy_v1_0 = {
 	.csiphy_reset_array_size = 5,
 	.csiphy_2ph_config_array_size = 14,
 	.csiphy_3ph_config_array_size = 19,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_1_0[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_1_1_HWREG_H_
@@ -19,6 +19,7 @@ struct csiphy_reg_parms_t csiphy_v1_1 = {
 	.csiphy_3ph_config_array_size = 43,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_1_1[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_1_2_1_HWREG_H_
@@ -19,6 +19,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = {
 	.csiphy_3ph_config_array_size = 33,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_1_2_1[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_1_2_2_HWREG_H_
@@ -19,6 +19,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_2 = {
 	.csiphy_3ph_config_array_size = 33,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_1_2_2[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h

@@ -21,6 +21,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = {
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
 	.prgm_cmn_reg_across_csiphy = 1,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_1_2_3[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_5_hwreg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_1_2_5_HWREG_H_
@@ -19,6 +19,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_5 = {
 	.csiphy_3ph_config_array_size = 30,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_1_2_5[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_1_2_HWREG_H_
@@ -19,6 +19,7 @@ struct csiphy_reg_parms_t csiphy_v1_2 = {
 	.csiphy_3ph_config_array_size = 33,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_1_2[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CSIPHY_2_0_HWREG_H_
@@ -19,6 +19,7 @@ struct csiphy_reg_parms_t csiphy_v2_0 = {
 	.csiphy_3ph_config_array_size = 17,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
+	.aon_sel_params = NULL,
 };
 
 struct csiphy_reg_t csiphy_common_reg_2_0[] = {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -8,6 +8,12 @@
 
 #include "../cam_csiphy_dev.h"
 
+struct cam_csiphy_aon_sel_params_t aon_cam_select_params = {
+	.aon_cam_sel_offset = 0x01E0,
+	.cam_sel_mask = BIT(0),
+	.mclk_sel_mask = BIT(8),
+};
+
 struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 	.mipi_csiphy_interrupt_status0_addr = 0x10B0,
 	.mipi_csiphy_interrupt_clear0_addr = 0x1058,
@@ -19,6 +25,7 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
 	.csiphy_interrupt_status_size = 11,
+	.aon_sel_params = &aon_cam_select_params,
 };
 
 struct csiphy_reg_t csiphy_common_reg_2_1_0[] = {