Merge "ipa: updates for ipa_reg_save()"

drivers/platform/msm/gsi/gsi.c

@@ -52,15 +52,6 @@
 #define GSI_MSB(num) ((u32)((num & GSI_MSB_MASK) >> 32))
 #define GSI_LSB(num) ((u32)(num & GSI_LSB_MASK))
 
-#define GSI_INST_RAM_FW_VER_OFFSET			(0)
-#define GSI_INST_RAM_FW_VER_GSI_3_0_OFFSET	(64)
-#define GSI_INST_RAM_FW_VER_HW_MASK			(0xFC00)
-#define GSI_INST_RAM_FW_VER_HW_SHIFT		(10)
-#define GSI_INST_RAM_FW_VER_FLAVOR_MASK		(0x380)
-#define GSI_INST_RAM_FW_VER_FLAVOR_SHIFT	(7)
-#define GSI_INST_RAM_FW_VER_FW_MASK			(0x7f)
-#define GSI_INST_RAM_FW_VER_FW_SHIFT		(0)
-
 #define GSI_FC_NUM_WORDS_PER_CHNL_SHRAM		(20)
 #define GSI_FC_STATE_INDEX_SHRAM			(7)
 #define GSI_FC_PENDING_MASK					(0x00080000)

drivers/platform/msm/gsi/gsi.h

@@ -36,6 +36,16 @@
 #define MAX_CHANNELS_SHARING_EVENT_RING 2
 #define MINIDUMP_MASK 0x10000
 
+#define GSI_INST_RAM_FW_VER_OFFSET                      (0)
+#define GSI_INST_RAM_FW_VER_GSI_3_0_OFFSET      (64)
+#define GSI_INST_RAM_FW_VER_GSI_5_5_OFFSET      (66)
+#define GSI_INST_RAM_FW_VER_HW_MASK                     (0xFC00)
+#define GSI_INST_RAM_FW_VER_HW_SHIFT            (10)
+#define GSI_INST_RAM_FW_VER_FLAVOR_MASK         (0x380)
+#define GSI_INST_RAM_FW_VER_FLAVOR_SHIFT        (7)
+#define GSI_INST_RAM_FW_VER_FW_MASK                     (0x7f)
+#define GSI_INST_RAM_FW_VER_FW_SHIFT            (0)
+
 #define GSI_IPC_LOGGING(buf, fmt, args...) \
 	do { \
 		if (buf) \

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h

@@ -445,7 +445,7 @@ enum ipa_hw_irq_srcs_e {
 /*
  * Total number of channel contexts that need to be saved for APPS
  */
-#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          20
+#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          27
 
 /*
  * Total number of channel contexts that need to be saved for UC

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.c

@@ -1075,15 +1075,25 @@ static void out_dword(
  */
 void ipa_save_gsi_ver(void)
 {
+	u32 gsi_fw_ver;
+
 	if (!ipa3_ctx->do_register_collection_on_crash)
 		return;
 
 	if (ipa3_ctx->ipa_hw_type < IPA_HW_v5_0)
-		ipa_reg_save.gsi.fw_ver =
+		gsi_fw_ver =
 		IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 0);
 	if (ipa3_ctx->ipa_hw_type == IPA_HW_v5_0)
-		ipa_reg_save.gsi.fw_ver =
+		gsi_fw_ver =
 		IPA_READ_1xVECTOR_REG(IPA_GSI_TOP_GSI_INST_RAM_n, 64);
+
+	ipa_reg_save.gsi.fw_ver.raw_version = gsi_fw_ver;
+	ipa_reg_save.gsi.fw_ver.hw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_HW_MASK) >>
+					GSI_INST_RAM_FW_VER_HW_SHIFT;
+	ipa_reg_save.gsi.fw_ver.flavor = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >>
+					GSI_INST_RAM_FW_VER_FLAVOR_SHIFT;
+	ipa_reg_save.gsi.fw_ver.fw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FW_MASK) >>
+					GSI_INST_RAM_FW_VER_FW_SHIFT;
 }
 
 /*

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_reg_dump.h

@@ -470,10 +470,31 @@ struct map_src_dst_addr_s {
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
 		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1),	\
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[20].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[21].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[22].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[23].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[24].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[25].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[26].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 1),	\
 		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \
 		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0),	\
@@ -628,6 +649,30 @@ struct map_src_dst_addr_s {
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
 		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[19].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[20].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[21].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[22].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[23].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[24].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 25), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[25].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 26), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[26].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
 		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
@@ -1565,6 +1610,14 @@ struct ipa_reg_save_gsi_gen_s {
 	  ipa_gsi_top_gsi_inst_ram_n;
 };
 
+/* GSI fw version data */
+struct ipa_reg_save_gsi_fw_version_s {
+	u32 raw_version;
+	u32 hw_version;
+	u32 flavor;
+	u32 fw_version;
+};
+
 /* GSI General EE register save data struct */
 struct ipa_reg_save_gsi_gen_ee_s {
 	struct gsi_hwio_def_gsi_manager_ee_qos_n_s
@@ -1997,7 +2050,7 @@ struct ipa_regs_save_hierarchy_s {
 
 /* Top level GSI register save data struct */
 struct gsi_regs_save_hierarchy_s {
-	u32 fw_ver;
+	struct ipa_reg_save_gsi_fw_version_s	fw_ver;
 	struct ipa_reg_save_gsi_gen_s		gen;
 	struct ipa_reg_save_gsi_gen_ee_s	gen_ee[IPA_REG_SAVE_GSI_NUM_EE];
 	struct ipa_reg_save_gsi_ch_cntxt_s	ch_cntxt;

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_hw_common_ex.h

@@ -444,7 +444,7 @@ enum ipa_hw_irq_srcs_e {
 /*
  * Total number of channel contexts that need to be saved for APPS
  */
-#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          20
+#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_A7          25
 
 /*
  * Total number of channel contexts that need to be saved for UC
@@ -459,7 +459,7 @@ enum ipa_hw_irq_srcs_e {
 /*
  * Total number of event ring contexts that need to be saved for APPS
  */
-#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7         27
+#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7         25
 
 /*
  * Total number of event ring contexts that need to be saved for UC

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.c

@@ -985,12 +985,21 @@ static void out_dword(
  */
 void ipa_save_gsi_ver(void)
 {
+	u32 gsi_fw_ver;
+
 	if (!ipa3_ctx->do_register_collection_on_crash)
 		return;
 
 	/* IPA_HW_v5_5 */
-	ipa_reg_save.gsi.fw_ver =
-	IPA_READ_1xVECTOR_REG(IPA_0_GSI_TOP_GSI_INST_RAM_n, 66);
+	gsi_fw_ver = IPA_READ_1xVECTOR_REG(IPA_0_GSI_TOP_GSI_INST_RAM_n, 66);
+
+	ipa_reg_save.gsi.fw_ver.raw_version = gsi_fw_ver;
+	ipa_reg_save.gsi.fw_ver.hw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_HW_MASK) >>
+					GSI_INST_RAM_FW_VER_HW_SHIFT;
+	ipa_reg_save.gsi.fw_ver.flavor = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FLAVOR_MASK) >>
+					GSI_INST_RAM_FW_VER_FLAVOR_SHIFT;
+	ipa_reg_save.gsi.fw_ver.fw_version = (gsi_fw_ver & GSI_INST_RAM_FW_VER_FW_MASK) >>
+					GSI_INST_RAM_FW_VER_FW_SHIFT;
 }
 
 /*

drivers/platform/msm/ipa/ipa_v3/dump/ipa5.5/ipa_reg_dump.h

@@ -443,10 +443,25 @@ struct map_src_dst_addr_s {
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
 		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[19].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1),	\
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[20].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[21].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[22].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[23].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+		(u32 *)&ipa_reg_save.gsi.ch_cntxt.a7[24].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 0),	\
 		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
-	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_UC_EE, 3), \
 		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0),	\
@@ -601,6 +616,24 @@ struct map_src_dst_addr_s {
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \
 		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 19), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[19].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 20), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[20].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 21), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[21].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 22), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[22].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 23), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[23].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
+	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 24), \
+		(u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[24].var_name, \
+		GEN_REG_ATTR(reg_name) }, \
 	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
 		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \
 		GEN_REG_ATTR(reg_name) }, \
@@ -1465,6 +1498,14 @@ struct ipa_reg_save_dst_rsrc_cnt_s {
 	  ipa_dst_rsrc_grp_4567_rsrc_type_cnt_n;
 };
 
+/* GSI fw version data */
+struct ipa_reg_save_gsi_fw_version_s {
+	u32 raw_version;
+	u32 hw_version;
+	u32 flavor;
+	u32 fw_version;
+};
+
 /* GSI General register save data struct */
 struct ipa_reg_save_gsi_gen_s {
 	struct gsi_hwio_def_gsi_cfg_s
@@ -1867,7 +1908,7 @@ struct ipa_regs_save_hierarchy_s {
 
 /* Top level GSI register save data struct */
 struct gsi_regs_save_hierarchy_s {
-	u32 fw_ver;
+	struct ipa_reg_save_gsi_fw_version_s	fw_ver;
 	struct ipa_reg_save_gsi_gen_s		gen;
 	struct ipa_reg_save_gsi_gen_ee_s	gen_ee[IPA_REG_SAVE_GSI_NUM_EE];
 	struct ipa_reg_save_gsi_ch_cntxt_s	ch_cntxt;