Merge "fw-api: Add qcnn6432 target header files to fw-api project"
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106
hw/qcn6432/HALcomdef.h
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106
hw/qcn6432/HALcomdef.h
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@@ -0,0 +1,106 @@
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
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||||
*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef HAL_COMDEF_H
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#define HAL_COMDEF_H
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/*
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* Assembly wrapper
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*/
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#ifndef _ARM_ASM_
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/*
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* C++ wrapper
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "com_dtypes.h"
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/* -----------------------------------------------------------------------
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** Types
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** ----------------------------------------------------------------------- */
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/*
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* Standard integer types.
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*
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* bool32 - boolean, 32 bit (TRUE or FALSE)
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*/
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#ifndef _BOOL32_DEFINED
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typedef unsigned long int bool32;
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#define _BOOL32_DEFINED
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#endif
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/*
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* Macro to allow forcing an enum to 32 bits. The argument should be
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* an identifier in the namespace of the enumeration in question, i.e.
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* for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
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*/
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#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
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/*===========================================================================
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FUNCTION inp, outp, inpw, outpw, inpdw, outpdw
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DESCRIPTION
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IN/OUT port macros for byte and word ports, typically inlined by compilers
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which support these routines
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PARAMETERS
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inp( xx_addr )
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inpw( xx_addr )
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inpdw( xx_addr )
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outp( xx_addr, xx_byte_val )
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outpw( xx_addr, xx_word_val )
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outpdw( xx_addr, xx_dword_val )
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xx_addr - Address of port to read or write (may be memory mapped)
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xx_byte_val - 8 bit value to write
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xx_word_val - 16 bit value to write
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xx_dword_val - 32 bit value to write
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DEPENDENCIES
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None
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RETURN VALUE
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inp/inpw/inpdw: the byte, word or dword read from the given address
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outp/outpw/outpdw: the byte, word or dword written to the given address
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SIDE EFFECTS
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None.
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===========================================================================*/
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/* ARM based targets use memory mapped i/o, so the inp/outp calls are
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** macroized to access memory directly
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*/
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#define inp(port) (*((volatile byte *) (port)))
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#define inpw(port) (*((volatile word *) (port)))
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#define inpdw(port) (*((volatile dword *)(port)))
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#define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
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#define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
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#define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
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#ifdef __cplusplus
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}
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#endif
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#endif /* !_ARM_ASM_ */
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#endif /* HAL_COMDEF_H */
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488
hw/qcn6432/HALhwio.h
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488
hw/qcn6432/HALhwio.h
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@@ -0,0 +1,488 @@
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
|
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* purpose with or without fee is hereby granted, provided that the above
|
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* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef HAL_HWIO_H
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#define HAL_HWIO_H
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/*
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* Common types.
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*/
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#include "HALcomdef.h"
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/* -----------------------------------------------------------------------
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** Macros
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** ----------------------------------------------------------------------- */
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/**
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@addtogroup macros
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@{
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*/
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/**
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* Map a base name to the pointer to access the base.
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*
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* This macro maps a base name to the pointer to access the base.
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* This is generally just used internally.
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*
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*/
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#define HWIO_BASE_PTR(base) base##_BASE_PTR
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/**
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* Declare a HWIO base pointer.
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*
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* This macro will declare a HWIO base pointer data structure. The pointer
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* will always be declared as a weak symbol so multiple declarations will
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* resolve correctly to the same data at link-time.
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*/
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#ifdef __ARMCC_VERSION
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#define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
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#else
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#define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
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#endif
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/**
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@}
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*/
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#ifdef CONFIG_WHAL_MM
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#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET
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#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET
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#endif
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/**
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@addtogroup hwio_macros
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@{
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*/
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/**
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* @name Address Macros
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*
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* Macros for getting register addresses.
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* These macros are used for retrieving the address of a register.
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* HWIO_ADDR* will return the directly accessible address (virtual or physical based
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* on environment), HWIO_PHYS* will always return the physical address.
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* The offset from the base region can be retrieved using HWIO_OFFS*.
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* The "X" extension is used for explicit addressing where the base address of
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* the module in question is provided as an argument to the macro.
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*
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* @{
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*/
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#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
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#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
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#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
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#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
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#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
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#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
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#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
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#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
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#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
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#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
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#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
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#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
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#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
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#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
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#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
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#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
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#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
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#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
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#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
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#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
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/** @} */
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/**
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* @name Input Macros
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*
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* These macros are used for reading from a named hardware register. Register
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* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
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* indicates that the input will be masked with the supplied mask. The HWIO_INF*
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* macros take a field name and will do the appropriate masking and shifting
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* to return just the value of that field.
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* The "X" extension is used for explicit addressing where the base address of
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* the module in question is provided as an argument to the macro.
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*
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* Generally you want to use either HWIO_IN or HWIO_INF (with required indexing).
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*
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* @{
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*/
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#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
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#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
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#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
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#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
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#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
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#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
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#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
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#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
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#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
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#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
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#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
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#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
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#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
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#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
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#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
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#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
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#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
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/** @} */
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/**
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* @name Output Macros
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*
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* These macros are used for writing to a named hardware register. Register
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* arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
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* indicates that the output will be masked with the supplied mask (meaning these
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* macros do a read first, mask in the supplied data, then write it back).
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* The "X" extension is used for explicit addressing where the base address of
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* the module in question is provided as an argument to the macro.
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* The HWIO_OUTF* macros take a field name and will do the appropriate masking
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* and shifting to output just the value of that field.
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* HWIO_OUTV* registers take a named value instead of a numeric value and
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* do the same masking/shifting as HWIO_OUTF.
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*
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* Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing).
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*
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* @{
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*/
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#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
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#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
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#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
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#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
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#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
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#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
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#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
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#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
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#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
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#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
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#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
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#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
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#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
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#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
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#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
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#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
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||||
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#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
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#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
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#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
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#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
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#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
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#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
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#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
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#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
|
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#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
|
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#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
|
||||
#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
|
||||
|
||||
#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
|
||||
#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
|
||||
#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
|
||||
|
||||
#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
|
||||
|
||||
#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Shift and Mask Macros
|
||||
*
|
||||
* Macros for getting shift and mask values for fields and registers.
|
||||
* HWIO_RMSK: The mask value for accessing an entire register. For example:
|
||||
* @code
|
||||
* HWIO_RMSK(REG) -> 0xFFFFFFFF
|
||||
* @endcode
|
||||
* HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n
|
||||
* HWIO_SHFT: The right-shift value for accessing a field in a register. For example:
|
||||
* @code
|
||||
* HWIO_SHFT(REG, FLD) -> 8
|
||||
* @endcode
|
||||
* HWIO_FMSK: The mask value for accessing a field in a register. For example:
|
||||
* @code
|
||||
* HWIO_FMSK(REG, FLD) -> 0xFF00
|
||||
* @endcode
|
||||
* HWIO_VAL: The value for a field in a register. For example:
|
||||
* @code
|
||||
* HWIO_VAL(REG, FLD, ON) -> 0x1
|
||||
* @endcode
|
||||
* HWIO_FVAL: This macro takes a numerical value and will shift and mask it into
|
||||
* the given field position. For example:
|
||||
* @code
|
||||
* HWIO_FVAL(REG, FLD, 0x1) -> 0x100
|
||||
* @endcode
|
||||
* HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it
|
||||
* into the given field position. For example:
|
||||
* @code
|
||||
* HWIO_FVALV(REG, FLD, ON) -> 0x100
|
||||
* @endcode
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
|
||||
#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
|
||||
#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
|
||||
#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
|
||||
#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
|
||||
#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
|
||||
#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
|
||||
#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Shadow Register Macros
|
||||
*
|
||||
* These macros are used for directly reading the value stored in a
|
||||
* shadow register.
|
||||
* Shadow registers are defined for write-only registers. Generally these
|
||||
* macros should not be necessary as HWIO_OUTM* macros will automatically use
|
||||
* the shadow values internally.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
|
||||
#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
@}
|
||||
*/ /* end_group */
|
||||
|
||||
|
||||
/** @cond */
|
||||
|
||||
/*
|
||||
* Map to final symbols. This remapping is done to allow register
|
||||
* redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN
|
||||
* then remappings like "#define xreg xregnew" do not work as expected.
|
||||
*/
|
||||
#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
|
||||
#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
|
||||
#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
|
||||
#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
|
||||
#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
|
||||
#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
|
||||
#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
|
||||
#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
|
||||
#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
|
||||
#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
|
||||
#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
|
||||
#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
|
||||
#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
|
||||
#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
|
||||
#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
|
||||
#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
|
||||
#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
|
||||
#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
|
||||
#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
|
||||
#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
|
||||
#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
|
||||
#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
|
||||
#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
|
||||
#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
|
||||
#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
|
||||
#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
|
||||
#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
|
||||
#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
|
||||
#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
|
||||
#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
|
||||
#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
|
||||
#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
|
||||
#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
|
||||
#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
|
||||
#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
|
||||
#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
|
||||
|
||||
#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
|
||||
#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
|
||||
#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
|
||||
#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
|
||||
#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
|
||||
#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
|
||||
#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
|
||||
#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
|
||||
#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
|
||||
#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
|
||||
#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
|
||||
#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
|
||||
#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
|
||||
#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
|
||||
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
|
||||
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
|
||||
}
|
||||
#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
|
||||
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
|
||||
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
|
||||
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
|
||||
}
|
||||
#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
|
||||
HWIO_##hwiosym##_OUTM(base, mask1, val1); \
|
||||
HWIO_##hwiosym##_OUTM(base, mask2, val2); \
|
||||
HWIO_##hwiosym##_OUTM(base, mask3, val3); \
|
||||
HWIO_##hwiosym##_OUTM(base, mask4, val4); \
|
||||
}
|
||||
|
||||
|
||||
#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
|
||||
#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
|
||||
#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
|
||||
#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
|
||||
#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
|
||||
#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
|
||||
#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
|
||||
#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
|
||||
#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
|
||||
#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
|
||||
#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
|
||||
|
||||
|
||||
/*
|
||||
* HWIO_INTLOCK
|
||||
*
|
||||
* Macro used by autogenerated code for mutual exclusion around
|
||||
* read-mask-write operations. This is not supported in HAL
|
||||
* code but can be overridden by non-HAL code.
|
||||
*/
|
||||
#define HWIO_INTLOCK()
|
||||
#define HWIO_INTFREE()
|
||||
|
||||
|
||||
/*
|
||||
* Input/output port macros for memory mapped IO.
|
||||
*/
|
||||
#define __inp(port) (*((volatile uint8 *) (port)))
|
||||
#define __inpw(port) (*((volatile uint16 *) (port)))
|
||||
#define __inpdw(port) (*((volatile uint32 *) (port)))
|
||||
#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
|
||||
#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
|
||||
#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
|
||||
|
||||
|
||||
#ifdef HAL_HWIO_EXTERNAL
|
||||
|
||||
/*
|
||||
* Replace macros with externally supplied functions.
|
||||
*/
|
||||
#undef __inp
|
||||
#undef __inpw
|
||||
#undef __inpdw
|
||||
#undef __outp
|
||||
#undef __outpw
|
||||
#undef __outpdw
|
||||
|
||||
#ifdef WCSS_IE_EN
|
||||
extern uint32 registerRead(unsigned long addr);
|
||||
extern void registerWrite(unsigned long addr, uint32 value);
|
||||
#define __inp(port) registerRead(port)
|
||||
#define __inpw(port) registerRead(port)
|
||||
#define __inpdw(port) registerRead(port)
|
||||
#define __outp(port, val) registerWrite(port, val)
|
||||
#define __outpw(port, val) registerWrite(port, val)
|
||||
#define __outpdw(port, val) registerWrite(port, val)
|
||||
#else
|
||||
#define __inp(port) __inp_extern((uint32) (port))
|
||||
#define __inpw(port) __inpw_extern((uint32) (port))
|
||||
#define __inpdw(port) __inpdw_extern((uint32) (port))
|
||||
#define __outp(port, val) __outp_extern((uint32) (port), val)
|
||||
#define __outpw(port, val) __outpw_extern((uint32) (port), val)
|
||||
#define __outpdw(port, val) __outpdw_extern((uint32) (port), val)
|
||||
|
||||
extern uint8 __inp_extern ( uint32 nAddr );
|
||||
extern uint16 __inpw_extern ( uint32 nAddr );
|
||||
extern uint32 __inpdw_extern ( uint32 nAddr );
|
||||
extern void __outp_extern ( uint32 nAddr, uint8 nData );
|
||||
extern void __outpw_extern ( uint32 nAddr, uint16 nData );
|
||||
extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* HAL_HWIO_EXTERNAL */
|
||||
|
||||
|
||||
/*
|
||||
* Base 8-bit byte accessing macros.
|
||||
*/
|
||||
#define in_byte(addr) (__inp(addr))
|
||||
#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
|
||||
#define out_byte(addr, val) __outp(addr,val)
|
||||
#define out_byte_masked(io, mask, val, shadow) \
|
||||
HWIO_INTLOCK(); \
|
||||
out_byte( io, shadow); \
|
||||
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
|
||||
HWIO_INTFREE()
|
||||
#define out_byte_masked_ns(io, mask, val, current_reg_content) \
|
||||
out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
|
||||
((uint16)((val) & (mask)))) )
|
||||
|
||||
|
||||
/*
|
||||
* Base 16-bit word accessing macros.
|
||||
*/
|
||||
#define in_word(addr) (__inpw(addr))
|
||||
#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
|
||||
#define out_word(addr, val) __outpw(addr,val)
|
||||
#define out_word_masked(io, mask, val, shadow) \
|
||||
HWIO_INTLOCK( ); \
|
||||
shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
|
||||
out_word( io, shadow); \
|
||||
HWIO_INTFREE( )
|
||||
#define out_word_masked_ns(io, mask, val, current_reg_content) \
|
||||
out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
|
||||
((uint16)((val) & (mask)))) )
|
||||
|
||||
|
||||
/*
|
||||
* Base 32-bit double-word accessing macros.
|
||||
*/
|
||||
#define in_dword(addr) (__inpdw(addr))
|
||||
#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
|
||||
#define out_dword(addr, val) __outpdw(addr,val)
|
||||
#define out_dword_masked(io, mask, val, shadow) \
|
||||
HWIO_INTLOCK(); \
|
||||
shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
|
||||
out_dword( io, shadow); \
|
||||
HWIO_INTFREE()
|
||||
#define out_dword_masked_ns(io, mask, val, current_reg_content) \
|
||||
out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
|
||||
((uint32)((val) & (mask)))) )
|
||||
|
||||
/** @endcond */
|
||||
|
||||
#endif /* HAL_HWIO_H */
|
||||
|
||||
164
hw/qcn6432/ack_report.h
Archivo normal
164
hw/qcn6432/ack_report.h
Archivo normal
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _ACK_REPORT_H_
|
||||
#define _ACK_REPORT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_ACK_REPORT 1
|
||||
|
||||
|
||||
struct ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t selfgen_response_reason : 4, // [3:0]
|
||||
ax_trigger_type : 4, // [7:4]
|
||||
sr_ppdu : 1, // [8:8]
|
||||
reserved : 7, // [15:9]
|
||||
frame_control : 16; // [31:16]
|
||||
#else
|
||||
uint32_t frame_control : 16, // [31:16]
|
||||
reserved : 7, // [15:9]
|
||||
sr_ppdu : 1, // [8:8]
|
||||
ax_trigger_type : 4, // [7:4]
|
||||
selfgen_response_reason : 4; // [3:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description SELFGEN_RESPONSE_REASON
|
||||
|
||||
Field that indicates why the received frame needs a response
|
||||
in SIFS time. The possible responses are listed in order.
|
||||
|
||||
|
||||
<enum 0 CTS_frame>
|
||||
<enum 1 ACK_frame>
|
||||
<enum 2 BA_frame >
|
||||
<enum 3 Qboost_trigger> Qboost trigger received
|
||||
<enum 4 PSPOLL_trigger> PSPOLL trigger received
|
||||
<enum 5 UAPSD_trigger > Unscheduled APSD trigger received
|
||||
|
||||
<enum 6 CBF_frame> the CBF frame needs to be send as
|
||||
a result of NDP or BRPOLL
|
||||
<enum 7 ax_su_trigger> 11ax trigger received for this
|
||||
device
|
||||
<enum 8 ax_wildcard_trigger> 11ax wildcardtrigger has
|
||||
been received
|
||||
<enum 9 ax_unassoc_wildcard_trigger> 11ax wildcard trigger
|
||||
for unassociated STAs has been received
|
||||
<enum 12 eht_su_trigger> EHT R1 trigger received for
|
||||
this device
|
||||
|
||||
<enum 10 MU_UL_response_to_response>
|
||||
|
||||
<enum 11 Ranging_NDP_LMR_frames> Ranging NDP + LMR need
|
||||
to be sent in response to ranging NDPA + NDP
|
||||
|
||||
<legal 0-12>
|
||||
*/
|
||||
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
|
||||
#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f
|
||||
|
||||
|
||||
/* Description AX_TRIGGER_TYPE
|
||||
|
||||
Field Only valid when selfgen_response_reason is an 11ax
|
||||
related trigger
|
||||
|
||||
The 11AX trigger type/ trigger number:
|
||||
It identifies which trigger was received.
|
||||
<enum 0 ax_trigger_basic>
|
||||
<enum 1 ax_trigger_brpoll>
|
||||
<enum 2 ax_trigger_mu_bar>
|
||||
<enum 3 ax_trigger_mu_rts>
|
||||
<enum 4 ax_trigger_buffer_size>
|
||||
<enum 5 ax_trigger_gcr_mu_bar>
|
||||
<enum 6 ax_trigger_BQRP>
|
||||
<enum 7 ax_trigger_NDP_fb_report_poll>
|
||||
<enum 8 ax_tb_ranging_trigger>
|
||||
<enum 9 ax_trigger_reserved_9>
|
||||
<enum 10 ax_trigger_reserved_10>
|
||||
<enum 11 ax_trigger_reserved_11>
|
||||
<enum 12 ax_trigger_reserved_12>
|
||||
<enum 13 ax_trigger_reserved_13>
|
||||
<enum 14 ax_trigger_reserved_14>
|
||||
<enum 15 ax_trigger_reserved_15>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
|
||||
#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0
|
||||
|
||||
|
||||
/* Description SR_PPDU
|
||||
|
||||
Field only valid with SRP Responder support
|
||||
|
||||
Indicates if the received frame was sent using SRP as indicated
|
||||
by the 'SR PPDU' bit in the 'CAS Control' in the 'HE A-Control'
|
||||
in one of the MPDUs received
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
|
||||
#define ACK_REPORT_SR_PPDU_LSB 8
|
||||
#define ACK_REPORT_SR_PPDU_MSB 8
|
||||
#define ACK_REPORT_SR_PPDU_MASK 0x00000100
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define ACK_REPORT_RESERVED_OFFSET 0x00000000
|
||||
#define ACK_REPORT_RESERVED_LSB 9
|
||||
#define ACK_REPORT_RESERVED_MSB 15
|
||||
#define ACK_REPORT_RESERVED_MASK 0x0000fe00
|
||||
|
||||
|
||||
/* Description FRAME_CONTROL
|
||||
|
||||
Field not valid when selfgen_response_reason is MU_UL_response_to_response
|
||||
|
||||
|
||||
For SU receptions:
|
||||
frame control field of the received frame
|
||||
|
||||
In 11ah Mode of Operation, for non-NDP frames the BW information
|
||||
is extracted from Frame Control fields [11:8].
|
||||
|
||||
Decode is as follows
|
||||
|
||||
Bits[11] - Dynamic/Static
|
||||
Bits[10:8] - Channel BW
|
||||
*/
|
||||
|
||||
#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
|
||||
#define ACK_REPORT_FRAME_CONTROL_LSB 16
|
||||
#define ACK_REPORT_FRAME_CONTROL_MSB 31
|
||||
#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
|
||||
|
||||
|
||||
|
||||
#endif // ACK_REPORT
|
||||
176
hw/qcn6432/buffer_addr_info.h
Archivo normal
176
hw/qcn6432/buffer_addr_info.h
Archivo normal
@@ -0,0 +1,176 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BUFFER_ADDR_INFO_H_
|
||||
#define _BUFFER_ADDR_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
|
||||
|
||||
|
||||
struct buffer_addr_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t buffer_addr_31_0 : 32; // [31:0]
|
||||
uint32_t buffer_addr_39_32 : 8, // [7:0]
|
||||
return_buffer_manager : 4, // [11:8]
|
||||
sw_buffer_cookie : 20; // [31:12]
|
||||
#else
|
||||
uint32_t buffer_addr_31_0 : 32; // [31:0]
|
||||
uint32_t sw_buffer_cookie : 20, // [31:12]
|
||||
return_buffer_manager : 4, // [11:8]
|
||||
buffer_addr_39_32 : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_31_0
|
||||
|
||||
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_39_32
|
||||
|
||||
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
||||
#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RETURN_BUFFER_MANAGER
|
||||
|
||||
Consumer: WBM
|
||||
Producer: SW/FW
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
||||
descriptor OR link descriptor that is being pointed to
|
||||
shall be returned after the frame has been processed. It
|
||||
is used by WBM for routing purposes.
|
||||
|
||||
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
||||
to the WMB buffer idle list
|
||||
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the WBM idle link descriptor idle list, where the chip
|
||||
0 WBM is chosen in case of a multi-chip config
|
||||
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 1 WBM idle link descriptor idle list
|
||||
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 2 WBM idle link descriptor idle list
|
||||
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
||||
returned to chip 3 WBM idle link descriptor idle list
|
||||
<enum 4 FW_BM> This buffer shall be returned to the FW
|
||||
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
||||
ring 0
|
||||
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
||||
ring 1
|
||||
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
||||
ring 2
|
||||
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
||||
ring 3
|
||||
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
||||
ring 4
|
||||
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
||||
ring 5
|
||||
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
||||
ring 6
|
||||
|
||||
<legal 0-12>
|
||||
*/
|
||||
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
||||
#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
||||
|
||||
|
||||
/* Description SW_BUFFER_COOKIE
|
||||
|
||||
Cookie field exclusively used by SW.
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
HW ignores the contents, accept that it passes the programmed
|
||||
value on to other descriptors together with the physical
|
||||
address
|
||||
|
||||
Field can be used by SW to for example associate the buffers
|
||||
physical address with the virtual address
|
||||
The bit definitions as used by SW are within SW HLD specification
|
||||
|
||||
|
||||
NOTE1:
|
||||
The three most significant bits can have a special meaning
|
||||
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
||||
and field transmit_bw_restriction is set
|
||||
|
||||
In case of NON punctured transmission:
|
||||
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
In case of punctured transmission:
|
||||
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
Note: a punctured transmission is indicated by the presence
|
||||
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
||||
#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
||||
|
||||
|
||||
|
||||
#endif // BUFFER_ADDR_INFO
|
||||
281
hw/qcn6432/ce_src_desc.h
Archivo normal
281
hw/qcn6432/ce_src_desc.h
Archivo normal
@@ -0,0 +1,281 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CE_SRC_DESC_H_
|
||||
#define _CE_SRC_DESC_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_CE_SRC_DESC 4
|
||||
|
||||
|
||||
struct ce_src_desc {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t src_buffer_low : 32; // [31:0]
|
||||
uint32_t src_buffer_high : 8, // [7:0]
|
||||
toeplitz_en : 1, // [8:8]
|
||||
src_swap : 1, // [9:9]
|
||||
dest_swap : 1, // [10:10]
|
||||
gather : 1, // [11:11]
|
||||
ce_res_0 : 1, // [12:12]
|
||||
barrier_read : 1, // [13:13]
|
||||
ce_res_1 : 2, // [15:14]
|
||||
length : 16; // [31:16]
|
||||
uint32_t fw_metadata : 16, // [15:0]
|
||||
ce_res_2 : 16; // [31:16]
|
||||
uint32_t ce_res_3 : 20, // [19:0]
|
||||
ring_id : 8, // [27:20]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
uint32_t src_buffer_low : 32; // [31:0]
|
||||
uint32_t length : 16, // [31:16]
|
||||
ce_res_1 : 2, // [15:14]
|
||||
barrier_read : 1, // [13:13]
|
||||
ce_res_0 : 1, // [12:12]
|
||||
gather : 1, // [11:11]
|
||||
dest_swap : 1, // [10:10]
|
||||
src_swap : 1, // [9:9]
|
||||
toeplitz_en : 1, // [8:8]
|
||||
src_buffer_high : 8; // [7:0]
|
||||
uint32_t ce_res_2 : 16, // [31:16]
|
||||
fw_metadata : 16; // [15:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
ring_id : 8, // [27:20]
|
||||
ce_res_3 : 20; // [19:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description SRC_BUFFER_LOW
|
||||
|
||||
LSB 32 bits of the 40 Bit Pointer to the source buffer
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31
|
||||
#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description SRC_BUFFER_HIGH
|
||||
|
||||
Bits [6:0] for 40 Bit Pointer to the source buffer
|
||||
Bit [7] can be programmed with VC bit.
|
||||
Note: CE Descriptor has 40-bit address. Only 37 bits are
|
||||
routed as address to NoC. Remaining bits are user bits.
|
||||
Bit [7] of SRC_BUFFER_HIGH can be used for VC configuration.
|
||||
0 indicate VC0 and 1 indicate VC1.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7
|
||||
#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description TOEPLITZ_EN
|
||||
|
||||
Enable generation of 32-bit Toeplitz-LFSR hash for the data
|
||||
transfer
|
||||
In case of gather field in first source ring entry of the
|
||||
gather copy cycle in taken into account.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8
|
||||
#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100
|
||||
|
||||
|
||||
/* Description SRC_SWAP
|
||||
|
||||
Treats source memory organization as big-endian. For each
|
||||
dword read (4 bytes), the byte 0 is swapped with byte 3
|
||||
and byte 1 is swapped with byte 2.
|
||||
In case of gather field in first source ring entry of the
|
||||
gather copy cycle in taken into account.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_SRC_SWAP_LSB 9
|
||||
#define CE_SRC_DESC_SRC_SWAP_MSB 9
|
||||
#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200
|
||||
|
||||
|
||||
/* Description DEST_SWAP
|
||||
|
||||
Treats destination memory organization as big-endian. For
|
||||
each dword write (4 bytes), the byte 0 is swapped with
|
||||
byte 3 and byte 1 is swapped with byte 2.
|
||||
In case of gather field in first source ring entry of the
|
||||
gather copy cycle in taken into account.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_DEST_SWAP_LSB 10
|
||||
#define CE_SRC_DESC_DEST_SWAP_MSB 10
|
||||
#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400
|
||||
|
||||
|
||||
/* Description GATHER
|
||||
|
||||
Enables gather of multiple copy engine source descriptors
|
||||
to one destination.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_GATHER_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_GATHER_LSB 11
|
||||
#define CE_SRC_DESC_GATHER_MSB 11
|
||||
#define CE_SRC_DESC_GATHER_MASK 0x00000800
|
||||
|
||||
|
||||
/* Description CE_RES_0
|
||||
|
||||
Reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_CE_RES_0_LSB 12
|
||||
#define CE_SRC_DESC_CE_RES_0_MSB 12
|
||||
#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description BARRIER_READ
|
||||
|
||||
Barrier Read enable
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_BARRIER_READ_LSB 13
|
||||
#define CE_SRC_DESC_BARRIER_READ_MSB 13
|
||||
#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000
|
||||
|
||||
|
||||
/* Description CE_RES_1
|
||||
|
||||
Reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_CE_RES_1_LSB 14
|
||||
#define CE_SRC_DESC_CE_RES_1_MSB 15
|
||||
#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
Length of the buffer in units of octets of the current descriptor
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004
|
||||
#define CE_SRC_DESC_LENGTH_LSB 16
|
||||
#define CE_SRC_DESC_LENGTH_MSB 31
|
||||
#define CE_SRC_DESC_LENGTH_MASK 0xffff0000
|
||||
|
||||
|
||||
/* Description FW_METADATA
|
||||
|
||||
Meta data used by FW
|
||||
In case of gather field in first source ring entry of the
|
||||
gather copy cycle in taken into account.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008
|
||||
#define CE_SRC_DESC_FW_METADATA_LSB 0
|
||||
#define CE_SRC_DESC_FW_METADATA_MSB 15
|
||||
#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description CE_RES_2
|
||||
|
||||
Reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008
|
||||
#define CE_SRC_DESC_CE_RES_2_LSB 16
|
||||
#define CE_SRC_DESC_CE_RES_2_MSB 31
|
||||
#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000
|
||||
|
||||
|
||||
/* Description CE_RES_3
|
||||
|
||||
Reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c
|
||||
#define CE_SRC_DESC_CE_RES_3_LSB 0
|
||||
#define CE_SRC_DESC_CE_RES_3_MSB 19
|
||||
#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff
|
||||
|
||||
|
||||
/* Description RING_ID
|
||||
|
||||
The buffer pointer ring ID.
|
||||
0 refers to the IDLE ring
|
||||
1 - N refers to other rings
|
||||
|
||||
Helps with debugging when dumping ring contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c
|
||||
#define CE_SRC_DESC_RING_ID_LSB 20
|
||||
#define CE_SRC_DESC_RING_ID_MSB 27
|
||||
#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into the Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_LSB 28
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_MSB 31
|
||||
#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
#endif // CE_SRC_DESC
|
||||
252
hw/qcn6432/ce_stat_desc.h
Archivo normal
252
hw/qcn6432/ce_stat_desc.h
Archivo normal
@@ -0,0 +1,252 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CE_STAT_DESC_H_
|
||||
#define _CE_STAT_DESC_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_CE_STAT_DESC 4
|
||||
|
||||
|
||||
struct ce_stat_desc {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ce_res_5 : 8, // [7:0]
|
||||
toeplitz_en : 1, // [8:8]
|
||||
src_swap : 1, // [9:9]
|
||||
dest_swap : 1, // [10:10]
|
||||
gather : 1, // [11:11]
|
||||
barrier_read : 1, // [12:12]
|
||||
ce_res_6 : 3, // [15:13]
|
||||
length : 16; // [31:16]
|
||||
uint32_t toeplitz_hash_0 : 32; // [31:0]
|
||||
uint32_t toeplitz_hash_1 : 32; // [31:0]
|
||||
uint32_t fw_metadata : 16, // [15:0]
|
||||
ce_res_7 : 4, // [19:16]
|
||||
ring_id : 8, // [27:20]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
uint32_t length : 16, // [31:16]
|
||||
ce_res_6 : 3, // [15:13]
|
||||
barrier_read : 1, // [12:12]
|
||||
gather : 1, // [11:11]
|
||||
dest_swap : 1, // [10:10]
|
||||
src_swap : 1, // [9:9]
|
||||
toeplitz_en : 1, // [8:8]
|
||||
ce_res_5 : 8; // [7:0]
|
||||
uint32_t toeplitz_hash_0 : 32; // [31:0]
|
||||
uint32_t toeplitz_hash_1 : 32; // [31:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
ring_id : 8, // [27:20]
|
||||
ce_res_7 : 4, // [19:16]
|
||||
fw_metadata : 16; // [15:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description CE_RES_5
|
||||
|
||||
Reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_CE_RES_5_LSB 0
|
||||
#define CE_STAT_DESC_CE_RES_5_MSB 7
|
||||
#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description TOEPLITZ_EN
|
||||
|
||||
32-bit Toeplitz-LFSR hash for the data transfer, Enabled
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8
|
||||
#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100
|
||||
|
||||
|
||||
/* Description SRC_SWAP
|
||||
|
||||
Source memory buffer swapped
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_SRC_SWAP_LSB 9
|
||||
#define CE_STAT_DESC_SRC_SWAP_MSB 9
|
||||
#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200
|
||||
|
||||
|
||||
/* Description DEST_SWAP
|
||||
|
||||
Destination memory buffer swapped
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_DEST_SWAP_LSB 10
|
||||
#define CE_STAT_DESC_DEST_SWAP_MSB 10
|
||||
#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400
|
||||
|
||||
|
||||
/* Description GATHER
|
||||
|
||||
Gather of multiple copy engine source descriptors to one
|
||||
destination enabled
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_GATHER_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_GATHER_LSB 11
|
||||
#define CE_STAT_DESC_GATHER_MSB 11
|
||||
#define CE_STAT_DESC_GATHER_MASK 0x00000800
|
||||
|
||||
|
||||
/* Description BARRIER_READ
|
||||
|
||||
Barrier read enabled
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_BARRIER_READ_LSB 12
|
||||
#define CE_STAT_DESC_BARRIER_READ_MSB 12
|
||||
#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description CE_RES_6
|
||||
|
||||
Reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_CE_RES_6_LSB 13
|
||||
#define CE_STAT_DESC_CE_RES_6_MSB 15
|
||||
#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
Sum of all the Lengths of the source descriptor in the gather
|
||||
chain
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000
|
||||
#define CE_STAT_DESC_LENGTH_LSB 16
|
||||
#define CE_STAT_DESC_LENGTH_MSB 31
|
||||
#define CE_STAT_DESC_LENGTH_MASK 0xffff0000
|
||||
|
||||
|
||||
/* Description TOEPLITZ_HASH_0
|
||||
|
||||
32 LS bits of 64 bit Toeplitz LFSR hash result
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description TOEPLITZ_HASH_1
|
||||
|
||||
32 MS bits of 64 bit Toeplitz LFSR hash result
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31
|
||||
#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description FW_METADATA
|
||||
|
||||
Meta data used by FW
|
||||
In case of gather field in first source ring entry of the
|
||||
gather copy cycle in taken into account.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_FW_METADATA_LSB 0
|
||||
#define CE_STAT_DESC_FW_METADATA_MSB 15
|
||||
#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description CE_RES_7
|
||||
|
||||
Reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_CE_RES_7_LSB 16
|
||||
#define CE_STAT_DESC_CE_RES_7_MSB 19
|
||||
#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description RING_ID
|
||||
|
||||
The buffer pointer ring ID.
|
||||
0 refers to the IDLE ring
|
||||
1 - N refers to other rings
|
||||
|
||||
Helps with debugging when dumping ring contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_RING_ID_LSB 20
|
||||
#define CE_STAT_DESC_RING_ID_MSB 27
|
||||
#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into the Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_LSB 28
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_MSB 31
|
||||
#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
#endif // CE_STAT_DESC
|
||||
375
hw/qcn6432/coex_rx_status.h
Archivo normal
375
hw/qcn6432/coex_rx_status.h
Archivo normal
@@ -0,0 +1,375 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COEX_RX_STATUS_H_
|
||||
#define _COEX_RX_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_COEX_RX_STATUS 2
|
||||
|
||||
#define NUM_OF_QWORDS_COEX_RX_STATUS 1
|
||||
|
||||
|
||||
struct coex_rx_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rx_mac_frame_status : 2, // [1:0]
|
||||
rx_with_tx_response : 1, // [2:2]
|
||||
rx_rate : 5, // [7:3]
|
||||
rx_bw : 3, // [10:8]
|
||||
single_mpdu : 1, // [11:11]
|
||||
filter_status : 1, // [12:12]
|
||||
ampdu : 1, // [13:13]
|
||||
directed : 1, // [14:14]
|
||||
reserved_0 : 1, // [15:15]
|
||||
rx_nss : 3, // [18:16]
|
||||
rx_rssi : 8, // [26:19]
|
||||
rx_type : 3, // [29:27]
|
||||
retry_bit_setting : 1, // [30:30]
|
||||
more_data_bit_setting : 1; // [31:31]
|
||||
uint32_t remain_rx_packet_time : 16, // [15:0]
|
||||
rx_remaining_fes_time : 16; // [31:16]
|
||||
#else
|
||||
uint32_t more_data_bit_setting : 1, // [31:31]
|
||||
retry_bit_setting : 1, // [30:30]
|
||||
rx_type : 3, // [29:27]
|
||||
rx_rssi : 8, // [26:19]
|
||||
rx_nss : 3, // [18:16]
|
||||
reserved_0 : 1, // [15:15]
|
||||
directed : 1, // [14:14]
|
||||
ampdu : 1, // [13:13]
|
||||
filter_status : 1, // [12:12]
|
||||
single_mpdu : 1, // [11:11]
|
||||
rx_bw : 3, // [10:8]
|
||||
rx_rate : 5, // [7:3]
|
||||
rx_with_tx_response : 1, // [2:2]
|
||||
rx_mac_frame_status : 2; // [1:0]
|
||||
uint32_t rx_remaining_fes_time : 16, // [31:16]
|
||||
remain_rx_packet_time : 16; // [15:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RX_MAC_FRAME_STATUS
|
||||
|
||||
RXPCU send this bit as 1 when it receives the begin of a
|
||||
frame from PHY, and it passes the address filter. RXPCUsend
|
||||
this bit as 0 when the frame ends. (on/off bit)
|
||||
<enum 0 ppdu_start> start of PPDU reception.
|
||||
For SU: Generated the first time the MPDU header passes
|
||||
the address filter and is destined to this STA.
|
||||
For MU: Generated the first time the MPDU header from any
|
||||
user passes the address filter and is destined to this
|
||||
STA.
|
||||
<enum 1 first_mpdu_FCS_pass> message only sent in case
|
||||
of A-MPDU reception.
|
||||
For SU: first time the FCS of an MPDU passes (and frame
|
||||
is destined to this device)
|
||||
For MU: first time the FCS of any MPDU passes (and frame
|
||||
is destined to this device)
|
||||
|
||||
<enum 2 ppdu_end> receive of PPDU frame reception has
|
||||
finished
|
||||
<enum 3 ppdu_end_due_to_phy_nap> receive of PPDU frame reception
|
||||
has finished as it has been aborted due to PHY NAP generation
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1
|
||||
#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003
|
||||
|
||||
|
||||
/* Description RX_WITH_TX_RESPONSE
|
||||
|
||||
Field only valid when rx_mac_frame_status is first_mpdu_FCS_pass
|
||||
or ppdu_end.
|
||||
|
||||
For SU: RXPCU set this bit to indicate it is expecting the
|
||||
TX to send a response after the receive.
|
||||
For MU: RXPCU set this bit to indicate it is expecting that
|
||||
at least for one of the users a response after the reception
|
||||
needs to be generated.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2
|
||||
#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004
|
||||
|
||||
|
||||
/* Description RX_RATE
|
||||
|
||||
For SU: RXPCU send the current receive rate at the beginning
|
||||
of receive when rate is available from PHY.
|
||||
For MU: RXPCU to use the current receive rate from the first
|
||||
USER that triggers this TLV to be generated.
|
||||
|
||||
Field is always valid
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_RATE_LSB 3
|
||||
#define COEX_RX_STATUS_RX_RATE_MSB 7
|
||||
#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8
|
||||
|
||||
|
||||
/* Description RX_BW
|
||||
|
||||
Actual RX bandwidth. Not SU or MU dependent.
|
||||
RXPCU send the current receive rate at the beginning of
|
||||
receive. This information is from PHY.
|
||||
Field is always valid
|
||||
|
||||
<enum 0 20_mhz>20 Mhz BW
|
||||
<enum 1 40_mhz>40 Mhz BW
|
||||
<enum 2 80_mhz>80 Mhz BW
|
||||
<enum 3 160_mhz>160 Mhz BW
|
||||
<enum 4 320_mhz>320 Mhz BW
|
||||
<enum 5 240_mhz>240 Mhz BW
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_BW_LSB 8
|
||||
#define COEX_RX_STATUS_RX_BW_MSB 10
|
||||
#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700
|
||||
|
||||
|
||||
/* Description SINGLE_MPDU
|
||||
|
||||
For SU: Once set the Received frame is a single MPDU. This
|
||||
can be a non-AMPDU reception or A-MPDU reception but with
|
||||
an EOF bit set (VHT single AMPDU).
|
||||
For MU: RXPCU to base this on the first USER that triggers
|
||||
this TLV to be generated.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11
|
||||
#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800
|
||||
|
||||
|
||||
/* Description FILTER_STATUS
|
||||
|
||||
1: LMAC is interested in receiving the full packet and forward
|
||||
it to downstream modules. 0: LMAC is not interested in
|
||||
receiving the packet.
|
||||
|
||||
Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,'
|
||||
Rx PCU will send this TLV for filtered-out packets as well,
|
||||
with appropriate info in the fields filter_status, AMPDU
|
||||
and Directed. Otherwise, and in other chips, this TLV is
|
||||
sent only for packets filtered in, with these fields set
|
||||
to zero.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_LSB 12
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_MSB 12
|
||||
#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000
|
||||
|
||||
|
||||
/* Description AMPDU
|
||||
|
||||
1: Indicates received frame is an AMPDU0: indicates received
|
||||
frames in not an AMPDU
|
||||
|
||||
Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,'
|
||||
Rx PCU will send this TLV for filtered-out packets as well,
|
||||
with appropriate info in the fields filter_status, AMPDU
|
||||
and Directed. Otherwise, and in other chips, this TLV is
|
||||
sent only for packets filtered in, with these fields set
|
||||
to zero.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_AMPDU_LSB 13
|
||||
#define COEX_RX_STATUS_AMPDU_MSB 13
|
||||
#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000
|
||||
|
||||
|
||||
/* Description DIRECTED
|
||||
|
||||
1: indicates AD1 matches our Receiver address0: indicates
|
||||
AD1 does not match our Receiver address
|
||||
|
||||
Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,'
|
||||
Rx PCU will send this TLV for filtered-out packets as well,
|
||||
with appropriate info in the fields filter_status, AMPDU
|
||||
and Directed. Otherwise, and in other chips, this TLV is
|
||||
sent only for packets filtered in, with these fields set
|
||||
to zero.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_DIRECTED_LSB 14
|
||||
#define COEX_RX_STATUS_DIRECTED_MSB 14
|
||||
#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RESERVED_0_LSB 15
|
||||
#define COEX_RX_STATUS_RESERVED_0_MSB 15
|
||||
#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000
|
||||
|
||||
|
||||
/* Description RX_NSS
|
||||
|
||||
For SU: Number of spatial streams in the reception. Field
|
||||
is always valid
|
||||
For MU: RXPCU to base this on the first USER that triggers
|
||||
this TLV to be generated.
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_NSS_LSB 16
|
||||
#define COEX_RX_STATUS_RX_NSS_MSB 18
|
||||
#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000
|
||||
|
||||
|
||||
/* Description RX_RSSI
|
||||
|
||||
RXPCU send the current receive RSSI (from the PHYRX_RSSI_LEGACY
|
||||
TLV) at the beginning of reception. This is information
|
||||
is from PHY and is not SU or MU dependent.
|
||||
Field is always valid
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_RSSI_LSB 19
|
||||
#define COEX_RX_STATUS_RX_RSSI_MSB 26
|
||||
#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000
|
||||
|
||||
|
||||
/* Description RX_TYPE
|
||||
|
||||
For SU: RXPCU send the current receive packet type. Field
|
||||
is always valid.This info is from MAC.
|
||||
For MU: RXPCU to base this on the first USER that triggers
|
||||
this TLV to be generated.
|
||||
|
||||
<enum 0 data >
|
||||
<enum 1 management>
|
||||
<enum 2 beacon>
|
||||
<enum 3 control> For reception of RTS frame
|
||||
<enum 4 control_response> For reception of CTS, ACK
|
||||
or BA frames
|
||||
<enum 5 others>
|
||||
<legal 0-5>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_TYPE_LSB 27
|
||||
#define COEX_RX_STATUS_RX_TYPE_MSB 29
|
||||
#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000
|
||||
|
||||
|
||||
/* Description RETRY_BIT_SETTING
|
||||
|
||||
For SU: Value of the retry bit in the frame control field
|
||||
of the first MPDU MAC header that passes the RxPCU frame
|
||||
filter
|
||||
For MU: RXPCU to base this on the first USER that triggers
|
||||
this TLV to be generated.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30
|
||||
#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000
|
||||
|
||||
|
||||
/* Description MORE_DATA_BIT_SETTING
|
||||
|
||||
For SU: Value of the more data bit in the frame control
|
||||
field of the first MPDU MAC header that passes the RxPCU
|
||||
frame filter
|
||||
For MU: RXPCU to base this on the first USER that triggers
|
||||
this TLV to be generated.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31
|
||||
#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description REMAIN_RX_PACKET_TIME
|
||||
|
||||
HWSCH sends current remaining rx PPDU frame time. This time
|
||||
covers the entire rx_frame. This information is not in
|
||||
the L-SIG and we expect to get it from PHY at the start
|
||||
of the reception.
|
||||
This is not SU or MU dependent.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47
|
||||
#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RX_REMAINING_FES_TIME
|
||||
|
||||
RXPCU sends the remaining time FES time the moment a frame
|
||||
with proper FCS is received. The time indicated is the
|
||||
remaining rx packet time with the duration field value added.
|
||||
As long as no frame with valid FCS is received, this field
|
||||
should be set equal to 'remain_rx_packet_time'
|
||||
This is not SU or MU dependent.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63
|
||||
#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // COEX_RX_STATUS
|
||||
481
hw/qcn6432/coex_tx_req.h
Archivo normal
481
hw/qcn6432/coex_tx_req.h
Archivo normal
@@ -0,0 +1,481 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _COEX_TX_REQ_H_
|
||||
#define _COEX_TX_REQ_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_COEX_TX_REQ 4
|
||||
|
||||
#define NUM_OF_QWORDS_COEX_TX_REQ 2
|
||||
|
||||
|
||||
struct coex_tx_req {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_pwr : 8, // [7:0]
|
||||
min_tx_pwr : 8, // [15:8]
|
||||
nss : 3, // [18:16]
|
||||
tx_chain_mask : 8, // [26:19]
|
||||
bw : 3, // [29:27]
|
||||
reserved_0 : 2; // [31:30]
|
||||
uint32_t alt_tx_pwr : 8, // [7:0]
|
||||
alt_min_tx_pwr : 8, // [15:8]
|
||||
alt_nss : 3, // [18:16]
|
||||
alt_tx_chain_mask : 8, // [26:19]
|
||||
alt_bw : 3, // [29:27]
|
||||
reserved_1 : 2; // [31:30]
|
||||
uint32_t tx_pwr_1 : 8, // [7:0]
|
||||
alt_tx_pwr_1 : 8, // [15:8]
|
||||
wlan_request_duration : 16; // [31:16]
|
||||
uint32_t wlan_pkt_type : 4, // [3:0]
|
||||
coex_tx_reason : 2, // [5:4]
|
||||
response_frame_type : 5, // [10:6]
|
||||
wlan_low_priority_slicing_allowed : 1, // [11:11]
|
||||
wlan_high_priority_slicing_allowed : 1, // [12:12]
|
||||
sch_tx_burst_ongoing : 1, // [13:13]
|
||||
coex_tx_priority : 4, // [17:14]
|
||||
reserved_3a : 14; // [31:18]
|
||||
#else
|
||||
uint32_t reserved_0 : 2, // [31:30]
|
||||
bw : 3, // [29:27]
|
||||
tx_chain_mask : 8, // [26:19]
|
||||
nss : 3, // [18:16]
|
||||
min_tx_pwr : 8, // [15:8]
|
||||
tx_pwr : 8; // [7:0]
|
||||
uint32_t reserved_1 : 2, // [31:30]
|
||||
alt_bw : 3, // [29:27]
|
||||
alt_tx_chain_mask : 8, // [26:19]
|
||||
alt_nss : 3, // [18:16]
|
||||
alt_min_tx_pwr : 8, // [15:8]
|
||||
alt_tx_pwr : 8; // [7:0]
|
||||
uint32_t wlan_request_duration : 16, // [31:16]
|
||||
alt_tx_pwr_1 : 8, // [15:8]
|
||||
tx_pwr_1 : 8; // [7:0]
|
||||
uint32_t reserved_3a : 14, // [31:18]
|
||||
coex_tx_priority : 4, // [17:14]
|
||||
sch_tx_burst_ongoing : 1, // [13:13]
|
||||
wlan_high_priority_slicing_allowed : 1, // [12:12]
|
||||
wlan_low_priority_slicing_allowed : 1, // [11:11]
|
||||
response_frame_type : 5, // [10:6]
|
||||
coex_tx_reason : 2, // [5:4]
|
||||
wlan_pkt_type : 4; // [3:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description TX_PWR
|
||||
|
||||
Default (desired) transmit parameter
|
||||
|
||||
Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_TX_PWR_LSB 0
|
||||
#define COEX_TX_REQ_TX_PWR_MSB 7
|
||||
#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description MIN_TX_PWR
|
||||
|
||||
Default (desired) transmit parameter
|
||||
|
||||
|
||||
Minimum allowed Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_LSB 8
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_MSB 15
|
||||
#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00
|
||||
|
||||
|
||||
/* Description NSS
|
||||
|
||||
Default (desired) transmit parameter
|
||||
|
||||
Number of spatial streams.
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_NSS_LSB 16
|
||||
#define COEX_TX_REQ_NSS_MSB 18
|
||||
#define COEX_TX_REQ_NSS_MASK 0x0000000000070000
|
||||
|
||||
|
||||
/* Description TX_CHAIN_MASK
|
||||
|
||||
Default (desired) transmit parameter
|
||||
|
||||
|
||||
Chain mask to support up to 8 antennas.
|
||||
<legal 1-255>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26
|
||||
#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000
|
||||
|
||||
|
||||
/* Description BW
|
||||
|
||||
Default (desired) transmit parameter
|
||||
|
||||
The BW of the upcoming transmission.
|
||||
|
||||
<enum 0 20_mhz>20 Mhz BW
|
||||
<enum 1 40_mhz>40 Mhz BW
|
||||
<enum 2 80_mhz>80 Mhz BW
|
||||
<enum 3 160_mhz>160 Mhz BW
|
||||
<enum 4 320_mhz>320 Mhz BW
|
||||
<enum 5 240_mhz>240 Mhz BW
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_BW_LSB 27
|
||||
#define COEX_TX_REQ_BW_MSB 29
|
||||
#define COEX_TX_REQ_BW_MASK 0x0000000038000000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_RESERVED_0_LSB 30
|
||||
#define COEX_TX_REQ_RESERVED_0_MSB 31
|
||||
#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000
|
||||
|
||||
|
||||
/* Description ALT_TX_PWR
|
||||
|
||||
Coex related AlternativeTransmit parameter
|
||||
|
||||
Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_LSB 32
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_MSB 39
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description ALT_MIN_TX_PWR
|
||||
|
||||
Coex related Alternative Transmit parameter
|
||||
|
||||
Minimum allowed Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47
|
||||
#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description ALT_NSS
|
||||
|
||||
Coex related Alternative Transmit parameter
|
||||
|
||||
Number of spatial streams.
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_ALT_NSS_LSB 48
|
||||
#define COEX_TX_REQ_ALT_NSS_MSB 50
|
||||
#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000
|
||||
|
||||
|
||||
/* Description ALT_TX_CHAIN_MASK
|
||||
|
||||
Coex related Alternative Transmit parameter
|
||||
|
||||
Chain mask to support up to 8 antennas.
|
||||
|
||||
<legal 1-255>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58
|
||||
#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
|
||||
|
||||
|
||||
/* Description ALT_BW
|
||||
|
||||
Coex related Alternative Transmit parameter.
|
||||
|
||||
The BW of the upcoming transmission.
|
||||
|
||||
<enum 0 20_mhz>20 Mhz BW
|
||||
<enum 1 40_mhz>40 Mhz BW
|
||||
<enum 2 80_mhz>80 Mhz BW
|
||||
<enum 3 160_mhz>160 Mhz BW
|
||||
<enum 4 320_mhz>320 Mhz BW
|
||||
<enum 5 240_mhz>240 Mhz BW
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_ALT_BW_LSB 59
|
||||
#define COEX_TX_REQ_ALT_BW_MSB 61
|
||||
#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_REQ_RESERVED_1_LSB 62
|
||||
#define COEX_TX_REQ_RESERVED_1_MSB 63
|
||||
#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000
|
||||
|
||||
|
||||
/* Description TX_PWR_1
|
||||
|
||||
Default (desired) transmit parameter for the second chain
|
||||
|
||||
|
||||
Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
|
||||
Note that there is no Min value for this
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_TX_PWR_1_LSB 0
|
||||
#define COEX_TX_REQ_TX_PWR_1_MSB 7
|
||||
#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description ALT_TX_PWR_1
|
||||
|
||||
Alternate (desired) transmit parameter for the second chain
|
||||
|
||||
|
||||
Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
|
||||
Note that there is no Min value for this
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15
|
||||
#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00
|
||||
|
||||
|
||||
/* Description WLAN_REQUEST_DURATION
|
||||
|
||||
The amount of time PDG might use for the upcoming transmission
|
||||
and corresponding reception if there is one...
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31
|
||||
#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description WLAN_PKT_TYPE
|
||||
|
||||
Packet type:
|
||||
<enum 0 dot11a>802.11a PPDU type
|
||||
<enum 1 dot11b>802.11b PPDU type
|
||||
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
|
||||
<enum 3 dot11ac>802.11ac PPDU type
|
||||
<enum 4 dot11ax>802.11ax PPDU type
|
||||
<enum 5 dot11ba>802.11ba (WUR) PPDU type
|
||||
<enum 6 dot11be>802.11be PPDU type
|
||||
<enum 7 dot11az>802.11az (ranging) PPDU type
|
||||
<enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported
|
||||
& aborted)
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35
|
||||
#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000
|
||||
|
||||
|
||||
/* Description COEX_TX_REASON
|
||||
|
||||
<enum 0 cxc_fes_protection_frame> RTS, CTS2Self or
|
||||
11h protection type transmission preceding the regular PPDU
|
||||
portion of the coming FES.
|
||||
<enum 1 cxc_fes_after_protection > Regular PPDU transmission
|
||||
that follows the transmission of medium protection frames:.
|
||||
|
||||
<enum 2 cxc_fes_only> Regular PPDU transmission without
|
||||
preceding medium protection frame exchanges.
|
||||
|
||||
<enum 3 cxc_response_frame>
|
||||
HW generated response frame.
|
||||
Details of the response frame type provided in field: Response_frame_type
|
||||
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_LSB 36
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_MSB 37
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000
|
||||
|
||||
|
||||
/* Description RESPONSE_FRAME_TYPE
|
||||
|
||||
Coex related field
|
||||
<enum 0 Resp_Non_11ah_ACK >
|
||||
<enum 1 Resp_Non_11ah_BA >
|
||||
<enum 2 Resp_Non_11ah_CTS >
|
||||
<enum 3 Resp_AH_NDP_CTS>
|
||||
<enum 4 Resp_AH_NDP_ACK>
|
||||
<enum 5 Resp_AH_NDP_BA>
|
||||
<enum 6 Resp_AH_NDP_MOD_ACK>
|
||||
<enum 7 Resp_AH_Normal_ACK>
|
||||
<enum 8 Resp_AH_Normal_BA>
|
||||
<enum 9 Resp_RTT_ACK>
|
||||
<enum 10 Resp_CBF_RESPONSE>
|
||||
<enum 11 Resp_MBA>
|
||||
<enum 12 Resp_Ranging_NDP>
|
||||
<enum 13 Resp_LMR_RESPONSE>
|
||||
<enum 14 Resp_TRIGGER_RESPONSE_BASIC>
|
||||
<enum 15 Resp_TRIGGER_RESPONSE_BUF_SIZE>
|
||||
<enum 16 Resp_TRIGGER_RESPONSE_BRPOLL>
|
||||
<enum 17 Resp_TRIGGER_RESPONSE_CTS>
|
||||
<enum 18 Resp_TRIGGER_RESPONSE_OTHER>
|
||||
|
||||
<legal 0-18>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000
|
||||
|
||||
|
||||
/* Description WLAN_LOW_PRIORITY_SLICING_ALLOWED
|
||||
|
||||
When set, COEX is allowed to invoke 'tx slicing' algorithms
|
||||
when WLAN tx is low priority when compared to BT activity,
|
||||
to get to more optimal throughput. Value 0 will disable
|
||||
this feature
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000
|
||||
|
||||
|
||||
/* Description WLAN_HIGH_PRIORITY_SLICING_ALLOWED
|
||||
|
||||
When set, COEX is allowed to invoke 'tx slicing' algorithms
|
||||
when WLAN tx is high priority when compared to BT activity,
|
||||
to get to more optimal throughput. Value 0 will disable
|
||||
this feature.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000
|
||||
|
||||
|
||||
/* Description SCH_TX_BURST_ONGOING
|
||||
|
||||
0: No action
|
||||
1: The next scheduling command needs to start at SIFS time
|
||||
after finishing the frame transmissions in this command.
|
||||
This allows for SIFS based bursting
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000
|
||||
|
||||
|
||||
/* Description COEX_TX_PRIORITY
|
||||
|
||||
Transmit priority. Used for Coex weight table look up in
|
||||
case of regular FES transmission. This value is typically
|
||||
programmed in relationship to the backoff engine. In case
|
||||
of self_gen tx, the value comes from a programmable register
|
||||
in the TXPCU. For BA and ACK packets, this is related to
|
||||
AC of the incoming frame. .
|
||||
|
||||
For a request type of "fes", the field is copied over from
|
||||
the scheduling command TLV.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_RESERVED_3A_LSB 50
|
||||
#define COEX_TX_REQ_RESERVED_3A_MSB 63
|
||||
#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000
|
||||
|
||||
|
||||
|
||||
#endif // COEX_TX_REQ
|
||||
340
hw/qcn6432/coex_tx_status.h
Archivo normal
340
hw/qcn6432/coex_tx_status.h
Archivo normal
@@ -0,0 +1,340 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _COEX_TX_STATUS_H_
|
||||
#define _COEX_TX_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_COEX_TX_STATUS 4
|
||||
|
||||
#define NUM_OF_QWORDS_COEX_TX_STATUS 2
|
||||
|
||||
|
||||
struct coex_tx_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 7, // [6:0]
|
||||
tx_bw : 3, // [9:7]
|
||||
tx_status_reason : 3, // [12:10]
|
||||
tx_wait_ack : 1, // [13:13]
|
||||
fes_tx_is_gen_frame : 1, // [14:14]
|
||||
sch_tx_burst_ongoing : 1, // [15:15]
|
||||
current_tx_duration : 16; // [31:16]
|
||||
uint32_t next_rx_active_time : 16, // [15:0]
|
||||
remaining_fes_time : 16; // [31:16]
|
||||
uint32_t tx_antenna_mask : 8, // [7:0]
|
||||
shared_ant_tx_pwr : 8, // [15:8]
|
||||
other_ant_tx_pwr : 8, // [23:16]
|
||||
reserved_2 : 8; // [31:24]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
uint32_t current_tx_duration : 16, // [31:16]
|
||||
sch_tx_burst_ongoing : 1, // [15:15]
|
||||
fes_tx_is_gen_frame : 1, // [14:14]
|
||||
tx_wait_ack : 1, // [13:13]
|
||||
tx_status_reason : 3, // [12:10]
|
||||
tx_bw : 3, // [9:7]
|
||||
reserved_0a : 7; // [6:0]
|
||||
uint32_t remaining_fes_time : 16, // [31:16]
|
||||
next_rx_active_time : 16; // [15:0]
|
||||
uint32_t reserved_2 : 8, // [31:24]
|
||||
other_ant_tx_pwr : 8, // [23:16]
|
||||
shared_ant_tx_pwr : 8, // [15:8]
|
||||
tx_antenna_mask : 8; // [7:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_RESERVED_0A_LSB 0
|
||||
#define COEX_TX_STATUS_RESERVED_0A_MSB 6
|
||||
#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f
|
||||
|
||||
|
||||
/* Description TX_BW
|
||||
|
||||
The BW of the upcoming transmission.
|
||||
Note: Coex might have changed this from the original request.
|
||||
See coex related fields below
|
||||
|
||||
<enum 0 20_mhz>20 Mhz BW
|
||||
<enum 1 40_mhz>40 Mhz BW
|
||||
<enum 2 80_mhz>80 Mhz BW
|
||||
<enum 3 160_mhz>160 Mhz BW
|
||||
<enum 4 320_mhz>320 Mhz BW
|
||||
<enum 5 240_mhz>240 Mhz BW
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_TX_BW_LSB 7
|
||||
#define COEX_TX_STATUS_TX_BW_MSB 9
|
||||
#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380
|
||||
|
||||
|
||||
/* Description TX_STATUS_REASON
|
||||
|
||||
<enum 0 FES_tx_start> TXPCU sends this status at the
|
||||
start of SCH initiated transmission (when the commands
|
||||
are given to the PHY). This includes the transmission of
|
||||
RTS and CTS
|
||||
Note that based on field 'Fes_tx_is_gen_frame' COEX can
|
||||
derive if this is a protection frame or regular PPDU.
|
||||
|
||||
<enum 1 FES_tx_end> TXPCU sends this status at the end
|
||||
of SCH initiated transmission (when PHY TX has confirmed
|
||||
the transmit over the medium has finished)
|
||||
|
||||
<enum 2 FES_end> TXPCU sends this status at the end
|
||||
of of the entire frame exchange sequence. This includes
|
||||
reception (or lack of..) of the ACK/BA/CTS frame
|
||||
TXPCU sends this FES after it has sent the TX_FES_STATUS
|
||||
TLV(s). This also sent in case of 11ax basic trigger response
|
||||
transmissions, when an ACK/BA is expected, and that got
|
||||
received.
|
||||
<enum 3 Response_tx_start> TXPCU sends this status at
|
||||
the start of Self gen initiated response transmission (when
|
||||
the commands are given to the PHY)
|
||||
<enum 4 Response_tx_end> TXPCU sends this status at
|
||||
the end of Self gen initiated response transmission (when
|
||||
PHY TX has confirmed the transmit over the medium has finished)
|
||||
|
||||
|
||||
<enum 5 No_tx_ongoing> TXPCU sends this TLV when forced
|
||||
by SW to do so. It is used to be able to get TXPCU and
|
||||
coex synchronized again in case of some error handling scenarios
|
||||
|
||||
|
||||
<legal 0-5>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00
|
||||
|
||||
|
||||
/* Description TX_WAIT_ACK
|
||||
|
||||
Field can only be set for the 'FES_tx_end' scenario.
|
||||
TXPCU sets this bit to 1 when it is waiting for an ACK/BA
|
||||
or CTS Response.
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000
|
||||
|
||||
|
||||
/* Description FES_TX_IS_GEN_FRAME
|
||||
|
||||
Field only valid in case tx_status_reason indicates FES_tx_start
|
||||
or FES_tx_end.
|
||||
|
||||
Field is set to 1 if the frame transmitted is a self generated
|
||||
frame like RTS, CTS 2 self or NDP
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description SCH_TX_BURST_ONGOING
|
||||
|
||||
The proposed change by HWSCH requires TXPCU to reflect
|
||||
TX_FES_SETUP.sch_tx_burst_ongoing field intoCOEX_TX_STATUS.sch_tx_burst_ongoing
|
||||
field, when tx_status_reason is FES_end.
|
||||
SCH will overwrite this bit (that is set it to 1), when
|
||||
TXPCU set the tx_status_reason to FES_end, and SCH determines
|
||||
that this FES is followed by other SIFS bursting based
|
||||
Scheduler commands.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000
|
||||
|
||||
|
||||
/* Description CURRENT_TX_DURATION
|
||||
|
||||
In case of FES related transmission:
|
||||
TXPCU sends current transmission time at the beginning of
|
||||
transmission. This time covers the entire (PPDU) tx_frame.
|
||||
This field is only valid when 'tx_status_reason' is equal
|
||||
to FES_tx_start or Response_tx_start. In other scenarios
|
||||
it is set to 0
|
||||
In us units <legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description NEXT_RX_ACTIVE_TIME
|
||||
|
||||
In case of FES transmission:
|
||||
The expected receive duration for ACK/CTS/BA frame after
|
||||
current transmission has finished. This field should be
|
||||
set at both the start and end of the transmission. When
|
||||
no frame reception is expected, this field is 0
|
||||
|
||||
In case of Response transmission or Trigger Response transmission:
|
||||
|
||||
The expected receive duration for upcoming reception. This
|
||||
field has the same value as the transmitted duration field.
|
||||
|
||||
|
||||
Note that for this scenario, there might be an other TX
|
||||
generated during this specified time. It is not known to
|
||||
this device what the transmitter is planning to do in the
|
||||
remainder of the TXOP. In other words, this value represents
|
||||
the best guess, but might not be fully accurate.
|
||||
|
||||
In us units
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description REMAINING_FES_TIME
|
||||
|
||||
In case of FES transmission:
|
||||
TXPCU sends the remaining FES time it expects to occupy
|
||||
the media.
|
||||
At the 'FES_tx_start', this value is the current_tx_duration
|
||||
+ value of inserted duration field.
|
||||
At the 'FES_tx_end', this value is equal to the duration
|
||||
field in the just transmitted frame.
|
||||
At the 'FES_end', this value is the remaining FES duration
|
||||
value. Note that this value should only be non zero in
|
||||
case of SIFS burting type of transmissions.
|
||||
In case of a FES failure, like reponse frame not received,
|
||||
this field is set to 0
|
||||
|
||||
In case of Self Gen response transmission (includes Trigger
|
||||
response):
|
||||
At the 'Response_tx_start', this field has the same value
|
||||
as the Current_tx_duration + inserted duration field
|
||||
At the 'Response_tx_end', this field has the same value
|
||||
as the inserted duration field
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description TX_ANTENNA_MASK
|
||||
|
||||
The actual used antennas for this transmission
|
||||
|
||||
For debug purpose only. PDG should not have modified the
|
||||
value given by the Coex.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description SHARED_ANT_TX_PWR
|
||||
|
||||
Actual tx power on the shared antenna
|
||||
TXPCU sends at the beginning of transmission when tx_frame
|
||||
is on.
|
||||
|
||||
For debug purpose only. PDG should not have modified the
|
||||
value given by the Coex.
|
||||
|
||||
Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00
|
||||
|
||||
|
||||
/* Description OTHER_ANT_TX_PWR
|
||||
|
||||
Actual tx power on the 'unshared' antenna(s)
|
||||
TXPCU sends at the beginning of transmission when tx_frame
|
||||
is on.
|
||||
|
||||
For debug purpose only. PDG should not have modified the
|
||||
value given by the Coex.
|
||||
|
||||
Transmit Power in s6.2 format.
|
||||
In units of 0.25 dBm
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000
|
||||
|
||||
|
||||
/* Description RESERVED_2
|
||||
|
||||
Generator should set to 0, consumer shall ignore <legal
|
||||
0>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_RESERVED_2_LSB 24
|
||||
#define COEX_TX_STATUS_RESERVED_2_MSB 31
|
||||
#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_LSB 32
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_MSB 63
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // COEX_TX_STATUS
|
||||
240
hw/qcn6432/com_dtypes.h
Archivo normal
240
hw/qcn6432/com_dtypes.h
Archivo normal
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef COM_DTYPES_H
|
||||
#define COM_DTYPES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* For NT apps we want to use the Win32 definitions and/or those
|
||||
supplied by the Win32 compiler for things like NULL, MAX, MIN
|
||||
abs, labs, etc.
|
||||
*/
|
||||
#ifdef T_WINNT
|
||||
#ifndef WIN32
|
||||
#define WIN32
|
||||
#endif
|
||||
#include <stdlib.h>
|
||||
#endif
|
||||
|
||||
/* ------------------------------------------------------------------------
|
||||
** Constants
|
||||
** ------------------------------------------------------------------------ */
|
||||
|
||||
#ifdef TRUE
|
||||
#undef TRUE
|
||||
#endif
|
||||
|
||||
#ifdef FALSE
|
||||
#undef FALSE
|
||||
#endif
|
||||
|
||||
/** @addtogroup utils_services
|
||||
@{ */
|
||||
|
||||
/** @name Macros for Common Data Types
|
||||
@{ */
|
||||
#define TRUE 1 /**< Boolean TRUE value. */
|
||||
#define FALSE 0 /**< Boolean FALSE value. */
|
||||
|
||||
#define ON 1 /**< ON value. */
|
||||
#define OFF 0 /**< OFF value. */
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0 /**< NULL value. */
|
||||
#endif
|
||||
/** @} */ /* end_name_group Macros for Common Data Types */
|
||||
|
||||
/* -----------------------------------------------------------------------
|
||||
** Standard Types
|
||||
** ----------------------------------------------------------------------- */
|
||||
|
||||
/** @} */ /* end_addtogroup utils_services */
|
||||
|
||||
/* The following definitions are the same across platforms. This first
|
||||
group are the sanctioned types.
|
||||
*/
|
||||
#ifndef _ARM_ASM_
|
||||
#ifndef _BOOLEAN_DEFINED
|
||||
|
||||
/** @addtogroup utils_services
|
||||
@{ */
|
||||
/** Boolean value type.
|
||||
*/
|
||||
typedef unsigned char boolean;
|
||||
#define _BOOLEAN_DEFINED
|
||||
#endif
|
||||
|
||||
/** @cond
|
||||
*/
|
||||
#if defined(DALSTDDEF_H) /* guards against a known re-definer */
|
||||
#define _BOOLEAN_DEFINED
|
||||
#define _UINT32_DEFINED
|
||||
#define _UINT16_DEFINED
|
||||
#define _UINT8_DEFINED
|
||||
#define _INT32_DEFINED
|
||||
#define _INT16_DEFINED
|
||||
#define _INT8_DEFINED
|
||||
#define _UINT64_DEFINED
|
||||
#define _INT64_DEFINED
|
||||
#define _BYTE_DEFINED
|
||||
#endif /* #if !defined(DALSTDDEF_H) */
|
||||
/** @endcond */
|
||||
|
||||
#ifndef _UINT32_DEFINED
|
||||
/** Unsigned 32-bit value.
|
||||
*/
|
||||
typedef unsigned int uint32;
|
||||
#define _UINT32_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT16_DEFINED
|
||||
/** Unsigned 16-bit value.
|
||||
*/
|
||||
typedef unsigned short uint16;
|
||||
#define _UINT16_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _UINT8_DEFINED
|
||||
/** Unsigned 8-bit value.
|
||||
*/
|
||||
typedef unsigned char uint8;
|
||||
#define _UINT8_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _INT32_DEFINED
|
||||
/** Signed 32-bit value.
|
||||
*/
|
||||
typedef signed int int32;
|
||||
#define _INT32_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _INT16_DEFINED
|
||||
/** Signed 16-bit value.
|
||||
*/
|
||||
typedef signed short int16;
|
||||
#define _INT16_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef _INT8_DEFINED
|
||||
/** Signed 8-bit value.
|
||||
*/
|
||||
typedef signed char int8;
|
||||
#define _INT8_DEFINED
|
||||
#endif
|
||||
|
||||
/** @cond
|
||||
*/
|
||||
/* This group are the deprecated types. Their use should be
|
||||
** discontinued and new code should use the types above
|
||||
*/
|
||||
#ifndef _BYTE_DEFINED
|
||||
/** DEPRECATED: Unsigned 8 bit value type.
|
||||
*/
|
||||
typedef unsigned char byte;
|
||||
#define _BYTE_DEFINED
|
||||
#endif
|
||||
|
||||
/** DEPRECATED: Unsinged 16 bit value type.
|
||||
*/
|
||||
typedef unsigned short word;
|
||||
/** DEPRECATED: Unsigned 32 bit value type.
|
||||
*/
|
||||
typedef unsigned long dword;
|
||||
|
||||
/** DEPRECATED: Unsigned 8 bit value type.
|
||||
*/
|
||||
typedef unsigned char uint1;
|
||||
/** DEPRECATED: Unsigned 16 bit value type.
|
||||
*/
|
||||
typedef unsigned short uint2;
|
||||
/** DEPRECATED: Unsigned 32 bit value type.
|
||||
*/
|
||||
typedef unsigned long uint4;
|
||||
|
||||
/** DEPRECATED: Signed 8 bit value type.
|
||||
*/
|
||||
typedef signed char int1;
|
||||
/** DEPRECATED: Signed 16 bit value type.
|
||||
*/
|
||||
typedef signed short int2;
|
||||
/** DEPRECATED: Signed 32 bit value type.
|
||||
*/
|
||||
typedef long int int4;
|
||||
|
||||
/** DEPRECATED: Signed 32 bit value.
|
||||
*/
|
||||
typedef signed long sint31;
|
||||
/** DEPRECATED: Signed 16 bit value.
|
||||
*/
|
||||
typedef signed short sint15;
|
||||
/** DEPRECATED: Signed 8 bit value.
|
||||
*/
|
||||
typedef signed char sint7;
|
||||
|
||||
typedef uint16 UWord16 ;
|
||||
typedef uint32 UWord32 ;
|
||||
typedef int32 Word32 ;
|
||||
typedef int16 Word16 ;
|
||||
typedef uint8 UWord8 ;
|
||||
typedef int8 Word8 ;
|
||||
typedef int32 Vect32 ;
|
||||
/** @endcond */
|
||||
|
||||
#if (! defined T_WINNT) && (! defined __GNUC__)
|
||||
/* Non WinNT Targets */
|
||||
#ifndef _INT64_DEFINED
|
||||
/** Signed 64-bit value.
|
||||
*/
|
||||
typedef long long int64;
|
||||
#define _INT64_DEFINED
|
||||
#endif
|
||||
#ifndef _UINT64_DEFINED
|
||||
/** Unsigned 64-bit value.
|
||||
*/
|
||||
typedef unsigned long long uint64;
|
||||
#define _UINT64_DEFINED
|
||||
#endif
|
||||
#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */
|
||||
/* WINNT or SOLARIS based targets */
|
||||
#if (defined __GNUC__)
|
||||
#ifndef _INT64_DEFINED
|
||||
typedef long long int64;
|
||||
#define _INT64_DEFINED
|
||||
#endif
|
||||
#ifndef _UINT64_DEFINED
|
||||
typedef unsigned long long uint64;
|
||||
#define _UINT64_DEFINED
|
||||
#endif
|
||||
#else
|
||||
typedef __int64 int64; /* Signed 64-bit value */
|
||||
#ifndef _UINT64_DEFINED
|
||||
typedef unsigned __int64 uint64; /* Unsigned 64-bit value */
|
||||
#define _UINT64_DEFINED
|
||||
#endif
|
||||
#endif
|
||||
#endif /* T_WINNT */
|
||||
|
||||
#endif /* _ARM_ASM_ */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/** @} */ /* end_addtogroup utils_services */
|
||||
#endif /* COM_DTYPES_H */
|
||||
219
hw/qcn6432/eht_sig_usr_mu_mimo_info.h
Archivo normal
219
hw/qcn6432/eht_sig_usr_mu_mimo_info.h
Archivo normal
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
#define _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
|
||||
|
||||
|
||||
struct eht_sig_usr_mu_mimo_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_coding : 1, // [15:15]
|
||||
sta_spatial_config : 6, // [21:16]
|
||||
reserved_0a : 1, // [22:22]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
subband80_cc_mask : 8; // [31:24]
|
||||
uint32_t user_order_subband80_0 : 8, // [7:0]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_3 : 8; // [31:24]
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8, // [31:24]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
reserved_0a : 1, // [22:22]
|
||||
sta_spatial_config : 6, // [21:16]
|
||||
sta_coding : 1, // [15:15]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_id : 11; // [10:0]
|
||||
uint32_t user_order_subband80_3 : 8, // [31:24]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_0 : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
0 - 13: MCS 0 - 13
|
||||
14: validate
|
||||
15: MCS 0 with DCM
|
||||
<legal 0-13, 15>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000
|
||||
|
||||
|
||||
/* Description STA_SPATIAL_CONFIG
|
||||
|
||||
Number of assigned spatial streams and their corresponding
|
||||
index.
|
||||
Total number of spatial streams assigned for the MU-MIMO
|
||||
allocation is also signaled.
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this EHT-SIG user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
|
||||
/* Description SUBBAND80_CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channels of what 80 MHz
|
||||
subbands this User field can go to
|
||||
Bit 0: lowest 80 MHz content channel 0
|
||||
Bit 1: lowest 80 MHz content channel 1
|
||||
Bit 2: 2nd lowest 80 MHz content channel 0
|
||||
...
|
||||
Bit 7: highest 80 MHz content channel 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_0
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the lowest
|
||||
80 MHz
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_1
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
lowest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_2
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
highest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_3
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the highest
|
||||
80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
#endif // EHT_SIG_USR_MU_MIMO_INFO
|
||||
250
hw/qcn6432/eht_sig_usr_ofdma_info.h
Archivo normal
250
hw/qcn6432/eht_sig_usr_ofdma_info.h
Archivo normal
@@ -0,0 +1,250 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
#define _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
|
||||
|
||||
|
||||
struct eht_sig_usr_ofdma_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
sta_mcs : 4, // [14:11]
|
||||
validate_0a : 1, // [15:15]
|
||||
nss : 4, // [19:16]
|
||||
txbf : 1, // [20:20]
|
||||
sta_coding : 1, // [21:21]
|
||||
reserved_0b : 1, // [22:22]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
subband80_cc_mask : 8; // [31:24]
|
||||
uint32_t user_order_subband80_0 : 8, // [7:0]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_3 : 8; // [31:24]
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8, // [31:24]
|
||||
rx_integrity_check_passed : 1, // [23:23]
|
||||
reserved_0b : 1, // [22:22]
|
||||
sta_coding : 1, // [21:21]
|
||||
txbf : 1, // [20:20]
|
||||
nss : 4, // [19:16]
|
||||
validate_0a : 1, // [15:15]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_id : 11; // [10:0]
|
||||
uint32_t user_order_subband80_3 : 8, // [31:24]
|
||||
user_order_subband80_2 : 8, // [23:16]
|
||||
user_order_subband80_1 : 8, // [15:8]
|
||||
user_order_subband80_0 : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
0 - 13: MCS 0 - 13
|
||||
14: validate
|
||||
15: MCS 0 with DCM
|
||||
<legal 0-13, 15>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
|
||||
/* Description VALIDATE_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
|
||||
/* Description NSS
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
The actual number of streams is 1 larger than indicated
|
||||
in this field.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this EHT-SIG user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
|
||||
/* Description SUBBAND80_CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channels of what 80 MHz
|
||||
subbands this User field can go to
|
||||
Bit 0: lowest 80 MHz content channel 0
|
||||
Bit 1: lowest 80 MHz content channel 1
|
||||
Bit 2: 2nd lowest 80 MHz content channel 0
|
||||
...
|
||||
Bit 7: highest 80 MHz content channel 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_0
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the lowest
|
||||
80 MHz
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_1
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
lowest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_2
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
highest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_3
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the highest
|
||||
80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
#endif // EHT_SIG_USR_OFDMA_INFO
|
||||
159
hw/qcn6432/eht_sig_usr_su_info.h
Archivo normal
159
hw/qcn6432/eht_sig_usr_su_info.h
Archivo normal
@@ -0,0 +1,159 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _EHT_SIG_USR_SU_INFO_H_
|
||||
#define _EHT_SIG_USR_SU_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
|
||||
|
||||
|
||||
struct eht_sig_usr_su_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
sta_mcs : 4, // [14:11]
|
||||
validate_0a : 1, // [15:15]
|
||||
nss : 4, // [19:16]
|
||||
txbf : 1, // [20:20]
|
||||
sta_coding : 1, // [21:21]
|
||||
reserved_0b : 9, // [30:22]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_0b : 9, // [30:22]
|
||||
sta_coding : 1, // [21:21]
|
||||
txbf : 1, // [20:20]
|
||||
nss : 4, // [19:16]
|
||||
validate_0a : 1, // [15:15]
|
||||
sta_mcs : 4, // [14:11]
|
||||
sta_id : 11; // [10:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
0 - 13: MCS 0 - 13
|
||||
14: MCS 0 with DCM and 2x duplicate
|
||||
15: MCS 0 with DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
|
||||
/* Description VALIDATE_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
|
||||
/* Description NSS
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
The actual number of streams is 1 larger than indicated
|
||||
in this field.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this EHT-SIG user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // EHT_SIG_USR_SU_INFO
|
||||
700
hw/qcn6432/expected_response.h
Archivo normal
700
hw/qcn6432/expected_response.h
Archivo normal
@@ -0,0 +1,700 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _EXPECTED_RESPONSE_H_
|
||||
#define _EXPECTED_RESPONSE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6
|
||||
|
||||
#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3
|
||||
|
||||
|
||||
struct expected_response {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_ad2_31_0 : 32; // [31:0]
|
||||
uint32_t tx_ad2_47_32 : 16, // [15:0]
|
||||
expected_response_type : 5, // [20:16]
|
||||
response_to_response : 3, // [23:21]
|
||||
su_ba_user_number : 1, // [24:24]
|
||||
response_info_part2_required : 1, // [25:25]
|
||||
transmitted_bssid_check_en : 1, // [26:26]
|
||||
reserved_1 : 5; // [31:27]
|
||||
uint32_t ndp_sta_partial_aid_2_8_0 : 11, // [10:0]
|
||||
reserved_2 : 10, // [20:11]
|
||||
ndp_sta_partial_aid1_8_0 : 11; // [31:21]
|
||||
uint32_t ast_index : 16, // [15:0]
|
||||
capture_ack_ba_sounding : 1, // [16:16]
|
||||
capture_sounding_1str_20mhz : 1, // [17:17]
|
||||
capture_sounding_1str_40mhz : 1, // [18:18]
|
||||
capture_sounding_1str_80mhz : 1, // [19:19]
|
||||
capture_sounding_1str_160mhz : 1, // [20:20]
|
||||
capture_sounding_1str_240mhz : 1, // [21:21]
|
||||
capture_sounding_1str_320mhz : 1, // [22:22]
|
||||
reserved_3a : 9; // [31:23]
|
||||
uint32_t fcs : 9, // [8:0]
|
||||
reserved_4a : 1, // [9:9]
|
||||
crc : 4, // [13:10]
|
||||
scrambler_seed : 7, // [20:14]
|
||||
reserved_4b : 11; // [31:21]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
uint32_t tx_ad2_31_0 : 32; // [31:0]
|
||||
uint32_t reserved_1 : 5, // [31:27]
|
||||
transmitted_bssid_check_en : 1, // [26:26]
|
||||
response_info_part2_required : 1, // [25:25]
|
||||
su_ba_user_number : 1, // [24:24]
|
||||
response_to_response : 3, // [23:21]
|
||||
expected_response_type : 5, // [20:16]
|
||||
tx_ad2_47_32 : 16; // [15:0]
|
||||
uint32_t ndp_sta_partial_aid1_8_0 : 11, // [31:21]
|
||||
reserved_2 : 10, // [20:11]
|
||||
ndp_sta_partial_aid_2_8_0 : 11; // [10:0]
|
||||
uint32_t reserved_3a : 9, // [31:23]
|
||||
capture_sounding_1str_320mhz : 1, // [22:22]
|
||||
capture_sounding_1str_240mhz : 1, // [21:21]
|
||||
capture_sounding_1str_160mhz : 1, // [20:20]
|
||||
capture_sounding_1str_80mhz : 1, // [19:19]
|
||||
capture_sounding_1str_40mhz : 1, // [18:18]
|
||||
capture_sounding_1str_20mhz : 1, // [17:17]
|
||||
capture_ack_ba_sounding : 1, // [16:16]
|
||||
ast_index : 16; // [15:0]
|
||||
uint32_t reserved_4b : 11, // [31:21]
|
||||
scrambler_seed : 7, // [20:14]
|
||||
crc : 4, // [13:10]
|
||||
reserved_4a : 1, // [9:9]
|
||||
fcs : 9; // [8:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description TX_AD2_31_0
|
||||
|
||||
Lower 32 bits of the transmitter address (AD2) of the last
|
||||
packet which was transmitted, which is used by RXPCU in
|
||||
Proxy STA mode.
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description TX_AD2_47_32
|
||||
|
||||
Upper 16 bits of the transmitter address (AD2) of the last
|
||||
packet which was transmitted, which is used by RXPCU in
|
||||
Proxy STA mode.
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description EXPECTED_RESPONSE_TYPE
|
||||
|
||||
Provides insight for RXPCU of what type of response is expected
|
||||
in the medium.
|
||||
|
||||
Mainly used for debugging purposes.
|
||||
|
||||
No matter what RXPCU receives, it shall always report it
|
||||
to TXPCU.
|
||||
|
||||
Only special scenario where RXPCU will have to generate
|
||||
a RECEIVED_RESPONSE_INFO TLV , even when no actual MPDU
|
||||
with passing FCS was received is when the response_type
|
||||
is set to: frameless_phyrx_response_accepted
|
||||
|
||||
<enum 0 no_response_expected>After transmission of this
|
||||
frame, no response in SIFS time is expected
|
||||
|
||||
When TXPCU sees this setting, it shall not generated the
|
||||
EXPECTED_RESPONSE TLV.
|
||||
|
||||
RXPCU should never see this setting
|
||||
<enum 1 ack_expected>An ACK frame is expected as response
|
||||
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 2 ba_64_bitmap_expected>BA with 64 bitmap is expected.
|
||||
|
||||
|
||||
PDG DOES NOT use the size info to calculated response duration.
|
||||
The length of the response will have to be programmed by
|
||||
SW in the per-BW 'Expected_ppdu_resp_length' field.
|
||||
|
||||
For TXPCU only the fact that it is a BA is important. Actual
|
||||
received BA size is not important
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 3 ba_256_expected>BA with 256 bitmap is expected.
|
||||
|
||||
PDG DOES NOT use the size info to calculated response duration.
|
||||
The length of the response will have to be programmed by
|
||||
SW in the per-BW 'Expected_ppdu_resp_length' field.
|
||||
|
||||
For TXPCU only the fact that it is a BA is important. Actual
|
||||
received BA size is not important
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 4 actionnoack_expected>SW sets this after sending
|
||||
NDP or BR-Poll.
|
||||
|
||||
As PDG has no idea on how long the reception is going to
|
||||
be, the reception time of the response will have to be
|
||||
programmed by SW in the 'Extend_duration_value_bw...' field
|
||||
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 5 ack_ba_expected>PDG uses the size info and assumes
|
||||
single BA format with ACK and 64 bitmap embedded.
|
||||
If SW expects more bitmaps in case of multi-TID, is shall
|
||||
program the 'Extend_duration_value_bw...' field for additional
|
||||
duration time.
|
||||
For TXPCU only the fact that an ACK and/or BA is received
|
||||
is important. Reception of only ACK or BA is also considered
|
||||
a success.
|
||||
SW also typically sets this when sending VHT single MPDU.
|
||||
Some chip vendors might send BA rather than ACK in response
|
||||
to VHT single MPDU but still we want to accept BA as well.
|
||||
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 6 cts_expected>SW sets this after queuing RTS frame
|
||||
as standalone packet and sending it.
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 7 ack_data_expected>SW sets this after sending PS-Poll.
|
||||
|
||||
|
||||
For TXPCU either ACK and/or data reception is considered
|
||||
success.
|
||||
PDG basis it's response duration calculation on an ACK.
|
||||
For the data portion, SW shall program the 'Extend_duration_value_bw...'
|
||||
field
|
||||
<enum 8 ndp_ack_expected>Reserved for 11ah usage.
|
||||
<enum 9 ndp_modified_ack>Reserved for 11ah usage
|
||||
<enum 10 ndp_ba_expected>Reserved for 11ah usage.
|
||||
<enum 11 ndp_cts_expected>Reserved for 11ah usage
|
||||
<enum 12 ndp_ack_or_ndp_modified_ack_expected>Reserved for
|
||||
11ah usage
|
||||
|
||||
TXPCU expects UL MU OFDMA or UL MU MIMO reception.
|
||||
As PDG does not know how RUs are assigned for the uplink
|
||||
portion, PDG can not calculate the uplink duration. Therefor
|
||||
SW shall program the 'Extend_duration_value_bw...' field
|
||||
|
||||
|
||||
RXPCU will report any frame received, irrespective of it
|
||||
having been UL MU or SU It is TXPCUs responsibility to
|
||||
distinguish between the UL MU or SU
|
||||
|
||||
TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap
|
||||
if indeed BA was received
|
||||
|
||||
TXPCU expects UL MU OFDMA or UL MU MIMO reception.
|
||||
As PDG does not know how RUs are assigned for the uplink
|
||||
portion, PDG can not calculate the uplink duration. Therefor
|
||||
SW shall program the 'Extend_duration_value_bw...' field
|
||||
|
||||
|
||||
RXPCU will report any frame received, irrespective of it
|
||||
having been UL MU or SU It is TXPCUs responsibility to
|
||||
distinguish between the UL MU or SU
|
||||
|
||||
TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap
|
||||
and MU_Response_BA_bitmap if indeed BA and data was received
|
||||
|
||||
When selected, CBF frames are expected to be received in
|
||||
MU reception (uplink OFDMA or uplink MIMO)
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received
|
||||
TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap
|
||||
if indeed CBF frames were received.
|
||||
<enum 16 ul_mu_frames_expected>When selected, MPDU frames
|
||||
are expected in the MU reception (uplink OFDMA or uplink
|
||||
MIMO)
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received
|
||||
|
||||
TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap
|
||||
if indeed frames were received.
|
||||
<enum 17 any_response_to_this_device>Any response expected
|
||||
to be send to this device in SIFS time is acceptable.
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received
|
||||
|
||||
For TXPCU, UL MU or SU is both acceptable.
|
||||
|
||||
Can be used for complex OFDMA scenarios. PDG can not calculate
|
||||
the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...'
|
||||
field
|
||||
<enum 18 any_response_accepted>Any frame in the medium to
|
||||
this or any other device, is acceptable as response.
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received
|
||||
|
||||
For TXPCU, UL MU or SU is both acceptable.
|
||||
|
||||
Can be used for complex OFDMA scenarios. PDG can not calculate
|
||||
the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...'
|
||||
field
|
||||
<enum 19 frameless_phyrx_response_accepted>Any MU frameless
|
||||
reception generated by the PHY is acceptable.
|
||||
|
||||
PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY,
|
||||
field Reception_type == reception_is_frameless
|
||||
|
||||
RXPCU will report any frame received, irrespective of it
|
||||
having been UL MU or SU.
|
||||
|
||||
This can be used for complex MU-MIMO or OFDMA scenarios,
|
||||
like receiving MU-CTS.
|
||||
|
||||
PDG can not calculate the uplink duration. Therefor SW shall
|
||||
program the 'Extend_duration_value_bw...' field
|
||||
<enum 20 ranging_ndp_and_lmr_expected>SW sets this after
|
||||
sending ranging NDPA followed by NDP as an ISTA and NDP
|
||||
and LMR (Action No Ack) are expected as back-to-back reception
|
||||
in SIFS.
|
||||
|
||||
As PDG has no idea on how long the reception is going to
|
||||
be, the reception time of the response will have to be
|
||||
programmed by SW in the 'Extend_duration_value_bw...' field
|
||||
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 21 ba_512_expected>BA with 512 bitmap is expected.
|
||||
|
||||
|
||||
PDG DOES NOT use the size info to calculated response duration.
|
||||
The length of the response will have to be programmed by
|
||||
SW in the per-BW 'Expected_ppdu_resp_length' field.
|
||||
|
||||
For TXPCU only the fact that it is a BA is important. Actual
|
||||
received BA size is not important
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 22 ba_1024_expected>BA with 1024 bitmap is expected.
|
||||
|
||||
|
||||
PDG DOES NOT use the size info to calculated response duration.
|
||||
The length of the response will have to be programmed by
|
||||
SW in the per-BW 'Expected_ppdu_resp_length' field.
|
||||
|
||||
For TXPCU only the fact that it is a BA is important. Actual
|
||||
received BA size is not important
|
||||
|
||||
RXPCU is just expecting any response. It is TXPCU who checks
|
||||
that the right response was received.
|
||||
<enum 23 ul_mu_ranging_cts2s_expected>When selected, CTS2S
|
||||
frames are expected to be received in MU reception (uplink
|
||||
OFDMA)
|
||||
|
||||
RXPCU shall check each response for CTS2S and report to
|
||||
TXPCU.
|
||||
|
||||
TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields
|
||||
'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S
|
||||
frames were received.
|
||||
<enum 24 ul_mu_ranging_ndp_expected>When selected, UL NDP
|
||||
frames are expected to be received in MU reception (uplink
|
||||
spatial multiplexing)
|
||||
|
||||
RXPCU shall check each response for NDP and report to TXPCU.
|
||||
|
||||
|
||||
TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields
|
||||
'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP
|
||||
frames were received.
|
||||
<enum 25 ul_mu_ranging_lmr_expected>When selected, LMR frames
|
||||
are expected to be received in MU reception (uplink OFDMA
|
||||
or uplink MIMO)
|
||||
|
||||
RXPCU shall check each response for LMR and report to TXPCU.
|
||||
|
||||
|
||||
TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields
|
||||
'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR
|
||||
frames were received.
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000
|
||||
|
||||
|
||||
/* Description RESPONSE_TO_RESPONSE
|
||||
|
||||
Field indicates if after receiving the PPDU response (indicated
|
||||
in the field above), TXPCU is expected to generate a reponse
|
||||
to the response
|
||||
|
||||
In case a response to response is expected, RXPCU shall
|
||||
first acknowledge the proper reception of the received frames,
|
||||
so that TXPCU can first wrapup that portion of the FES.
|
||||
|
||||
<enum 0 None> No response after response allowed.
|
||||
<enum 1 SU_BA> The response after response that TXPCU is
|
||||
allowed to generate is a single BA. Even if RXPCU is indicating
|
||||
that multiple users are received, TXPCU shall only send
|
||||
a BA for 1 STA. Response_to_response rates can be found
|
||||
in fields 'response_to_response_rate_info_bw...'
|
||||
<enum 2 MU_BA> The response after response that TXPCU is
|
||||
allowed to generate is only Multi Destination Multi User
|
||||
BA. Response_to_response rates can be found in fields 'response_to_response_rate_info_bw...'
|
||||
|
||||
|
||||
<enum 3 RESPONSE_TO_RESPONSE_CMD> A response to response
|
||||
is expected to be generated. In other words, RXPCU will
|
||||
likely indicate to TXPCU at the end of upcoming reception
|
||||
that a response is needed. TXPCU is however to ignore this
|
||||
indication from RXPCU, and assume for a moment that no
|
||||
response to response is needed, as all the details on how
|
||||
to handle this is provided in the next scheduling command,
|
||||
which is marked as a 'response_to_response' type.
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000
|
||||
|
||||
|
||||
/* Description SU_BA_USER_NUMBER
|
||||
|
||||
Field only valid when Response_to_response is SU_BA
|
||||
|
||||
Indicates the user number of which the BA will be send after
|
||||
receiving the uplink OFDMA.
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000
|
||||
|
||||
|
||||
/* Description RESPONSE_INFO_PART2_REQUIRED
|
||||
|
||||
Field only valid when Response_type is NOT set to No_response_expected
|
||||
|
||||
|
||||
When set to 1, RXPCU shall generate the RECEIVED_RESPONSE_INFO_PART2
|
||||
TLV after having received the response frame. TXPCU shall
|
||||
wait for this TLV before sending the TX_FES_STATUS_END
|
||||
TLV.
|
||||
|
||||
When NOT set, RXPCU shall NOT generate the above mentioned
|
||||
TLV. TXPCU shall not wait for this TLV and after having
|
||||
received RECEIVED_RESPONSE_INFO TLV, it can immediately
|
||||
generate the TX_FES_STATUS_END TLV.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000
|
||||
|
||||
|
||||
/* Description TRANSMITTED_BSSID_CHECK_EN
|
||||
|
||||
When set to 1, RXPCU shall assume group addressed frame
|
||||
with Tx_AD2 equal to TBSSID was sent. RxPCU should properly
|
||||
handle receive frame(s) from STA(s) which A1 is TBSSID
|
||||
or any VAPs.When NOT set, RXPCU shall compare received frame's
|
||||
A1 with Tx_AD2 only.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_LSB 59
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_MSB 63
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000
|
||||
|
||||
|
||||
/* Description NDP_STA_PARTIAL_AID_2_8_0
|
||||
|
||||
This field is applicable only in 11ah mode of operation.
|
||||
This field carries the information needed for RxPCU to qualify
|
||||
valid NDP-CTS
|
||||
|
||||
When an RTS is being transmitted, this field provides the
|
||||
partial AID of STA/BSSID of the transmitter,so the received
|
||||
RA/BSSID of the NDP CTS response frame can be compared
|
||||
to validate it. This value is provided by SW for valiadating
|
||||
the NDP CTS.
|
||||
|
||||
This filed also carries information for TA of the NDP Modified
|
||||
ACK when an NDP PS-Poll is transmitted.
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description RESERVED_2
|
||||
|
||||
Reserved: Generator should set to 0, consumer shall ignore
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_LSB 11
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_MSB 20
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800
|
||||
|
||||
|
||||
/* Description NDP_STA_PARTIAL_AID1_8_0
|
||||
|
||||
This field is applicable only in 11ah mode of operation.
|
||||
This field carries the information needed for RxPCU to qualify
|
||||
valid NDP Modified ACK
|
||||
|
||||
TxPCU provides the partial AID (RA) of the NDP PS-Poll frame.
|
||||
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000
|
||||
|
||||
|
||||
/* Description AST_INDEX
|
||||
|
||||
The AST index of the receive Ack/BA. This information is
|
||||
provided from the TXPCU to the RXPCU for receive Ack/BA.
|
||||
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_LSB 32
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_MSB 47
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description CAPTURE_ACK_BA_SOUNDING
|
||||
|
||||
If set enables capture of 1str and 2str sounding on Ack
|
||||
or BA as long as the corresponding capture_sounding_1str_##mhz
|
||||
bits is set.
|
||||
|
||||
If clear the capture of sounding on Ack or BA is disabled
|
||||
even if the corresponding capture_sounding_1str_##mhz is
|
||||
set.
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000
|
||||
|
||||
|
||||
/* Description CAPTURE_SOUNDING_1STR_20MHZ
|
||||
|
||||
Capture sounding for 1 stream 20 MHz receive packets
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000
|
||||
|
||||
|
||||
/* Description CAPTURE_SOUNDING_1STR_40MHZ
|
||||
|
||||
Capture sounding for 1 stream 40 MHz receive packets
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000
|
||||
|
||||
|
||||
/* Description CAPTURE_SOUNDING_1STR_80MHZ
|
||||
|
||||
Capture sounding for 1 stream 80 MHz receive packets
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000
|
||||
|
||||
|
||||
/* Description CAPTURE_SOUNDING_1STR_160MHZ
|
||||
|
||||
Capture sounding for 1 stream 160 MHz receive packets
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000
|
||||
|
||||
|
||||
/* Description CAPTURE_SOUNDING_1STR_240MHZ
|
||||
|
||||
Capture sounding for 1 stream 240 MHz receive packets
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000
|
||||
|
||||
|
||||
/* Description CAPTURE_SOUNDING_1STR_320MHZ
|
||||
|
||||
Capture sounding for 1 stream 320 MHz receive packets
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
Reserved: Generator should set to 0, consumer shall ignore
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000
|
||||
|
||||
|
||||
/* Description FCS
|
||||
|
||||
Tx Frame's FCS[31:23]
|
||||
|
||||
TODO: describe what this is used for ...
|
||||
|
||||
For aggregates and NDP frames, this field is reserved and
|
||||
TxPCU should populate this to Zero.
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_FCS_LSB 0
|
||||
#define EXPECTED_RESPONSE_FCS_MSB 8
|
||||
#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff
|
||||
|
||||
|
||||
/* Description RESERVED_4A
|
||||
|
||||
Reserved: Generator should set to 0, consumer shall ignore
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
TODO: describe what this is used for ...
|
||||
|
||||
Tx SIG's CRC[3:0]
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_CRC_LSB 10
|
||||
#define EXPECTED_RESPONSE_CRC_MSB 13
|
||||
#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00
|
||||
|
||||
|
||||
/* Description SCRAMBLER_SEED
|
||||
|
||||
TODO: describe what this is used for ...
|
||||
|
||||
Tx Frames SERVICE[6:0]
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000
|
||||
|
||||
|
||||
/* Description RESERVED_4B
|
||||
|
||||
Reserved: Generator should set to 0, consumer shall ignore
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // EXPECTED_RESPONSE
|
||||
418
hw/qcn6432/he_sig_a_mu_dl_info.h
Archivo normal
418
hw/qcn6432/he_sig_a_mu_dl_info.h
Archivo normal
@@ -0,0 +1,418 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HE_SIG_A_MU_DL_INFO_H_
|
||||
#define _HE_SIG_A_MU_DL_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
|
||||
|
||||
|
||||
struct he_sig_a_mu_dl_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t dl_ul_flag : 1, // [0:0]
|
||||
mcs_of_sig_b : 3, // [3:1]
|
||||
dcm_of_sig_b : 1, // [4:4]
|
||||
bss_color_id : 6, // [10:5]
|
||||
spatial_reuse : 4, // [14:11]
|
||||
transmit_bw : 3, // [17:15]
|
||||
num_sig_b_symbols : 4, // [21:18]
|
||||
comp_mode_sig_b : 1, // [22:22]
|
||||
cp_ltf_size : 2, // [24:23]
|
||||
doppler_indication : 1, // [25:25]
|
||||
reserved_0a : 6; // [31:26]
|
||||
uint32_t txop_duration : 7, // [6:0]
|
||||
reserved_1a : 1, // [7:7]
|
||||
num_ltf_symbols : 3, // [10:8]
|
||||
ldpc_extra_symbol : 1, // [11:11]
|
||||
stbc : 1, // [12:12]
|
||||
packet_extension_a_factor : 2, // [14:13]
|
||||
packet_extension_pe_disambiguity : 1, // [15:15]
|
||||
crc : 4, // [19:16]
|
||||
tail : 6, // [25:20]
|
||||
reserved_1b : 5, // [30:26]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t reserved_0a : 6, // [31:26]
|
||||
doppler_indication : 1, // [25:25]
|
||||
cp_ltf_size : 2, // [24:23]
|
||||
comp_mode_sig_b : 1, // [22:22]
|
||||
num_sig_b_symbols : 4, // [21:18]
|
||||
transmit_bw : 3, // [17:15]
|
||||
spatial_reuse : 4, // [14:11]
|
||||
bss_color_id : 6, // [10:5]
|
||||
dcm_of_sig_b : 1, // [4:4]
|
||||
mcs_of_sig_b : 3, // [3:1]
|
||||
dl_ul_flag : 1; // [0:0]
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_1b : 5, // [30:26]
|
||||
tail : 6, // [25:20]
|
||||
crc : 4, // [19:16]
|
||||
packet_extension_pe_disambiguity : 1, // [15:15]
|
||||
packet_extension_a_factor : 2, // [14:13]
|
||||
stbc : 1, // [12:12]
|
||||
ldpc_extra_symbol : 1, // [11:11]
|
||||
num_ltf_symbols : 3, // [10:8]
|
||||
reserved_1a : 1, // [7:7]
|
||||
txop_duration : 7; // [6:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
NOTE: This is unsupported for "HE MU" format (including "MU_SU")
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0
|
||||
#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001
|
||||
|
||||
|
||||
/* Description MCS_OF_SIG_B
|
||||
|
||||
Indicates the MCS of HE-SIG-B
|
||||
<legal 0-5>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3
|
||||
#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e
|
||||
|
||||
|
||||
/* Description DCM_OF_SIG_B
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
to HE-SIG-B
|
||||
|
||||
0: No DCM for HE_SIG_B
|
||||
1: DCM for HE_SIG_B
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4
|
||||
#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10
|
||||
#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
For 20MHz one SR field corresponding to entire 20MHz (other
|
||||
3 fields indicate identical values)
|
||||
For 40MHz two SR fields for each 20MHz (other 2 fields indicate
|
||||
identical values)
|
||||
For 80MHz four SR fields for each 20MHz
|
||||
For 160MHz four SR fields for each 40MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14
|
||||
#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
<enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble puncturing
|
||||
mode
|
||||
<enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz non-preamble
|
||||
puncturing mode
|
||||
<enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble puncturing
|
||||
in 80 MHz, where in the preamble only the secondary 20
|
||||
MHz is punctured
|
||||
<enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for preamble
|
||||
puncturing in 80 MHz, where in the preamble only one of
|
||||
the two 20 MHz sub-channels in secondary 40 MHz is punctured.
|
||||
|
||||
<enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble puncturing
|
||||
in 160 MHz or 80+80 MHz, where in the primary 80 MHz of
|
||||
the preamble only the secondary 20 MHz is punctured.
|
||||
<enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for preamble
|
||||
puncturing in 160 MHz or 80+80 MHz, where in the primary
|
||||
80 MHz of the preamble the primary 40 MHz is present.
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal 0-7>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17
|
||||
#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000
|
||||
|
||||
|
||||
/* Description NUM_SIG_B_SYMBOLS
|
||||
|
||||
Number of symbols
|
||||
|
||||
For OFDMA, the actual number of symbols is 1 larger then
|
||||
indicated in this field.
|
||||
|
||||
For MU-MIMO this is equal to the number of users - 1: the
|
||||
following encoding is used:
|
||||
1 => 2 users
|
||||
2 => 3 users
|
||||
Etc.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
|
||||
|
||||
|
||||
/* Description COMP_MODE_SIG_B
|
||||
|
||||
Indicates the compression mode of HE-SIG-B
|
||||
|
||||
0: Regular [uncomp mode]
|
||||
1: compressed mode (full-BW MU-MIMO only)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22
|
||||
#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000
|
||||
|
||||
|
||||
/* Description CP_LTF_SIZE
|
||||
|
||||
Indicates the CP and HE-LTF type
|
||||
|
||||
<enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
|
||||
<enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
|
||||
<enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
|
||||
<enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24
|
||||
#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000
|
||||
|
||||
|
||||
/* Description DOPPLER_INDICATION
|
||||
|
||||
0: No Doppler support
|
||||
1: Doppler support
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25
|
||||
#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6
|
||||
#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080
|
||||
|
||||
|
||||
/* Description NUM_LTF_SYMBOLS
|
||||
|
||||
Indicates the number of HE-LTF symbols
|
||||
|
||||
0: 1 LTF
|
||||
1: 2 LTFs
|
||||
2: 4 LTFs
|
||||
3: 6 LTFs
|
||||
4: 8 LTFs
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10
|
||||
#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
If LDPC,
|
||||
0: LDPC extra symbol not present
|
||||
1: LDPC extra symbol present
|
||||
Else
|
||||
Set to 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11
|
||||
#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Indicates whether STBC is applied
|
||||
0: No STBC
|
||||
1: STBC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12
|
||||
#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_A_FACTOR
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with these two bits indicating the "a-factor"
|
||||
|
||||
<enum 0 a_factor_4>
|
||||
<enum 1 a_factor_1>
|
||||
<enum 2 a_factor_2>
|
||||
<enum 3 a_factor_3>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_PE_DISAMBIGUITY
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with this bit indicating the PE-Disambiguity
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
|
||||
#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19
|
||||
#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25
|
||||
#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30
|
||||
#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // HE_SIG_A_MU_DL_INFO
|
||||
215
hw/qcn6432/he_sig_a_mu_ul_info.h
Archivo normal
215
hw/qcn6432/he_sig_a_mu_ul_info.h
Archivo normal
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HE_SIG_A_MU_UL_INFO_H_
|
||||
#define _HE_SIG_A_MU_UL_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
|
||||
|
||||
|
||||
struct he_sig_a_mu_ul_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t format_indication : 1, // [0:0]
|
||||
bss_color_id : 6, // [6:1]
|
||||
spatial_reuse : 16, // [22:7]
|
||||
reserved_0a : 1, // [23:23]
|
||||
transmit_bw : 2, // [25:24]
|
||||
reserved_0b : 6; // [31:26]
|
||||
uint32_t txop_duration : 7, // [6:0]
|
||||
reserved_1a : 9, // [15:7]
|
||||
crc : 4, // [19:16]
|
||||
tail : 6, // [25:20]
|
||||
reserved_1b : 5, // [30:26]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t reserved_0b : 6, // [31:26]
|
||||
transmit_bw : 2, // [25:24]
|
||||
reserved_0a : 1, // [23:23]
|
||||
spatial_reuse : 16, // [22:7]
|
||||
bss_color_id : 6, // [6:1]
|
||||
format_indication : 1; // [0:0]
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_1b : 5, // [30:26]
|
||||
tail : 6, // [25:20]
|
||||
crc : 4, // [19:16]
|
||||
reserved_1a : 9, // [15:7]
|
||||
txop_duration : 7; // [6:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description FORMAT_INDICATION
|
||||
|
||||
Indicates whether the transmission is SU PPDU or a trigger
|
||||
based UL MU PDDU
|
||||
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
|
||||
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6
|
||||
#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22
|
||||
#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
<enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
|
||||
<enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25
|
||||
#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6
|
||||
#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Set to value indicated in the trigger frame
|
||||
<legal 255>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
This CRC may also cover some fields of L-SIG (TBD)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19
|
||||
#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
|
||||
used
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25
|
||||
#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30
|
||||
#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // HE_SIG_A_MU_UL_INFO
|
||||
540
hw/qcn6432/he_sig_a_su_info.h
Archivo normal
540
hw/qcn6432/he_sig_a_su_info.h
Archivo normal
@@ -0,0 +1,540 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HE_SIG_A_SU_INFO_H_
|
||||
#define _HE_SIG_A_SU_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
|
||||
|
||||
|
||||
struct he_sig_a_su_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t format_indication : 1, // [0:0]
|
||||
beam_change : 1, // [1:1]
|
||||
dl_ul_flag : 1, // [2:2]
|
||||
transmit_mcs : 4, // [6:3]
|
||||
dcm : 1, // [7:7]
|
||||
bss_color_id : 6, // [13:8]
|
||||
reserved_0a : 1, // [14:14]
|
||||
spatial_reuse : 4, // [18:15]
|
||||
transmit_bw : 2, // [20:19]
|
||||
cp_ltf_size : 2, // [22:21]
|
||||
nsts : 3, // [25:23]
|
||||
reserved_0b : 6; // [31:26]
|
||||
uint32_t txop_duration : 7, // [6:0]
|
||||
coding : 1, // [7:7]
|
||||
ldpc_extra_symbol : 1, // [8:8]
|
||||
stbc : 1, // [9:9]
|
||||
txbf : 1, // [10:10]
|
||||
packet_extension_a_factor : 2, // [12:11]
|
||||
packet_extension_pe_disambiguity : 1, // [13:13]
|
||||
reserved_1a : 1, // [14:14]
|
||||
doppler_indication : 1, // [15:15]
|
||||
crc : 4, // [19:16]
|
||||
tail : 6, // [25:20]
|
||||
dot11ax_su_extended : 1, // [26:26]
|
||||
dot11ax_ext_ru_size : 3, // [29:27]
|
||||
rx_ndp : 1, // [30:30]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t reserved_0b : 6, // [31:26]
|
||||
nsts : 3, // [25:23]
|
||||
cp_ltf_size : 2, // [22:21]
|
||||
transmit_bw : 2, // [20:19]
|
||||
spatial_reuse : 4, // [18:15]
|
||||
reserved_0a : 1, // [14:14]
|
||||
bss_color_id : 6, // [13:8]
|
||||
dcm : 1, // [7:7]
|
||||
transmit_mcs : 4, // [6:3]
|
||||
dl_ul_flag : 1, // [2:2]
|
||||
beam_change : 1, // [1:1]
|
||||
format_indication : 1; // [0:0]
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
rx_ndp : 1, // [30:30]
|
||||
dot11ax_ext_ru_size : 3, // [29:27]
|
||||
dot11ax_su_extended : 1, // [26:26]
|
||||
tail : 6, // [25:20]
|
||||
crc : 4, // [19:16]
|
||||
doppler_indication : 1, // [15:15]
|
||||
reserved_1a : 1, // [14:14]
|
||||
packet_extension_pe_disambiguity : 1, // [13:13]
|
||||
packet_extension_a_factor : 2, // [12:11]
|
||||
txbf : 1, // [10:10]
|
||||
stbc : 1, // [9:9]
|
||||
ldpc_extra_symbol : 1, // [8:8]
|
||||
coding : 1, // [7:7]
|
||||
txop_duration : 7; // [6:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description FORMAT_INDICATION
|
||||
|
||||
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
|
||||
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0
|
||||
#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001
|
||||
|
||||
|
||||
/* Description BEAM_CHANGE
|
||||
|
||||
Indicates whether spatial mapping is changed between legacy
|
||||
and HE portion of preamble. If not, channel estimation
|
||||
can include legacy preamble to improve accuracy
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1
|
||||
#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2
|
||||
#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004
|
||||
|
||||
|
||||
/* Description TRANSMIT_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078
|
||||
|
||||
|
||||
/* Description DCM
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_DCM_LSB 7
|
||||
#define HE_SIG_A_SU_INFO_DCM_MSB 7
|
||||
#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13
|
||||
#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
For 20MHz one SR field corresponding to entire 20MHz (other
|
||||
3 fields indicate identical values)
|
||||
For 40MHz two SR fields for each 20MHz (other 2 fields indicate
|
||||
identical values)
|
||||
For 80MHz four SR fields for each 20MHz
|
||||
For 160MHz four SR fields for each 40MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18
|
||||
#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
For HE SU PPDU
|
||||
|
||||
|
||||
|
||||
<enum 0 HE_SIG_A_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_BW80> 80 Mhz
|
||||
<enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
|
||||
|
||||
For HE Extended Range SU PPDU
|
||||
Set to 0 for 242-tone RU
|
||||
|
||||
Set to 1 for right 106-tone RU within
|
||||
the primary 20 MHz
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20
|
||||
#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000
|
||||
|
||||
|
||||
/* Description CP_LTF_SIZE
|
||||
|
||||
Indicates the CP and HE-LTF type
|
||||
|
||||
<enum 0 OneX_LTF_0_8CP> 1xLTF + 0.8 us CP
|
||||
<enum 1 TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
|
||||
<enum 2 TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
|
||||
|
||||
<enum 3 FourX_LTF_0_8CP_3_2CP>
|
||||
When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
|
||||
When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
|
||||
In this scenario, Neither DCM nor STBC is applied to HE
|
||||
data field.
|
||||
|
||||
NOTE:
|
||||
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
|
||||
0 = 1xLTF + 0.4 usec
|
||||
1 = 2xLTF + 0.4 usec
|
||||
2~3 = Reserved
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22
|
||||
#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
Indicates number of streams used for the SU transmission
|
||||
|
||||
|
||||
For HE SU PPDU
|
||||
|
||||
|
||||
Set to n for n+1 space time stream,
|
||||
where n = 0, 1, 2,.....,7.
|
||||
|
||||
|
||||
|
||||
|
||||
For HE Extended Range PPDU
|
||||
|
||||
|
||||
Set to 0 for 1 space time stream.
|
||||
Value 1 is TBD
|
||||
|
||||
|
||||
|
||||
Values 2 - 7 are reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_NSTS_LSB 23
|
||||
#define HE_SIG_A_SU_INFO_NSTS_MSB 25
|
||||
#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6
|
||||
#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f
|
||||
|
||||
|
||||
/* Description CODING
|
||||
|
||||
Distinguishes between BCC and LDPC coding.
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_CODING_LSB 7
|
||||
#define HE_SIG_A_SU_INFO_CODING_MSB 7
|
||||
#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
If LDPC,
|
||||
0: LDPC extra symbol not present
|
||||
1: LDPC extra symbol present
|
||||
Else
|
||||
Set to 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8
|
||||
#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Indicates whether STBC is applied
|
||||
0: No STBC
|
||||
1: STBC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_STBC_LSB 9
|
||||
#define HE_SIG_A_SU_INFO_STBC_MSB 9
|
||||
#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_TXBF_LSB 10
|
||||
#define HE_SIG_A_SU_INFO_TXBF_MSB 10
|
||||
#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_A_FACTOR
|
||||
|
||||
Common trigger info
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with these two bits indicating the "a-factor"
|
||||
|
||||
<enum 0 a_factor_4>
|
||||
<enum 1 a_factor_1>
|
||||
<enum 2 a_factor_2>
|
||||
<enum 3 a_factor_3>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_PE_DISAMBIGUITY
|
||||
|
||||
Common trigger info
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with this bit indicating the PE-Disambiguity
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
|
||||
#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Note: per standard, set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14
|
||||
#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000
|
||||
|
||||
|
||||
/* Description DOPPLER_INDICATION
|
||||
|
||||
0: No Doppler support
|
||||
1: Doppler support
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15
|
||||
#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_CRC_LSB 16
|
||||
#define HE_SIG_A_SU_INFO_CRC_MSB 19
|
||||
#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_TAIL_LSB 20
|
||||
#define HE_SIG_A_SU_INFO_TAIL_MSB 25
|
||||
#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
|
||||
/* Description DOT11AX_SU_EXTENDED
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:
|
||||
On RX side, evaluated by MAC HW. This is the only way for
|
||||
MAC RX to know that this was an HE_SIG_A_SU received in
|
||||
'extended' format
|
||||
|
||||
When set, the 11ax frame is of the extended range format
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
|
||||
|
||||
|
||||
/* Description DOT11AX_EXT_RU_SIZE
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:
|
||||
Field only contains valid info when dot11ax_su_extended
|
||||
is set.
|
||||
|
||||
On RX side, evaluated by MAC HW. This is the only way for
|
||||
MAC RX to know what the number of based RUs was in this
|
||||
extended range reception. It is used by the MAC to determine
|
||||
the RU size for the response...
|
||||
|
||||
<enum 0 EXT_RU_26>
|
||||
<enum 1 EXT_RU_52>
|
||||
<enum 2 EXT_RU_106>
|
||||
<enum 3 EXT_RU_242><legal 0-3>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29
|
||||
#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:Valid on RX side only, and looked at by MAC HW
|
||||
|
||||
When set, PHY has received (expected) NDP frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30
|
||||
#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // HE_SIG_A_SU_INFO
|
||||
81
hw/qcn6432/he_sig_b1_mu_info.h
Archivo normal
81
hw/qcn6432/he_sig_b1_mu_info.h
Archivo normal
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HE_SIG_B1_MU_INFO_H_
|
||||
#define _HE_SIG_B1_MU_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
|
||||
|
||||
|
||||
struct he_sig_b1_mu_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ru_allocation : 8, // [7:0]
|
||||
reserved_0 : 23, // [30:8]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_0 : 23, // [30:8]
|
||||
ru_allocation : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RU_ALLOCATION
|
||||
|
||||
RU allocation for the user(s) following this common portion
|
||||
of the SIG
|
||||
|
||||
For details, refer to RU_TYPE description
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7
|
||||
#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30
|
||||
#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing the HE-SIG-B common info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // HE_SIG_B1_MU_INFO
|
||||
210
hw/qcn6432/he_sig_b2_mu_info.h
Archivo normal
210
hw/qcn6432/he_sig_b2_mu_info.h
Archivo normal
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HE_SIG_B2_MU_INFO_H_
|
||||
#define _HE_SIG_B2_MU_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
|
||||
|
||||
|
||||
struct he_sig_b2_mu_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
sta_spatial_config : 4, // [14:11]
|
||||
sta_mcs : 4, // [18:15]
|
||||
reserved_set_to_1 : 1, // [19:19]
|
||||
sta_coding : 1, // [20:20]
|
||||
reserved_0a : 7, // [27:21]
|
||||
nsts : 3, // [30:28]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
uint32_t user_order : 8, // [7:0]
|
||||
cc_mask : 8, // [15:8]
|
||||
reserved_1a : 16; // [31:16]
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
nsts : 3, // [30:28]
|
||||
reserved_0a : 7, // [27:21]
|
||||
sta_coding : 1, // [20:20]
|
||||
reserved_set_to_1 : 1, // [19:19]
|
||||
sta_mcs : 4, // [18:15]
|
||||
sta_spatial_config : 4, // [14:11]
|
||||
sta_id : 11; // [10:0]
|
||||
uint32_t reserved_1a : 16, // [31:16]
|
||||
cc_mask : 8, // [15:8]
|
||||
user_order : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10
|
||||
#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
/* Description STA_SPATIAL_CONFIG
|
||||
|
||||
Number of assigned spatial streams and their corresponding
|
||||
index.
|
||||
Total number of spatial streams assigned for the MU-MIMO
|
||||
allocation is also signaled.
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14
|
||||
#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18
|
||||
#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000
|
||||
|
||||
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20
|
||||
#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
MAC RX side usage only:
|
||||
Needed by RXPCU. Provided by PHY so that RXPCU does not
|
||||
need to have the RU number decoding logic.
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_LSB 28
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_MSB 30
|
||||
#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this HE-SIG-B user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
/* Description USER_ORDER
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7
|
||||
#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channel this User field
|
||||
can go to
|
||||
Bit 0: content channel 0
|
||||
Bit 1: content channel 1
|
||||
The other bits are unused, but could repeat the above pattern
|
||||
for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15
|
||||
#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31
|
||||
#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
|
||||
|
||||
#endif // HE_SIG_B2_MU_INFO
|
||||
216
hw/qcn6432/he_sig_b2_ofdma_info.h
Archivo normal
216
hw/qcn6432/he_sig_b2_ofdma_info.h
Archivo normal
@@ -0,0 +1,216 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HE_SIG_B2_OFDMA_INFO_H_
|
||||
#define _HE_SIG_B2_OFDMA_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
|
||||
|
||||
|
||||
struct he_sig_b2_ofdma_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11, // [10:0]
|
||||
nsts : 3, // [13:11]
|
||||
txbf : 1, // [14:14]
|
||||
sta_mcs : 4, // [18:15]
|
||||
sta_dcm : 1, // [19:19]
|
||||
sta_coding : 1, // [20:20]
|
||||
reserved_0 : 10, // [30:21]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
uint32_t user_order : 8, // [7:0]
|
||||
cc_mask : 8, // [15:8]
|
||||
reserved_1a : 16; // [31:16]
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_0 : 10, // [30:21]
|
||||
sta_coding : 1, // [20:20]
|
||||
sta_dcm : 1, // [19:19]
|
||||
sta_mcs : 4, // [18:15]
|
||||
txbf : 1, // [14:14]
|
||||
nsts : 3, // [13:11]
|
||||
sta_id : 11; // [10:0]
|
||||
uint32_t reserved_1a : 16, // [31:16]
|
||||
cc_mask : 8, // [15:8]
|
||||
user_order : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
MAC RX side usage only:
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13
|
||||
#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14
|
||||
#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000
|
||||
|
||||
|
||||
/* Description STA_DCM
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20
|
||||
#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this HE-SIG-B user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
/* Description USER_ORDER
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7
|
||||
#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channel this User field
|
||||
can go to
|
||||
Bit 0: content channel 0
|
||||
Bit 1: content channel 1
|
||||
The other bits are unused, but could repeat the above pattern
|
||||
for compatibility with 'EHT_SIG_USR_OFDMA_INFO.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15
|
||||
#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31
|
||||
#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000
|
||||
|
||||
|
||||
|
||||
#endif // HE_SIG_B2_OFDMA_INFO
|
||||
292
hw/qcn6432/ht_sig_info.h
Archivo normal
292
hw/qcn6432/ht_sig_info.h
Archivo normal
@@ -0,0 +1,292 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HT_SIG_INFO_H_
|
||||
#define _HT_SIG_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_HT_SIG_INFO 2
|
||||
|
||||
|
||||
struct ht_sig_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t mcs : 7, // [6:0]
|
||||
cbw : 1, // [7:7]
|
||||
length : 16, // [23:8]
|
||||
reserved_0 : 8; // [31:24]
|
||||
uint32_t smoothing : 1, // [0:0]
|
||||
not_sounding : 1, // [1:1]
|
||||
ht_reserved : 1, // [2:2]
|
||||
aggregation : 1, // [3:3]
|
||||
stbc : 2, // [5:4]
|
||||
fec_coding : 1, // [6:6]
|
||||
short_gi : 1, // [7:7]
|
||||
num_ext_sp_str : 2, // [9:8]
|
||||
crc : 8, // [17:10]
|
||||
signal_tail : 6, // [23:18]
|
||||
reserved_1 : 7, // [30:24]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t reserved_0 : 8, // [31:24]
|
||||
length : 16, // [23:8]
|
||||
cbw : 1, // [7:7]
|
||||
mcs : 7; // [6:0]
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved_1 : 7, // [30:24]
|
||||
signal_tail : 6, // [23:18]
|
||||
crc : 8, // [17:10]
|
||||
num_ext_sp_str : 2, // [9:8]
|
||||
short_gi : 1, // [7:7]
|
||||
fec_coding : 1, // [6:6]
|
||||
stbc : 2, // [5:4]
|
||||
aggregation : 1, // [3:3]
|
||||
ht_reserved : 1, // [2:2]
|
||||
not_sounding : 1, // [1:1]
|
||||
smoothing : 1; // [0:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation Coding Scheme:
|
||||
0-7 are used for single stream
|
||||
8-15 are used for 2 streams
|
||||
16-23 are used for 3 streams
|
||||
24-31 are used for 4 streams
|
||||
32 is used for duplicate HT20 (unsupported)
|
||||
33-76 is used for unequal modulation (unsupported)
|
||||
77-127 is reserved.
|
||||
<legal 0-31>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_MCS_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_MCS_LSB 0
|
||||
#define HT_SIG_INFO_MCS_MSB 6
|
||||
#define HT_SIG_INFO_MCS_MASK 0x0000007f
|
||||
|
||||
|
||||
/* Description CBW
|
||||
|
||||
Packet bandwidth:
|
||||
<enum 0 ht_20_mhz>
|
||||
<enum 1 ht_40_mhz>
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_CBW_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_CBW_LSB 7
|
||||
#define HT_SIG_INFO_CBW_MSB 7
|
||||
#define HT_SIG_INFO_CBW_MASK 0x00000080
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
This is the MPDU or A-MPDU length in octets of the PPDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_LENGTH_LSB 8
|
||||
#define HT_SIG_INFO_LENGTH_MSB 23
|
||||
#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
This field is not part of HT-SIG
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define HT_SIG_INFO_RESERVED_0_LSB 24
|
||||
#define HT_SIG_INFO_RESERVED_0_MSB 31
|
||||
#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description SMOOTHING
|
||||
|
||||
Field indicates if smoothing is needed
|
||||
E_num 0 do_smoothing Unsupported setting: indicates
|
||||
smoothing is often used for beamforming
|
||||
<enum 1 no_smoothing> Indicates no smoothing is used
|
||||
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_SMOOTHING_LSB 0
|
||||
#define HT_SIG_INFO_SMOOTHING_MSB 0
|
||||
#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001
|
||||
|
||||
|
||||
/* Description NOT_SOUNDING
|
||||
|
||||
E_num 0 sounding Unsupported setting: indicates sounding
|
||||
is used
|
||||
<enum 1 no_sounding> Indicates no sounding is used
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_LSB 1
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_MSB 1
|
||||
#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002
|
||||
|
||||
|
||||
/* Description HT_RESERVED
|
||||
|
||||
Reserved: Should be set to 1 by the MAC and ignored by the
|
||||
PHY
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_HT_RESERVED_LSB 2
|
||||
#define HT_SIG_INFO_HT_RESERVED_MSB 2
|
||||
#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004
|
||||
|
||||
|
||||
/* Description AGGREGATION
|
||||
|
||||
<enum 0 mpdu> Indicates MPDU format
|
||||
<enum 1 a_mpdu> Indicates A-MPDU format
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_AGGREGATION_LSB 3
|
||||
#define HT_SIG_INFO_AGGREGATION_MSB 3
|
||||
#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
<enum 0 no_stbc> Indicates no STBC
|
||||
<enum 1 1_str_stbc> Indicates 1 stream STBC
|
||||
E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported)
|
||||
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_STBC_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_STBC_LSB 4
|
||||
#define HT_SIG_INFO_STBC_MSB 5
|
||||
#define HT_SIG_INFO_STBC_MASK 0x00000030
|
||||
|
||||
|
||||
/* Description FEC_CODING
|
||||
|
||||
<enum 0 ht_bcc> Indicates BCC coding
|
||||
<enum 1 ht_ldpc> Indicates LDPC coding
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_FEC_CODING_LSB 6
|
||||
#define HT_SIG_INFO_FEC_CODING_MSB 6
|
||||
#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040
|
||||
|
||||
|
||||
/* Description SHORT_GI
|
||||
|
||||
<enum 0 ht_normal_gi> Indicates normal guard interval
|
||||
|
||||
<enum 1 ht_short_gi> Indicates short guard interval
|
||||
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_SHORT_GI_LSB 7
|
||||
#define HT_SIG_INFO_SHORT_GI_MSB 7
|
||||
#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080
|
||||
|
||||
|
||||
/* Description NUM_EXT_SP_STR
|
||||
|
||||
Number of extension spatial streams: (Used for TxBF)
|
||||
<enum 0 0_ext_sp_str> No extension spatial streams
|
||||
E_num 1 1_ext_sp_str Not supported: 1 extension spatial
|
||||
streams
|
||||
E_num 2 2_ext_sp_str Not supported: 2 extension spatial
|
||||
streams
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9
|
||||
#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0].
|
||||
The generator polynomial is G(D) = D8 + D2 + D + 1. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_CRC_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_CRC_LSB 10
|
||||
#define HT_SIG_INFO_CRC_MSB 17
|
||||
#define HT_SIG_INFO_CRC_MASK 0x0003fc00
|
||||
|
||||
|
||||
/* Description SIGNAL_TAIL
|
||||
|
||||
The 6 bits of tail is always set to 0 is used to flush the
|
||||
BCC encoder and decoder. <legal 0>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23
|
||||
#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
This field is not part of HT-SIG:
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY. <legal 0>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_RESERVED_1_LSB 24
|
||||
#define HT_SIG_INFO_RESERVED_1_MSB 30
|
||||
#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HT-SIG CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // HT_SIG_INFO
|
||||
200
hw/qcn6432/l_sig_a_info.h
Archivo normal
200
hw/qcn6432/l_sig_a_info.h
Archivo normal
@@ -0,0 +1,200 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _L_SIG_A_INFO_H_
|
||||
#define _L_SIG_A_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_L_SIG_A_INFO 1
|
||||
|
||||
|
||||
struct l_sig_a_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rate : 4, // [3:0]
|
||||
lsig_reserved : 1, // [4:4]
|
||||
length : 12, // [16:5]
|
||||
parity : 1, // [17:17]
|
||||
tail : 6, // [23:18]
|
||||
pkt_type : 4, // [27:24]
|
||||
captured_implicit_sounding : 1, // [28:28]
|
||||
reserved : 2, // [30:29]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved : 2, // [30:29]
|
||||
captured_implicit_sounding : 1, // [28:28]
|
||||
pkt_type : 4, // [27:24]
|
||||
tail : 6, // [23:18]
|
||||
parity : 1, // [17:17]
|
||||
length : 12, // [16:5]
|
||||
lsig_reserved : 1, // [4:4]
|
||||
rate : 4; // [3:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RATE
|
||||
|
||||
This format is originally defined for OFDM as a 4 bit field
|
||||
but the 5th bit was added to indicate 11b formatted frames.
|
||||
In the standard bit [4] is specified as reserved. For
|
||||
11b frames this L-SIG is transformed in the PHY into the
|
||||
11b preamble format. The following are the rates:
|
||||
<enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
|
||||
<enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
|
||||
<enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
|
||||
<enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
|
||||
<enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
|
||||
<enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
|
||||
<enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
|
||||
<enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
|
||||
<legal 8-15>
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_RATE_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_RATE_LSB 0
|
||||
#define L_SIG_A_INFO_RATE_MSB 3
|
||||
#define L_SIG_A_INFO_RATE_MASK 0x0000000f
|
||||
|
||||
|
||||
/* Description LSIG_RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4
|
||||
#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
The length indicates the number of octets in this MPDU.
|
||||
Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be
|
||||
this length provides the spoofed length for the PPDU.
|
||||
This length provides part of the information (viz. PPDU
|
||||
duration) to derive the actually PSDU length. For legacy
|
||||
OFDM and 11B frames the maximum length is 4095.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_LENGTH_LSB 5
|
||||
#define L_SIG_A_INFO_LENGTH_MSB 16
|
||||
#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0
|
||||
|
||||
|
||||
/* Description PARITY
|
||||
|
||||
11a/n/ac TX: This field provides even parity over the first
|
||||
18 bits of the signal field which means that the sum of
|
||||
1s in the signal field will always be even on transmission.
|
||||
The value of the field is computed by the MAC.
|
||||
11a/n/ac RX: this field contains the received parity field
|
||||
from the L-SIG symbol for the current packet.
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_PARITY_LSB 17
|
||||
#define L_SIG_A_INFO_PARITY_MSB 17
|
||||
#define L_SIG_A_INFO_PARITY_MASK 0x00020000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
The 6 bits of tail is always set to 0 is used to flush the
|
||||
BCC encoder and decoder. <legal 0>
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_TAIL_LSB 18
|
||||
#define L_SIG_A_INFO_TAIL_MSB 23
|
||||
#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000
|
||||
|
||||
|
||||
/* Description PKT_TYPE
|
||||
|
||||
Only used on the RX side.
|
||||
Note: This is not really part of L-SIG
|
||||
|
||||
Packet type:
|
||||
<enum 0 dot11a>802.11a PPDU type
|
||||
<enum 1 dot11b>802.11b PPDU type
|
||||
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
|
||||
<enum 3 dot11ac>802.11ac PPDU type
|
||||
<enum 4 dot11ax>802.11ax PPDU type
|
||||
<enum 5 dot11ba>802.11ba (WUR) PPDU type
|
||||
<enum 6 dot11be>802.11be PPDU type
|
||||
<enum 7 dot11az>802.11az (ranging) PPDU type
|
||||
<enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported
|
||||
& aborted)
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_PKT_TYPE_LSB 24
|
||||
#define L_SIG_A_INFO_PKT_TYPE_MSB 27
|
||||
#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000
|
||||
|
||||
|
||||
/* Description CAPTURED_IMPLICIT_SOUNDING
|
||||
|
||||
Only used on the RX side.
|
||||
Note: This is not really part of L-SIG
|
||||
|
||||
This indicates that the PHY has captured implicit sounding.
|
||||
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28
|
||||
#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the transmitting MAC and
|
||||
ignored by the PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_RESERVED_LSB 29
|
||||
#define L_SIG_A_INFO_RESERVED_MSB 30
|
||||
#define L_SIG_A_INFO_RESERVED_MASK 0x60000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the L-SIG integrity
|
||||
check has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // L_SIG_A_INFO
|
||||
98
hw/qcn6432/l_sig_b_info.h
Archivo normal
98
hw/qcn6432/l_sig_b_info.h
Archivo normal
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _L_SIG_B_INFO_H_
|
||||
#define _L_SIG_B_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_L_SIG_B_INFO 1
|
||||
|
||||
|
||||
struct l_sig_b_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rate : 4, // [3:0]
|
||||
length : 12, // [15:4]
|
||||
reserved : 15, // [30:16]
|
||||
rx_integrity_check_passed : 1; // [31:31]
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1, // [31:31]
|
||||
reserved : 15, // [30:16]
|
||||
length : 12, // [15:4]
|
||||
rate : 4; // [3:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RATE
|
||||
|
||||
<enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
|
||||
<enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
|
||||
<enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
|
||||
<enum 4 cck_11_mbps_long> CCK 11 Mbps long
|
||||
<enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
|
||||
<enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
|
||||
<enum 7 cck_11_mbps_short> CCK 11 Mbps short
|
||||
<legal 1-7>
|
||||
*/
|
||||
|
||||
#define L_SIG_B_INFO_RATE_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_RATE_LSB 0
|
||||
#define L_SIG_B_INFO_RATE_MSB 3
|
||||
#define L_SIG_B_INFO_RATE_MASK 0x0000000f
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
The length indicates the number of octets in this MPDU.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_LENGTH_LSB 4
|
||||
#define L_SIG_B_INFO_LENGTH_MSB 15
|
||||
#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the transmitting MAC and
|
||||
ignored by the PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_RESERVED_LSB 16
|
||||
#define L_SIG_B_INFO_RESERVED_MSB 30
|
||||
#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the .11b PHY header
|
||||
CRC check has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
|
||||
|
||||
#endif // L_SIG_B_INFO
|
||||
82
hw/qcn6432/macrx_abort_request_info.h
Archivo normal
82
hw/qcn6432/macrx_abort_request_info.h
Archivo normal
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACRX_ABORT_REQUEST_INFO_H_
|
||||
#define _MACRX_ABORT_REQUEST_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
|
||||
|
||||
|
||||
struct macrx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t macrx_abort_reason : 8, // [7:0]
|
||||
reserved_0 : 8; // [15:8]
|
||||
#else
|
||||
uint16_t reserved_0 : 8, // [15:8]
|
||||
macrx_abort_reason : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACRX_ABORT_REASON
|
||||
|
||||
<enum 0 macrx_abort_sw_initiated>
|
||||
<enum 1 macrx_abort_obss_reception> Upon receiving this
|
||||
abort reason, PHY should stop reception of the current frame
|
||||
and go back into a search mode
|
||||
<enum 2 macrx_abort_other>
|
||||
<enum 3 macrx_abort_sw_initiated_channel_switch> MAC FW
|
||||
issued an abort for channel switch reasons
|
||||
<enum 4 macrx_abort_sw_initiated_power_save> MAC FW issued
|
||||
an abort power save reasons
|
||||
<enum 5 macrx_abort_too_much_bad_data> RXPCU is terminating
|
||||
the current ongoing reception, as the data that MAC is
|
||||
receiving seems to be all garbage... The PER is too high,
|
||||
or in case of MU UL, Likely the trigger frame never got
|
||||
properly received by any of the targeted MU UL devices.
|
||||
After the abort, PHYRX can resume a normal search mode.
|
||||
<enum 6 macrx_abort_ul_mu_early_abort> RXPCU is terminating
|
||||
the current ongoing UL MU reception, because at the end
|
||||
of the "early_termination_window," the required number
|
||||
of users with at least one valid MPDU delimiter was not
|
||||
reached. Likely the trigger frame never got properly received
|
||||
by the required number of targeted devices. After the abort,
|
||||
PHYRX can resume a normal search mode.
|
||||
|
||||
<legal 0-6>
|
||||
*/
|
||||
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7
|
||||
#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
|
||||
#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00
|
||||
|
||||
|
||||
|
||||
#endif // MACRX_ABORT_REQUEST_INFO
|
||||
208
hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h
Archivo normal
208
hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h
Archivo normal
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
|
||||
#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "eht_sig_usr_mu_mimo_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1
|
||||
|
||||
|
||||
struct mactx_eht_sig_usr_mu_mimo {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
|
||||
#else
|
||||
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
0 - 13: MCS 0 - 13
|
||||
14: validate
|
||||
15: MCS 0 with DCM
|
||||
<legal 0-13, 15>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000
|
||||
|
||||
|
||||
/* Description STA_SPATIAL_CONFIG
|
||||
|
||||
Number of assigned spatial streams and their corresponding
|
||||
index.
|
||||
Total number of spatial streams assigned for the MU-MIMO
|
||||
allocation is also signaled.
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this EHT-SIG user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
|
||||
|
||||
|
||||
/* Description SUBBAND80_CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channels of what 80 MHz
|
||||
subbands this User field can go to
|
||||
Bit 0: lowest 80 MHz content channel 0
|
||||
Bit 1: lowest 80 MHz content channel 1
|
||||
Bit 2: 2nd lowest 80 MHz content channel 0
|
||||
...
|
||||
Bit 7: highest 80 MHz content channel 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_0
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the lowest
|
||||
80 MHz
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_1
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
lowest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_2
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
highest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_3
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the highest
|
||||
80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_EHT_SIG_USR_MU_MIMO
|
||||
235
hw/qcn6432/mactx_eht_sig_usr_ofdma.h
Archivo normal
235
hw/qcn6432/mactx_eht_sig_usr_ofdma.h
Archivo normal
@@ -0,0 +1,235 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
|
||||
#define _MACTX_EHT_SIG_USR_OFDMA_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "eht_sig_usr_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1
|
||||
|
||||
|
||||
struct mactx_eht_sig_usr_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
|
||||
#else
|
||||
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
0 - 13: MCS 0 - 13
|
||||
14: validate
|
||||
15: MCS 0 with DCM
|
||||
<legal 0-13, 15>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
|
||||
|
||||
|
||||
/* Description VALIDATE_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
|
||||
|
||||
|
||||
/* Description NSS
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
The actual number of streams is 1 larger than indicated
|
||||
in this field.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this EHT-SIG user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
|
||||
|
||||
|
||||
/* Description SUBBAND80_CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channels of what 80 MHz
|
||||
subbands this User field can go to
|
||||
Bit 0: lowest 80 MHz content channel 0
|
||||
Bit 1: lowest 80 MHz content channel 1
|
||||
Bit 2: 2nd lowest 80 MHz content channel 0
|
||||
...
|
||||
Bit 7: highest 80 MHz content channel 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_0
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the lowest
|
||||
80 MHz
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_1
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
lowest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_2
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the 2nd
|
||||
highest 80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
|
||||
|
||||
|
||||
/* Description USER_ORDER_SUBBAND80_3
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field within the highest
|
||||
80 MHz
|
||||
See 'user_order_subband80_0.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_EHT_SIG_USR_OFDMA
|
||||
169
hw/qcn6432/mactx_eht_sig_usr_su.h
Archivo normal
169
hw/qcn6432/mactx_eht_sig_usr_su.h
Archivo normal
@@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_SU_H_
|
||||
#define _MACTX_EHT_SIG_USR_SU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "eht_sig_usr_su_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1
|
||||
|
||||
|
||||
struct mactx_eht_sig_usr_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_EHT_SIG_USR_SU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
0 - 13: MCS 0 - 13
|
||||
14: MCS 0 with DCM and 2x duplicate
|
||||
15: MCS 0 with DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
|
||||
|
||||
|
||||
/* Description VALIDATE_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
|
||||
|
||||
|
||||
/* Description NSS
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
The actual number of streams is 1 larger than indicated
|
||||
in this field.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this EHT-SIG user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_EHT_SIG_USR_SU
|
||||
390
hw/qcn6432/mactx_he_sig_a_mu_dl.h
Archivo normal
390
hw/qcn6432/mactx_he_sig_a_mu_dl.h
Archivo normal
@@ -0,0 +1,390 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_MU_DL_H_
|
||||
#define _MACTX_HE_SIG_A_MU_DL_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_mu_dl_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1
|
||||
|
||||
|
||||
struct mactx_he_sig_a_mu_dl {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_HE_SIG_A_MU_DL_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
NOTE: This is unsupported for "HE MU" format (including "MU_SU")
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description MCS_OF_SIG_B
|
||||
|
||||
Indicates the MCS of HE-SIG-B
|
||||
<legal 0-5>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e
|
||||
|
||||
|
||||
/* Description DCM_OF_SIG_B
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
to HE-SIG-B
|
||||
|
||||
0: No DCM for HE_SIG_B
|
||||
1: DCM for HE_SIG_B
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
For 20MHz one SR field corresponding to entire 20MHz (other
|
||||
3 fields indicate identical values)
|
||||
For 40MHz two SR fields for each 20MHz (other 2 fields indicate
|
||||
identical values)
|
||||
For 80MHz four SR fields for each 20MHz
|
||||
For 160MHz four SR fields for each 40MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
<enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble puncturing
|
||||
mode
|
||||
<enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz non-preamble
|
||||
puncturing mode
|
||||
<enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble puncturing
|
||||
in 80 MHz, where in the preamble only the secondary 20
|
||||
MHz is punctured
|
||||
<enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for preamble
|
||||
puncturing in 80 MHz, where in the preamble only one of
|
||||
the two 20 MHz sub-channels in secondary 40 MHz is punctured.
|
||||
|
||||
<enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble puncturing
|
||||
in 160 MHz or 80+80 MHz, where in the primary 80 MHz of
|
||||
the preamble only the secondary 20 MHz is punctured.
|
||||
<enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for preamble
|
||||
puncturing in 160 MHz or 80+80 MHz, where in the primary
|
||||
80 MHz of the preamble the primary 40 MHz is present.
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal 0-7>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000
|
||||
|
||||
|
||||
/* Description NUM_SIG_B_SYMBOLS
|
||||
|
||||
Number of symbols
|
||||
|
||||
For OFDMA, the actual number of symbols is 1 larger then
|
||||
indicated in this field.
|
||||
|
||||
For MU-MIMO this is equal to the number of users - 1: the
|
||||
following encoding is used:
|
||||
1 => 2 users
|
||||
2 => 3 users
|
||||
Etc.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
|
||||
|
||||
|
||||
/* Description COMP_MODE_SIG_B
|
||||
|
||||
Indicates the compression mode of HE-SIG-B
|
||||
|
||||
0: Regular [uncomp mode]
|
||||
1: compressed mode (full-BW MU-MIMO only)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
|
||||
|
||||
|
||||
/* Description CP_LTF_SIZE
|
||||
|
||||
Indicates the CP and HE-LTF type
|
||||
|
||||
<enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
|
||||
<enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
|
||||
<enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
|
||||
<enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000
|
||||
|
||||
|
||||
/* Description DOPPLER_INDICATION
|
||||
|
||||
0: No Doppler support
|
||||
1: Doppler support
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000
|
||||
|
||||
|
||||
/* Description NUM_LTF_SYMBOLS
|
||||
|
||||
Indicates the number of HE-LTF symbols
|
||||
|
||||
0: 1 LTF
|
||||
1: 2 LTFs
|
||||
2: 4 LTFs
|
||||
3: 6 LTFs
|
||||
4: 8 LTFs
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
If LDPC,
|
||||
0: LDPC extra symbol not present
|
||||
1: LDPC extra symbol present
|
||||
Else
|
||||
Set to 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Indicates whether STBC is applied
|
||||
0: No STBC
|
||||
1: STBC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_A_FACTOR
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with these two bits indicating the "a-factor"
|
||||
|
||||
<enum 0 a_factor_4>
|
||||
<enum 1 a_factor_1>
|
||||
<enum 2 a_factor_2>
|
||||
<enum 3 a_factor_3>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_PE_DISAMBIGUITY
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with this bit indicating the PE-Disambiguity
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_HE_SIG_A_MU_DL
|
||||
202
hw/qcn6432/mactx_he_sig_a_mu_ul.h
Archivo normal
202
hw/qcn6432/mactx_he_sig_a_mu_ul.h
Archivo normal
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_MU_UL_H_
|
||||
#define _MACTX_HE_SIG_A_MU_UL_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_mu_ul_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1
|
||||
|
||||
|
||||
struct mactx_he_sig_a_mu_ul {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_HE_SIG_A_MU_UL_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description FORMAT_INDICATION
|
||||
|
||||
Indicates whether the transmission is SU PPDU or a trigger
|
||||
based UL MU PDDU
|
||||
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
|
||||
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
<enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
|
||||
<enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Set to value indicated in the trigger frame
|
||||
<legal 255>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
This CRC may also cover some fields of L-SIG (TBD)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
|
||||
used
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_HE_SIG_A_MU_UL
|
||||
497
hw/qcn6432/mactx_he_sig_a_su.h
Archivo normal
497
hw/qcn6432/mactx_he_sig_a_su.h
Archivo normal
@@ -0,0 +1,497 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_SU_H_
|
||||
#define _MACTX_HE_SIG_A_SU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_su_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1
|
||||
|
||||
|
||||
struct mactx_he_sig_a_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
|
||||
#else
|
||||
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_HE_SIG_A_SU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description FORMAT_INDICATION
|
||||
|
||||
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
|
||||
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description BEAM_CHANGE
|
||||
|
||||
Indicates whether spatial mapping is changed between legacy
|
||||
and HE portion of preamble. If not, channel estimation
|
||||
can include legacy preamble to improve accuracy
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004
|
||||
|
||||
|
||||
/* Description TRANSMIT_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078
|
||||
|
||||
|
||||
/* Description DCM
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
For 20MHz one SR field corresponding to entire 20MHz (other
|
||||
3 fields indicate identical values)
|
||||
For 40MHz two SR fields for each 20MHz (other 2 fields indicate
|
||||
identical values)
|
||||
For 80MHz four SR fields for each 20MHz
|
||||
For 160MHz four SR fields for each 40MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
For HE SU PPDU
|
||||
|
||||
|
||||
|
||||
<enum 0 HE_SIG_A_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_BW80> 80 Mhz
|
||||
<enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
|
||||
|
||||
For HE Extended Range SU PPDU
|
||||
Set to 0 for 242-tone RU
|
||||
|
||||
Set to 1 for right 106-tone RU within
|
||||
the primary 20 MHz
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000
|
||||
|
||||
|
||||
/* Description CP_LTF_SIZE
|
||||
|
||||
Indicates the CP and HE-LTF type
|
||||
|
||||
<enum 0 OneX_LTF_0_8CP> 1xLTF + 0.8 us CP
|
||||
<enum 1 TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
|
||||
<enum 2 TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
|
||||
|
||||
<enum 3 FourX_LTF_0_8CP_3_2CP>
|
||||
When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
|
||||
When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
|
||||
In this scenario, Neither DCM nor STBC is applied to HE
|
||||
data field.
|
||||
|
||||
NOTE:
|
||||
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
|
||||
0 = 1xLTF + 0.4 usec
|
||||
1 = 2xLTF + 0.4 usec
|
||||
2~3 = Reserved
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
Indicates number of streams used for the SU transmission
|
||||
|
||||
|
||||
For HE SU PPDU
|
||||
|
||||
|
||||
Set to n for n+1 space time stream,
|
||||
where n = 0, 1, 2,.....,7.
|
||||
|
||||
|
||||
|
||||
|
||||
For HE Extended Range PPDU
|
||||
|
||||
|
||||
Set to 0 for 1 space time stream.
|
||||
Value 1 is TBD
|
||||
|
||||
|
||||
|
||||
Values 2 - 7 are reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
|
||||
/* Description CODING
|
||||
|
||||
Distinguishes between BCC and LDPC coding.
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
If LDPC,
|
||||
0: LDPC extra symbol not present
|
||||
1: LDPC extra symbol present
|
||||
Else
|
||||
Set to 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Indicates whether STBC is applied
|
||||
0: No STBC
|
||||
1: STBC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_A_FACTOR
|
||||
|
||||
Common trigger info
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with these two bits indicating the "a-factor"
|
||||
|
||||
<enum 0 a_factor_4>
|
||||
<enum 1 a_factor_1>
|
||||
<enum 2 a_factor_2>
|
||||
<enum 3 a_factor_3>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_PE_DISAMBIGUITY
|
||||
|
||||
Common trigger info
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with this bit indicating the PE-Disambiguity
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Note: per standard, set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000
|
||||
|
||||
|
||||
/* Description DOPPLER_INDICATION
|
||||
|
||||
0: No Doppler support
|
||||
1: Doppler support
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description DOT11AX_SU_EXTENDED
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:
|
||||
On RX side, evaluated by MAC HW. This is the only way for
|
||||
MAC RX to know that this was an HE_SIG_A_SU received in
|
||||
'extended' format
|
||||
|
||||
When set, the 11ax frame is of the extended range format
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
|
||||
|
||||
|
||||
/* Description DOT11AX_EXT_RU_SIZE
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:
|
||||
Field only contains valid info when dot11ax_su_extended
|
||||
is set.
|
||||
|
||||
On RX side, evaluated by MAC HW. This is the only way for
|
||||
MAC RX to know what the number of based RUs was in this
|
||||
extended range reception. It is used by the MAC to determine
|
||||
the RU size for the response...
|
||||
|
||||
<enum 0 EXT_RU_26>
|
||||
<enum 1 EXT_RU_52>
|
||||
<enum 2 EXT_RU_106>
|
||||
<enum 3 EXT_RU_242><legal 0-3>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:Valid on RX side only, and looked at by MAC HW
|
||||
|
||||
When set, PHY has received (expected) NDP frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_HE_SIG_A_SU
|
||||
101
hw/qcn6432/mactx_he_sig_b1_mu.h
Archivo normal
101
hw/qcn6432/mactx_he_sig_b1_mu.h
Archivo normal
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B1_MU_H_
|
||||
#define _MACTX_HE_SIG_B1_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b1_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1
|
||||
|
||||
|
||||
struct mactx_he_sig_b1_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_HE_SIG_B1_MU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description RU_ALLOCATION
|
||||
|
||||
RU allocation for the user(s) following this common portion
|
||||
of the SIG
|
||||
|
||||
For details, refer to RU_TYPE description
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing the HE-SIG-B common info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_HE_SIG_B1_MU
|
||||
199
hw/qcn6432/mactx_he_sig_b2_mu.h
Archivo normal
199
hw/qcn6432/mactx_he_sig_b2_mu.h
Archivo normal
@@ -0,0 +1,199 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B2_MU_H_
|
||||
#define _MACTX_HE_SIG_B2_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b2_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1
|
||||
|
||||
|
||||
struct mactx_he_sig_b2_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
|
||||
#else
|
||||
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_HE_SIG_B2_MU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description STA_SPATIAL_CONFIG
|
||||
|
||||
Number of assigned spatial streams and their corresponding
|
||||
index.
|
||||
Total number of spatial streams assigned for the MU-MIMO
|
||||
allocation is also signaled.
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
|
||||
|
||||
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
MAC RX side usage only:
|
||||
Needed by RXPCU. Provided by PHY so that RXPCU does not
|
||||
need to have the RU number decoding logic.
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this HE-SIG-B user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description USER_ORDER
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channel this User field
|
||||
can go to
|
||||
Bit 0: content channel 0
|
||||
Bit 1: content channel 1
|
||||
The other bits are unused, but could repeat the above pattern
|
||||
for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_HE_SIG_B2_MU
|
||||
205
hw/qcn6432/mactx_he_sig_b2_ofdma.h
Archivo normal
205
hw/qcn6432/mactx_he_sig_b2_ofdma.h
Archivo normal
@@ -0,0 +1,205 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
|
||||
#define _MACTX_HE_SIG_B2_OFDMA_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b2_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1
|
||||
|
||||
|
||||
struct mactx_he_sig_b2_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
|
||||
#else
|
||||
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
MAC RX side usage only:
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
|
||||
|
||||
|
||||
/* Description STA_DCM
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this HE-SIG-B user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description USER_ORDER
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channel this User field
|
||||
can go to
|
||||
Bit 0: content channel 0
|
||||
Bit 1: content channel 1
|
||||
The other bits are unused, but could repeat the above pattern
|
||||
for compatibility with 'EHT_SIG_USR_OFDMA_INFO.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_HE_SIG_B2_OFDMA
|
||||
271
hw/qcn6432/mactx_ht_sig.h
Archivo normal
271
hw/qcn6432/mactx_ht_sig.h
Archivo normal
@@ -0,0 +1,271 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_HT_SIG_H_
|
||||
#define _MACTX_HT_SIG_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "ht_sig_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HT_SIG 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HT_SIG 1
|
||||
|
||||
|
||||
struct mactx_ht_sig {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct ht_sig_info mactx_ht_sig_info_details;
|
||||
#else
|
||||
struct ht_sig_info mactx_ht_sig_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_HT_SIG_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation Coding Scheme:
|
||||
0-7 are used for single stream
|
||||
8-15 are used for 2 streams
|
||||
16-23 are used for 3 streams
|
||||
24-31 are used for 4 streams
|
||||
32 is used for duplicate HT20 (unsupported)
|
||||
33-76 is used for unequal modulation (unsupported)
|
||||
77-127 is reserved.
|
||||
<legal 0-31>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f
|
||||
|
||||
|
||||
/* Description CBW
|
||||
|
||||
Packet bandwidth:
|
||||
<enum 0 ht_20_mhz>
|
||||
<enum 1 ht_40_mhz>
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
This is the MPDU or A-MPDU length in octets of the PPDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
This field is not part of HT-SIG
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description SMOOTHING
|
||||
|
||||
Field indicates if smoothing is needed
|
||||
E_num 0 do_smoothing Unsupported setting: indicates
|
||||
smoothing is often used for beamforming
|
||||
<enum 1 no_smoothing> Indicates no smoothing is used
|
||||
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000
|
||||
|
||||
|
||||
/* Description NOT_SOUNDING
|
||||
|
||||
E_num 0 sounding Unsupported setting: indicates sounding
|
||||
is used
|
||||
<enum 1 no_sounding> Indicates no sounding is used
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000
|
||||
|
||||
|
||||
/* Description HT_RESERVED
|
||||
|
||||
Reserved: Should be set to 1 by the MAC and ignored by the
|
||||
PHY
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000
|
||||
|
||||
|
||||
/* Description AGGREGATION
|
||||
|
||||
<enum 0 mpdu> Indicates MPDU format
|
||||
<enum 1 a_mpdu> Indicates A-MPDU format
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
<enum 0 no_stbc> Indicates no STBC
|
||||
<enum 1 1_str_stbc> Indicates 1 stream STBC
|
||||
E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported)
|
||||
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000
|
||||
|
||||
|
||||
/* Description FEC_CODING
|
||||
|
||||
<enum 0 ht_bcc> Indicates BCC coding
|
||||
<enum 1 ht_ldpc> Indicates LDPC coding
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000
|
||||
|
||||
|
||||
/* Description SHORT_GI
|
||||
|
||||
<enum 0 ht_normal_gi> Indicates normal guard interval
|
||||
|
||||
<enum 1 ht_short_gi> Indicates short guard interval
|
||||
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000
|
||||
|
||||
|
||||
/* Description NUM_EXT_SP_STR
|
||||
|
||||
Number of extension spatial streams: (Used for TxBF)
|
||||
<enum 0 0_ext_sp_str> No extension spatial streams
|
||||
E_num 1 1_ext_sp_str Not supported: 1 extension spatial
|
||||
streams
|
||||
E_num 2 2_ext_sp_str Not supported: 2 extension spatial
|
||||
streams
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0].
|
||||
The generator polynomial is G(D) = D8 + D2 + D + 1. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
|
||||
|
||||
|
||||
/* Description SIGNAL_TAIL
|
||||
|
||||
The 6 bits of tail is always set to 0 is used to flush the
|
||||
BCC encoder and decoder. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
This field is not part of HT-SIG:
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HT-SIG CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_HT_SIG
|
||||
208
hw/qcn6432/mactx_l_sig_a.h
Archivo normal
208
hw/qcn6432/mactx_l_sig_a.h
Archivo normal
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_L_SIG_A_H_
|
||||
#define _MACTX_L_SIG_A_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "l_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_L_SIG_A 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_L_SIG_A 1
|
||||
|
||||
|
||||
struct mactx_l_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_a_info mactx_l_sig_a_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct l_sig_a_info mactx_l_sig_a_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_L_SIG_A_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description RATE
|
||||
|
||||
This format is originally defined for OFDM as a 4 bit field
|
||||
but the 5th bit was added to indicate 11b formatted frames.
|
||||
In the standard bit [4] is specified as reserved. For
|
||||
11b frames this L-SIG is transformed in the PHY into the
|
||||
11b preamble format. The following are the rates:
|
||||
<enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
|
||||
<enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
|
||||
<enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
|
||||
<enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
|
||||
<enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
|
||||
<enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
|
||||
<enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
|
||||
<enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
|
||||
<legal 8-15>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f
|
||||
|
||||
|
||||
/* Description LSIG_RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
The length indicates the number of octets in this MPDU.
|
||||
Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be
|
||||
this length provides the spoofed length for the PPDU.
|
||||
This length provides part of the information (viz. PPDU
|
||||
duration) to derive the actually PSDU length. For legacy
|
||||
OFDM and 11B frames the maximum length is 4095.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0
|
||||
|
||||
|
||||
/* Description PARITY
|
||||
|
||||
11a/n/ac TX: This field provides even parity over the first
|
||||
18 bits of the signal field which means that the sum of
|
||||
1s in the signal field will always be even on transmission.
|
||||
The value of the field is computed by the MAC.
|
||||
11a/n/ac RX: this field contains the received parity field
|
||||
from the L-SIG symbol for the current packet.
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
The 6 bits of tail is always set to 0 is used to flush the
|
||||
BCC encoder and decoder. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000
|
||||
|
||||
|
||||
/* Description PKT_TYPE
|
||||
|
||||
Only used on the RX side.
|
||||
Note: This is not really part of L-SIG
|
||||
|
||||
Packet type:
|
||||
<enum 0 dot11a>802.11a PPDU type
|
||||
<enum 1 dot11b>802.11b PPDU type
|
||||
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
|
||||
<enum 3 dot11ac>802.11ac PPDU type
|
||||
<enum 4 dot11ax>802.11ax PPDU type
|
||||
<enum 5 dot11ba>802.11ba (WUR) PPDU type
|
||||
<enum 6 dot11be>802.11be PPDU type
|
||||
<enum 7 dot11az>802.11az (ranging) PPDU type
|
||||
<enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported
|
||||
& aborted)
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
|
||||
|
||||
|
||||
/* Description CAPTURED_IMPLICIT_SOUNDING
|
||||
|
||||
Only used on the RX side.
|
||||
Note: This is not really part of L-SIG
|
||||
|
||||
This indicates that the PHY has captured implicit sounding.
|
||||
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the transmitting MAC and
|
||||
ignored by the PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the L-SIG integrity
|
||||
check has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_L_SIG_A
|
||||
116
hw/qcn6432/mactx_l_sig_b.h
Archivo normal
116
hw/qcn6432/mactx_l_sig_b.h
Archivo normal
@@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_L_SIG_B_H_
|
||||
#define _MACTX_L_SIG_B_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "l_sig_b_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_L_SIG_B 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_L_SIG_B 1
|
||||
|
||||
|
||||
struct mactx_l_sig_b {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_b_info mactx_l_sig_b_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct l_sig_b_info mactx_l_sig_b_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_L_SIG_B_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description RATE
|
||||
|
||||
<enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
|
||||
<enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
|
||||
<enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
|
||||
<enum 4 cck_11_mbps_long> CCK 11 Mbps long
|
||||
<enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
|
||||
<enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
|
||||
<enum 7 cck_11_mbps_short> CCK 11 Mbps short
|
||||
<legal 1-7>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
The length indicates the number of octets in this MPDU.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the transmitting MAC and
|
||||
ignored by the PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the .11b PHY header
|
||||
CRC check has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_L_SIG_B
|
||||
1079
hw/qcn6432/mactx_phy_desc.h
Archivo normal
1079
hw/qcn6432/mactx_phy_desc.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
109
hw/qcn6432/mactx_service.h
Archivo normal
109
hw/qcn6432/mactx_service.h
Archivo normal
@@ -0,0 +1,109 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_SERVICE_H_
|
||||
#define _MACTX_SERVICE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "service_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_SERVICE 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_SERVICE 1
|
||||
|
||||
|
||||
struct mactx_service {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct service_info mactx_service_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct service_info mactx_service_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_SERVICE_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT.
|
||||
|
||||
In case of EHT, instead of 'SERVICE_INFO' the STRUCT 'EHT_SERVICE_INFO'
|
||||
is used. See detailed description of the STRUCT.
|
||||
*/
|
||||
|
||||
|
||||
/* Description SCRAMBLER_SEED
|
||||
|
||||
This field provides the 7-bit seed for the data scrambler.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000000
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_LSB 0
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_MSB 6
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_MASK 0x000000000000007f
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Reserved. Set to 0 by sender and ignored by receiver. <legal
|
||||
0>
|
||||
*/
|
||||
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_LSB 7
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_MSB 7
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_MASK 0x0000000000000080
|
||||
|
||||
|
||||
/* Description SIG_B_CRC_USER
|
||||
|
||||
In case of vht transmission: vht_sig_b_crc_user
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_OFFSET 0x0000000000000000
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_LSB 8
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_MSB 15
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_MASK 0x000000000000ff00
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_LSB 16
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_MSB 31
|
||||
#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_SERVICE_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_SERVICE_TLV64_PADDING_LSB 32
|
||||
#define MACTX_SERVICE_TLV64_PADDING_MSB 63
|
||||
#define MACTX_SERVICE_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_SERVICE
|
||||
347
hw/qcn6432/mactx_u_sig_eht_su_mu.h
Archivo normal
347
hw/qcn6432/mactx_u_sig_eht_su_mu.h
Archivo normal
@@ -0,0 +1,347 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
|
||||
#define _MACTX_U_SIG_EHT_SU_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "u_sig_eht_su_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1
|
||||
|
||||
|
||||
struct mactx_u_sig_eht_su_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
|
||||
#else
|
||||
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description PHY_VERSION
|
||||
|
||||
<enum 0 U_SIG_VERSION_EHT>
|
||||
Values 1 - 7 are reserved.
|
||||
<legal 0
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU
|
||||
|
||||
<enum 0 U_SIG_BW20> 20 MHz
|
||||
<enum 1 U_SIG_BW40> 40 MHz
|
||||
<enum 2 U_SIG_BW80> 80 MHz
|
||||
<enum 3 U_SIG_BW160> 160 MHz
|
||||
<enum 4 U_SIG_BW320> 320 MHz
|
||||
<enum 5 U_SIG_BW320_2> DO NOT USE
|
||||
|
||||
Microcode remaps 'U_SIG_BW320' based on channelization.
|
||||
|
||||
On RX side, field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
|
||||
|
||||
|
||||
/* Description DISREGARD_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1s
|
||||
<legal 31>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000
|
||||
|
||||
|
||||
/* Description VALIDATE_0B
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000
|
||||
|
||||
|
||||
/* Description RESERVED_0C
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description EHT_PPDU_SIG_CMN_TYPE
|
||||
|
||||
<enum 3 EHT_PPDU_SIG_rsvd> DO NOT USE
|
||||
<enum 0 EHT_PPDU_SIG_TB_or_DL_OFDMA> Need to look at both
|
||||
EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO)
|
||||
|
||||
<enum 2 EHT_PPDU_SIG_DL_MU_MIMO> Need to look at both EHT-SIG
|
||||
content channels
|
||||
<enum 1 EHT_PPDU_SIG_SU> Need to look at only one EHT-SIG
|
||||
content channel
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
|
||||
|
||||
|
||||
/* Description VALIDATE_1A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000
|
||||
|
||||
|
||||
/* Description PUNCTURED_CHANNEL_INFORMATION
|
||||
|
||||
For OFDMA BW 20 MHz or 40 MHz:
|
||||
Set to all 1s, i.e. 31
|
||||
|
||||
For OFDMA of higher BW:
|
||||
Bit 3 = lowest 20 MHz in the current 80 MHz
|
||||
Bit 6 = highest 20 MHz in the current 80 MHz
|
||||
Bit 7 = 1
|
||||
|
||||
Each bit indicates whether the 20 MHz is modulated or punctured
|
||||
|
||||
0 = punctured
|
||||
1 = modulated
|
||||
|
||||
For non-OFDMA:
|
||||
Set to a 5-bit value encoding the puncture pattern, a.k.a. 'U_sig_puncture_pattern_encoding'
|
||||
elsewhere in the data structures
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000
|
||||
|
||||
|
||||
/* Description VALIDATE_1B
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000
|
||||
|
||||
|
||||
/* Description MCS_OF_EHT_SIG
|
||||
|
||||
Indicates the MCS of EHT-SIG
|
||||
0 - 1: MCS 0 - 1
|
||||
2: MCS 3
|
||||
3: MCS 0 with DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000
|
||||
|
||||
|
||||
/* Description NUM_EHT_SIG_SYMBOLS
|
||||
|
||||
Number of symbols
|
||||
|
||||
The actual number of symbols is 1 larger than indicated
|
||||
in this field.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for U-SIG contents
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description DOT11AX_SU_EXTENDED
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side: On RX side, evaluated by MAC HW
|
||||
|
||||
This is the only way for MAC RX to know that this was a
|
||||
U_SIG_EHT_SU received in extended range format.
|
||||
|
||||
When set, the 11be frame is of the extended range format.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1D
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side: On RX side, looked at by MAC HW
|
||||
|
||||
When set, PHY has received an (expected) NDP frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the U-SIG CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_U_SIG_EHT_SU_MU
|
||||
249
hw/qcn6432/mactx_u_sig_eht_tb.h
Archivo normal
249
hw/qcn6432/mactx_u_sig_eht_tb.h
Archivo normal
@@ -0,0 +1,249 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_U_SIG_EHT_TB_H_
|
||||
#define _MACTX_U_SIG_EHT_TB_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "u_sig_eht_tb_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1
|
||||
|
||||
|
||||
struct mactx_u_sig_eht_tb {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
|
||||
#else
|
||||
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_U_SIG_EHT_TB_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description PHY_VERSION
|
||||
|
||||
<enum 0 U_SIG_VERSION_EHT>
|
||||
Values 1 - 7 are reserved.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU, as indicated in the trigger frame
|
||||
|
||||
|
||||
<enum 0 U_SIG_BW20> 20 MHz
|
||||
<enum 1 U_SIG_BW40> 40 MHz
|
||||
<enum 2 U_SIG_BW80> 80 MHz
|
||||
<enum 3 U_SIG_BW160> 160 MHz
|
||||
<enum 4 U_SIG_BW320> 320 MHz channelization scheme 1
|
||||
<enum 5 U_SIG_BW320_2> 320 MHz channelization scheme 2
|
||||
|
||||
On RX side, field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
|
||||
|
||||
|
||||
/* Description DISREGARD_0A
|
||||
|
||||
Set to value indicated in the trigger frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000
|
||||
|
||||
|
||||
/* Description RESERVED_0C
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description EHT_PPDU_SIG_CMN_TYPE
|
||||
|
||||
<enum 3 EHT_PPDU_SIG_rsvd> DO NOT USE
|
||||
<enum 0 EHT_PPDU_SIG_TB_or_DL_OFDMA> Need to look at both
|
||||
EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO)
|
||||
|
||||
<enum 2 EHT_PPDU_SIG_DL_MU_MIMO> Need to look at both EHT-SIG
|
||||
content channels
|
||||
<enum 1 EHT_PPDU_SIG_SU> Need to look at only one EHT-SIG
|
||||
content channel
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
|
||||
|
||||
|
||||
/* Description VALIDATE_1A
|
||||
|
||||
Set to value indicated in the trigger frame
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
TODO: Placeholder
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000
|
||||
|
||||
|
||||
/* Description DISREGARD_1B
|
||||
|
||||
Set to value indicated in the trigger frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for U-SIG contents
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1C
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the U-SIG CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_U_SIG_EHT_TB
|
||||
1305
hw/qcn6432/mactx_user_desc_common.h
Archivo normal
1305
hw/qcn6432/mactx_user_desc_common.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
473
hw/qcn6432/mactx_user_desc_per_user.h
Archivo normal
473
hw/qcn6432/mactx_user_desc_per_user.h
Archivo normal
@@ -0,0 +1,473 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_USER_DESC_PER_USER_H_
|
||||
#define _MACTX_USER_DESC_PER_USER_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2
|
||||
|
||||
|
||||
struct mactx_user_desc_per_user {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t psdu_length : 24, // [23:0]
|
||||
reserved_0a : 8; // [31:24]
|
||||
uint32_t ru_start_index : 8, // [7:0]
|
||||
ru_size : 4, // [11:8]
|
||||
reserved_1b : 4, // [15:12]
|
||||
ofdma_mu_mimo_enabled : 1, // [16:16]
|
||||
nss : 3, // [19:17]
|
||||
stream_offset : 3, // [22:20]
|
||||
reserved_1c : 1, // [23:23]
|
||||
mcs : 4, // [27:24]
|
||||
dcm : 1, // [28:28]
|
||||
reserved_1d : 3; // [31:29]
|
||||
uint32_t fec_type : 1, // [0:0]
|
||||
reserved_2a : 7, // [7:1]
|
||||
user_bf_type : 2, // [9:8]
|
||||
reserved_2b : 6, // [15:10]
|
||||
drop_user_cbf : 1, // [16:16]
|
||||
reserved_2c : 7, // [23:17]
|
||||
ldpc_extra_symbol : 1, // [24:24]
|
||||
force_extra_symbol : 1, // [25:25]
|
||||
reserved_2d : 6; // [31:26]
|
||||
uint32_t sw_peer_id : 16, // [15:0]
|
||||
per_user_subband_mask : 16; // [31:16]
|
||||
#else
|
||||
uint32_t reserved_0a : 8, // [31:24]
|
||||
psdu_length : 24; // [23:0]
|
||||
uint32_t reserved_1d : 3, // [31:29]
|
||||
dcm : 1, // [28:28]
|
||||
mcs : 4, // [27:24]
|
||||
reserved_1c : 1, // [23:23]
|
||||
stream_offset : 3, // [22:20]
|
||||
nss : 3, // [19:17]
|
||||
ofdma_mu_mimo_enabled : 1, // [16:16]
|
||||
reserved_1b : 4, // [15:12]
|
||||
ru_size : 4, // [11:8]
|
||||
ru_start_index : 8; // [7:0]
|
||||
uint32_t reserved_2d : 6, // [31:26]
|
||||
force_extra_symbol : 1, // [25:25]
|
||||
ldpc_extra_symbol : 1, // [24:24]
|
||||
reserved_2c : 7, // [23:17]
|
||||
drop_user_cbf : 1, // [16:16]
|
||||
reserved_2b : 6, // [15:10]
|
||||
user_bf_type : 2, // [9:8]
|
||||
reserved_2a : 7, // [7:1]
|
||||
fec_type : 1; // [0:0]
|
||||
uint32_t per_user_subband_mask : 16, // [31:16]
|
||||
sw_peer_id : 16; // [15:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PSDU_LENGTH
|
||||
|
||||
PSDU Length for the User in octets
|
||||
NOTE: This also holds good for .11ba packets
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description RU_START_INDEX
|
||||
|
||||
Field only valid in case of .11ax or .11be OFDMA transmission
|
||||
(=> from MACTX_PHY_DESC, field MU_type == OFDMA)
|
||||
OR
|
||||
11ax SU "Narrow band" transmission.
|
||||
|
||||
RU Number to which User is assigned
|
||||
RU numbering is over the entire BW, starting from 0 and
|
||||
for the different users in increasing frequency order and
|
||||
not primary-secondary order.
|
||||
|
||||
For DL OFDMA transmissions, PDG shall fill this as instructed
|
||||
by SW.
|
||||
|
||||
For UL OFDMA transmissions, the RU number within 80 MHz
|
||||
is available from the RU allocation information in the trigger.
|
||||
For 160 MHz UL OFDMA transmissions, the trigger RU allocation
|
||||
only mentions primary/secondary 80 MHz. PDG needs to convert
|
||||
this to lower/higher 80 MHz.
|
||||
|
||||
If in 'PCU_PPDU_SETUP_START'/'MACTX_PRE_PHY_DESC,' CCA_Subband_channel_bonding_mask
|
||||
bit 0 is mapped to any of bits 4 - 7 of Freq_Subband_channel_bonding_mask,
|
||||
then the primary 80 MHz is the higher 80 MHz and the secondary
|
||||
80 MHz is the lower one.
|
||||
Otherwise (if CCA_Subband_channel_bonding_mask bit 0 is
|
||||
mapped to any of bits 0 - 3 of Freq_Subband_channel_bonding_mask,
|
||||
then the primary 80 MHz is the lower 80 MHz and the secondary
|
||||
80 MHz is the higher one.
|
||||
|
||||
<legal 0-147>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description RU_SIZE
|
||||
|
||||
The size of the RU for this user
|
||||
|
||||
In case of HE extended range transmission, e-num 2 (10MHz)
|
||||
or e-num 7 (20MHz) are used.
|
||||
|
||||
In case of trig transmission or OFDMA single user or MU-MIMO
|
||||
single user transmission, if the RU allocated to the user
|
||||
is the full BW (with respect to AP_bw) then the e-num 7
|
||||
is used.
|
||||
For all other cases, e-nums corresponding to the RU size
|
||||
allocated to the user is used.
|
||||
|
||||
In case of EHT duplicate transmissions, this field indicates
|
||||
the width of the actual content before duplication, e.g.
|
||||
a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth
|
||||
fields indicating 160 MHz and this field set to e-num 4
|
||||
(RU_484).
|
||||
|
||||
<enum 0 RU_26>
|
||||
<enum 1 RU_52>
|
||||
<enum 2 RU_106>
|
||||
<enum 3 RU_242>
|
||||
<enum 4 RU_484>
|
||||
<enum 5 RU_996>
|
||||
<enum 6 RU_1992>
|
||||
<enum 7 RU_FULLBW> Set when the RU occupies the full packet
|
||||
bandwidth
|
||||
<enum 8 RU_FULLBW_240> Set when the RU occupies the full
|
||||
packet bandwidth
|
||||
<enum 9 RU_FULLBW_320> Set when the RU occupies the full
|
||||
packet bandwidth
|
||||
<enum 10 RU_MULTI_LARGE> HW will use per-user sub-band-mask
|
||||
to infer the actual RU-size for Multi-large-RU/SU-Puncturing
|
||||
|
||||
<enum 11 RU_78> multi small RU
|
||||
<enum 12 RU_132> multi small RU<legal 0-12>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000
|
||||
|
||||
|
||||
/* Description OFDMA_MU_MIMO_ENABLED
|
||||
|
||||
Field only valid in case of .11ax or .11be OFDMA transmission
|
||||
(=> from MACTX_PHY_DESC, field MU_type == OFDMA)
|
||||
|
||||
When set, for this user there is MIMO transmission within
|
||||
the RU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000
|
||||
|
||||
|
||||
/* Description NSS
|
||||
|
||||
Number of Spatial Streams occupied by the User
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_LSB 49
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_MSB 51
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000
|
||||
|
||||
|
||||
/* Description STREAM_OFFSET
|
||||
|
||||
Field only valid in case of MU-MIMO transmission (=> from
|
||||
MACTX_PHY_DESC, field MU_type == MU-MIMO)
|
||||
OR
|
||||
when field Ofdma_mu_mimo_enabled is set
|
||||
|
||||
Stream Offset from which the User occupies the Streams
|
||||
|
||||
Note MAC:
|
||||
directly from pdg_fes_setup, based on BW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1C
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation Coding Scheme for the User
|
||||
|
||||
The MCS to be used for the upcoming transmission. It must
|
||||
match the 4-bit MCS value that is sent in the appropriate
|
||||
signal field for the given packet type, except that EHT
|
||||
BPSK with DCM and/or duplicate is encoded as '0.'
|
||||
|
||||
|
||||
For details, refer to the SIG field, related to this pkt_type.
|
||||
|
||||
(Note that this is slightly different then what is on the
|
||||
MAC side defined as "MCS_TYPE". For this reason, the 'legal
|
||||
values' here are NOT defined as MCS_TYPE)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_LSB 56
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_MSB 59
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000
|
||||
|
||||
|
||||
/* Description DCM
|
||||
|
||||
Field only valid in case of 11ax transmission
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_LSB 60
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_MSB 60
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1D
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000
|
||||
|
||||
|
||||
/* Description FEC_TYPE
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe
|
||||
|
||||
|
||||
/* Description USER_BF_TYPE
|
||||
|
||||
This field is valid for all packets using multiple antennas
|
||||
because it defines whether the user's tones will be beamformed,
|
||||
spatially spread, both or none of the above.
|
||||
|
||||
<enum 0 USER_NO_BF> Direct mapping from Stream to Chain
|
||||
|
||||
<enum 1 USER_WALSH_ONLY> Enable Walsh mapping only
|
||||
<enum 2 USER_BF_ONLY> Enable Beamforming only
|
||||
<enum 3 USER_WALSH_AND_BF> Enable Walsh and Beamforming
|
||||
|
||||
|
||||
NOTE: USER_NO_BF and USER_BF_ONLY are not allowed if the
|
||||
number of spatial streams (NSS) < the number of Tx chains
|
||||
(NTx).
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300
|
||||
|
||||
|
||||
/* Description RESERVED_2B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00
|
||||
|
||||
|
||||
/* Description DROP_USER_CBF
|
||||
|
||||
This user shall be dropped because of CBF FCS failure or
|
||||
no CBF reception.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000
|
||||
|
||||
|
||||
/* Description RESERVED_2C
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
Set to 1 if the LDPC PPDU encoding process (if an SU PPDU),
|
||||
or at least one LDPC user's PPDU encoding process (if an
|
||||
MU PPDU), results in an extra OFDM symbol (or symbols)
|
||||
as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
|
||||
(Encoding process for MU PPDUs). Set to 0 otherwise.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000
|
||||
|
||||
|
||||
/* Description FORCE_EXTRA_SYMBOL
|
||||
|
||||
Set to 1 to force an extra OFDM symbol (or symbols) even
|
||||
if none of the users' PPDU encoding process resuls in an
|
||||
extra OFDM symbol (or symbols).
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000
|
||||
|
||||
|
||||
/* Description RESERVED_2D
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description SW_PEER_ID
|
||||
|
||||
When set to 0, SW did not populate this field.
|
||||
|
||||
The SW peer ID for this user
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description PER_USER_SUBBAND_MASK
|
||||
|
||||
This specifies a per-20 MHz (frequency order) subband mask
|
||||
per-user to be used in case of either multi-large-RU or
|
||||
preamble puncturing.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_USER_DESC_PER_USER
|
||||
361
hw/qcn6432/mactx_vht_sig_a.h
Archivo normal
361
hw/qcn6432/mactx_vht_sig_a.h
Archivo normal
@@ -0,0 +1,361 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_A_H_
|
||||
#define _MACTX_VHT_SIG_A_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1
|
||||
|
||||
|
||||
struct mactx_vht_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_a_info mactx_vht_sig_a_info_details;
|
||||
#else
|
||||
struct vht_sig_a_info mactx_vht_sig_a_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_A_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description BANDWIDTH
|
||||
|
||||
Packet bandwidth
|
||||
|
||||
<enum 0 20_MHZ_11AC>
|
||||
<enum 1 40_MHZ_11AC>
|
||||
<enum 2 80_MHZ_11AC>
|
||||
<enum 3 160_MHZ_11AC>
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003
|
||||
|
||||
|
||||
/* Description VHTA_RESERVED_0
|
||||
|
||||
Reserved. Set to 1 by MAC, PHY should ignore
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Space time block coding:
|
||||
<enum 0 stbc_disabled> Indicates STBC is disabled
|
||||
<enum 1 stbc_enabled> Indicates STBC is enabled on
|
||||
all streams
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008
|
||||
|
||||
|
||||
/* Description GROUP_ID
|
||||
|
||||
In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
|
||||
to an AP or to a mesh STA, the Group ID field is set to
|
||||
0, otherwise it is set to 63. In an NDP PPDU the Group
|
||||
ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6
|
||||
(Transmission of a VHT NDP). For a MU-MIMO PPDU the Group
|
||||
ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group
|
||||
ID). <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0
|
||||
|
||||
|
||||
/* Description N_STS
|
||||
|
||||
For MU:
|
||||
3 bits/user with maximum of 4 users (user u uses
|
||||
vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
|
||||
3)
|
||||
Set to 0 for 0 space time streams
|
||||
Set to 1 for 1 space time stream
|
||||
Set to 2 for 2 space time streams
|
||||
Set to 3 for 3 space time streams
|
||||
Set to 4 for 4 space time streams (not supported in Wifi
|
||||
3.0)
|
||||
Values 5-7 are reserved
|
||||
In this field, references to user "u" should be interpreted
|
||||
as MU user "u". As described in the previous chapter in
|
||||
this document (see chapter on User number), the MU user
|
||||
value for a given client is defined for each MU group that
|
||||
the client participates in. The MU user number is not related
|
||||
to the internal user number that is used within the BFer.
|
||||
|
||||
|
||||
|
||||
For SU:
|
||||
vht_sig_a[0][12:10]
|
||||
Set to 0 for 1 space time stream
|
||||
Set to 1 for 2 space time streams
|
||||
Set to 2 for 3 space time streams
|
||||
Set to 3 for 4 space time streams
|
||||
Set to 4 for 5 space time streams
|
||||
Set to 5 for 6 space time streams
|
||||
Set to 6 for 7 space time streams
|
||||
Set to 7 for 8 space time streams
|
||||
|
||||
vht_sig_a[0][21:13]
|
||||
Partial AID:
|
||||
Set to the value of the TXVECTOR parameter PARTIAL_AID.
|
||||
Partial AID provides an abbreviated indication of the intended
|
||||
recipient(s) of the frame (see IEEE802.11ac_D1.0 Section
|
||||
9.17a (Partial AID in VHT PPDUs)).
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00
|
||||
|
||||
|
||||
/* Description TXOP_PS_NOT_ALLOWED
|
||||
|
||||
E_num 0 txop_ps_allowed Not supported: If set to by
|
||||
VHT AP if it allows non-AP VHT STAs in TXOP power save
|
||||
mode to enter Doze state during a TXOP
|
||||
<enum 1 no_txop_ps_allowed> Otherwise
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000
|
||||
|
||||
|
||||
/* Description VHTA_RESERVED_0B
|
||||
|
||||
Reserved: Should be set to 1 by the MAC and ignored by the
|
||||
PHY <legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
This field is not part of HT-SIG:
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description GI_SETTING
|
||||
|
||||
<enum 0 normal_gi> Indicates short guard interval is
|
||||
not used in the data field
|
||||
<enum 1 short_gi> Indicates short guard interval is
|
||||
used in the data field
|
||||
<enum 3 short_gi_ambiguity> Indicates short guard interval
|
||||
is used in the data field and NSYM mod 10 = 9
|
||||
NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME
|
||||
and PSDU_LENGTH calculation).
|
||||
<legal 0,1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000
|
||||
|
||||
|
||||
/* Description SU_MU_CODING
|
||||
|
||||
For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an
|
||||
MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
|
||||
B2 indicates the coding used for user 0; set to 0 for BCC
|
||||
and 1 for LDPC. If the MU[0] NSTS field is 0, then this
|
||||
field is reserved and set to 1
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
Set to 1 if the LDPC PPDU encoding process (if an SU PPDU),
|
||||
or at least one LDPC user's PPDU encoding process (if an
|
||||
MU PPDU), results in an extra OFDM symbol (or symbols)
|
||||
as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
|
||||
(Encoding process for MU PPDUs). Set to 0 otherwise.
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
For SU:
|
||||
Set to 0 for BPSK 1/2
|
||||
Set to 1 for QPSK 1/2
|
||||
Set to 2 for QPSK 3/4
|
||||
Set to 3 for 16-QAM 1/2
|
||||
Set to 4 for 16-QAM 3/4
|
||||
Set to 5 for 64-QAM 2/3
|
||||
Set to 6 for 64-QAM 3/4
|
||||
Set to 7 for 64-QAM 5/6
|
||||
Set to 8 for 256-QAM 3/4
|
||||
Set to 9 for 256-QAM 5/6
|
||||
For MU:
|
||||
If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates
|
||||
coding for user 1: set to 0 for BCC, 1 for LDPC.
|
||||
If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
|
||||
reserved and set to 1.
|
||||
If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates
|
||||
coding for user 2: set to 0 for BCC, 1 for LDPC.
|
||||
If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
|
||||
reserved and set to 1.
|
||||
If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates
|
||||
coding for user 3: set to 0 for BCC, 1 for LDPC.
|
||||
If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
|
||||
reserved and set to 1.
|
||||
vht_sig_a[1][7] is reserved and set to 1
|
||||
<legal 0-15>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000
|
||||
|
||||
|
||||
/* Description BEAMFORMED
|
||||
|
||||
For SU:
|
||||
Set to 1 if a Beamforming steering matrix is applied to
|
||||
the waveform in an SU transmission as described in IEEE802.11ac_D1.0
|
||||
Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise.
|
||||
|
||||
For MU:
|
||||
Reserved and set to 1
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000
|
||||
|
||||
|
||||
/* Description VHTA_RESERVED_1
|
||||
|
||||
Reserved and set to 1. <legal 1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4
|
||||
(CRC calculation for HTSIG) with C7 in vht_sig_a[1][10],
|
||||
etc. <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
This field is not part of HT-SIG:
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_A
|
||||
437
hw/qcn6432/mactx_vht_sig_b_mu160.h
Archivo normal
437
hw/qcn6432/mactx_vht_sig_b_mu160.h
Archivo normal
@@ -0,0 +1,437 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU160_H_
|
||||
#define _MACTX_VHT_SIG_B_MU160_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_mu160 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_MU160_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation as described in vht_sig_a mcs field <legal 0-11>
|
||||
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_A
|
||||
|
||||
Same as "length". This field is not valid for RX packets
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
|
||||
|
||||
|
||||
/* Description MCS_COPY_A
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets <legal
|
||||
0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_A
|
||||
|
||||
Same as "tail". This field is not valid for RX packets <legal
|
||||
0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_B
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
|
||||
|
||||
|
||||
/* Description MCS_COPY_B
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_B
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_2
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_C
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
|
||||
|
||||
|
||||
/* Description MCS_COPY_C
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_C
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_3
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_D
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff
|
||||
|
||||
|
||||
/* Description MCS_COPY_D
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_D
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_4
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_E
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000
|
||||
|
||||
|
||||
/* Description MCS_COPY_E
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_E
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_5
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_F
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff
|
||||
|
||||
|
||||
/* Description MCS_COPY_F
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_F
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description MU_USER_NUMBER
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Mapping from user number (BFer hardware specific) to mu_user_number.
|
||||
The reader is directed to the previous chapter (User Number)
|
||||
for a definition of the terms user and mu_user. <legal
|
||||
0-3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_G
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000
|
||||
|
||||
|
||||
/* Description MCS_COPY_G
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_G
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_7
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_MU160
|
||||
123
hw/qcn6432/mactx_vht_sig_b_mu20.h
Archivo normal
123
hw/qcn6432/mactx_vht_sig_b_mu20.h
Archivo normal
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU20_H_
|
||||
#define _MACTX_VHT_SIG_B_MU20_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu20_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_mu20 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_MU20_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4)
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation as described in vht_sig_a mcs field
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000
|
||||
|
||||
|
||||
/* Description MU_USER_NUMBER
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Mapping from user number (BFer hardware specific) to mu_user_number.
|
||||
The reader is directed to the previous chapter (User Number)
|
||||
for a definition of the terms user and mu_user.
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_MU20
|
||||
156
hw/qcn6432/mactx_vht_sig_b_mu40.h
Archivo normal
156
hw/qcn6432/mactx_vht_sig_b_mu40.h
Archivo normal
@@ -0,0 +1,156 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU40_H_
|
||||
#define _MACTX_VHT_SIG_B_MU40_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu40_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_mu40 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_MU40_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation as described in vht_sig_a mcs field
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
Set to 0.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000
|
||||
|
||||
|
||||
/* Description MU_USER_NUMBER
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Mapping from user number (BFer hardware specific) to mu_user_number.
|
||||
The reader is directed to the previous chapter (User Number)
|
||||
for a definition of the terms user and mu_user. <legal
|
||||
0-3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000
|
||||
|
||||
|
||||
/* Description MCS_COPY
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets. <legal
|
||||
0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_MU40
|
||||
241
hw/qcn6432/mactx_vht_sig_b_mu80.h
Archivo normal
241
hw/qcn6432/mactx_vht_sig_b_mu80.h
Archivo normal
@@ -0,0 +1,241 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU80_H_
|
||||
#define _MACTX_VHT_SIG_B_MU80_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu80_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_mu80 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_MU80_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation as described in vht_sig_a mcs field <legal 0-11>
|
||||
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_A
|
||||
|
||||
Same as "length". This field is not valid for RX packets
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
|
||||
|
||||
|
||||
/* Description MCS_COPY_A
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets <legal
|
||||
0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_A
|
||||
|
||||
Same as "tail". This field is not valid for RX packets <legal
|
||||
0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_B
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
|
||||
|
||||
|
||||
/* Description MCS_COPY_B
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_B
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description MU_USER_NUMBER
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Mapping from user number (BFer hardware specific) to mu_user_number.
|
||||
The reader is directed to the previous chapter (User Number)
|
||||
for a definition of the terms user and mu_user. <legal
|
||||
0-3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_C
|
||||
|
||||
Same as "length". This field is not valid for RX packets. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
|
||||
|
||||
|
||||
/* Description MCS_COPY_C
|
||||
|
||||
Same as "mcs". This field is not valid for RX packets.
|
||||
|
||||
<legal 0-11>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_C
|
||||
|
||||
Same as "tail". This field is not valid for RX packets.
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_3
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_MU80
|
||||
506
hw/qcn6432/mactx_vht_sig_b_su160.h
Archivo normal
506
hw/qcn6432/mactx_vht_sig_b_su160.h
Archivo normal
@@ -0,0 +1,506 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU160_H_
|
||||
#define _MACTX_VHT_SIG_B_SU160_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_su160 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_SU160_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4)
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED
|
||||
|
||||
Reserved: Set to all ones for non-NDP frames and ignored
|
||||
on receive <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_A
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_A
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_A
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_A
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_B
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_B
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_B
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_2
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_B
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_C
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_C
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_C
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_3
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_C
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_D
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_D
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_D
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_4
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_D
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_E
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_E
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_E
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_5
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_E
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_F
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_F
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_F
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_6
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_F
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_G
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_G
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_G
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_7
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_G
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_SU160
|
||||
123
hw/qcn6432/mactx_vht_sig_b_su20.h
Archivo normal
123
hw/qcn6432/mactx_vht_sig_b_su20.h
Archivo normal
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU20_H_
|
||||
#define _MACTX_VHT_SIG_B_SU20_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su20_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_su20 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_SU20_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4)
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED
|
||||
|
||||
Reserved: Set to all ones for non-NDP frames and ignored
|
||||
on receive
|
||||
<legal 2,7>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_SU20
|
||||
164
hw/qcn6432/mactx_vht_sig_b_su40.h
Archivo normal
164
hw/qcn6432/mactx_vht_sig_b_su40.h
Archivo normal
@@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU40_H_
|
||||
#define _MACTX_VHT_SIG_B_SU40_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su40_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_su40 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_SU40_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4)
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED
|
||||
|
||||
Reserved: Set to all ones and ignored on receive <legal
|
||||
3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY
|
||||
|
||||
Same as "vhtb_reserved" <legal 3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_COPY
|
||||
|
||||
Same as "reserved" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_SU40
|
||||
278
hw/qcn6432/mactx_vht_sig_b_su80.h
Archivo normal
278
hw/qcn6432/mactx_vht_sig_b_su80.h
Archivo normal
@@ -0,0 +1,278 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU80_H_
|
||||
#define _MACTX_VHT_SIG_B_SU80_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su80_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2
|
||||
|
||||
|
||||
struct mactx_vht_sig_b_su80 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MACTX_VHT_SIG_B_SU80_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4)
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED
|
||||
|
||||
Reserved: Set to all ones for non-NDP frames and ignored
|
||||
on receive <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_A
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_A
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_A
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_A
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_B
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_B
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_B
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
|
||||
/* Description RESERVED_2
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_B
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description LENGTH_COPY_C
|
||||
|
||||
Same as "length" <legal all>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
|
||||
|
||||
|
||||
/* Description VHTB_RESERVED_COPY_C
|
||||
|
||||
Same as "vhtb_reserved" <legal 1,3>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
|
||||
|
||||
|
||||
/* Description TAIL_COPY_C
|
||||
|
||||
Same as "tail" <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_3
|
||||
|
||||
Reserved: Set to 0 and ignored on receive <legal 0>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP_COPY_C
|
||||
|
||||
Not part of VHT-SIG-B.
|
||||
Used to identify received NDP frame
|
||||
<legal 0,1>
|
||||
*/
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MACTX_VHT_SIG_B_SU80
|
||||
105
hw/qcn6432/mlo_sta_id_details.h
Archivo normal
105
hw/qcn6432/mlo_sta_id_details.h
Archivo normal
@@ -0,0 +1,105 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MLO_STA_ID_DETAILS_H_
|
||||
#define _MLO_STA_ID_DETAILS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
|
||||
|
||||
|
||||
struct mlo_sta_id_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t nstr_mlo_sta_id : 10, // [9:0]
|
||||
block_self_ml_sync : 1, // [10:10]
|
||||
block_partner_ml_sync : 1, // [11:11]
|
||||
nstr_mlo_sta_id_valid : 1, // [12:12]
|
||||
reserved_0a : 3; // [15:13]
|
||||
#else
|
||||
uint16_t reserved_0a : 3, // [15:13]
|
||||
nstr_mlo_sta_id_valid : 1, // [12:12]
|
||||
block_partner_ml_sync : 1, // [11:11]
|
||||
block_self_ml_sync : 1, // [10:10]
|
||||
nstr_mlo_sta_id : 10; // [9:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description NSTR_MLO_STA_ID
|
||||
|
||||
ID of peer participating in non-STR MLO
|
||||
*/
|
||||
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
|
||||
/* Description BLOCK_SELF_ML_SYNC
|
||||
|
||||
Only valid for TX
|
||||
|
||||
When set, this provides an indication to block the peer
|
||||
for self-link.
|
||||
*/
|
||||
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
|
||||
/* Description BLOCK_PARTNER_ML_SYNC
|
||||
|
||||
Only valid for TX
|
||||
|
||||
When set, this provides an indication to block the peer
|
||||
for partner links.
|
||||
*/
|
||||
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
|
||||
/* Description NSTR_MLO_STA_ID_VALID
|
||||
|
||||
All the fields in this TLV are valid only if this bit is
|
||||
set.
|
||||
*/
|
||||
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
|
||||
|
||||
#endif // MLO_STA_ID_DETAILS
|
||||
155
hw/qcn6432/mon_buffer_addr.h
Archivo normal
155
hw/qcn6432/mon_buffer_addr.h
Archivo normal
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MON_BUFFER_ADDR_H_
|
||||
#define _MON_BUFFER_ADDR_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4
|
||||
|
||||
#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2
|
||||
|
||||
|
||||
struct mon_buffer_addr {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t buffer_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t buffer_virt_addr_63_32 : 32; // [31:0]
|
||||
uint32_t dma_length : 12, // [11:0]
|
||||
reserved_2a : 4, // [15:12]
|
||||
msdu_continuation : 1, // [16:16]
|
||||
truncated : 1, // [17:17]
|
||||
reserved_2b : 14; // [31:18]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
uint32_t buffer_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t buffer_virt_addr_63_32 : 32; // [31:0]
|
||||
uint32_t reserved_2b : 14, // [31:18]
|
||||
truncated : 1, // [17:17]
|
||||
msdu_continuation : 1, // [16:16]
|
||||
reserved_2a : 4, // [15:12]
|
||||
dma_length : 12; // [11:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description BUFFER_VIRT_ADDR_31_0
|
||||
|
||||
Lower 32 bits of the 64-bit virtual address of the packet
|
||||
buffer
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description BUFFER_VIRT_ADDR_63_32
|
||||
|
||||
Upper 32 bits of the 64-bit virtual address of the packet
|
||||
buffer
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description DMA_LENGTH
|
||||
|
||||
The number of bytes DMA'd into the packet buffer MINUS 1.
|
||||
|
||||
|
||||
The packet could be truncated in case of a 'TX_FLUSH' or
|
||||
'RX_FLUSH,' or in case of drops due to back-pressure.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff
|
||||
|
||||
|
||||
/* Description RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000
|
||||
|
||||
|
||||
/* Description MSDU_CONTINUATION
|
||||
|
||||
When set, this packet buffer was not able to hold the entire
|
||||
MSDU. The next buffer will therefore contain additional
|
||||
packet bytes.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000
|
||||
|
||||
|
||||
/* Description TRUNCATED
|
||||
|
||||
When set, this TLV belongs to a previously truncated MPDU.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_LSB 17
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_MSB 17
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000
|
||||
|
||||
|
||||
/* Description RESERVED_2B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // MON_BUFFER_ADDR
|
||||
224
hw/qcn6432/mon_destination_ring.h
Archivo normal
224
hw/qcn6432/mon_destination_ring.h
Archivo normal
@@ -0,0 +1,224 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MON_DESTINATION_RING_H_
|
||||
#define _MON_DESTINATION_RING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
|
||||
|
||||
|
||||
struct mon_destination_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0]
|
||||
uint32_t ppdu_id : 32; // [31:0]
|
||||
uint32_t end_offset : 12, // [11:0]
|
||||
reserved_3a : 4, // [15:12]
|
||||
end_reason : 2, // [17:16]
|
||||
initiator : 1, // [18:18]
|
||||
empty_descriptor : 1, // [19:19]
|
||||
ring_id : 8, // [27:20]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0]
|
||||
uint32_t ppdu_id : 32; // [31:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
ring_id : 8, // [27:20]
|
||||
empty_descriptor : 1, // [19:19]
|
||||
initiator : 1, // [18:18]
|
||||
end_reason : 2, // [17:16]
|
||||
reserved_3a : 4, // [15:12]
|
||||
end_offset : 12; // [11:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STAT_BUF_VIRT_ADDR_31_0
|
||||
|
||||
Lower 32 bits of the 64-bit virtual address of the status
|
||||
buffer
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description STAT_BUF_VIRT_ADDR_63_32
|
||||
|
||||
Upper 32 bits of the 64-bit virtual address of the status
|
||||
buffer
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description PPDU_ID
|
||||
|
||||
TXMON fills this with the schedule_id from 'TX_FES_SETUP'
|
||||
when Initiator = 1.
|
||||
TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO'
|
||||
when Initiator = 0.
|
||||
RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.'
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008
|
||||
#define MON_DESTINATION_RING_PPDU_ID_LSB 0
|
||||
#define MON_DESTINATION_RING_PPDU_ID_MSB 31
|
||||
#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description END_OFFSET
|
||||
|
||||
The offset (in units of 4 bytes) into the status buffer
|
||||
where DMA ended, i.e. offset to the last TLV + last TLV
|
||||
size MINUS 1.
|
||||
|
||||
In case of a 'TX_FLUSH' or 'RX_FLUSH,' this reflects the
|
||||
offset at which flush occurred.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_END_OFFSET_LSB 0
|
||||
#define MON_DESTINATION_RING_END_OFFSET_MSB 11
|
||||
#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_LSB 12
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_MSB 15
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x0000f000
|
||||
|
||||
|
||||
/* Description END_REASON
|
||||
|
||||
<enum 0 MON_status_buffer_full> The status buffer was fully
|
||||
written.
|
||||
<enum 1 MON_flush_detected> A 'TX_FLUSH' or 'RX_FLUSH' was
|
||||
received. This is implicitly the end of the Tx FES or Rx
|
||||
PPDU. The status buffer data can be discarded by SW.
|
||||
<enum 2 MON_end_of_PPDU> A 'TX_FES_STATUS_END' or 'RX_PPDU_END'
|
||||
was received indicating the end of the Tx FES or Rx PPDU.
|
||||
|
||||
<enum 3 MON_PPDU_truncated> The PPDU got truncated due to
|
||||
a system-level error.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_END_REASON_LSB 16
|
||||
#define MON_DESTINATION_RING_END_REASON_MSB 17
|
||||
#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000
|
||||
|
||||
|
||||
/* Description INITIATOR
|
||||
|
||||
1: This descriptor belongs to a TX FES (TXOP initiator)
|
||||
0: This descriptor belongs to a response TX (TXOP responder)
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_INITIATOR_LSB 18
|
||||
#define MON_DESTINATION_RING_INITIATOR_MSB 18
|
||||
#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000
|
||||
|
||||
|
||||
/* Description EMPTY_DESCRIPTOR
|
||||
|
||||
0: This descriptor is written on a flush or the end of a
|
||||
PPDU or the end of status buffer
|
||||
1: This descriptor is written to indicate drop information
|
||||
(see 'MON_DESTINATION_RING_WITH_DROP' structure)
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000
|
||||
|
||||
|
||||
/* Description RING_ID
|
||||
|
||||
Consumer: SW/REO/DEBUG
|
||||
Producer: SRNG (of TXMON/RXMON)
|
||||
|
||||
For debugging.
|
||||
This field is filled in by the SRNG module.
|
||||
It help to identify the ring that is being looked
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_RING_ID_LSB 20
|
||||
#define MON_DESTINATION_RING_RING_ID_MSB 27
|
||||
#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
Consumer: SW/DEBUG
|
||||
Producer: SRNG (of TXMON/RXMON)
|
||||
|
||||
For debugging.
|
||||
This field is filled in by the SRNG module.
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into this Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
#endif // MON_DESTINATION_RING
|
||||
250
hw/qcn6432/mon_destination_ring_with_drop.h
Archivo normal
250
hw/qcn6432/mon_destination_ring_with_drop.h
Archivo normal
@@ -0,0 +1,250 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MON_DESTINATION_RING_WITH_DROP_H_
|
||||
#define _MON_DESTINATION_RING_WITH_DROP_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MON_DESTINATION_RING_WITH_DROP 4
|
||||
|
||||
|
||||
struct mon_destination_ring_with_drop {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ppdu_drop_cnt : 10, // [9:0]
|
||||
mpdu_drop_cnt : 10, // [19:10]
|
||||
tlv_drop_cnt : 10, // [29:20]
|
||||
end_of_ppdu_seen : 1, // [30:30]
|
||||
reserved_0a : 1; // [31:31]
|
||||
uint32_t reserved_1a : 32; // [31:0]
|
||||
uint32_t ppdu_id : 32; // [31:0]
|
||||
uint32_t reserved_3a : 18, // [17:0]
|
||||
initiator : 1, // [18:18]
|
||||
empty_descriptor : 1, // [19:19]
|
||||
ring_id : 8, // [27:20]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
uint32_t reserved_0a : 1, // [31:31]
|
||||
end_of_ppdu_seen : 1, // [30:30]
|
||||
tlv_drop_cnt : 10, // [29:20]
|
||||
mpdu_drop_cnt : 10, // [19:10]
|
||||
ppdu_drop_cnt : 10; // [9:0]
|
||||
uint32_t reserved_1a : 32; // [31:0]
|
||||
uint32_t ppdu_id : 32; // [31:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
ring_id : 8, // [27:20]
|
||||
empty_descriptor : 1, // [19:19]
|
||||
initiator : 1, // [18:18]
|
||||
reserved_3a : 18; // [17:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PPDU_DROP_CNT
|
||||
|
||||
The number of PPDUs dropped due to the back-pressure
|
||||
|
||||
Set to 1023 if >1023 PPDUs got dropped
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_LSB 0
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_MSB 9
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_MASK 0x000003ff
|
||||
|
||||
|
||||
/* Description MPDU_DROP_CNT
|
||||
|
||||
The number of MPDUs dropped within the first PPDU due to
|
||||
the back-pressure
|
||||
|
||||
Set to 1023 if >1023 MPDUs got dropped
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_LSB 10
|
||||
#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_MSB 19
|
||||
#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_MASK 0x000ffc00
|
||||
|
||||
|
||||
/* Description TLV_DROP_CNT
|
||||
|
||||
The number of PPDU-level (global or per-user) TLVs dropped
|
||||
within the first PPDU due to the back-pressure
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_LSB 20
|
||||
#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_MSB 29
|
||||
#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_MASK 0x3ff00000
|
||||
|
||||
|
||||
/* Description END_OF_PPDU_SEEN
|
||||
|
||||
Field valid only if mpdu_drop_cnt > 0 or tlv_drop_cnt >
|
||||
0
|
||||
|
||||
Set by TXMON if 'TX_FES_STATUS_END' is received for a partially
|
||||
dropped PPDU when Initiator = 1.
|
||||
Set by TXMON if 'RESPONSE_END_STATUS' is received for a
|
||||
partially dropped PPDU when Initiator = 0.
|
||||
Set by RXMON if 'RX_PPDU_END_STATUS_DONE' is received for
|
||||
a partially dropped PPDU.
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_LSB 30
|
||||
#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_MSB 30
|
||||
#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_MASK 0x40000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_LSB 31
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_MSB 31
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_MASK 0x80000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_OFFSET 0x00000004
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_LSB 0
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_MSB 31
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description PPDU_ID
|
||||
|
||||
The ID of the last PPDU which saw the back-pressure on AXI
|
||||
|
||||
|
||||
TXMON fills this with the schedule_id from 'TX_FES_SETUP'
|
||||
when Initiator = 1.
|
||||
TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO'
|
||||
when Initiator = 0.
|
||||
RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.'
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_OFFSET 0x00000008
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_LSB 0
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_MSB 31
|
||||
#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_LSB 0
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_MSB 17
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_MASK 0x0003ffff
|
||||
|
||||
|
||||
/* Description INITIATOR
|
||||
|
||||
1: This descriptor belongs to a TX FES (TXOP initiator)
|
||||
0: This descriptor belongs to a response TX (TXOP responder)
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_LSB 18
|
||||
#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_MSB 18
|
||||
#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_MASK 0x00040000
|
||||
|
||||
|
||||
/* Description EMPTY_DESCRIPTOR
|
||||
|
||||
0: This descriptor is written on a flush or the end of a
|
||||
PPDU or the end of status buffer (see 'MON_DESTINATION_RING'
|
||||
structure)
|
||||
1: This descriptor is written to indicate drop information
|
||||
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_LSB 19
|
||||
#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_MSB 19
|
||||
#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_MASK 0x00080000
|
||||
|
||||
|
||||
/* Description RING_ID
|
||||
|
||||
Consumer: SW/REO/DEBUG
|
||||
Producer: SRNG (of TXMON/RXMON)
|
||||
|
||||
For debugging.
|
||||
This field is filled in by the SRNG module.
|
||||
It help to identify the ring that is being looked
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RING_ID_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RING_ID_LSB 20
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RING_ID_MSB 27
|
||||
#define MON_DESTINATION_RING_WITH_DROP_RING_ID_MASK 0x0ff00000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
Consumer: SW/DEBUG
|
||||
Producer: SRNG (of TXMON/RXMON)
|
||||
|
||||
For debugging.
|
||||
This field is filled in by the SRNG module.
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into this Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_LSB 28
|
||||
#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_MSB 31
|
||||
#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
#endif // MON_DESTINATION_RING_WITH_DROP
|
||||
137
hw/qcn6432/mon_drop.h
Archivo normal
137
hw/qcn6432/mon_drop.h
Archivo normal
@@ -0,0 +1,137 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MON_DROP_H_
|
||||
#define _MON_DROP_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MON_DROP 2
|
||||
|
||||
#define NUM_OF_QWORDS_MON_DROP 1
|
||||
|
||||
|
||||
struct mon_drop {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ppdu_id : 32; // [31:0]
|
||||
uint32_t ppdu_drop_cnt : 10, // [9:0]
|
||||
mpdu_drop_cnt : 10, // [19:10]
|
||||
tlv_drop_cnt : 10, // [29:20]
|
||||
end_of_ppdu_seen : 1, // [30:30]
|
||||
reserved_1a : 1; // [31:31]
|
||||
#else
|
||||
uint32_t ppdu_id : 32; // [31:0]
|
||||
uint32_t reserved_1a : 1, // [31:31]
|
||||
end_of_ppdu_seen : 1, // [30:30]
|
||||
tlv_drop_cnt : 10, // [29:20]
|
||||
mpdu_drop_cnt : 10, // [19:10]
|
||||
ppdu_drop_cnt : 10; // [9:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PPDU_ID
|
||||
|
||||
The ID of the last PPDU which saw the back-pressure on AXI
|
||||
|
||||
|
||||
TXMON fills this with the schedule_id from 'TX_FES_SETUP'
|
||||
in case of a TX FES (TXOP initiator).
|
||||
TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO'
|
||||
in case of a response TX (TXOP responder).
|
||||
RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.'
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_PPDU_ID_LSB 0
|
||||
#define MON_DROP_PPDU_ID_MSB 31
|
||||
#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description PPDU_DROP_CNT
|
||||
|
||||
The number of PPDUs dropped due to the back-pressure
|
||||
|
||||
Set to 1023 if >1023 PPDUs got dropped
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_PPDU_DROP_CNT_LSB 32
|
||||
#define MON_DROP_PPDU_DROP_CNT_MSB 41
|
||||
#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000
|
||||
|
||||
|
||||
/* Description MPDU_DROP_CNT
|
||||
|
||||
The number of MPDUs dropped within the first PPDU due to
|
||||
the back-pressure
|
||||
|
||||
Set to 1023 if >1023 MPDUs got dropped
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_MPDU_DROP_CNT_LSB 42
|
||||
#define MON_DROP_MPDU_DROP_CNT_MSB 51
|
||||
#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000
|
||||
|
||||
|
||||
/* Description TLV_DROP_CNT
|
||||
|
||||
The number of PPDU-level (global or per-user) TLVs dropped
|
||||
within the first PPDU due to the back-pressure
|
||||
*/
|
||||
|
||||
#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_TLV_DROP_CNT_LSB 52
|
||||
#define MON_DROP_TLV_DROP_CNT_MSB 61
|
||||
#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000
|
||||
|
||||
|
||||
/* Description END_OF_PPDU_SEEN
|
||||
|
||||
Field valid only if mpdu_drop_cnt > 0 or tlv_drop_cnt >
|
||||
0
|
||||
|
||||
Set by TXMON if 'TX_FES_STATUS_END' is received but dropped
|
||||
in case of a TX FES (TXOP initiator).
|
||||
Set by TXMON if 'RESPONSE_END_STATUS' is received but dropped
|
||||
in case of a response TX (TXOP responder).
|
||||
Set by RXMON if 'RX_PPDU_END' is received but dropped
|
||||
*/
|
||||
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_LSB 62
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_MSB 62
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_RESERVED_1A_LSB 63
|
||||
#define MON_DROP_RESERVED_1A_MSB 63
|
||||
#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // MON_DROP
|
||||
212
hw/qcn6432/mon_ingress_ring.h
Archivo normal
212
hw/qcn6432/mon_ingress_ring.h
Archivo normal
@@ -0,0 +1,212 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _MON_INGRESS_RING_H_
|
||||
#define _MON_INGRESS_RING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "buffer_addr_info.h"
|
||||
#define NUM_OF_DWORDS_MON_INGRESS_RING 4
|
||||
|
||||
|
||||
struct mon_ingress_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct buffer_addr_info buffer_addr_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t buffer_virt_addr_63_32 : 32; // [31:0]
|
||||
#else
|
||||
struct buffer_addr_info buffer_addr_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t buffer_virt_addr_63_32 : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_INFO_DETAILS
|
||||
|
||||
Consumer: TXMON/RXMON
|
||||
Producer: SW
|
||||
|
||||
Details of the physical address of the buffer
|
||||
|
||||
'Sw_buffer_cookie' and 'Return_buffer_manager' sub-fields
|
||||
are reserved and unused by TXMON/RXMON.
|
||||
*/
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_31_0
|
||||
|
||||
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_39_32
|
||||
|
||||
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RETURN_BUFFER_MANAGER
|
||||
|
||||
Consumer: WBM
|
||||
Producer: SW/FW
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
||||
descriptor OR link descriptor that is being pointed to
|
||||
shall be returned after the frame has been processed. It
|
||||
is used by WBM for routing purposes.
|
||||
|
||||
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
||||
to the WMB buffer idle list
|
||||
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the WBM idle link descriptor idle list, where the chip
|
||||
0 WBM is chosen in case of a multi-chip config
|
||||
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 1 WBM idle link descriptor idle list
|
||||
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 2 WBM idle link descriptor idle list
|
||||
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
||||
returned to chip 3 WBM idle link descriptor idle list
|
||||
<enum 4 FW_BM> This buffer shall be returned to the FW
|
||||
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
||||
ring 0
|
||||
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
||||
ring 1
|
||||
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
||||
ring 2
|
||||
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
||||
ring 3
|
||||
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
||||
ring 4
|
||||
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
||||
ring 5
|
||||
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
||||
ring 6
|
||||
|
||||
<legal 0-12>
|
||||
*/
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
||||
|
||||
|
||||
/* Description SW_BUFFER_COOKIE
|
||||
|
||||
Cookie field exclusively used by SW.
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
HW ignores the contents, accept that it passes the programmed
|
||||
value on to other descriptors together with the physical
|
||||
address
|
||||
|
||||
Field can be used by SW to for example associate the buffers
|
||||
physical address with the virtual address
|
||||
The bit definitions as used by SW are within SW HLD specification
|
||||
|
||||
|
||||
NOTE1:
|
||||
The three most significant bits can have a special meaning
|
||||
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
||||
and field transmit_bw_restriction is set
|
||||
|
||||
In case of NON punctured transmission:
|
||||
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
In case of punctured transmission:
|
||||
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
Note: a punctured transmission is indicated by the presence
|
||||
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
|
||||
|
||||
|
||||
/* Description BUFFER_VIRT_ADDR_31_0
|
||||
|
||||
Lower 32 bits of the 64-bit virtual address corresponding
|
||||
to Buffer_addr_info_details
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description BUFFER_VIRT_ADDR_63_32
|
||||
|
||||
Upper 32 bits of the 64-bit virtual address corresponding
|
||||
to Buffer_addr_info_details
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
|
||||
|
||||
#endif // MON_INGRESS_RING
|
||||
308
hw/qcn6432/no_ack_report.h
Archivo normal
308
hw/qcn6432/no_ack_report.h
Archivo normal
@@ -0,0 +1,308 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NO_ACK_REPORT_H_
|
||||
#define _NO_ACK_REPORT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_NO_ACK_REPORT 4
|
||||
|
||||
|
||||
struct no_ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t no_ack_transmit_reason : 4, // [3:0]
|
||||
macrx_abort_reason : 4, // [7:4]
|
||||
phyrx_abort_reason : 8, // [15:8]
|
||||
frame_control : 16; // [31:16]
|
||||
uint32_t rx_ppdu_duration : 24, // [23:0]
|
||||
sr_ppdu_during_obss : 1, // [24:24]
|
||||
selfgen_response_reason_to_sr_ppdu : 4, // [28:25]
|
||||
reserved_1 : 3; // [31:29]
|
||||
uint32_t pre_bt_broadcast_status_details : 12, // [11:0]
|
||||
first_bt_broadcast_status_details : 12, // [23:12]
|
||||
reserved_2 : 8; // [31:24]
|
||||
uint32_t second_bt_broadcast_status_details : 12, // [11:0]
|
||||
reserved_3 : 20; // [31:12]
|
||||
#else
|
||||
uint32_t frame_control : 16, // [31:16]
|
||||
phyrx_abort_reason : 8, // [15:8]
|
||||
macrx_abort_reason : 4, // [7:4]
|
||||
no_ack_transmit_reason : 4; // [3:0]
|
||||
uint32_t reserved_1 : 3, // [31:29]
|
||||
selfgen_response_reason_to_sr_ppdu : 4, // [28:25]
|
||||
sr_ppdu_during_obss : 1, // [24:24]
|
||||
rx_ppdu_duration : 24; // [23:0]
|
||||
uint32_t reserved_2 : 8, // [31:24]
|
||||
first_bt_broadcast_status_details : 12, // [23:12]
|
||||
pre_bt_broadcast_status_details : 12; // [11:0]
|
||||
uint32_t reserved_3 : 20, // [31:12]
|
||||
second_bt_broadcast_status_details : 12; // [11:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description NO_ACK_TRANSMIT_REASON
|
||||
|
||||
Field that indicates why the received frame is not needing
|
||||
any transmit response in SIFS time.
|
||||
|
||||
The possible responses are listed in order.
|
||||
|
||||
<enum 0 NO_ACK_FCS_errors > All received frames have
|
||||
FCS errors.
|
||||
<enum 1 Unicast_no_ack_frame_received > All received
|
||||
frames did not require a response.
|
||||
<enum 2 NO_ACK_Broadcast> Broadcast frame received
|
||||
<enum 3 NO_ACK_Multicast> Multicast frame received
|
||||
<enum 4 Not_directed> Frames received are not directed
|
||||
to this device (based on addr1)
|
||||
<enum 5 AST_no_ack> The AST entry indicated that NO
|
||||
ACK shall be send
|
||||
<enum 6 PHY_GID_mismatch> PHY dropped the incoming frame
|
||||
dur to GID mismatch
|
||||
<enum 7 PHY_AID_mismatch> PHY dropped the incoming frame
|
||||
dur to AID mismatch
|
||||
<enum 8 NO_ACK_PHY_error> PHY reported an error during
|
||||
reception. For details, see the 'phy_error...' fields
|
||||
<enum 9 RTS_bw_not_available> The requested BW for the
|
||||
CTS response frame is not available
|
||||
<enum 10 NDPA_Frame> An NDPA frame got received
|
||||
<enum 11 NDP_Frame> An NDP frame got received
|
||||
<enum 12 Trigger_NAV_blocked> a trigger frame was received,
|
||||
but due to NAV setting, no response could be generated
|
||||
<enum 13 Trigger_no_AID> A trigger frame was received,
|
||||
but this device's AID was not in the list
|
||||
<enum 14 NO_ACK_MAC_ABORT_REQ > No ACK is needed as
|
||||
SW asked RXPCU to send a abort_request to the PHYRX
|
||||
<enum 15 no_response_other> placeholder in case non
|
||||
of the above properly cover the reasons
|
||||
|
||||
Also see the field SR_PPDU_during_OBSS.
|
||||
<legal 0-15>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f
|
||||
|
||||
|
||||
/* Description MACRX_ABORT_REASON
|
||||
|
||||
Field only valid when No_ack_transmit_reason is set to NO_ACK_MAC_ABORT_REQ
|
||||
|
||||
|
||||
Error field received from MACRX_ABORT_REQUEST.Macrx_abort_reason[2:0]
|
||||
|
||||
<Legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0
|
||||
|
||||
|
||||
/* Description PHYRX_ABORT_REASON
|
||||
|
||||
Field only valid when No_ack_transmit_reason is set to NO_ACK_PHY_error
|
||||
|
||||
|
||||
Error field received from PHYRX_ABORT_REQUEST.Phyrx_abort_reason
|
||||
|
||||
|
||||
<Legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description FRAME_CONTROL
|
||||
|
||||
frame control field of the received (first properly received)
|
||||
frame
|
||||
|
||||
<Legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
|
||||
|
||||
|
||||
/* Description RX_PPDU_DURATION
|
||||
|
||||
The length of this PPDU reception in us
|
||||
<Legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff
|
||||
|
||||
|
||||
/* Description SR_PPDU_DURING_OBSS
|
||||
|
||||
Field only valid with SRP Responder support
|
||||
|
||||
Indicates that the received frame was sent using SRP as
|
||||
indicated by the 'SR PPDU' bit in the 'CAS Control' in the
|
||||
'HE A-Control' in one of the MPDUs received, and that the
|
||||
response could not be generated due to OBSS traffic setting
|
||||
the NAV
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000
|
||||
|
||||
|
||||
/* Description SELFGEN_RESPONSE_REASON_TO_SR_PPDU
|
||||
|
||||
Field only valid with SRP Responder support
|
||||
|
||||
This field indicates why the received SR PPDU needs a response
|
||||
in SIFS time. The e-num used is the same as in the field
|
||||
selfgen_response_reason in 'ACK_REPORT' structure although
|
||||
some of these will be unused in case of an SR PPDU.
|
||||
|
||||
<enum 0 CTS_frame>
|
||||
<enum 1 ACK_frame>
|
||||
<enum 2 BA_frame >
|
||||
<enum 3 Qboost_trigger> Qboost trigger received
|
||||
<enum 4 PSPOLL_trigger> PSPOLL trigger received
|
||||
<enum 5 UAPSD_trigger > Unscheduled APSD trigger received
|
||||
|
||||
<enum 6 CBF_frame> the CBF frame needs to be send as
|
||||
a result of NDP or BRPOLL
|
||||
<enum 7 ax_su_trigger> 11ax trigger received for this
|
||||
device
|
||||
<enum 8 ax_wildcard_trigger> 11ax wildcardtrigger has
|
||||
been received
|
||||
<enum 9 ax_unassoc_wildcard_trigger> 11ax wildcard trigger
|
||||
for unassociated STAs has been received
|
||||
<enum 12 eht_su_trigger> EHT R1 trigger received for
|
||||
this device
|
||||
<enum 10 MU_UL_response_to_response>
|
||||
|
||||
<enum 11 Ranging_NDP_LMR_frames> Ranging NDP + LMR need
|
||||
to be sent in response to ranging NDPA + NDP
|
||||
|
||||
<legal 0-12>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RESERVED_1_LSB 29
|
||||
#define NO_ACK_REPORT_RESERVED_1_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
|
||||
/* Description PRE_BT_BROADCAST_STATUS_DETAILS
|
||||
|
||||
Same contents as field "bt_broadcast_status_details" for
|
||||
the first received COEX_STATUS_BROADCAST tlv during this
|
||||
PPDU reception.
|
||||
After power up, this field is all initialized to 0
|
||||
|
||||
Bits: [31:28]: always 0
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
|
||||
/* Description FIRST_BT_BROADCAST_STATUS_DETAILS
|
||||
|
||||
Same contents as field "bt_broadcast_status_details" for
|
||||
the first received COEX_STATUS_BROADCAST tlv during this
|
||||
PPDU reception.
|
||||
|
||||
If no COEX_STATUS_BROADCAST tlv is received during this
|
||||
PPDU reception, this field will be set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
|
||||
|
||||
|
||||
/* Description RESERVED_2
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_RESERVED_2_LSB 24
|
||||
#define NO_ACK_REPORT_RESERVED_2_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description SECOND_BT_BROADCAST_STATUS_DETAILS
|
||||
|
||||
Same contents as field "bt_broadcast_status_details" for
|
||||
the second received COEX_STATUS_BROADCAST tlv during this
|
||||
PPDU reception.
|
||||
|
||||
If no second COEX_STATUS_BROADCAST tlv is received during
|
||||
this PPDU reception, this field will be set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
|
||||
/* Description RESERVED_3
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_RESERVED_3_LSB 12
|
||||
#define NO_ACK_REPORT_RESERVED_3_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000
|
||||
|
||||
|
||||
|
||||
#endif // NO_ACK_REPORT
|
||||
2619
hw/qcn6432/ofdma_trigger_details.h
Archivo normal
2619
hw/qcn6432/ofdma_trigger_details.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
7454
hw/qcn6432/pcu_ppdu_setup_init.h
Archivo normal
7454
hw/qcn6432/pcu_ppdu_setup_init.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
1399
hw/qcn6432/pdg_response.h
Archivo normal
1399
hw/qcn6432/pdg_response.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
1033
hw/qcn6432/pdg_response_rate_setting.h
Archivo normal
1033
hw/qcn6432/pdg_response_rate_setting.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
204
hw/qcn6432/pdg_tx_req.h
Archivo normal
204
hw/qcn6432/pdg_tx_req.h
Archivo normal
@@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PDG_TX_REQ_H_
|
||||
#define _PDG_TX_REQ_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_PDG_TX_REQ 2
|
||||
|
||||
#define NUM_OF_QWORDS_PDG_TX_REQ 1
|
||||
|
||||
|
||||
struct pdg_tx_req {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_reason : 2, // [1:0]
|
||||
use_puncture_pattern : 2, // [3:2]
|
||||
req_bw : 3, // [6:4]
|
||||
puncture_pattern_number : 6, // [12:7]
|
||||
reserved_0b : 1, // [13:13]
|
||||
req_paprd : 1, // [14:14]
|
||||
duration_field_boundary_valid : 1, // [15:15]
|
||||
duration_field_boundary : 16; // [31:16]
|
||||
uint32_t puncture_subband_mask : 16, // [15:0]
|
||||
reserved_0c : 16; // [31:16]
|
||||
#else
|
||||
uint32_t duration_field_boundary : 16, // [31:16]
|
||||
duration_field_boundary_valid : 1, // [15:15]
|
||||
req_paprd : 1, // [14:14]
|
||||
reserved_0b : 1, // [13:13]
|
||||
puncture_pattern_number : 6, // [12:7]
|
||||
req_bw : 3, // [6:4]
|
||||
use_puncture_pattern : 2, // [3:2]
|
||||
tx_reason : 2; // [1:0]
|
||||
uint32_t reserved_0c : 16, // [31:16]
|
||||
puncture_subband_mask : 16; // [15:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description TX_REASON
|
||||
|
||||
<enum 0 tx_fes_protection_frame> RTS, CTS2Self or 11h
|
||||
protection type transmission preceding the regular PPDU
|
||||
portion of the coming FES.
|
||||
<enum 1 tx_fes_after_protection > Regular PPDU transmission
|
||||
that follows the transmission of medium protection frames:.
|
||||
|
||||
<enum 2 tx_fes_only> Regular PPDU transmission without
|
||||
preceding medium protection frame exchanges.
|
||||
|
||||
Note: Response frame transmissions are initiated with the
|
||||
PDG_RESPONSE TLV
|
||||
|
||||
<legal 0-2>
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_TX_REASON_LSB 0
|
||||
#define PDG_TX_REQ_TX_REASON_MSB 1
|
||||
#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003
|
||||
|
||||
|
||||
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c
|
||||
|
||||
|
||||
/* Description REQ_BW
|
||||
|
||||
Field not valid when use_puncture_pattern is set to PUNCTURE_FROM_TX_SETUP
|
||||
|
||||
|
||||
The BW of the upcoming transmission.
|
||||
Note: Coex might have changed this from the original request.
|
||||
|
||||
|
||||
<enum 0 20_mhz>20 Mhz BW
|
||||
<enum 1 40_mhz>40 Mhz BW
|
||||
<enum 2 80_mhz>80 Mhz BW
|
||||
<enum 3 160_mhz>160 Mhz BW
|
||||
<enum 4 320_mhz>320 Mhz BW
|
||||
<enum 5 240_mhz>240 Mhz BW
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_REQ_BW_LSB 4
|
||||
#define PDG_TX_REQ_REQ_BW_MSB 6
|
||||
#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070
|
||||
|
||||
|
||||
/* Description PUNCTURE_PATTERN_NUMBER
|
||||
|
||||
Field only valid when "use_puncture_pattern" is set.
|
||||
|
||||
The pattern number in case punctured transmission is enabled
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_RESERVED_0B_LSB 13
|
||||
#define PDG_TX_REQ_RESERVED_0B_MSB 13
|
||||
#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000
|
||||
|
||||
|
||||
#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_REQ_PAPRD_LSB 14
|
||||
#define PDG_TX_REQ_REQ_PAPRD_MSB 14
|
||||
#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description DURATION_FIELD_BOUNDARY_VALID
|
||||
|
||||
When set, PDG should take the 'duration_field_boundary'
|
||||
value into account when it is calculating the TX and RX
|
||||
boundaries for the upcoming transmission. Both RX and TX
|
||||
should not go beyond this time duration provided.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000
|
||||
|
||||
|
||||
/* Description DURATION_FIELD_BOUNDARY
|
||||
|
||||
Field only valid when 'Duration_field_boundary_valid' is
|
||||
set
|
||||
|
||||
Amount of time to both TX and RX boundaries that PDG should
|
||||
take into account for the upcoming transmission.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description PUNCTURE_SUBBAND_MASK
|
||||
|
||||
Field only valid when use_puncture_pattern is set to PUNCTURE_FROM_ALL_ALLOWED_MODES
|
||||
|
||||
|
||||
This mask indicates which 20 Mhz channels are actively used
|
||||
in this transmission.
|
||||
|
||||
Bit 0: primary 20 Mhz
|
||||
Bit 1: secondary 20 MHz
|
||||
Etc.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_0C
|
||||
|
||||
Reserved for future power bits: Generator should set to
|
||||
0, consumer shall ignore <legal 0>
|
||||
*/
|
||||
|
||||
#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_RESERVED_0C_LSB 48
|
||||
#define PDG_TX_REQ_RESERVED_0C_MSB 63
|
||||
#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PDG_TX_REQ
|
||||
214
hw/qcn6432/phyrx_abort_request_info.h
Archivo normal
214
hw/qcn6432/phyrx_abort_request_info.h
Archivo normal
@@ -0,0 +1,214 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
|
||||
#define _PHYRX_ABORT_REQUEST_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
|
||||
|
||||
|
||||
struct phyrx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t phyrx_abort_reason : 8, // [7:0]
|
||||
phy_enters_nap_state : 1, // [8:8]
|
||||
phy_enters_defer_state : 1, // [9:9]
|
||||
reserved_0 : 6, // [15:10]
|
||||
receive_duration : 16; // [31:16]
|
||||
#else
|
||||
uint32_t receive_duration : 16, // [31:16]
|
||||
reserved_0 : 6, // [15:10]
|
||||
phy_enters_defer_state : 1, // [9:9]
|
||||
phy_enters_nap_state : 1, // [8:8]
|
||||
phyrx_abort_reason : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_ABORT_REASON
|
||||
|
||||
<enum 0 phyrx_err_phy_off> Reception aborted due to receiving
|
||||
a PHY_OFF TLV
|
||||
<enum 1 phyrx_err_synth_off>
|
||||
<enum 2 phyrx_err_ofdma_timing>
|
||||
<enum 3 phyrx_err_ofdma_signal_parity>
|
||||
<enum 4 phyrx_err_ofdma_rate_illegal>
|
||||
<enum 5 phyrx_err_ofdma_length_illegal>
|
||||
<enum 6 phyrx_err_ofdma_restart>
|
||||
<enum 7 phyrx_err_ofdma_service>
|
||||
<enum 8 phyrx_err_ppdu_ofdma_power_drop>
|
||||
|
||||
<enum 9 phyrx_err_cck_blokker>
|
||||
<enum 10 phyrx_err_cck_timing>
|
||||
<enum 11 phyrx_err_cck_header_crc>
|
||||
<enum 12 phyrx_err_cck_rate_illegal>
|
||||
<enum 13 phyrx_err_cck_length_illegal>
|
||||
<enum 14 phyrx_err_cck_restart>
|
||||
<enum 15 phyrx_err_cck_service>
|
||||
<enum 16 phyrx_err_cck_power_drop>
|
||||
|
||||
<enum 17 phyrx_err_ht_crc_err>
|
||||
<enum 18 phyrx_err_ht_length_illegal>
|
||||
<enum 19 phyrx_err_ht_rate_illegal>
|
||||
<enum 20 phyrx_err_ht_zlf>
|
||||
<enum 21 phyrx_err_false_radar_ext>
|
||||
<enum 22 phyrx_err_green_field>
|
||||
<enum 60 phyrx_err_ht_nsym_lt_zero>
|
||||
|
||||
<enum 23 phyrx_err_bw_gt_dyn_bw>
|
||||
<enum 24 phyrx_err_leg_ht_mismatch>
|
||||
<enum 25 phyrx_err_vht_crc_error>
|
||||
<enum 26 phyrx_err_vht_siga_unsupported>
|
||||
<enum 27 phyrx_err_vht_lsig_len_invalid>
|
||||
<enum 28 phyrx_err_vht_ndp_or_zlf>
|
||||
<enum 29 phyrx_err_vht_nsym_lt_zero>
|
||||
<enum 30 phyrx_err_vht_rx_extra_symbol_mismatch>
|
||||
<enum 31 phyrx_err_vht_rx_skip_group_id0>
|
||||
<enum 32 phyrx_err_vht_rx_skip_group_id1to62>
|
||||
<enum 33 phyrx_err_vht_rx_skip_group_id63>
|
||||
<enum 34 phyrx_err_ofdm_ldpc_decoder_disabled>
|
||||
<enum 35 phyrx_err_defer_nap>
|
||||
|
||||
<enum 61 phyrx_err_vht_lsig_rate_mismatch>
|
||||
<enum 62 phyrx_err_vht_paid_gid_mismatch>
|
||||
<enum 63 phyrx_err_vht_unsupported_bw>
|
||||
<enum 64 phyrx_err_vht_gi_disam_mismatch>
|
||||
|
||||
<enum 36 phyrx_err_fdomain_timeout>
|
||||
<enum 37 phyrx_err_lsig_rel_check>
|
||||
<enum 38 phyrx_err_bt_collision>
|
||||
<enum 39 phyrx_err_unsupported_mu_feedback>
|
||||
<enum 40 phyrx_err_ppdu_tx_interrupt_rx>
|
||||
<enum 41 phyrx_err_unsupported_cbf>
|
||||
|
||||
<enum 42 phyrx_err_other> Should not really be used. If
|
||||
needed, ask for documentation update
|
||||
|
||||
<enum 43 phyrx_err_he_siga_unsupported > <enum 44 phyrx_err_he_crc_error
|
||||
> <enum 45 phyrx_err_he_sigb_unsupported > <enum 46 phyrx_err_he_mu_mode_unsupported
|
||||
> <enum 47 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero
|
||||
> <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50
|
||||
phyrx_err_he_num_users_unsupported ><enum 51 phyrx_err_he_sounding_params_unsupported
|
||||
>
|
||||
<enum 54 phyrx_err_he_sigb_crc_error>
|
||||
<enum 55 phyrx_err_he_ext_su_unsupported>
|
||||
<enum 56 phyrx_err_he_trig_unsupported>
|
||||
<enum 57 phyrx_err_he_lsig_len_invalid>
|
||||
<enum 58 phyrx_err_he_lsig_rate_mismatch>
|
||||
<enum 59 phyrx_err_ofdma_signal_reliability>
|
||||
|
||||
<enum 77 phyrx_err_wur_detection>
|
||||
|
||||
<enum 72 phyrx_err_u_sig_crc_error>
|
||||
<enum 73 phyrx_err_u_sig_unsupported_mode>
|
||||
<enum 74 phyrx_err_u_sig_rsvd_err>
|
||||
<enum 75 phyrx_err_u_sig_mcs_error>
|
||||
<enum 76 phyrx_err_u_sig_bw_error>
|
||||
<enum 79 phyrx_err_u_sig_320_channel_mismatch>
|
||||
<enum 71 phyrx_err_eht_sig_crc_error>
|
||||
<enum 78 phyrx_err_eht_sig_unsupported_mode>
|
||||
|
||||
<enum 80 phyrx_err_ehtplus_er_detection>
|
||||
|
||||
<enum 52 phyrx_err_MU_UL_no_power_detected>
|
||||
<enum 53 phyrx_err_MU_UL_not_for_me>
|
||||
|
||||
<enum 65 phyrx_err_rx_wdg_timeout>
|
||||
<enum 66 phyrx_err_sizing_evt_unexpected>
|
||||
<enum 67 phyrx_err_spectralscan>
|
||||
<enum 68 phyrx_err_radar_misdetected_as_ofdm>
|
||||
<enum 69 phyrx_err_rx_stuck>
|
||||
<enum 70 phyrx_err_invalid_11b_state>
|
||||
|
||||
<legal 0 - 80>
|
||||
*/
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description PHY_ENTERS_NAP_STATE
|
||||
|
||||
When set, PHY enters PHY NAP state after sending this abort
|
||||
|
||||
|
||||
Note that nap and defer state are mutually exclusive.
|
||||
|
||||
Field put pro-actively in place....usage still to be agreed
|
||||
upon.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100
|
||||
|
||||
|
||||
/* Description PHY_ENTERS_DEFER_STATE
|
||||
|
||||
When set, PHY enters PHY defer state after sending this
|
||||
abort
|
||||
|
||||
Note that nap and defer state are mutually exclusive.
|
||||
|
||||
Field put pro-actively in place....usage still to be agreed
|
||||
upon.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9
|
||||
#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00
|
||||
|
||||
|
||||
/* Description RECEIVE_DURATION
|
||||
|
||||
The remaining receive duration of this PPDU in the medium
|
||||
(in us). When PHY does not know this duration when this
|
||||
TLV is generated, the field will be set to 0.
|
||||
The timing reference point is the reception by the MAC of
|
||||
this TLV. The value shall be accurate to within 2us.
|
||||
|
||||
In case Phy_enters_nap_state and/or Phy_enters_defer_state
|
||||
is set, there is a possibility that MAC PMM can also decide
|
||||
to go into a low(er) power state.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31
|
||||
#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_ABORT_REQUEST_INFO
|
||||
403
hw/qcn6432/phyrx_common_user_info.h
Archivo normal
403
hw/qcn6432/phyrx_common_user_info.h
Archivo normal
@@ -0,0 +1,403 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_COMMON_USER_INFO_H_
|
||||
#define _PHYRX_COMMON_USER_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2
|
||||
|
||||
|
||||
struct phyrx_common_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t receive_duration : 16, // [15:0]
|
||||
reserved_0a : 16; // [31:16]
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6, // [5:0]
|
||||
reserved_1a : 26; // [31:6]
|
||||
uint32_t eht_ppdu_type : 2, // [1:0]
|
||||
bss_color_id : 6, // [7:2]
|
||||
dl_ul_flag : 1, // [8:8]
|
||||
txop_duration : 7, // [15:9]
|
||||
cp_setting : 2, // [17:16]
|
||||
ltf_size : 2, // [19:18]
|
||||
spatial_reuse : 4, // [23:20]
|
||||
rx_ndp : 1, // [24:24]
|
||||
dot11be_su_extended : 1, // [25:25]
|
||||
reserved_2a : 6; // [31:26]
|
||||
uint32_t eht_duplicate : 2, // [1:0]
|
||||
eht_sig_cmn_field_type : 2, // [3:2]
|
||||
doppler_indication : 1, // [4:4]
|
||||
sta_id : 11, // [15:5]
|
||||
puncture_bitmap : 16; // [31:16]
|
||||
#else
|
||||
uint32_t reserved_0a : 16, // [31:16]
|
||||
receive_duration : 16; // [15:0]
|
||||
uint32_t reserved_1a : 26, // [31:6]
|
||||
u_sig_puncture_pattern_encoding : 6; // [5:0]
|
||||
uint32_t reserved_2a : 6, // [31:26]
|
||||
dot11be_su_extended : 1, // [25:25]
|
||||
rx_ndp : 1, // [24:24]
|
||||
spatial_reuse : 4, // [23:20]
|
||||
ltf_size : 2, // [19:18]
|
||||
cp_setting : 2, // [17:16]
|
||||
txop_duration : 7, // [15:9]
|
||||
dl_ul_flag : 1, // [8:8]
|
||||
bss_color_id : 6, // [7:2]
|
||||
eht_ppdu_type : 2; // [1:0]
|
||||
uint32_t puncture_bitmap : 16, // [31:16]
|
||||
sta_id : 11, // [15:5]
|
||||
doppler_indication : 1, // [4:4]
|
||||
eht_sig_cmn_field_type : 2, // [3:2]
|
||||
eht_duplicate : 2; // [1:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RECEIVE_DURATION
|
||||
|
||||
The remaining receive duration of this PPDU in the medium
|
||||
(in us).
|
||||
The timing reference point is the assertion of 'rx_frame'
|
||||
by PHY for the PPDU reception. The value shall be accurate
|
||||
to within 2us.
|
||||
RXPCU shall subtract the time elapsed between 'rx_frame'
|
||||
assertion and reception of this TLV to find the actual remaining
|
||||
receive duration.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15
|
||||
#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description U_SIG_PUNCTURE_PATTERN_ENCODING
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
The 6-bit value used in U-SIG and/or EHT-SIG Common field
|
||||
for the puncture pattern
|
||||
<legal 0-29>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37
|
||||
#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 38
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 63
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0xffffffc000000000
|
||||
|
||||
|
||||
/* Description EHT_PPDU_TYPE
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
<enum 0 EHT_PPDU_rsvd> DO NOT USE
|
||||
<enum 1 EHT_PPDU_TB>
|
||||
<enum 2 EHT_PPDU_MU> Need to look at both EHT-SIG content
|
||||
channels
|
||||
<enum 3 EHT_PPDU_SU> Need to look at only one EHT-SIG content
|
||||
channel
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x0000000000000003
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7
|
||||
#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8
|
||||
#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15
|
||||
#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00
|
||||
|
||||
|
||||
/* Description CP_SETTING
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
<enum 0 gi_0_8_us > Legacy normal GI
|
||||
<enum 1 gi_0_4_us > Legacy short GI
|
||||
<enum 2 gi_1_6_us > HE related GI
|
||||
<enum 3 gi_3_2_us > HE related GI
|
||||
<legal 0 - 3>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17
|
||||
#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000
|
||||
|
||||
|
||||
/* Description LTF_SIZE
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
Ltf size
|
||||
|
||||
<enum 0 ltf_1x >
|
||||
<enum 1 ltf_2x >
|
||||
<enum 2 ltf_4x >
|
||||
<legal 0 - 2>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19
|
||||
#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
TODO: Placeholder
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23
|
||||
#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
On RX side, looked at by MAC HW
|
||||
|
||||
When set, PHY has received an (expected) NDP frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24
|
||||
#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000
|
||||
|
||||
|
||||
/* Description DOT11BE_SU_EXTENDED
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
On RX side, evaluated by MAC HW
|
||||
|
||||
This is the only way for MAC RX to know that this was a
|
||||
U_SIG_EHT_SU received in extended range format.
|
||||
|
||||
When set, the 11be frame is of the extended range format.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25
|
||||
#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x0000000002000000
|
||||
|
||||
|
||||
/* Description RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31
|
||||
#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description EHT_DUPLICATE
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
Indicates EHT duplicate modulation
|
||||
|
||||
<enum 0 eht_no_duplicate>
|
||||
<enum 1 eht_2x_duplicate>
|
||||
<enum 2 eht_4x_duplicate>
|
||||
|
||||
<legal 0-2>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000
|
||||
|
||||
|
||||
/* Description EHT_SIG_CMN_FIELD_TYPE
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
Indicates the type of EHT-SIG Common field
|
||||
|
||||
<enum 0 EHT_SIG_CMN_NO_PUNC> Non-OFDMA, EHT-SIG Common field
|
||||
does not contain puncturing information
|
||||
<enum 1 EHT_SIG_CMN_PUNC> Non-OFDMA, EHT-SIG Common field
|
||||
contains puncturing information
|
||||
<enum 2 EHT_SIG_OFDMA>
|
||||
OFDMA, EHT-SIG Common field contains RU structure
|
||||
<legal 0-2>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 34
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 35
|
||||
#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000
|
||||
|
||||
|
||||
/* Description DOPPLER_INDICATION
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV.
|
||||
|
||||
|
||||
0: No Doppler support
|
||||
1: Doppler support
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36
|
||||
#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV
|
||||
and EHT_PPDU_type is EHT_PPDU_MU (MU-MIMO or OFDMA).
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47
|
||||
#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000
|
||||
|
||||
|
||||
/* Description PUNCTURE_BITMAP
|
||||
|
||||
Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV
|
||||
and EHT_SIG_CMN_field_type is EHT_SIG_CMN_PUNC.
|
||||
|
||||
Indicates which 20 MHz sub-bands will be modulated vs punctured
|
||||
(bits [15:0]) in CCA order (primary/secondary)
|
||||
|
||||
Bit 0: primary 20MHz sub-band
|
||||
Bit 1: secondary 20 MHz sub-band
|
||||
Bit 2: first 20 MHz sub-band in secondary 40 MHz
|
||||
Bit 3: second 20 MHz sub-band in secondary 40 MHz
|
||||
...
|
||||
Bit 15: last 20MHz sub-band in secondary 160 MHz
|
||||
A value of 0 means the band is punctured
|
||||
A value of 1 means the band is modulated
|
||||
|
||||
If the PPDU BW is less than 320 MHz, the MSB bits are reserved
|
||||
and set to 0.
|
||||
*/
|
||||
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63
|
||||
#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_COMMON_USER_INFO
|
||||
390
hw/qcn6432/phyrx_he_sig_a_mu_dl.h
Archivo normal
390
hw/qcn6432/phyrx_he_sig_a_mu_dl.h
Archivo normal
@@ -0,0 +1,390 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
|
||||
#define _PHYRX_HE_SIG_A_MU_DL_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_mu_dl_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1
|
||||
|
||||
|
||||
struct phyrx_he_sig_a_mu_dl {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
NOTE: This is unsupported for "HE MU" format (including "MU_SU")
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description MCS_OF_SIG_B
|
||||
|
||||
Indicates the MCS of HE-SIG-B
|
||||
<legal 0-5>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e
|
||||
|
||||
|
||||
/* Description DCM_OF_SIG_B
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
to HE-SIG-B
|
||||
|
||||
0: No DCM for HE_SIG_B
|
||||
1: DCM for HE_SIG_B
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
For 20MHz one SR field corresponding to entire 20MHz (other
|
||||
3 fields indicate identical values)
|
||||
For 40MHz two SR fields for each 20MHz (other 2 fields indicate
|
||||
identical values)
|
||||
For 80MHz four SR fields for each 20MHz
|
||||
For 160MHz four SR fields for each 40MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
<enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble puncturing
|
||||
mode
|
||||
<enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz non-preamble
|
||||
puncturing mode
|
||||
<enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble puncturing
|
||||
in 80 MHz, where in the preamble only the secondary 20
|
||||
MHz is punctured
|
||||
<enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for preamble
|
||||
puncturing in 80 MHz, where in the preamble only one of
|
||||
the two 20 MHz sub-channels in secondary 40 MHz is punctured.
|
||||
|
||||
<enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble puncturing
|
||||
in 160 MHz or 80+80 MHz, where in the primary 80 MHz of
|
||||
the preamble only the secondary 20 MHz is punctured.
|
||||
<enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for preamble
|
||||
puncturing in 160 MHz or 80+80 MHz, where in the primary
|
||||
80 MHz of the preamble the primary 40 MHz is present.
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal 0-7>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000
|
||||
|
||||
|
||||
/* Description NUM_SIG_B_SYMBOLS
|
||||
|
||||
Number of symbols
|
||||
|
||||
For OFDMA, the actual number of symbols is 1 larger then
|
||||
indicated in this field.
|
||||
|
||||
For MU-MIMO this is equal to the number of users - 1: the
|
||||
following encoding is used:
|
||||
1 => 2 users
|
||||
2 => 3 users
|
||||
Etc.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
|
||||
|
||||
|
||||
/* Description COMP_MODE_SIG_B
|
||||
|
||||
Indicates the compression mode of HE-SIG-B
|
||||
|
||||
0: Regular [uncomp mode]
|
||||
1: compressed mode (full-BW MU-MIMO only)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
|
||||
|
||||
|
||||
/* Description CP_LTF_SIZE
|
||||
|
||||
Indicates the CP and HE-LTF type
|
||||
|
||||
<enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
|
||||
<enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
|
||||
<enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
|
||||
<enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000
|
||||
|
||||
|
||||
/* Description DOPPLER_INDICATION
|
||||
|
||||
0: No Doppler support
|
||||
1: Doppler support
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000
|
||||
|
||||
|
||||
/* Description NUM_LTF_SYMBOLS
|
||||
|
||||
Indicates the number of HE-LTF symbols
|
||||
|
||||
0: 1 LTF
|
||||
1: 2 LTFs
|
||||
2: 4 LTFs
|
||||
3: 6 LTFs
|
||||
4: 8 LTFs
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
If LDPC,
|
||||
0: LDPC extra symbol not present
|
||||
1: LDPC extra symbol present
|
||||
Else
|
||||
Set to 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Indicates whether STBC is applied
|
||||
0: No STBC
|
||||
1: STBC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_A_FACTOR
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with these two bits indicating the "a-factor"
|
||||
|
||||
<enum 0 a_factor_4>
|
||||
<enum 1 a_factor_1>
|
||||
<enum 2 a_factor_2>
|
||||
<enum 3 a_factor_3>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_PE_DISAMBIGUITY
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with this bit indicating the PE-Disambiguity
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_HE_SIG_A_MU_DL
|
||||
202
hw/qcn6432/phyrx_he_sig_a_mu_ul.h
Archivo normal
202
hw/qcn6432/phyrx_he_sig_a_mu_ul.h
Archivo normal
@@ -0,0 +1,202 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
|
||||
#define _PHYRX_HE_SIG_A_MU_UL_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_mu_ul_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1
|
||||
|
||||
|
||||
struct phyrx_he_sig_a_mu_ul {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description FORMAT_INDICATION
|
||||
|
||||
Indicates whether the transmission is SU PPDU or a trigger
|
||||
based UL MU PDDU
|
||||
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
|
||||
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
<enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
|
||||
<enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Set to value indicated in the trigger frame
|
||||
<legal 255>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
This CRC may also cover some fields of L-SIG (TBD)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
|
||||
used
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_HE_SIG_A_MU_UL
|
||||
497
hw/qcn6432/phyrx_he_sig_a_su.h
Archivo normal
497
hw/qcn6432/phyrx_he_sig_a_su.h
Archivo normal
@@ -0,0 +1,497 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_A_SU_H_
|
||||
#define _PHYRX_HE_SIG_A_SU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_su_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1
|
||||
|
||||
|
||||
struct phyrx_he_sig_a_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
|
||||
#else
|
||||
struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_HE_SIG_A_SU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description FORMAT_INDICATION
|
||||
|
||||
<enum 0 HE_SIGA_FORMAT_HE_TRIG>
|
||||
<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description BEAM_CHANGE
|
||||
|
||||
Indicates whether spatial mapping is changed between legacy
|
||||
and HE portion of preamble. If not, channel estimation
|
||||
can include legacy preamble to improve accuracy
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002
|
||||
|
||||
|
||||
/* Description DL_UL_FLAG
|
||||
|
||||
Differentiates between DL and UL transmission
|
||||
|
||||
<enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
|
||||
<enum 1 DL_UL_FLAG_IS_UL>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004
|
||||
|
||||
|
||||
/* Description TRANSMIT_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078
|
||||
|
||||
|
||||
/* Description DCM
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080
|
||||
|
||||
|
||||
/* Description BSS_COLOR_ID
|
||||
|
||||
BSS color ID
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
Note: spec indicates this shall be set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description SPATIAL_REUSE
|
||||
|
||||
Spatial reuse
|
||||
|
||||
For 20MHz one SR field corresponding to entire 20MHz (other
|
||||
3 fields indicate identical values)
|
||||
For 40MHz two SR fields for each 20MHz (other 2 fields indicate
|
||||
identical values)
|
||||
For 80MHz four SR fields for each 20MHz
|
||||
For 160MHz four SR fields for each 40MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000
|
||||
|
||||
|
||||
/* Description TRANSMIT_BW
|
||||
|
||||
Bandwidth of the PPDU.
|
||||
|
||||
For HE SU PPDU
|
||||
|
||||
|
||||
|
||||
<enum 0 HE_SIG_A_BW20> 20 Mhz
|
||||
<enum 1 HE_SIG_A_BW40> 40 Mhz
|
||||
<enum 2 HE_SIG_A_BW80> 80 Mhz
|
||||
<enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
|
||||
|
||||
For HE Extended Range SU PPDU
|
||||
Set to 0 for 242-tone RU
|
||||
|
||||
Set to 1 for right 106-tone RU within
|
||||
the primary 20 MHz
|
||||
|
||||
On RX side, Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000
|
||||
|
||||
|
||||
/* Description CP_LTF_SIZE
|
||||
|
||||
Indicates the CP and HE-LTF type
|
||||
|
||||
<enum 0 OneX_LTF_0_8CP> 1xLTF + 0.8 us CP
|
||||
<enum 1 TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
|
||||
<enum 2 TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
|
||||
|
||||
<enum 3 FourX_LTF_0_8CP_3_2CP>
|
||||
When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
|
||||
When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
|
||||
In this scenario, Neither DCM nor STBC is applied to HE
|
||||
data field.
|
||||
|
||||
NOTE:
|
||||
If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
|
||||
0 = 1xLTF + 0.4 usec
|
||||
1 = 2xLTF + 0.4 usec
|
||||
2~3 = Reserved
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
Indicates number of streams used for the SU transmission
|
||||
|
||||
|
||||
For HE SU PPDU
|
||||
|
||||
|
||||
Set to n for n+1 space time stream,
|
||||
where n = 0, 1, 2,.....,7.
|
||||
|
||||
|
||||
|
||||
|
||||
For HE Extended Range PPDU
|
||||
|
||||
|
||||
Set to 0 for 1 space time stream.
|
||||
Value 1 is TBD
|
||||
|
||||
|
||||
|
||||
Values 2 - 7 are reserved
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description TXOP_DURATION
|
||||
|
||||
Indicates the remaining time in the current TXOP
|
||||
|
||||
Field Used by MAC HW
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
|
||||
/* Description CODING
|
||||
|
||||
Distinguishes between BCC and LDPC coding.
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
If LDPC,
|
||||
0: LDPC extra symbol not present
|
||||
1: LDPC extra symbol present
|
||||
Else
|
||||
Set to 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Indicates whether STBC is applied
|
||||
0: No STBC
|
||||
1: STBC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_A_FACTOR
|
||||
|
||||
Common trigger info
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with these two bits indicating the "a-factor"
|
||||
|
||||
<enum 0 a_factor_4>
|
||||
<enum 1 a_factor_1>
|
||||
<enum 2 a_factor_2>
|
||||
<enum 3 a_factor_3>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
|
||||
|
||||
|
||||
/* Description PACKET_EXTENSION_PE_DISAMBIGUITY
|
||||
|
||||
Common trigger info
|
||||
|
||||
the packet extension duration of the trigger-based PPDU
|
||||
response with this bit indicating the PE-Disambiguity
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
Note: per standard, set to 1
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000
|
||||
|
||||
|
||||
/* Description DOPPLER_INDICATION
|
||||
|
||||
0: No Doppler support
|
||||
1: Doppler support
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC for HE-SIG-A contents.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
|
||||
/* Description DOT11AX_SU_EXTENDED
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:
|
||||
On RX side, evaluated by MAC HW. This is the only way for
|
||||
MAC RX to know that this was an HE_SIG_A_SU received in
|
||||
'extended' format
|
||||
|
||||
When set, the 11ax frame is of the extended range format
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
|
||||
|
||||
|
||||
/* Description DOT11AX_EXT_RU_SIZE
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:
|
||||
Field only contains valid info when dot11ax_su_extended
|
||||
is set.
|
||||
|
||||
On RX side, evaluated by MAC HW. This is the only way for
|
||||
MAC RX to know what the number of based RUs was in this
|
||||
extended range reception. It is used by the MAC to determine
|
||||
the RU size for the response...
|
||||
|
||||
<enum 0 EXT_RU_26>
|
||||
<enum 1 EXT_RU_52>
|
||||
<enum 2 EXT_RU_106>
|
||||
<enum 3 EXT_RU_242><legal 0-3>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000
|
||||
|
||||
|
||||
/* Description RX_NDP
|
||||
|
||||
TX side:
|
||||
Set to 0
|
||||
|
||||
RX side:Valid on RX side only, and looked at by MAC HW
|
||||
|
||||
When set, PHY has received (expected) NDP frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HE-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_HE_SIG_A_SU
|
||||
101
hw/qcn6432/phyrx_he_sig_b1_mu.h
Archivo normal
101
hw/qcn6432/phyrx_he_sig_b1_mu.h
Archivo normal
@@ -0,0 +1,101 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_B1_MU_H_
|
||||
#define _PHYRX_HE_SIG_B1_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b1_mu_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1
|
||||
|
||||
|
||||
struct phyrx_he_sig_b1_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_HE_SIG_B1_MU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description RU_ALLOCATION
|
||||
|
||||
RU allocation for the user(s) following this common portion
|
||||
of the SIG
|
||||
|
||||
For details, refer to RU_TYPE description
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing the HE-SIG-B common info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
|
||||
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
|
||||
#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_HE_SIG_B1_MU
|
||||
198
hw/qcn6432/phyrx_he_sig_b2_mu.h
Archivo normal
198
hw/qcn6432/phyrx_he_sig_b2_mu.h
Archivo normal
@@ -0,0 +1,198 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_B2_MU_H_
|
||||
#define _PHYRX_HE_SIG_B2_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b2_mu_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1
|
||||
|
||||
|
||||
struct phyrx_he_sig_b2_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
|
||||
#else
|
||||
struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_HE_SIG_B2_MU_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description STA_SPATIAL_CONFIG
|
||||
|
||||
Number of assigned spatial streams and their corresponding
|
||||
index.
|
||||
Total number of spatial streams assigned for the MU-MIMO
|
||||
allocation is also signaled.
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
|
||||
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
MAC RX side usage only:
|
||||
Needed by RXPCU. Provided by PHY so that RXPCU does not
|
||||
need to have the RU number decoding logic.
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this HE-SIG-B user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description USER_ORDER
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channel this User field
|
||||
can go to
|
||||
Bit 0: content channel 0
|
||||
Bit 1: content channel 1
|
||||
The other bits are unused, but could repeat the above pattern
|
||||
for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63
|
||||
#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_HE_SIG_B2_MU
|
||||
205
hw/qcn6432/phyrx_he_sig_b2_ofdma.h
Archivo normal
205
hw/qcn6432/phyrx_he_sig_b2_ofdma.h
Archivo normal
@@ -0,0 +1,205 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
|
||||
#define _PHYRX_HE_SIG_B2_OFDMA_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b2_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1
|
||||
|
||||
|
||||
struct phyrx_he_sig_b2_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
|
||||
#else
|
||||
struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description STA_ID
|
||||
|
||||
Identifies the STA that is addressed. Details of STA ID
|
||||
are TBD
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
|
||||
/* Description NSTS
|
||||
|
||||
MAC RX side usage only:
|
||||
|
||||
Number of spatial streams for this user
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800
|
||||
|
||||
|
||||
/* Description TXBF
|
||||
|
||||
Indicates whether beamforming is applied
|
||||
0: No beamforming
|
||||
1: beamforming
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description STA_MCS
|
||||
|
||||
Indicates the data MCS
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
|
||||
|
||||
|
||||
/* Description STA_DCM
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000
|
||||
|
||||
|
||||
/* Description STA_CODING
|
||||
|
||||
Distinguishes between BCC/LDPC
|
||||
|
||||
0: BCC
|
||||
1: LDPC
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the CRC check of the
|
||||
codeblock containing this HE-SIG-B user info has passed,
|
||||
else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description USER_ORDER
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Ordering index of the User field
|
||||
Gaps between the ordering indices of User fields indicate
|
||||
that the microcode shall generate "unallocated RU" User
|
||||
fields (STAID=2046) to fill the gaps.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description CC_MASK
|
||||
|
||||
RX side: Set to 0
|
||||
TX side: Indicates what content channel this User field
|
||||
can go to
|
||||
Bit 0: content channel 0
|
||||
Bit 1: content channel 1
|
||||
The other bits are unused, but could repeat the above pattern
|
||||
for compatibility with 'EHT_SIG_USR_OFDMA_INFO.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63
|
||||
#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_HE_SIG_B2_OFDMA
|
||||
271
hw/qcn6432/phyrx_ht_sig.h
Archivo normal
271
hw/qcn6432/phyrx_ht_sig.h
Archivo normal
@@ -0,0 +1,271 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_HT_SIG_H_
|
||||
#define _PHYRX_HT_SIG_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "ht_sig_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_HT_SIG 1
|
||||
|
||||
|
||||
struct phyrx_ht_sig {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct ht_sig_info phyrx_ht_sig_info_details;
|
||||
#else
|
||||
struct ht_sig_info phyrx_ht_sig_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_HT_SIG_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
Modulation Coding Scheme:
|
||||
0-7 are used for single stream
|
||||
8-15 are used for 2 streams
|
||||
16-23 are used for 3 streams
|
||||
24-31 are used for 4 streams
|
||||
32 is used for duplicate HT20 (unsupported)
|
||||
33-76 is used for unequal modulation (unsupported)
|
||||
77-127 is reserved.
|
||||
<legal 0-31>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f
|
||||
|
||||
|
||||
/* Description CBW
|
||||
|
||||
Packet bandwidth:
|
||||
<enum 0 ht_20_mhz>
|
||||
<enum 1 ht_40_mhz>
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
This is the MPDU or A-MPDU length in octets of the PPDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
This field is not part of HT-SIG
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description SMOOTHING
|
||||
|
||||
Field indicates if smoothing is needed
|
||||
E_num 0 do_smoothing Unsupported setting: indicates
|
||||
smoothing is often used for beamforming
|
||||
<enum 1 no_smoothing> Indicates no smoothing is used
|
||||
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000
|
||||
|
||||
|
||||
/* Description NOT_SOUNDING
|
||||
|
||||
E_num 0 sounding Unsupported setting: indicates sounding
|
||||
is used
|
||||
<enum 1 no_sounding> Indicates no sounding is used
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000
|
||||
|
||||
|
||||
/* Description HT_RESERVED
|
||||
|
||||
Reserved: Should be set to 1 by the MAC and ignored by the
|
||||
PHY
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000
|
||||
|
||||
|
||||
/* Description AGGREGATION
|
||||
|
||||
<enum 0 mpdu> Indicates MPDU format
|
||||
<enum 1 a_mpdu> Indicates A-MPDU format
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
<enum 0 no_stbc> Indicates no STBC
|
||||
<enum 1 1_str_stbc> Indicates 1 stream STBC
|
||||
E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported)
|
||||
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000
|
||||
|
||||
|
||||
/* Description FEC_CODING
|
||||
|
||||
<enum 0 ht_bcc> Indicates BCC coding
|
||||
<enum 1 ht_ldpc> Indicates LDPC coding
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000
|
||||
|
||||
|
||||
/* Description SHORT_GI
|
||||
|
||||
<enum 0 ht_normal_gi> Indicates normal guard interval
|
||||
|
||||
<enum 1 ht_short_gi> Indicates short guard interval
|
||||
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000
|
||||
|
||||
|
||||
/* Description NUM_EXT_SP_STR
|
||||
|
||||
Number of extension spatial streams: (Used for TxBF)
|
||||
<enum 0 0_ext_sp_str> No extension spatial streams
|
||||
E_num 1 1_ext_sp_str Not supported: 1 extension spatial
|
||||
streams
|
||||
E_num 2 2_ext_sp_str Not supported: 2 extension spatial
|
||||
streams
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0].
|
||||
The generator polynomial is G(D) = D8 + D2 + D + 1. <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
|
||||
|
||||
|
||||
/* Description SIGNAL_TAIL
|
||||
|
||||
The 6 bits of tail is always set to 0 is used to flush the
|
||||
BCC encoder and decoder. <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
This field is not part of HT-SIG:
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY. <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the HT-SIG CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_HT_SIG
|
||||
208
hw/qcn6432/phyrx_l_sig_a.h
Archivo normal
208
hw/qcn6432/phyrx_l_sig_a.h
Archivo normal
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_L_SIG_A_H_
|
||||
#define _PHYRX_L_SIG_A_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "l_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1
|
||||
|
||||
|
||||
struct phyrx_l_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_a_info phyrx_l_sig_a_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct l_sig_a_info phyrx_l_sig_a_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_L_SIG_A_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description RATE
|
||||
|
||||
This format is originally defined for OFDM as a 4 bit field
|
||||
but the 5th bit was added to indicate 11b formatted frames.
|
||||
In the standard bit [4] is specified as reserved. For
|
||||
11b frames this L-SIG is transformed in the PHY into the
|
||||
11b preamble format. The following are the rates:
|
||||
<enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
|
||||
<enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
|
||||
<enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
|
||||
<enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
|
||||
<enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
|
||||
<enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
|
||||
<enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
|
||||
<enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
|
||||
<legal 8-15>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f
|
||||
|
||||
|
||||
/* Description LSIG_RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
The length indicates the number of octets in this MPDU.
|
||||
Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be
|
||||
this length provides the spoofed length for the PPDU.
|
||||
This length provides part of the information (viz. PPDU
|
||||
duration) to derive the actually PSDU length. For legacy
|
||||
OFDM and 11B frames the maximum length is 4095.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0
|
||||
|
||||
|
||||
/* Description PARITY
|
||||
|
||||
11a/n/ac TX: This field provides even parity over the first
|
||||
18 bits of the signal field which means that the sum of
|
||||
1s in the signal field will always be even on transmission.
|
||||
The value of the field is computed by the MAC.
|
||||
11a/n/ac RX: this field contains the received parity field
|
||||
from the L-SIG symbol for the current packet.
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
The 6 bits of tail is always set to 0 is used to flush the
|
||||
BCC encoder and decoder. <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000
|
||||
|
||||
|
||||
/* Description PKT_TYPE
|
||||
|
||||
Only used on the RX side.
|
||||
Note: This is not really part of L-SIG
|
||||
|
||||
Packet type:
|
||||
<enum 0 dot11a>802.11a PPDU type
|
||||
<enum 1 dot11b>802.11b PPDU type
|
||||
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
|
||||
<enum 3 dot11ac>802.11ac PPDU type
|
||||
<enum 4 dot11ax>802.11ax PPDU type
|
||||
<enum 5 dot11ba>802.11ba (WUR) PPDU type
|
||||
<enum 6 dot11be>802.11be PPDU type
|
||||
<enum 7 dot11az>802.11az (ranging) PPDU type
|
||||
<enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported
|
||||
& aborted)
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
|
||||
|
||||
|
||||
/* Description CAPTURED_IMPLICIT_SOUNDING
|
||||
|
||||
Only used on the RX side.
|
||||
Note: This is not really part of L-SIG
|
||||
|
||||
This indicates that the PHY has captured implicit sounding.
|
||||
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the transmitting MAC and
|
||||
ignored by the PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the L-SIG integrity
|
||||
check has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32
|
||||
#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63
|
||||
#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_L_SIG_A
|
||||
116
hw/qcn6432/phyrx_l_sig_b.h
Archivo normal
116
hw/qcn6432/phyrx_l_sig_b.h
Archivo normal
@@ -0,0 +1,116 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_L_SIG_B_H_
|
||||
#define _PHYRX_L_SIG_B_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "l_sig_b_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1
|
||||
|
||||
|
||||
struct phyrx_l_sig_b {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_b_info phyrx_l_sig_b_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct l_sig_b_info phyrx_l_sig_b_info_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_L_SIG_B_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description RATE
|
||||
|
||||
<enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
|
||||
<enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
|
||||
<enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
|
||||
<enum 4 cck_11_mbps_long> CCK 11 Mbps long
|
||||
<enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
|
||||
<enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
|
||||
<enum 7 cck_11_mbps_short> CCK 11 Mbps short
|
||||
<legal 1-7>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f
|
||||
|
||||
|
||||
/* Description LENGTH
|
||||
|
||||
The length indicates the number of octets in this MPDU.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
Reserved: Should be set to 0 by the transmitting MAC and
|
||||
ignored by the PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the .11b PHY header
|
||||
CRC check has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32
|
||||
#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63
|
||||
#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_L_SIG_B
|
||||
911
hw/qcn6432/phyrx_location.h
Archivo normal
911
hw/qcn6432/phyrx_location.h
Archivo normal
@@ -0,0 +1,911 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_LOCATION_H_
|
||||
#define _PHYRX_LOCATION_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "rx_location_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_LOCATION 28
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_LOCATION 14
|
||||
|
||||
|
||||
struct phyrx_location {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct rx_location_info rx_location_info_details;
|
||||
#else
|
||||
struct rx_location_info rx_location_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RX_LOCATION_INFO_DETAILS
|
||||
|
||||
Overview of location related info
|
||||
*/
|
||||
|
||||
|
||||
/* Description RX_LOCATION_INFO_VALID
|
||||
|
||||
<enum 0 rx_location_info_is_not_valid>
|
||||
<enum 1 rx_location_info_is_valid>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description RTT_HW_IFFT_MODE
|
||||
|
||||
Indicator showing if HW IFFT mode or SW IFFT mode
|
||||
|
||||
<enum 0 location_sw_ifft_mode>
|
||||
<enum 1 location_hw_ifft_mode>
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002
|
||||
|
||||
|
||||
/* Description RTT_11AZ_MODE
|
||||
|
||||
Indicator showing RTT5/.11mc or .11az mode for debug
|
||||
|
||||
<enum 0 location_rtt5_mode> legacy RTT5/.11mc mode
|
||||
<enum 1 location_11az_ISTA> .11az ISTA location info. sent
|
||||
on Rx path after receiving R2I LMR
|
||||
<enum 2 location_RSVD>
|
||||
<enum 3 location_11az_RSTA> .11az RSTA location info. sent
|
||||
on Tx path after transmitting R2I LMR
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x000000000000000c
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0
|
||||
|
||||
|
||||
/* Description RTT_NUM_FAC
|
||||
|
||||
Number of valid first arrival correction (FAC) values (in
|
||||
fields rtt_fac_0 - rtt_fac_31)
|
||||
<legal 0-32>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00
|
||||
|
||||
|
||||
/* Description RTT_RX_CHAIN_MASK
|
||||
|
||||
Rx chain mask, each bit is a Rx chain
|
||||
0: the Rx chain is not used
|
||||
1: the Rx chain is used
|
||||
|
||||
Up to 4 Rx chains are supported.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000
|
||||
|
||||
|
||||
/* Description RTT_NUM_STREAMS
|
||||
|
||||
Number of streams used
|
||||
|
||||
Up to 8 streams are supported.
|
||||
|
||||
<legal 0-8>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description RTT_FIRST_SELECTED_CHAIN
|
||||
|
||||
For legacy RTT5/.11mc mode, this field shows the first selected
|
||||
Rx chain that is used for FAC calculations, when forced
|
||||
by a virtual register.
|
||||
|
||||
<enum 0 location_selected_chain_is_0>
|
||||
<enum 1 location_selected_chain_is_1>
|
||||
<enum 2 location_selected_chain_is_2>
|
||||
<enum 3 location_selected_chain_is_3>
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description RTT_SECOND_SELECTED_CHAIN
|
||||
|
||||
For legacy RTT5/.11mc mode, this field shows the second
|
||||
selected Rx chain that is used for FAC calculations, when
|
||||
forced by a virtual register.
|
||||
|
||||
<enum 0 location_selected_chain_is_0>
|
||||
<enum 1 location_selected_chain_is_1>
|
||||
<enum 2 location_selected_chain_is_2>
|
||||
<enum 3 location_selected_chain_is_3>
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description RTT_CFR_STATUS
|
||||
|
||||
Status of channel frequency response dump
|
||||
|
||||
<enum 0 location_CFR_dump_not_valid>
|
||||
<enum 1 location_CFR_dump_valid>
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000
|
||||
|
||||
|
||||
/* Description RTT_CIR_STATUS
|
||||
|
||||
Status of channel impulse response dump
|
||||
|
||||
<enum 0 location_CIR_dump_not_valid>
|
||||
<enum 1 location_CIR_dump_valid>
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000
|
||||
|
||||
|
||||
/* Description RTT_CHE_BUFFER_POINTER_LOW32
|
||||
|
||||
The low 32 bits of the 40 bits pointer pointed to the external
|
||||
RTT channel information buffer
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RTT_CHE_BUFFER_POINTER_HIGH8
|
||||
|
||||
The high 8 bits of the 40 bits pointer pointed to the external
|
||||
RTT channel information buffer
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_3
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000
|
||||
|
||||
|
||||
/* Description RTT_PKT_BW_VHT
|
||||
|
||||
Indicate the bandwidth of (V)HT/HE-LTF
|
||||
|
||||
<enum 0 location_pkt_bw_20MHz>
|
||||
<enum 1 location_pkt_bw_40MHz>
|
||||
<enum 2 location_pkt_bw_80MHz>
|
||||
<enum 3 location_pkt_bw_160MHz>
|
||||
<enum 4 location_pkt_bw_240MHz> Only valid for CFR, FAC
|
||||
calculations are not PoR for 240 MHz.
|
||||
<enum 5 location_pkt_bw_320MHz> Only valid for CFR, FAC
|
||||
calculations are not PoR for 320 MHz.
|
||||
<legal 0-5>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000
|
||||
|
||||
|
||||
/* Description RTT_PKT_BW_LEG
|
||||
|
||||
Indicate the bandwidth of L-LTF
|
||||
|
||||
<enum 0 location_pkt_bw_20MHz>
|
||||
<enum 1 location_pkt_bw_40MHz>
|
||||
<enum 2 location_pkt_bw_80MHz>
|
||||
<enum 3 location_pkt_bw_160MHz>
|
||||
<enum 4 location_pkt_bw_240MHz> Only valid for CFR, FAC
|
||||
calculations are not PoR for 240 MHz.
|
||||
<enum 5 location_pkt_bw_320MHz> Only valid for CFR, FAC
|
||||
calculations are not PoR for 320 MHz.
|
||||
<legal 0-5>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000
|
||||
|
||||
|
||||
/* Description RTT_MCS_RATE
|
||||
|
||||
Bits 0~4 indicate MCS rate, if Legacy,
|
||||
0: 48 Mbps,
|
||||
1: 24 Mbps,
|
||||
2: 12 Mbps,
|
||||
3: 6 Mbps,
|
||||
4: 54 Mbps,
|
||||
5: 36 Mbps,
|
||||
6: 18 Mbps,
|
||||
7: 9 Mbps,
|
||||
8-15: reserved
|
||||
|
||||
if HT, 0-7: MCS0-MCS7, 8-15: reserved,
|
||||
if VHT, 0-9: MCS0-MCS9, 10-15: reserved,
|
||||
if HE or EHT, 0-11: MCS0-MCS11, 12-13: 4096QAM, 14-15: reserved
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000
|
||||
|
||||
|
||||
/* Description RTT_CFO_MEASUREMENT
|
||||
|
||||
CFO measurement. Needed for passive locationing
|
||||
|
||||
14 bits, signed 1.13. 13 bits fraction to provide a resolution
|
||||
of 153 Hz
|
||||
|
||||
In units of cycles/800 ns
|
||||
<legal 0-16383>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_PREAMBLE_TYPE
|
||||
|
||||
Indicate preamble type
|
||||
|
||||
<enum 0 location_preamble_type_legacy>
|
||||
<enum 1 location_preamble_type_ht>
|
||||
<enum 2 location_preamble_type_vht>
|
||||
<enum 3 location_preamble_type_he_su_4xltf>
|
||||
<enum 4 location_preamble_type_he_su_2xltf>
|
||||
<enum 5 location_preamble_type_he_su_1xltf>
|
||||
<enum 6 location_preamble_type_he_trigger_based_ul_4xltf>
|
||||
|
||||
<enum 7 location_preamble_type_he_trigger_based_ul_2xltf>
|
||||
|
||||
<enum 8 location_preamble_type_he_trigger_based_ul_1xltf>
|
||||
|
||||
<enum 9 location_preamble_type_he_mu_4xltf>
|
||||
<enum 10 location_preamble_type_he_mu_2xltf>
|
||||
<enum 11 location_preamble_type_he_mu_1xltf>
|
||||
<enum 12 location_preamble_type_he_extended_range_su_4xltf>
|
||||
|
||||
<enum 13 location_preamble_type_he_extended_range_su_2xltf>
|
||||
|
||||
<enum 14 location_preamble_type_he_extended_range_su_1xltf>
|
||||
|
||||
<legal 0-14>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000
|
||||
|
||||
|
||||
/* Description RTT_GI_TYPE
|
||||
|
||||
Indicate GI (guard interval) type
|
||||
|
||||
<enum 0 location_gi_0_8_us > HE related GI. Can also be
|
||||
used for HE
|
||||
<enum 1 location_gi_0_4_us > HE related GI. Can also be
|
||||
used for HE
|
||||
<enum 2 location_gi_1_6_us > HE related GI
|
||||
<enum 3 location_gi_3_2_us > HE related GI
|
||||
<legal 0 - 3>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description RX_START_TS
|
||||
|
||||
RX packet start timestamp lower 32 bits
|
||||
|
||||
It reports the time the first L-STF ADC sample arrived at
|
||||
RX antenna.
|
||||
|
||||
The clock unit is 960MHz.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RX_START_TS_UPPER
|
||||
|
||||
RX packet start timestamp upper 32 bits
|
||||
|
||||
It reports the time the first L-STF ADC sample arrived at
|
||||
RX antenna.
|
||||
|
||||
The clock unit is 960MHz.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RX_END_TS
|
||||
|
||||
RX packet end timestamp lower 32 bits
|
||||
|
||||
It reports the time the last symbol's last ADC sample arrived
|
||||
at RX antenna.
|
||||
|
||||
The clock unit is 960MHz. Only 32 bits are reported.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description GAIN_CHAIN0
|
||||
|
||||
Reports the total gain in dB and the gain table index to
|
||||
support angle of arrival for chain0
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description GAIN_CHAIN1
|
||||
|
||||
Reports the total gain in dB and the gain table index to
|
||||
support angle of arrival for chain1
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description GAIN_CHAIN2
|
||||
|
||||
Reports the total gain in dB and the gain table index to
|
||||
support angle of arrival for chain2
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description GAIN_CHAIN3
|
||||
|
||||
Reports the total gain in dB and the gain table index to
|
||||
support angle of arrival for chain3
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description GAIN_REPORT_STATUS
|
||||
|
||||
Number of valid gain reports (in fields gain_chain0 - gain_chain_3)
|
||||
|
||||
<legal 0-4>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description RTT_TIMING_BACKOFF_SEL
|
||||
|
||||
Indicate which timing backoff value is used
|
||||
|
||||
<enum 0 timing_backoff_low_rssi>
|
||||
<enum 1 timing_backoff_mid_rssi>
|
||||
<enum 2 timing_backoff_high_rssi>
|
||||
<enum 3 reserved>
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00
|
||||
|
||||
|
||||
/* Description RTT_FAC_COMBINED
|
||||
|
||||
Final adjusted and combined first arrival correction value
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_0
|
||||
|
||||
The fields 'rtt_fac_0' - 'rtt_fac_31' show the RTT first
|
||||
arrival correction (FAC) value computed from the LTFs on
|
||||
the selected Rx chains.
|
||||
|
||||
16 bits, signed 11.5. 11 integer bits to cover -3.2us to
|
||||
3.2us, and 5 fraction bits to cover 160 MHz with 32x FAC
|
||||
interpolation.
|
||||
|
||||
The clock unit is 320MHz.
|
||||
|
||||
For .11az/MIMO, the FACs will be stored in spatial stream
|
||||
order with multiple chains reported together for each stream. [ss0-ch0,
|
||||
ss0-ch1, ..., ss1-ch0, ss1-ch1, ...]
|
||||
|
||||
For legacy RTT5/.11mc, the FACs will be stored in preamble
|
||||
order with multiple chains reported together for each LTF. [legacy-ch0,
|
||||
legacy-ch1, ..., (v)ht/he-ch0, (v)ht/he-ch1, ...]
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_1
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_2
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_3
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_4
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_5
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_6
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_7
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_8
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_9
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_10
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_11
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_12
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_13
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_14
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_15
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_16
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_17
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_18
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_19
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_20
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_21
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_22
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_23
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_24
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_25
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_26
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_27
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RTT_FAC_28
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_29
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description RTT_FAC_30
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description RTT_FAC_31
|
||||
|
||||
See 'rtt_fac_0' description
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RESERVED_27A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_LOCATION
|
||||
98
hw/qcn6432/phyrx_other_receive_info_ru_details.h
Archivo normal
98
hw/qcn6432/phyrx_other_receive_info_ru_details.h
Archivo normal
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
|
||||
#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2
|
||||
|
||||
|
||||
struct phyrx_other_receive_info_ru_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ru_details_channel_0 : 32; // [31:0]
|
||||
uint32_t ru_details_channel_1 : 32; // [31:0]
|
||||
uint32_t spare : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
uint32_t ru_details_channel_0 : 32; // [31:0]
|
||||
uint32_t ru_details_channel_1 : 32; // [31:0]
|
||||
uint32_t spare : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RU_DETAILS_CHANNEL_0
|
||||
|
||||
Ru_allocation from content channel 0
|
||||
[7:0] for 20/40 MHz
|
||||
[15:0] for 80 MHz
|
||||
[31:0] for 160 MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RU_DETAILS_CHANNEL_1
|
||||
|
||||
Ru_allocation from content channel 1
|
||||
[7:0] for 40 MHz
|
||||
[15:0] for 80 MHz
|
||||
[31:0] for 160 MHz
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description SPARE
|
||||
|
||||
Extra spare bits added to convey additional information
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63
|
||||
#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS
|
||||
1135
hw/qcn6432/phyrx_pkt_end.h
Archivo normal
1135
hw/qcn6432/phyrx_pkt_end.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
1159
hw/qcn6432/phyrx_pkt_end_info.h
Archivo normal
1159
hw/qcn6432/phyrx_pkt_end_info.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
2243
hw/qcn6432/phyrx_rssi_legacy.h
Archivo normal
2243
hw/qcn6432/phyrx_rssi_legacy.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
361
hw/qcn6432/phyrx_vht_sig_a.h
Archivo normal
361
hw/qcn6432/phyrx_vht_sig_a.h
Archivo normal
@@ -0,0 +1,361 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYRX_VHT_SIG_A_H_
|
||||
#define _PHYRX_VHT_SIG_A_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
|
||||
|
||||
#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1
|
||||
|
||||
|
||||
struct phyrx_vht_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
|
||||
#else
|
||||
struct vht_sig_a_info phyrx_vht_sig_a_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYRX_VHT_SIG_A_INFO_DETAILS
|
||||
|
||||
See detailed description of the STRUCT
|
||||
*/
|
||||
|
||||
|
||||
/* Description BANDWIDTH
|
||||
|
||||
Packet bandwidth
|
||||
|
||||
<enum 0 20_MHZ_11AC>
|
||||
<enum 1 40_MHZ_11AC>
|
||||
<enum 2 80_MHZ_11AC>
|
||||
<enum 3 160_MHZ_11AC>
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003
|
||||
|
||||
|
||||
/* Description VHTA_RESERVED_0
|
||||
|
||||
Reserved. Set to 1 by MAC, PHY should ignore
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
Space time block coding:
|
||||
<enum 0 stbc_disabled> Indicates STBC is disabled
|
||||
<enum 1 stbc_enabled> Indicates STBC is enabled on
|
||||
all streams
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008
|
||||
|
||||
|
||||
/* Description GROUP_ID
|
||||
|
||||
In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
|
||||
to an AP or to a mesh STA, the Group ID field is set to
|
||||
0, otherwise it is set to 63. In an NDP PPDU the Group
|
||||
ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6
|
||||
(Transmission of a VHT NDP). For a MU-MIMO PPDU the Group
|
||||
ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group
|
||||
ID). <legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0
|
||||
|
||||
|
||||
/* Description N_STS
|
||||
|
||||
For MU:
|
||||
3 bits/user with maximum of 4 users (user u uses
|
||||
vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
|
||||
3)
|
||||
Set to 0 for 0 space time streams
|
||||
Set to 1 for 1 space time stream
|
||||
Set to 2 for 2 space time streams
|
||||
Set to 3 for 3 space time streams
|
||||
Set to 4 for 4 space time streams (not supported in Wifi
|
||||
3.0)
|
||||
Values 5-7 are reserved
|
||||
In this field, references to user "u" should be interpreted
|
||||
as MU user "u". As described in the previous chapter in
|
||||
this document (see chapter on User number), the MU user
|
||||
value for a given client is defined for each MU group that
|
||||
the client participates in. The MU user number is not related
|
||||
to the internal user number that is used within the BFer.
|
||||
|
||||
|
||||
|
||||
For SU:
|
||||
vht_sig_a[0][12:10]
|
||||
Set to 0 for 1 space time stream
|
||||
Set to 1 for 2 space time streams
|
||||
Set to 2 for 3 space time streams
|
||||
Set to 3 for 4 space time streams
|
||||
Set to 4 for 5 space time streams
|
||||
Set to 5 for 6 space time streams
|
||||
Set to 6 for 7 space time streams
|
||||
Set to 7 for 8 space time streams
|
||||
|
||||
vht_sig_a[0][21:13]
|
||||
Partial AID:
|
||||
Set to the value of the TXVECTOR parameter PARTIAL_AID.
|
||||
Partial AID provides an abbreviated indication of the intended
|
||||
recipient(s) of the frame (see IEEE802.11ac_D1.0 Section
|
||||
9.17a (Partial AID in VHT PPDUs)).
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00
|
||||
|
||||
|
||||
/* Description TXOP_PS_NOT_ALLOWED
|
||||
|
||||
E_num 0 txop_ps_allowed Not supported: If set to by
|
||||
VHT AP if it allows non-AP VHT STAs in TXOP power save
|
||||
mode to enter Doze state during a TXOP
|
||||
<enum 1 no_txop_ps_allowed> Otherwise
|
||||
<legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000
|
||||
|
||||
|
||||
/* Description VHTA_RESERVED_0B
|
||||
|
||||
Reserved: Should be set to 1 by the MAC and ignored by the
|
||||
PHY <legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000
|
||||
|
||||
|
||||
/* Description RESERVED_0
|
||||
|
||||
This field is not part of HT-SIG:
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description GI_SETTING
|
||||
|
||||
<enum 0 normal_gi> Indicates short guard interval is
|
||||
not used in the data field
|
||||
<enum 1 short_gi> Indicates short guard interval is
|
||||
used in the data field
|
||||
<enum 3 short_gi_ambiguity> Indicates short guard interval
|
||||
is used in the data field and NSYM mod 10 = 9
|
||||
NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME
|
||||
and PSDU_LENGTH calculation).
|
||||
<legal 0,1,3>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000
|
||||
|
||||
|
||||
/* Description SU_MU_CODING
|
||||
|
||||
For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an
|
||||
MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
|
||||
B2 indicates the coding used for user 0; set to 0 for BCC
|
||||
and 1 for LDPC. If the MU[0] NSTS field is 0, then this
|
||||
field is reserved and set to 1
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000
|
||||
|
||||
|
||||
/* Description LDPC_EXTRA_SYMBOL
|
||||
|
||||
Set to 1 if the LDPC PPDU encoding process (if an SU PPDU),
|
||||
or at least one LDPC user's PPDU encoding process (if an
|
||||
MU PPDU), results in an extra OFDM symbol (or symbols)
|
||||
as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
|
||||
(Encoding process for MU PPDUs). Set to 0 otherwise.
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000
|
||||
|
||||
|
||||
/* Description MCS
|
||||
|
||||
For SU:
|
||||
Set to 0 for BPSK 1/2
|
||||
Set to 1 for QPSK 1/2
|
||||
Set to 2 for QPSK 3/4
|
||||
Set to 3 for 16-QAM 1/2
|
||||
Set to 4 for 16-QAM 3/4
|
||||
Set to 5 for 64-QAM 2/3
|
||||
Set to 6 for 64-QAM 3/4
|
||||
Set to 7 for 64-QAM 5/6
|
||||
Set to 8 for 256-QAM 3/4
|
||||
Set to 9 for 256-QAM 5/6
|
||||
For MU:
|
||||
If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates
|
||||
coding for user 1: set to 0 for BCC, 1 for LDPC.
|
||||
If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
|
||||
reserved and set to 1.
|
||||
If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates
|
||||
coding for user 2: set to 0 for BCC, 1 for LDPC.
|
||||
If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
|
||||
reserved and set to 1.
|
||||
If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates
|
||||
coding for user 3: set to 0 for BCC, 1 for LDPC.
|
||||
If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
|
||||
reserved and set to 1.
|
||||
vht_sig_a[1][7] is reserved and set to 1
|
||||
<legal 0-15>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000
|
||||
|
||||
|
||||
/* Description BEAMFORMED
|
||||
|
||||
For SU:
|
||||
Set to 1 if a Beamforming steering matrix is applied to
|
||||
the waveform in an SU transmission as described in IEEE802.11ac_D1.0
|
||||
Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise.
|
||||
|
||||
For MU:
|
||||
Reserved and set to 1
|
||||
<legal 0-1>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000
|
||||
|
||||
|
||||
/* Description VHTA_RESERVED_1
|
||||
|
||||
Reserved and set to 1. <legal 1>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000
|
||||
|
||||
|
||||
/* Description CRC
|
||||
|
||||
CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4
|
||||
(CRC calculation for HTSIG) with C7 in vht_sig_a[1][10],
|
||||
etc. <legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
|
||||
|
||||
|
||||
/* Description TAIL
|
||||
|
||||
Used to terminate the trellis of the convolutional decoder.
|
||||
Set to 0. <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
This field is not part of HT-SIG:
|
||||
Reserved: Should be set to 0 by the MAC and ignored by the
|
||||
PHY <legal 0>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
|
||||
|
||||
|
||||
/* Description RX_INTEGRITY_CHECK_PASSED
|
||||
|
||||
TX side: Set to 0
|
||||
RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check
|
||||
has passed, else set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // PHYRX_VHT_SIG_A
|
||||
242
hw/qcn6432/phytx_abort_request_info.h
Archivo normal
242
hw/qcn6432/phytx_abort_request_info.h
Archivo normal
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
#define _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
|
||||
|
||||
|
||||
struct phytx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t phytx_abort_reason : 8, // [7:0]
|
||||
user_number : 6, // [13:8]
|
||||
reserved : 2; // [15:14]
|
||||
#else
|
||||
uint16_t reserved : 2, // [15:14]
|
||||
user_number : 6, // [13:8]
|
||||
phytx_abort_reason : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHYTX_ABORT_REASON
|
||||
|
||||
Reason for early termination of TX packet by the PHY
|
||||
|
||||
<enum 0 no_phytx_error_reported>This value is the default
|
||||
value the MAC will fill in the status TLV (when not PHY
|
||||
abort was received).
|
||||
|
||||
Note that when PHY generates the PHYTX_ABORT_REQUEST, this
|
||||
value shall never be used.
|
||||
<enum 1 error_txtd_ifft_underrun>PHY ran out of transmit
|
||||
data due to transmit underrun - this field is user-specific
|
||||
(see user_number field)
|
||||
<enum 2 error_tx_invalid_tlv>
|
||||
<enum 3 error_tx_unexpected_tlv>
|
||||
<enum 4 error_tx_pkt_end_error>
|
||||
<enum 5 error_tx_bw_is_gt_dyn_bw>
|
||||
<enum 6 error_txtd_pkt_start_error>
|
||||
<enum 7 error_txfd_pre_phy_tlv_ooo>
|
||||
<enum 8 error_txtd_mu_data_underrun>
|
||||
<enum 9 error_tx_legacy_rate_illegal>
|
||||
<enum 10 error_tx_fifo_error>
|
||||
<enum 11 error_tx_ack_wd_error>
|
||||
<enum 12 error_tx_tpc_miss>
|
||||
<enum 13 error_mac_tx_abort>
|
||||
<enum 14 error_tx_pcss_phy_desc_wdg_timeout>
|
||||
<enum 15 error_unsupported_cbf>
|
||||
<enum 16 error_cv_static_bandwidth_mismatch>
|
||||
<enum 17 error_cv_dynamic_bandwidth_mismatch>
|
||||
<enum 18 error_cv_unsupported_nss_total>
|
||||
<enum 19 error_nss_bf_params_mismatch>
|
||||
<enum 20 error_txbf_fail>
|
||||
<enum 21 error_txbf_snd_fail>This used to be called 'error_illegal_nss.'
|
||||
|
||||
<enum 22 error_otp_txbf>
|
||||
<enum 23 error_tx_inv_chainmask>
|
||||
<enum 24 error_cv_index_assign_overload>This error indicates
|
||||
that CV prefetch command indicated a CV index that is not
|
||||
available.
|
||||
<enum 25 error_cv_index_delete>This error indicates that
|
||||
CV delete command indicated a CV index that did not contain
|
||||
any valid info
|
||||
<enum 26 error_tx_he_rate_illegal>Error found with the HE
|
||||
transmission parameters
|
||||
<enum 27 error_tx_pcss_wdg_timeout>
|
||||
<enum 28 error_tx_tlv_tag_mismatch>
|
||||
<enum 29 error_tx_cck_fifo_flush>
|
||||
<enum 30 error_tx_no_mac_pkt_end>
|
||||
<enum 31 error_tx_abort_for_mac_war>
|
||||
<enum 32 error_tx_stuck>
|
||||
<enum 33 error_tx_invalid_uplink_tlv>
|
||||
<enum 34 error_txfd_txcck_illegal_tx_rate_error>
|
||||
<enum 35 error_txfd_txcck_underrun_error>
|
||||
<enum 36 error_txfd_mpi_req_grant_error>
|
||||
<enum 37 error_txfd_control_tlv_fifo_ovfl_error>
|
||||
<enum 38 error_txfd_tlv_fifo_overflow_error>
|
||||
<enum 39 error_txfd_data_fifo_underflow_error>
|
||||
<enum 40 error_txfd_data_fifo_overflow_error>
|
||||
<enum 41 error_txfd_service_fifo_overflow_error>
|
||||
<enum 42 error_txfd_he_sigb_fifo_overflow_error>
|
||||
<enum 43 error_txfd_spurious_data_fifo_error>
|
||||
<enum 44 error_txfd_he_siga_fifo_ovfl_error>
|
||||
<enum 45 error_txfd_unknown_tlv_error>
|
||||
<enum 46 error_txfd_mac_response_ordering_error>
|
||||
<enum 47 error_txfd_unexpected_mac_pkt_end_error>
|
||||
<enum 48 error_txfd_tlv_fifo_rd_hang_error>All FIFO read
|
||||
hang errors use this value.
|
||||
<enum 49 error_txfd_tlv_fifo_no_rd_error>All FIFO no read
|
||||
errors use this value.
|
||||
<enum 50 error_txfd_ordering_fifo_no_rd_error>
|
||||
<enum 51 error_txfd_illegal_cf_tlv_error>
|
||||
<enum 52 error_txfd_user_ru_hang_error>
|
||||
<enum 53 error_txfd_stream_ru_hang_error>
|
||||
<enum 54 error_txfd_num_pad_bits_error>
|
||||
<enum 55 error_txfd_phy_abort_ack_wd_to_error>
|
||||
<enum 56 error_txfd_pre_pkt_isr_not_done_before_phy_desc_error>
|
||||
|
||||
<enum 57 error_txfd_bf_weights_not_ready_error>
|
||||
<enum 58 error_txfd_req_timer_breach_error>
|
||||
<enum 59 error_txfd_wd_to_error>
|
||||
<enum 60 error_txfd_legacy_bf_weights_not_ready_error>
|
||||
<enum 61 error_txfd_axi_slave_to_error>
|
||||
<enum 62 error_txfd_hw_acc_error>
|
||||
<enum 63 error_txfd_txb_req_fifo_underrun_error>
|
||||
<enum 64 error_txfd_unknown_ru_alloc_error>
|
||||
<enum 65 error_txfd_more_user_desc_per_user_tlvs_error>
|
||||
<enum 66 error_txfd_ldpc_param_calc_to_error>
|
||||
<enum 69 error_txfd_cbf_start_before_expect_cbf_clear_error>
|
||||
|
||||
<enum 70 error_txfd_out_of_range_cbf_user_id_error>
|
||||
<enum 71 error_txfd_less_cbf_data_error>
|
||||
<enum 72 error_txfd_more_cbf_data_error>
|
||||
<enum 73 error_txfd_cbf_done_not_received_error>
|
||||
<enum 74 error_txfd_mpi_cbf_valid_to_error>
|
||||
<enum 75 error_txfd_cbf_start_missing_error>
|
||||
<enum 76 error_txfd_mimo_ctrl_error>
|
||||
<enum 77 error_txfd_cbf_buffer_ovfl_error>
|
||||
<enum 78 error_txfd_dma0_hang_error>
|
||||
<enum 79 error_txfd_dma1_hang_error>
|
||||
<enum 80 error_txfd_b2b_cbf_start_error>
|
||||
<enum 81 error_txfd_b2b_cbf_done_error>
|
||||
<enum 82 error_txfd_unsaved_cv_error>
|
||||
<enum 83 error_txfd_wt_mem_wr_conflict_error>
|
||||
<enum 84 error_txfd_wt_mem_rd_conflict_error>
|
||||
<enum 85 error_txfd_qre_intf_to_error>
|
||||
<enum 86 error_txfd_qre_txbf_stomp_rx_error>
|
||||
<enum 87 error_txfd_qre_rx_stomp_txbf_error>
|
||||
<enum 88 error_txfd_precoding_start_before_bf_param_clr_error>
|
||||
|
||||
<enum 89 error_txfd_tone_map_lut_rd_conflict_error>
|
||||
<enum 90 error_txfd_precoding_fifo_ovfl_error>
|
||||
<enum 91 error_txfd_precoding_fifo_udfl_error>
|
||||
<enum 92 error_txfd_txbf_axi_slave_to_error>
|
||||
<enum 93 error_txfd_less_prefetch_tlvs_error>
|
||||
<enum 94 error_txfd_more_prefetch_tlvs_error>
|
||||
<enum 95 error_txfd_prefetch_fifo_ovfl_error>
|
||||
<enum 96 error_txfd_prefetch_fifo_udfl_error>
|
||||
<enum 97 error_txfd_precoding_error>
|
||||
<enum 98 error_txfd_cv_ctrl_state_to_error>
|
||||
<enum 99 error_txfd_txbfp_qre_tone_udfl_error>
|
||||
<enum 100 error_txfd_less_bf_param_per_user_tlvs_error>
|
||||
<enum 101 error_txfd_more_bf_param_per_user_tlvs_error>
|
||||
<enum 102 error_txfd_bf_param_common_unexpected_error>
|
||||
<enum 103 error_txfd_less_expect_cbf_per_user_tlvs_error>
|
||||
|
||||
<enum 104 error_txfd_more_expect_cbf_per_user_tlvs_error>
|
||||
|
||||
<enum 105 error_txfd_precoding_stg1_stg2_wait_to_error>
|
||||
<enum 106 error_txfd_expect_cbf_per_user_before_common_error>
|
||||
|
||||
<enum 107 error_txfd_prefetch_per_user_before_common_error>
|
||||
|
||||
<enum 108 error_txfd_bf_param_per_user_before_common_error>
|
||||
|
||||
<enum 109 error_txfd_ndp_cbf_bw_mismatch_error>
|
||||
<enum 110 error_txtd_tx_pre_desc_error>
|
||||
<enum 111 error_txtd_tx_desc_error>
|
||||
<enum 112 error_txtd_start_error>
|
||||
<enum 113 error_txtd_sym_error>
|
||||
<enum 114 error_txtd_multi_sym_error>
|
||||
<enum 115 error_txtd_pre_data_error>
|
||||
<enum 116 error_txtd_pkt_data_error>
|
||||
<enum 117 error_txtd_pkt_end_error>
|
||||
<enum 118 error_txtd_tx_frame_unexp>
|
||||
<enum 119 error_txtd_start_unexp>
|
||||
<enum 120 error_txtd_fft_error_1>
|
||||
<enum 121 error_txtd_fft_error_2>
|
||||
<enum 122 error_txtd_uld_sym_cp_len_zero>
|
||||
<enum 123 error_txtd_start_done>
|
||||
<enum 124 error_txtd_start_nonidle>
|
||||
<enum 125 error_txtd_tx_abort_nonidle>
|
||||
<enum 126 error_txtd_tx_abort_done>
|
||||
<enum 127 error_txtd_tx_abort_idle>
|
||||
<enum 128 error_txtd_cck_sample_overflow>
|
||||
<enum 129 error_txtd_cck_timeout>
|
||||
<enum 130 error_txtd_ofdm_sym_mismatch>
|
||||
<enum 131 error_txtd_tx_vld_unalign_error>
|
||||
<enum 132 error_txtd_fft_cdc_fifo>This is the merged Rx/Tx
|
||||
CDC FIFO empty/full error code
|
||||
<enum 133 error_mac_tb_ppdu_abort>All 'error_txtd_chn' codes
|
||||
use this value as well.
|
||||
<enum 136 error_abort_req_from_macrx_enum_05>This code is
|
||||
used to abort the Tx when MAC Rx issues an abort request
|
||||
with code 05 "macrx_abort_too_much_bad_data."
|
||||
<enum 137 error_tx_extra_sym_mismatch>
|
||||
<enum 138 error_tx_vht_length_not_multiple_of_3>
|
||||
<enum 139 error_tx_11b_rate_illegal>
|
||||
<enum 140 error_tx_ht_rate_illegal>
|
||||
<enum 141 error_tx_vht_rate_illegal>
|
||||
<enum 142 error_mac_rf_only_abort>
|
||||
<enum 255 error_tx_invalid_error_code>
|
||||
*/
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description USER_NUMBER
|
||||
|
||||
For some errors, the user for which this error was detected
|
||||
can be indicated in this field.
|
||||
<legal 0-36>
|
||||
*/
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000
|
||||
|
||||
|
||||
|
||||
#endif // PHYTX_ABORT_REQUEST_INFO
|
||||
89
hw/qcn6432/phytx_ppdu_header_info_request.h
Archivo normal
89
hw/qcn6432/phytx_ppdu_header_info_request.h
Archivo normal
@@ -0,0 +1,89 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
|
||||
#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
|
||||
|
||||
#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
|
||||
|
||||
|
||||
struct phytx_ppdu_header_info_request {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t request_type : 5, // [4:0]
|
||||
reserved : 11; // [15:5]
|
||||
uint16_t tlv32_padding : 16; // [15:0]
|
||||
#else
|
||||
uint16_t reserved : 11, // [15:5]
|
||||
request_type : 5; // [4:0]
|
||||
uint16_t tlv32_padding : 16; // [15:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description REQUEST_TYPE
|
||||
|
||||
Reason for the request by PHY
|
||||
<enum 0 request_L_SIG_B>
|
||||
<enum 1 request_L_SIG_A>
|
||||
<enum 2 request_USER_DESC>
|
||||
<enum 3 request_HT_SIG>
|
||||
<enum 4 request_VHT_SIG_A>
|
||||
<enum 5 request_VHT_SIG_B >
|
||||
<enum 6 request_TX_SERVICE>
|
||||
<enum 7 request_HE_SIG_A>
|
||||
<enum 8 request_HE_SIG_B>
|
||||
<enum 9 request_U_SIG>
|
||||
<enum 10 request_EHT_SIG>
|
||||
|
||||
<legal 0-10>
|
||||
*/
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f
|
||||
|
||||
|
||||
/* Description RESERVED
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0
|
||||
|
||||
|
||||
/* Description TLV32_PADDING
|
||||
|
||||
Automatic WORD padding inserted while converting TLV16 to
|
||||
TLV32 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff
|
||||
|
||||
|
||||
|
||||
#endif // PHYTX_PPDU_HEADER_INFO_REQUEST
|
||||
993
hw/qcn6432/receive_rssi_info.h
Archivo normal
993
hw/qcn6432/receive_rssi_info.h
Archivo normal
@@ -0,0 +1,993 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RECEIVE_RSSI_INFO_H_
|
||||
#define _RECEIVE_RSSI_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
|
||||
|
||||
|
||||
struct receive_rssi_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rssi_pri20_chain0 : 8, // [7:0]
|
||||
rssi_ext20_chain0 : 8, // [15:8]
|
||||
rssi_ext40_low20_chain0 : 8, // [23:16]
|
||||
rssi_ext40_high20_chain0 : 8; // [31:24]
|
||||
uint32_t rssi_ext80_low20_chain0 : 8, // [7:0]
|
||||
rssi_ext80_low_high20_chain0 : 8, // [15:8]
|
||||
rssi_ext80_high_low20_chain0 : 8, // [23:16]
|
||||
rssi_ext80_high20_chain0 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_0_chain0 : 8, // [7:0]
|
||||
rssi_ext160_1_chain0 : 8, // [15:8]
|
||||
rssi_ext160_2_chain0 : 8, // [23:16]
|
||||
rssi_ext160_3_chain0 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_4_chain0 : 8, // [7:0]
|
||||
rssi_ext160_5_chain0 : 8, // [15:8]
|
||||
rssi_ext160_6_chain0 : 8, // [23:16]
|
||||
rssi_ext160_7_chain0 : 8; // [31:24]
|
||||
uint32_t rssi_pri20_chain1 : 8, // [7:0]
|
||||
rssi_ext20_chain1 : 8, // [15:8]
|
||||
rssi_ext40_low20_chain1 : 8, // [23:16]
|
||||
rssi_ext40_high20_chain1 : 8; // [31:24]
|
||||
uint32_t rssi_ext80_low20_chain1 : 8, // [7:0]
|
||||
rssi_ext80_low_high20_chain1 : 8, // [15:8]
|
||||
rssi_ext80_high_low20_chain1 : 8, // [23:16]
|
||||
rssi_ext80_high20_chain1 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_0_chain1 : 8, // [7:0]
|
||||
rssi_ext160_1_chain1 : 8, // [15:8]
|
||||
rssi_ext160_2_chain1 : 8, // [23:16]
|
||||
rssi_ext160_3_chain1 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_4_chain1 : 8, // [7:0]
|
||||
rssi_ext160_5_chain1 : 8, // [15:8]
|
||||
rssi_ext160_6_chain1 : 8, // [23:16]
|
||||
rssi_ext160_7_chain1 : 8; // [31:24]
|
||||
uint32_t rssi_pri20_chain2 : 8, // [7:0]
|
||||
rssi_ext20_chain2 : 8, // [15:8]
|
||||
rssi_ext40_low20_chain2 : 8, // [23:16]
|
||||
rssi_ext40_high20_chain2 : 8; // [31:24]
|
||||
uint32_t rssi_ext80_low20_chain2 : 8, // [7:0]
|
||||
rssi_ext80_low_high20_chain2 : 8, // [15:8]
|
||||
rssi_ext80_high_low20_chain2 : 8, // [23:16]
|
||||
rssi_ext80_high20_chain2 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_0_chain2 : 8, // [7:0]
|
||||
rssi_ext160_1_chain2 : 8, // [15:8]
|
||||
rssi_ext160_2_chain2 : 8, // [23:16]
|
||||
rssi_ext160_3_chain2 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_4_chain2 : 8, // [7:0]
|
||||
rssi_ext160_5_chain2 : 8, // [15:8]
|
||||
rssi_ext160_6_chain2 : 8, // [23:16]
|
||||
rssi_ext160_7_chain2 : 8; // [31:24]
|
||||
uint32_t rssi_pri20_chain3 : 8, // [7:0]
|
||||
rssi_ext20_chain3 : 8, // [15:8]
|
||||
rssi_ext40_low20_chain3 : 8, // [23:16]
|
||||
rssi_ext40_high20_chain3 : 8; // [31:24]
|
||||
uint32_t rssi_ext80_low20_chain3 : 8, // [7:0]
|
||||
rssi_ext80_low_high20_chain3 : 8, // [15:8]
|
||||
rssi_ext80_high_low20_chain3 : 8, // [23:16]
|
||||
rssi_ext80_high20_chain3 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_0_chain3 : 8, // [7:0]
|
||||
rssi_ext160_1_chain3 : 8, // [15:8]
|
||||
rssi_ext160_2_chain3 : 8, // [23:16]
|
||||
rssi_ext160_3_chain3 : 8; // [31:24]
|
||||
uint32_t rssi_ext160_4_chain3 : 8, // [7:0]
|
||||
rssi_ext160_5_chain3 : 8, // [15:8]
|
||||
rssi_ext160_6_chain3 : 8, // [23:16]
|
||||
rssi_ext160_7_chain3 : 8; // [31:24]
|
||||
#else
|
||||
uint32_t rssi_ext40_high20_chain0 : 8, // [31:24]
|
||||
rssi_ext40_low20_chain0 : 8, // [23:16]
|
||||
rssi_ext20_chain0 : 8, // [15:8]
|
||||
rssi_pri20_chain0 : 8; // [7:0]
|
||||
uint32_t rssi_ext80_high20_chain0 : 8, // [31:24]
|
||||
rssi_ext80_high_low20_chain0 : 8, // [23:16]
|
||||
rssi_ext80_low_high20_chain0 : 8, // [15:8]
|
||||
rssi_ext80_low20_chain0 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_3_chain0 : 8, // [31:24]
|
||||
rssi_ext160_2_chain0 : 8, // [23:16]
|
||||
rssi_ext160_1_chain0 : 8, // [15:8]
|
||||
rssi_ext160_0_chain0 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_7_chain0 : 8, // [31:24]
|
||||
rssi_ext160_6_chain0 : 8, // [23:16]
|
||||
rssi_ext160_5_chain0 : 8, // [15:8]
|
||||
rssi_ext160_4_chain0 : 8; // [7:0]
|
||||
uint32_t rssi_ext40_high20_chain1 : 8, // [31:24]
|
||||
rssi_ext40_low20_chain1 : 8, // [23:16]
|
||||
rssi_ext20_chain1 : 8, // [15:8]
|
||||
rssi_pri20_chain1 : 8; // [7:0]
|
||||
uint32_t rssi_ext80_high20_chain1 : 8, // [31:24]
|
||||
rssi_ext80_high_low20_chain1 : 8, // [23:16]
|
||||
rssi_ext80_low_high20_chain1 : 8, // [15:8]
|
||||
rssi_ext80_low20_chain1 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_3_chain1 : 8, // [31:24]
|
||||
rssi_ext160_2_chain1 : 8, // [23:16]
|
||||
rssi_ext160_1_chain1 : 8, // [15:8]
|
||||
rssi_ext160_0_chain1 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_7_chain1 : 8, // [31:24]
|
||||
rssi_ext160_6_chain1 : 8, // [23:16]
|
||||
rssi_ext160_5_chain1 : 8, // [15:8]
|
||||
rssi_ext160_4_chain1 : 8; // [7:0]
|
||||
uint32_t rssi_ext40_high20_chain2 : 8, // [31:24]
|
||||
rssi_ext40_low20_chain2 : 8, // [23:16]
|
||||
rssi_ext20_chain2 : 8, // [15:8]
|
||||
rssi_pri20_chain2 : 8; // [7:0]
|
||||
uint32_t rssi_ext80_high20_chain2 : 8, // [31:24]
|
||||
rssi_ext80_high_low20_chain2 : 8, // [23:16]
|
||||
rssi_ext80_low_high20_chain2 : 8, // [15:8]
|
||||
rssi_ext80_low20_chain2 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_3_chain2 : 8, // [31:24]
|
||||
rssi_ext160_2_chain2 : 8, // [23:16]
|
||||
rssi_ext160_1_chain2 : 8, // [15:8]
|
||||
rssi_ext160_0_chain2 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_7_chain2 : 8, // [31:24]
|
||||
rssi_ext160_6_chain2 : 8, // [23:16]
|
||||
rssi_ext160_5_chain2 : 8, // [15:8]
|
||||
rssi_ext160_4_chain2 : 8; // [7:0]
|
||||
uint32_t rssi_ext40_high20_chain3 : 8, // [31:24]
|
||||
rssi_ext40_low20_chain3 : 8, // [23:16]
|
||||
rssi_ext20_chain3 : 8, // [15:8]
|
||||
rssi_pri20_chain3 : 8; // [7:0]
|
||||
uint32_t rssi_ext80_high20_chain3 : 8, // [31:24]
|
||||
rssi_ext80_high_low20_chain3 : 8, // [23:16]
|
||||
rssi_ext80_low_high20_chain3 : 8, // [15:8]
|
||||
rssi_ext80_low20_chain3 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_3_chain3 : 8, // [31:24]
|
||||
rssi_ext160_2_chain3 : 8, // [23:16]
|
||||
rssi_ext160_1_chain3 : 8, // [15:8]
|
||||
rssi_ext160_0_chain3 : 8; // [7:0]
|
||||
uint32_t rssi_ext160_7_chain3 : 8, // [31:24]
|
||||
rssi_ext160_6_chain3 : 8, // [23:16]
|
||||
rssi_ext160_5_chain3 : 8, // [15:8]
|
||||
rssi_ext160_4_chain3 : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RSSI_PRI20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_LOW20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_HIGH20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 80, low-high 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 80, high-low 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH20_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_0_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_1_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_2_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_3_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_4_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_5_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_6_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_7_CHAIN0
|
||||
|
||||
RSSI of RX PPDU on chain 0 of extension 160, highest 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_PRI20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_LOW20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_HIGH20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 80, low-high 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 80, high-low 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH20_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_0_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_1_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_2_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_3_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_4_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_5_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_6_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_7_CHAIN1
|
||||
|
||||
RSSI of RX PPDU on chain 1 of extension 160, highest 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_PRI20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_LOW20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_HIGH20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 80, low-high 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 80, high-low 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH20_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_0_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_1_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_2_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_3_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_4_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_5_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_6_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_7_CHAIN2
|
||||
|
||||
RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_PRI20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_LOW20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT40_HIGH20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth.
|
||||
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 80, low-high 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 80, high-low 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT80_HIGH20_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_0_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_1_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_2_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_3_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_4_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_5_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_6_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz
|
||||
bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description RSSI_EXT160_7_CHAIN3
|
||||
|
||||
RSSI of RX PPDU on chain 3 of extension 160, highest 20
|
||||
MHz bandwidth.
|
||||
Value of 0x80 indicates invalid.
|
||||
*/
|
||||
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31
|
||||
#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
#endif // RECEIVE_RSSI_INFO
|
||||
704
hw/qcn6432/receive_user_info.h
Archivo normal
704
hw/qcn6432/receive_user_info.h
Archivo normal
@@ -0,0 +1,704 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RECEIVE_USER_INFO_H_
|
||||
#define _RECEIVE_USER_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
|
||||
|
||||
|
||||
struct receive_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t phy_ppdu_id : 16, // [15:0]
|
||||
user_rssi : 8, // [23:16]
|
||||
pkt_type : 4, // [27:24]
|
||||
stbc : 1, // [28:28]
|
||||
reception_type : 3; // [31:29]
|
||||
uint32_t rate_mcs : 4, // [3:0]
|
||||
sgi : 2, // [5:4]
|
||||
he_ranging_ndp : 1, // [6:6]
|
||||
reserved_1a : 1, // [7:7]
|
||||
mimo_ss_bitmap : 8, // [15:8]
|
||||
receive_bandwidth : 3, // [18:16]
|
||||
reserved_1b : 5, // [23:19]
|
||||
dl_ofdma_user_index : 8; // [31:24]
|
||||
uint32_t dl_ofdma_content_channel : 1, // [0:0]
|
||||
reserved_2a : 7, // [7:1]
|
||||
nss : 3, // [10:8]
|
||||
stream_offset : 3, // [13:11]
|
||||
sta_dcm : 1, // [14:14]
|
||||
ldpc : 1, // [15:15]
|
||||
ru_type_80_0 : 4, // [19:16]
|
||||
ru_type_80_1 : 4, // [23:20]
|
||||
ru_type_80_2 : 4, // [27:24]
|
||||
ru_type_80_3 : 4; // [31:28]
|
||||
uint32_t ru_start_index_80_0 : 6, // [5:0]
|
||||
reserved_3a : 2, // [7:6]
|
||||
ru_start_index_80_1 : 6, // [13:8]
|
||||
reserved_3b : 2, // [15:14]
|
||||
ru_start_index_80_2 : 6, // [21:16]
|
||||
reserved_3c : 2, // [23:22]
|
||||
ru_start_index_80_3 : 6, // [29:24]
|
||||
reserved_3d : 2; // [31:30]
|
||||
uint32_t user_fd_rssi_seg0 : 32; // [31:0]
|
||||
uint32_t user_fd_rssi_seg1 : 32; // [31:0]
|
||||
uint32_t user_fd_rssi_seg2 : 32; // [31:0]
|
||||
uint32_t user_fd_rssi_seg3 : 32; // [31:0]
|
||||
#else
|
||||
uint32_t reception_type : 3, // [31:29]
|
||||
stbc : 1, // [28:28]
|
||||
pkt_type : 4, // [27:24]
|
||||
user_rssi : 8, // [23:16]
|
||||
phy_ppdu_id : 16; // [15:0]
|
||||
uint32_t dl_ofdma_user_index : 8, // [31:24]
|
||||
reserved_1b : 5, // [23:19]
|
||||
receive_bandwidth : 3, // [18:16]
|
||||
mimo_ss_bitmap : 8, // [15:8]
|
||||
reserved_1a : 1, // [7:7]
|
||||
he_ranging_ndp : 1, // [6:6]
|
||||
sgi : 2, // [5:4]
|
||||
rate_mcs : 4; // [3:0]
|
||||
uint32_t ru_type_80_3 : 4, // [31:28]
|
||||
ru_type_80_2 : 4, // [27:24]
|
||||
ru_type_80_1 : 4, // [23:20]
|
||||
ru_type_80_0 : 4, // [19:16]
|
||||
ldpc : 1, // [15:15]
|
||||
sta_dcm : 1, // [14:14]
|
||||
stream_offset : 3, // [13:11]
|
||||
nss : 3, // [10:8]
|
||||
reserved_2a : 7, // [7:1]
|
||||
dl_ofdma_content_channel : 1; // [0:0]
|
||||
uint32_t reserved_3d : 2, // [31:30]
|
||||
ru_start_index_80_3 : 6, // [29:24]
|
||||
reserved_3c : 2, // [23:22]
|
||||
ru_start_index_80_2 : 6, // [21:16]
|
||||
reserved_3b : 2, // [15:14]
|
||||
ru_start_index_80_1 : 6, // [13:8]
|
||||
reserved_3a : 2, // [7:6]
|
||||
ru_start_index_80_0 : 6; // [5:0]
|
||||
uint32_t user_fd_rssi_seg0 : 32; // [31:0]
|
||||
uint32_t user_fd_rssi_seg1 : 32; // [31:0]
|
||||
uint32_t user_fd_rssi_seg2 : 32; // [31:0]
|
||||
uint32_t user_fd_rssi_seg3 : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description PHY_PPDU_ID
|
||||
|
||||
A ppdu counter value that PHY increments for every PPDU
|
||||
received. The counter value wraps around
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15
|
||||
#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description USER_RSSI
|
||||
|
||||
RSSI for this user
|
||||
Frequency domain RSSI measurement for this user. Based on
|
||||
the channel estimate.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_LSB 16
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_MSB 23
|
||||
#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description PKT_TYPE
|
||||
|
||||
Packet type:
|
||||
|
||||
<enum 0 dot11a>802.11a PPDU type
|
||||
<enum 1 dot11b>802.11b PPDU type
|
||||
<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
|
||||
<enum 3 dot11ac>802.11ac PPDU type
|
||||
<enum 4 dot11ax>802.11ax PPDU type
|
||||
<enum 5 dot11ba>802.11ba (WUR) PPDU type
|
||||
<enum 6 dot11be>802.11be PPDU type
|
||||
<enum 7 dot11az>802.11az (ranging) PPDU type
|
||||
<enum 8 dot11n_gf>802.11n Green Field PPDU type (unsupported
|
||||
& aborted)
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27
|
||||
#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000
|
||||
|
||||
|
||||
/* Description STBC
|
||||
|
||||
When set, use STBC transmission rates
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_STBC_LSB 28
|
||||
#define RECEIVE_USER_INFO_STBC_MSB 28
|
||||
#define RECEIVE_USER_INFO_STBC_MASK 0x10000000
|
||||
|
||||
|
||||
/* Description RECEPTION_TYPE
|
||||
|
||||
Indicates what type of reception this is.
|
||||
<enum 0 reception_type_SU > Basic SU reception (not
|
||||
part of OFDMA or MU-MIMO)
|
||||
<enum 1 reception_type_MU_MIMO > This is related to
|
||||
DL type of reception
|
||||
<enum 2 reception_type_MU_OFDMA > This is related to
|
||||
DL type of reception
|
||||
<enum 3 reception_type_MU_OFDMA_MIMO > This is related
|
||||
to DL type of reception
|
||||
<enum 4 reception_type_UL_MU_MIMO > This is related
|
||||
to UL type of reception
|
||||
<enum 5 reception_type_UL_MU_OFDMA > This is related
|
||||
to UL type of reception
|
||||
<enum 6 reception_type_UL_MU_OFDMA_MIMO > This is related
|
||||
to UL type of reception
|
||||
|
||||
<legal 0-6>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31
|
||||
#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000
|
||||
|
||||
|
||||
/* Description RATE_MCS
|
||||
|
||||
For details, refer to MCS_TYPE description
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_LSB 0
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_MSB 3
|
||||
#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f
|
||||
|
||||
|
||||
/* Description SGI
|
||||
|
||||
Field only valid when pkt type is HT, VHT or HE.
|
||||
|
||||
<enum 0 gi_0_8_us > Legacy normal GI. Can also be used
|
||||
for HE
|
||||
<enum 1 gi_0_4_us > Legacy short GI. Can also be used
|
||||
for HE
|
||||
<enum 2 gi_1_6_us > HE related GI
|
||||
<enum 3 gi_3_2_us > HE related GI
|
||||
<legal 0 - 3>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_SGI_LSB 4
|
||||
#define RECEIVE_USER_INFO_SGI_MSB 5
|
||||
#define RECEIVE_USER_INFO_SGI_MASK 0x00000030
|
||||
|
||||
|
||||
/* Description HE_RANGING_NDP
|
||||
|
||||
Set to 1 for expected HE TB ranging NDP Rx in response to
|
||||
sounding/secure sounding ranging Trigger Tx
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_HE_RANGING_NDP_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_HE_RANGING_NDP_LSB 6
|
||||
#define RECEIVE_USER_INFO_HE_RANGING_NDP_MSB 6
|
||||
#define RECEIVE_USER_INFO_HE_RANGING_NDP_MASK 0x00000040
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080
|
||||
|
||||
|
||||
/* Description MIMO_SS_BITMAP
|
||||
|
||||
Bitmap, with each bit indicating if the related spatial
|
||||
stream is used for this STA
|
||||
LSB related to SS 0
|
||||
|
||||
0: spatial stream not used for this reception
|
||||
1: spatial stream used for this reception
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15
|
||||
#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description RECEIVE_BANDWIDTH
|
||||
|
||||
Full receive Bandwidth
|
||||
|
||||
<enum 0 20_mhz>20 Mhz BW
|
||||
<enum 1 40_mhz>40 Mhz BW
|
||||
<enum 2 80_mhz>80 Mhz BW
|
||||
<enum 3 160_mhz>160 Mhz BW
|
||||
<enum 4 320_mhz>320 Mhz BW
|
||||
<enum 5 240_mhz>240 Mhz BW
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18
|
||||
#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000
|
||||
|
||||
|
||||
/* Description RESERVED_1B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23
|
||||
#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000
|
||||
|
||||
|
||||
/* Description DL_OFDMA_USER_INDEX
|
||||
|
||||
Field only valid in the of DL MU OFDMA reception
|
||||
|
||||
The user number within the RU_allocation.
|
||||
|
||||
This is needed for SW to determine the exact RU position
|
||||
within the reception.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description DL_OFDMA_CONTENT_CHANNEL
|
||||
|
||||
Field only valid in the of DL MU OFDMA/MIMO reception
|
||||
|
||||
In case of DL MU reception, this field indicates the content
|
||||
channel number where PHY found the RU information for this
|
||||
user
|
||||
|
||||
This is needed for SW to determine the exact RU position
|
||||
within the reception.
|
||||
|
||||
<enum 0 content_channel_1>
|
||||
<enum 1 content_channel_2>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0
|
||||
#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
|
||||
|
||||
|
||||
/* Description RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe
|
||||
|
||||
|
||||
/* Description NSS
|
||||
|
||||
Field only valid in case of Uplink_receive_type == mimo_only
|
||||
OR ofdma_mimo
|
||||
|
||||
Number of Spatial Streams occupied by the User
|
||||
|
||||
<enum 0 1_spatial_stream>Single spatial stream
|
||||
<enum 1 2_spatial_streams>2 spatial streams
|
||||
<enum 2 3_spatial_streams>3 spatial streams
|
||||
<enum 3 4_spatial_streams>4 spatial streams
|
||||
<enum 4 5_spatial_streams>5 spatial streams
|
||||
<enum 5 6_spatial_streams>6 spatial streams
|
||||
<enum 6 7_spatial_streams>7 spatial streams
|
||||
<enum 7 8_spatial_streams>8 spatial streams
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_NSS_LSB 8
|
||||
#define RECEIVE_USER_INFO_NSS_MSB 10
|
||||
#define RECEIVE_USER_INFO_NSS_MASK 0x00000700
|
||||
|
||||
|
||||
/* Description STREAM_OFFSET
|
||||
|
||||
Field only valid in case of Uplink_receive_type == mimo_only
|
||||
OR ofdma_mimo
|
||||
|
||||
Stream Offset from which the User occupies the Streams
|
||||
|
||||
Note MAC:
|
||||
directly from pdg_fes_setup, based on BW
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13
|
||||
#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800
|
||||
|
||||
|
||||
/* Description STA_DCM
|
||||
|
||||
Indicates whether dual sub-carrier modulation is applied
|
||||
|
||||
0: No DCM
|
||||
1:DCM
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_STA_DCM_LSB 14
|
||||
#define RECEIVE_USER_INFO_STA_DCM_MSB 14
|
||||
#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000
|
||||
|
||||
|
||||
/* Description LDPC
|
||||
|
||||
When set, use LDPC transmission rates were used.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_LDPC_LSB 15
|
||||
#define RECEIVE_USER_INFO_LDPC_MSB 15
|
||||
#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000
|
||||
|
||||
|
||||
/* Description RU_TYPE_80_0
|
||||
|
||||
Indicates the size of the RU in the first 80 MHz sub-band
|
||||
|
||||
<enum 0 RU_26_per80>
|
||||
<enum 1 RU_52_per80>
|
||||
<enum 2 RU_78_per80>
|
||||
<enum 3 RU_106_per80>
|
||||
<enum 4 RU_132_per80>
|
||||
<enum 5 RU_242_per80>
|
||||
<enum 6 RU_484_per80>
|
||||
<enum 7 RU_726_per80>
|
||||
<enum 8 RU_996_per80>
|
||||
<enum 9 RU_996x2>
|
||||
<enum 10 RU_996x3>
|
||||
<enum 11 RU_996x4>
|
||||
<enum 12 RU_rsvd0> DO NOT USE
|
||||
<enum 13 RU_rsvd1> DO NOT USE
|
||||
<enum 14 RU_rsvd2> DO NOT USE
|
||||
<enum 15 RU_NONE> No RUs in this 80 MHz
|
||||
<legal 0-15>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description RU_TYPE_80_1
|
||||
|
||||
Indicates the size of the RU in the second 80 MHz sub-band
|
||||
|
||||
<enum 0 RU_26_per80>
|
||||
<enum 1 RU_52_per80>
|
||||
<enum 2 RU_78_per80>
|
||||
<enum 3 RU_106_per80>
|
||||
<enum 4 RU_132_per80>
|
||||
<enum 5 RU_242_per80>
|
||||
<enum 6 RU_484_per80>
|
||||
<enum 7 RU_726_per80>
|
||||
<enum 8 RU_996_per80>
|
||||
<enum 9 RU_996x2>
|
||||
<enum 10 RU_996x3>
|
||||
<enum 11 RU_996x4>
|
||||
<enum 12 RU_rsvd0> DO NOT USE
|
||||
<enum 13 RU_rsvd1> DO NOT USE
|
||||
<enum 14 RU_rsvd2> DO NOT USE
|
||||
<enum 15 RU_NONE> No RUs in this 80 MHz
|
||||
<legal 0-15>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000
|
||||
|
||||
|
||||
/* Description RU_TYPE_80_2
|
||||
|
||||
Indicates the size of the RU in the third 80 MHz sub-band
|
||||
|
||||
<enum 0 RU_26_per80>
|
||||
<enum 1 RU_52_per80>
|
||||
<enum 2 RU_78_per80>
|
||||
<enum 3 RU_106_per80>
|
||||
<enum 4 RU_132_per80>
|
||||
<enum 5 RU_242_per80>
|
||||
<enum 6 RU_484_per80>
|
||||
<enum 7 RU_726_per80>
|
||||
<enum 8 RU_996_per80>
|
||||
<enum 9 RU_996x2>
|
||||
<enum 10 RU_996x3>
|
||||
<enum 11 RU_996x4>
|
||||
<enum 12 RU_rsvd0> DO NOT USE
|
||||
<enum 13 RU_rsvd1> DO NOT USE
|
||||
<enum 14 RU_rsvd2> DO NOT USE
|
||||
<enum 15 RU_NONE> No RUs in this 80 MHz
|
||||
<legal 0-15>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000
|
||||
|
||||
|
||||
/* Description RU_TYPE_80_3
|
||||
|
||||
Indicates the size of the RU in the fourth 80 MHz sub-band
|
||||
|
||||
<enum 0 RU_26_per80>
|
||||
<enum 1 RU_52_per80>
|
||||
<enum 2 RU_78_per80>
|
||||
<enum 3 RU_106_per80>
|
||||
<enum 4 RU_132_per80>
|
||||
<enum 5 RU_242_per80>
|
||||
<enum 6 RU_484_per80>
|
||||
<enum 7 RU_726_per80>
|
||||
<enum 8 RU_996_per80>
|
||||
<enum 9 RU_996x2>
|
||||
<enum 10 RU_996x3>
|
||||
<enum 11 RU_996x4>
|
||||
<enum 12 RU_rsvd0> DO NOT USE
|
||||
<enum 13 RU_rsvd1> DO NOT USE
|
||||
<enum 14 RU_rsvd2> DO NOT USE
|
||||
<enum 15 RU_NONE> No RUs in this 80 MHz
|
||||
<legal 0-15>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31
|
||||
#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description RU_START_INDEX_80_0
|
||||
|
||||
RU index number to which User is assigned in the first 80
|
||||
MHz
|
||||
RU numbering is over the entire BW, starting from 0 and
|
||||
in increasing frequency order and not primary-secondary
|
||||
order
|
||||
<legal 0-36>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7
|
||||
#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0
|
||||
|
||||
|
||||
/* Description RU_START_INDEX_80_1
|
||||
|
||||
RU index number to which User is assigned in the second
|
||||
80 MHz
|
||||
RU numbering is over the entire BW, starting from 0 and
|
||||
in increasing frequency order and not primary-secondary
|
||||
order
|
||||
<legal 0-36>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00
|
||||
|
||||
|
||||
/* Description RESERVED_3B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15
|
||||
#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000
|
||||
|
||||
|
||||
/* Description RU_START_INDEX_80_2
|
||||
|
||||
RU index number to which User is assigned in the third 80
|
||||
MHz
|
||||
RU numbering is over the entire BW, starting from 0 and
|
||||
in increasing frequency order and not primary-secondary
|
||||
order
|
||||
<legal 0-36>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000
|
||||
|
||||
|
||||
/* Description RESERVED_3C
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23
|
||||
#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000
|
||||
|
||||
|
||||
/* Description RU_START_INDEX_80_3
|
||||
|
||||
RU index number to which User is assigned in the fourth
|
||||
80 MHz
|
||||
RU numbering is over the entire BW, starting from 0 and
|
||||
in increasing frequency order and not primary-secondary
|
||||
order
|
||||
<legal 0-36>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29
|
||||
#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000
|
||||
|
||||
|
||||
/* Description RESERVED_3D
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31
|
||||
#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000
|
||||
|
||||
|
||||
/* Description USER_FD_RSSI_SEG0
|
||||
|
||||
Frequency domain RSSI measurement for the lowest 80 MHz
|
||||
subband of this user, per spatial stream
|
||||
[7:0]: first spatial stream
|
||||
...
|
||||
[31:24]: fourth spatial stream
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description USER_FD_RSSI_SEG1
|
||||
|
||||
Frequency domain RSSI measurement for the second lowest
|
||||
80 MHz subband of this user, per spatial stream
|
||||
[7:0]: first spatial stream
|
||||
...
|
||||
[31:24]: fourth spatial stream
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description USER_FD_RSSI_SEG2
|
||||
|
||||
Frequency domain RSSI measurement for the third lowest 80
|
||||
MHz subband of this user, per spatial stream
|
||||
[7:0]: first spatial stream
|
||||
...
|
||||
[31:24]: fourth spatial stream
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description USER_FD_RSSI_SEG3
|
||||
|
||||
Frequency domain RSSI measurement for the highest 80 MHz
|
||||
subband of this user, per spatial stream
|
||||
[7:0]: first spatial stream
|
||||
...
|
||||
[31:24]: fourth spatial stream
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31
|
||||
#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff
|
||||
|
||||
|
||||
|
||||
#endif // RECEIVE_USER_INFO
|
||||
3075
hw/qcn6432/received_response_user_15_8.h
Archivo normal
3075
hw/qcn6432/received_response_user_15_8.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
3074
hw/qcn6432/received_response_user_23_16.h
Archivo normal
3074
hw/qcn6432/received_response_user_23_16.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
3077
hw/qcn6432/received_response_user_31_24.h
Archivo normal
3077
hw/qcn6432/received_response_user_31_24.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
1936
hw/qcn6432/received_response_user_36_32.h
Archivo normal
1936
hw/qcn6432/received_response_user_36_32.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
3076
hw/qcn6432/received_response_user_7_0.h
Archivo normal
3076
hw/qcn6432/received_response_user_7_0.h
Archivo normal
La diferencia del archivo ha sido suprimido porque es demasiado grande
Cargar Diff
458
hw/qcn6432/received_response_user_info.h
Archivo normal
458
hw/qcn6432/received_response_user_info.h
Archivo normal
@@ -0,0 +1,458 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
|
||||
#define _RECEIVED_RESPONSE_USER_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
|
||||
|
||||
|
||||
struct received_response_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t mpdu_fcs_pass_count : 12, // [11:0]
|
||||
mpdu_fcs_fail_count : 12, // [23:12]
|
||||
qosnull_frame_count : 4, // [27:24]
|
||||
reserved_0a : 3, // [30:28]
|
||||
user_info_valid : 1; // [31:31]
|
||||
uint32_t null_delimiter_count : 22, // [21:0]
|
||||
reserved_1a : 9, // [30:22]
|
||||
ht_control_valid : 1; // [31:31]
|
||||
uint32_t ht_control : 32; // [31:0]
|
||||
uint32_t qos_control_valid : 16, // [15:0]
|
||||
eosp : 16; // [31:16]
|
||||
uint32_t qos_control_15_8_tid_0 : 8, // [7:0]
|
||||
qos_control_15_8_tid_1 : 8, // [15:8]
|
||||
qos_control_15_8_tid_2 : 8, // [23:16]
|
||||
qos_control_15_8_tid_3 : 8; // [31:24]
|
||||
uint32_t qos_control_15_8_tid_4 : 8, // [7:0]
|
||||
qos_control_15_8_tid_5 : 8, // [15:8]
|
||||
qos_control_15_8_tid_6 : 8, // [23:16]
|
||||
qos_control_15_8_tid_7 : 8; // [31:24]
|
||||
uint32_t qos_control_15_8_tid_8 : 8, // [7:0]
|
||||
qos_control_15_8_tid_9 : 8, // [15:8]
|
||||
qos_control_15_8_tid_10 : 8, // [23:16]
|
||||
qos_control_15_8_tid_11 : 8; // [31:24]
|
||||
uint32_t qos_control_15_8_tid_12 : 8, // [7:0]
|
||||
qos_control_15_8_tid_13 : 8, // [15:8]
|
||||
qos_control_15_8_tid_14 : 8, // [23:16]
|
||||
qos_control_15_8_tid_15 : 8; // [31:24]
|
||||
#else
|
||||
uint32_t user_info_valid : 1, // [31:31]
|
||||
reserved_0a : 3, // [30:28]
|
||||
qosnull_frame_count : 4, // [27:24]
|
||||
mpdu_fcs_fail_count : 12, // [23:12]
|
||||
mpdu_fcs_pass_count : 12; // [11:0]
|
||||
uint32_t ht_control_valid : 1, // [31:31]
|
||||
reserved_1a : 9, // [30:22]
|
||||
null_delimiter_count : 22; // [21:0]
|
||||
uint32_t ht_control : 32; // [31:0]
|
||||
uint32_t eosp : 16, // [31:16]
|
||||
qos_control_valid : 16; // [15:0]
|
||||
uint32_t qos_control_15_8_tid_3 : 8, // [31:24]
|
||||
qos_control_15_8_tid_2 : 8, // [23:16]
|
||||
qos_control_15_8_tid_1 : 8, // [15:8]
|
||||
qos_control_15_8_tid_0 : 8; // [7:0]
|
||||
uint32_t qos_control_15_8_tid_7 : 8, // [31:24]
|
||||
qos_control_15_8_tid_6 : 8, // [23:16]
|
||||
qos_control_15_8_tid_5 : 8, // [15:8]
|
||||
qos_control_15_8_tid_4 : 8; // [7:0]
|
||||
uint32_t qos_control_15_8_tid_11 : 8, // [31:24]
|
||||
qos_control_15_8_tid_10 : 8, // [23:16]
|
||||
qos_control_15_8_tid_9 : 8, // [15:8]
|
||||
qos_control_15_8_tid_8 : 8; // [7:0]
|
||||
uint32_t qos_control_15_8_tid_15 : 8, // [31:24]
|
||||
qos_control_15_8_tid_14 : 8, // [23:16]
|
||||
qos_control_15_8_tid_13 : 8, // [15:8]
|
||||
qos_control_15_8_tid_12 : 8; // [7:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description MPDU_FCS_PASS_COUNT
|
||||
|
||||
The number of MPDUs received with correct FCS.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
|
||||
/* Description MPDU_FCS_FAIL_COUNT
|
||||
|
||||
The number of MPDUs received with wrong FCS.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
|
||||
/* Description QOSNULL_FRAME_COUNT
|
||||
|
||||
The number of QoSNULL frames received with correct FCS.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
|
||||
/* Description USER_INFO_VALID
|
||||
|
||||
When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains
|
||||
valid information.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
|
||||
/* Description NULL_DELIMITER_COUNT
|
||||
|
||||
The number of valid, properly formed NULL delimiters received
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
|
||||
/* Description HT_CONTROL_VALID
|
||||
|
||||
When set, indicates that the received MPDUs included an
|
||||
HT Control field
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
|
||||
/* Description HT_CONTROL
|
||||
|
||||
Field only valid if HT_Control_valid is set
|
||||
Received HT Control value
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_VALID
|
||||
|
||||
Each bit when set, indicates that the received MPDUs included
|
||||
that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*'
|
||||
field are valid.
|
||||
Bit 0: TID 0
|
||||
...
|
||||
Bit 15: TID 15
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description EOSP
|
||||
|
||||
Each bit only valid if the corresponding bit of QoS_Control_valid
|
||||
is set.
|
||||
|
||||
Received EOSP bit for each TID
|
||||
Bit 0: TID 0
|
||||
...
|
||||
Bit 15: TID 15
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_0
|
||||
|
||||
Field only valid if QoS_Control_valid[0] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_1
|
||||
|
||||
Field only valid if QoS_Control_valid[1] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 1
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_2
|
||||
|
||||
Field only valid if QoS_Control_valid[2] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 2
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_3
|
||||
|
||||
Field only valid if QoS_Control_valid[3] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 3
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_4
|
||||
|
||||
Field only valid if QoS_Control_valid[4] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 4
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_5
|
||||
|
||||
Field only valid if QoS_Control_valid[5] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 5
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_6
|
||||
|
||||
Field only valid if QoS_Control_valid[6] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 6
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_7
|
||||
|
||||
Field only valid if QoS_Control_valid[7] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 7
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_8
|
||||
|
||||
Field only valid if QoS_Control_valid[8] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 8
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_9
|
||||
|
||||
Field only valid if QoS_Control_valid[9] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 9
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_10
|
||||
|
||||
Field only valid if QoS_Control_valid[10] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 10
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_11
|
||||
|
||||
Field only valid if QoS_Control_valid[11] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 11
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_12
|
||||
|
||||
Field only valid if QoS_Control_valid[12] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 12
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_13
|
||||
|
||||
Field only valid if QoS_Control_valid[13] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 13
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_14
|
||||
|
||||
Field only valid if QoS_Control_valid[14] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 14
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_15_8_TID_15
|
||||
|
||||
Field only valid if QoS_Control_valid[15] is set.
|
||||
|
||||
Received bits [15:8] of QoS Control for TID 15
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
|
||||
|
||||
#endif // RECEIVED_RESPONSE_USER_INFO
|
||||
335
hw/qcn6432/received_trigger_info.h
Archivo normal
335
hw/qcn6432/received_trigger_info.h
Archivo normal
@@ -0,0 +1,335 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RECEIVED_TRIGGER_INFO_H_
|
||||
#define _RECEIVED_TRIGGER_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "received_trigger_info_details.h"
|
||||
#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6
|
||||
|
||||
#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3
|
||||
|
||||
|
||||
struct received_trigger_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct received_trigger_info_details received_trigger_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct received_trigger_info_details received_trigger_details;
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description RECEIVED_TRIGGER_DETAILS
|
||||
|
||||
Info related to the type of trigger (that potentially requires
|
||||
SIFS response) that was received
|
||||
*/
|
||||
|
||||
|
||||
/* Description TRIGGER_TYPE
|
||||
|
||||
This field indicates for what type of trigger has been received
|
||||
|
||||
|
||||
<enum 0 SCH_Qboost_trigger>
|
||||
<enum 1 SCH_PSPOLL_trigger>
|
||||
<enum 2 SCH_UAPSD_trigger>
|
||||
<enum 3 SCH_11ax_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 7 SCH_EHT_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 4 SCH_11ax_wildcard_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 5 SCH_11ax_unassoc_wildcard_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 6 SCH_11az_ranging_trigger> Field "AX_trigger_type"
|
||||
indicates the subtype of the received trigger
|
||||
|
||||
<legal 0-7>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f
|
||||
|
||||
|
||||
/* Description AX_TRIGGER_SOURCE
|
||||
|
||||
Field Only valid when Trigger_type is an 11ax related trigger
|
||||
|
||||
|
||||
<enum 0 11ax_trigger_frame>
|
||||
<enum 1 he_control_based_trigger>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010
|
||||
|
||||
|
||||
/* Description AX_TRIGGER_TYPE
|
||||
|
||||
Field Only valid when Trigger_type is an 11ax related trigger
|
||||
|
||||
|
||||
The 11AX trigger type/ trigger number:
|
||||
It identifies which trigger was received.
|
||||
<enum 0 ax_trigger_basic>
|
||||
<enum 1 ax_trigger_brpoll>
|
||||
<enum 2 ax_trigger_mu_bar>
|
||||
<enum 3 ax_trigger_mu_rts>
|
||||
<enum 4 ax_trigger_buffer_size>
|
||||
<enum 5 ax_trigger_gcr_mu_bar>
|
||||
<enum 6 ax_trigger_BQRP>
|
||||
<enum 7 ax_trigger_NDP_fb_report_poll>
|
||||
<enum 8 ax_tb_ranging_trigger> Indicates the reception of
|
||||
Ranging Trigger Frame of subvariant indicated by Ranging_Trigger_Subtype
|
||||
|
||||
<enum 9 ax_trigger_reserved_9>
|
||||
<enum 10 ax_trigger_reserved_10>
|
||||
<enum 11 ax_trigger_reserved_11>
|
||||
<enum 12 ax_trigger_reserved_12>
|
||||
<enum 13 ax_trigger_reserved_13>
|
||||
<enum 14 ax_trigger_reserved_14>
|
||||
<enum 15 ax_trigger_reserved_15>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0
|
||||
|
||||
|
||||
/* Description TRIGGER_SOURCE_STA_FULL_AID
|
||||
|
||||
The sta_full_aid of the sta/ap that generated the trigger.
|
||||
|
||||
Comes from the address_search_entry
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00
|
||||
|
||||
|
||||
/* Description FRAME_CONTROL_VALID
|
||||
|
||||
When set, the 'frame_control' field contains valid info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_VALID
|
||||
|
||||
When set, the 'QoS_control' field contains valid info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000
|
||||
|
||||
|
||||
/* Description HE_CONTROL_INFO_VALID
|
||||
|
||||
When set, the 'HE control' field contains valid info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000
|
||||
|
||||
|
||||
/* Description RANGING_TRIGGER_SUBTYPE
|
||||
|
||||
Field only valid if AX_Trigger_type = ax_tb_ranging_trigger
|
||||
|
||||
|
||||
Indicates the Trigger subtype for the current ranging TF
|
||||
|
||||
|
||||
<enum 0 TF_Poll>
|
||||
<enum 1 TF_Sound>
|
||||
<enum 2 TF_Secure_Sound>
|
||||
<enum 3 TF_Report>
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000001e000000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_LSB 29
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MASK 0x00000000e0000000
|
||||
|
||||
|
||||
/* Description PHY_PPDU_ID
|
||||
|
||||
A ppdu counter value that PHY increments for every PPDU
|
||||
received. The counter value wraps around
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description LSIG_RESPONSE_LENGTH
|
||||
|
||||
Field only valid in case of OFDMA trigger
|
||||
|
||||
Indicates the value of the L-SIG Length field of the HE
|
||||
trigger-based PPDU that is the response to the Trigger frame
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 60
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf000000000000000
|
||||
|
||||
|
||||
/* Description FRAME_CONTROL
|
||||
|
||||
frame control field of the received frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description QOS_CONTROL
|
||||
|
||||
frame control field of the received frame (if present)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description SW_PEER_ID
|
||||
|
||||
A unique identifier for this STA. Extracted from the Address_Search_Entry
|
||||
|
||||
|
||||
Used by the SCH to find linkage between this trigger and
|
||||
potentially pre-programmed responses.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 48
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xffff000000000000
|
||||
|
||||
|
||||
/* Description HE_CONTROL
|
||||
|
||||
Field only valid when HE_control_info_valid is set
|
||||
|
||||
This is the 'RAW HE_CONTROL field' that was present in the
|
||||
frame.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_LSB 32
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MSB 63
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // RECEIVED_TRIGGER_INFO
|
||||
342
hw/qcn6432/received_trigger_info_details.h
Archivo normal
342
hw/qcn6432/received_trigger_info_details.h
Archivo normal
@@ -0,0 +1,342 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
|
||||
#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
|
||||
|
||||
|
||||
struct received_trigger_info_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t trigger_type : 4, // [3:0]
|
||||
ax_trigger_source : 1, // [4:4]
|
||||
ax_trigger_type : 4, // [8:5]
|
||||
trigger_source_sta_full_aid : 13, // [21:9]
|
||||
frame_control_valid : 1, // [22:22]
|
||||
qos_control_valid : 1, // [23:23]
|
||||
he_control_info_valid : 1, // [24:24]
|
||||
ranging_trigger_subtype : 4, // [28:25]
|
||||
reserved_0b : 3; // [31:29]
|
||||
uint32_t phy_ppdu_id : 16, // [15:0]
|
||||
lsig_response_length : 12, // [27:16]
|
||||
reserved_1a : 4; // [31:28]
|
||||
uint32_t frame_control : 16, // [15:0]
|
||||
qos_control : 16; // [31:16]
|
||||
uint32_t sw_peer_id : 16, // [15:0]
|
||||
reserved_3a : 16; // [31:16]
|
||||
uint32_t he_control : 32; // [31:0]
|
||||
#else
|
||||
uint32_t reserved_0b : 3, // [31:29]
|
||||
ranging_trigger_subtype : 4, // [28:25]
|
||||
he_control_info_valid : 1, // [24:24]
|
||||
qos_control_valid : 1, // [23:23]
|
||||
frame_control_valid : 1, // [22:22]
|
||||
trigger_source_sta_full_aid : 13, // [21:9]
|
||||
ax_trigger_type : 4, // [8:5]
|
||||
ax_trigger_source : 1, // [4:4]
|
||||
trigger_type : 4; // [3:0]
|
||||
uint32_t reserved_1a : 4, // [31:28]
|
||||
lsig_response_length : 12, // [27:16]
|
||||
phy_ppdu_id : 16; // [15:0]
|
||||
uint32_t qos_control : 16, // [31:16]
|
||||
frame_control : 16; // [15:0]
|
||||
uint32_t reserved_3a : 16, // [31:16]
|
||||
sw_peer_id : 16; // [15:0]
|
||||
uint32_t he_control : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description TRIGGER_TYPE
|
||||
|
||||
This field indicates for what type of trigger has been received
|
||||
|
||||
|
||||
<enum 0 SCH_Qboost_trigger>
|
||||
<enum 1 SCH_PSPOLL_trigger>
|
||||
<enum 2 SCH_UAPSD_trigger>
|
||||
<enum 3 SCH_11ax_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 7 SCH_EHT_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 4 SCH_11ax_wildcard_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 5 SCH_11ax_unassoc_wildcard_trigger>
|
||||
Field "AX_trigger_type" indicates the ID of the received
|
||||
trigger
|
||||
<enum 6 SCH_11az_ranging_trigger> Field "AX_trigger_type"
|
||||
indicates the subtype of the received trigger
|
||||
|
||||
<legal 0-7>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
|
||||
|
||||
|
||||
/* Description AX_TRIGGER_SOURCE
|
||||
|
||||
Field Only valid when Trigger_type is an 11ax related trigger
|
||||
|
||||
|
||||
<enum 0 11ax_trigger_frame>
|
||||
<enum 1 he_control_based_trigger>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
|
||||
|
||||
|
||||
/* Description AX_TRIGGER_TYPE
|
||||
|
||||
Field Only valid when Trigger_type is an 11ax related trigger
|
||||
|
||||
|
||||
The 11AX trigger type/ trigger number:
|
||||
It identifies which trigger was received.
|
||||
<enum 0 ax_trigger_basic>
|
||||
<enum 1 ax_trigger_brpoll>
|
||||
<enum 2 ax_trigger_mu_bar>
|
||||
<enum 3 ax_trigger_mu_rts>
|
||||
<enum 4 ax_trigger_buffer_size>
|
||||
<enum 5 ax_trigger_gcr_mu_bar>
|
||||
<enum 6 ax_trigger_BQRP>
|
||||
<enum 7 ax_trigger_NDP_fb_report_poll>
|
||||
<enum 8 ax_tb_ranging_trigger> Indicates the reception of
|
||||
Ranging Trigger Frame of subvariant indicated by Ranging_Trigger_Subtype
|
||||
|
||||
<enum 9 ax_trigger_reserved_9>
|
||||
<enum 10 ax_trigger_reserved_10>
|
||||
<enum 11 ax_trigger_reserved_11>
|
||||
<enum 12 ax_trigger_reserved_12>
|
||||
<enum 13 ax_trigger_reserved_13>
|
||||
<enum 14 ax_trigger_reserved_14>
|
||||
<enum 15 ax_trigger_reserved_15>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
|
||||
|
||||
|
||||
/* Description TRIGGER_SOURCE_STA_FULL_AID
|
||||
|
||||
The sta_full_aid of the sta/ap that generated the trigger.
|
||||
|
||||
Comes from the address_search_entry
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
|
||||
|
||||
|
||||
/* Description FRAME_CONTROL_VALID
|
||||
|
||||
When set, the 'frame_control' field contains valid info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
|
||||
|
||||
|
||||
/* Description QOS_CONTROL_VALID
|
||||
|
||||
When set, the 'QoS_control' field contains valid info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
|
||||
|
||||
|
||||
/* Description HE_CONTROL_INFO_VALID
|
||||
|
||||
When set, the 'HE control' field contains valid info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
|
||||
|
||||
|
||||
/* Description RANGING_TRIGGER_SUBTYPE
|
||||
|
||||
Field only valid if AX_Trigger_type = ax_tb_ranging_trigger
|
||||
|
||||
|
||||
Indicates the Trigger subtype for the current ranging TF
|
||||
|
||||
|
||||
<enum 0 TF_Poll>
|
||||
<enum 1 TF_Sound>
|
||||
<enum 2 TF_Secure_Sound>
|
||||
<enum 3 TF_Report>
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
|
||||
|
||||
|
||||
/* Description RESERVED_0B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000
|
||||
|
||||
|
||||
/* Description PHY_PPDU_ID
|
||||
|
||||
A ppdu counter value that PHY increments for every PPDU
|
||||
received. The counter value wraps around
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description LSIG_RESPONSE_LENGTH
|
||||
|
||||
Field only valid in case of OFDMA trigger
|
||||
|
||||
Indicates the value of the L-SIG Length field of the HE
|
||||
trigger-based PPDU that is the response to the Trigger frame
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
|
||||
|
||||
|
||||
/* Description RESERVED_1A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description FRAME_CONTROL
|
||||
|
||||
frame control field of the received frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description QOS_CONTROL
|
||||
|
||||
frame control field of the received frame (if present)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000
|
||||
|
||||
|
||||
/* Description SW_PEER_ID
|
||||
|
||||
A unique identifier for this STA. Extracted from the Address_Search_Entry
|
||||
|
||||
|
||||
Used by the SCH to find linkage between this trigger and
|
||||
potentially pre-programmed responses.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000
|
||||
|
||||
|
||||
/* Description HE_CONTROL
|
||||
|
||||
Field only valid when HE_control_info_valid is set
|
||||
|
||||
This is the 'RAW HE_CONTROL field' that was present in the
|
||||
frame.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff
|
||||
|
||||
|
||||
|
||||
#endif // RECEIVED_TRIGGER_INFO_DETAILS
|
||||
563
hw/qcn6432/reo_descriptor_threshold_reached_status.h
Archivo normal
563
hw/qcn6432/reo_descriptor_threshold_reached_status.h
Archivo normal
@@ -0,0 +1,563 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
|
||||
#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26
|
||||
|
||||
#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13
|
||||
|
||||
|
||||
struct reo_descriptor_threshold_reached_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t threshold_index : 2, // [1:0]
|
||||
reserved_2 : 30; // [31:2]
|
||||
uint32_t link_descriptor_counter0 : 24, // [23:0]
|
||||
reserved_3 : 8; // [31:24]
|
||||
uint32_t link_descriptor_counter1 : 24, // [23:0]
|
||||
reserved_4 : 8; // [31:24]
|
||||
uint32_t link_descriptor_counter2 : 24, // [23:0]
|
||||
reserved_5 : 8; // [31:24]
|
||||
uint32_t link_descriptor_counter_sum : 26, // [25:0]
|
||||
reserved_6 : 6; // [31:26]
|
||||
uint32_t reserved_7 : 32; // [31:0]
|
||||
uint32_t reserved_8 : 32; // [31:0]
|
||||
uint32_t reserved_9a : 32; // [31:0]
|
||||
uint32_t reserved_10a : 32; // [31:0]
|
||||
uint32_t reserved_11a : 32; // [31:0]
|
||||
uint32_t reserved_12a : 32; // [31:0]
|
||||
uint32_t reserved_13a : 32; // [31:0]
|
||||
uint32_t reserved_14a : 32; // [31:0]
|
||||
uint32_t reserved_15a : 32; // [31:0]
|
||||
uint32_t reserved_16a : 32; // [31:0]
|
||||
uint32_t reserved_17a : 32; // [31:0]
|
||||
uint32_t reserved_18a : 32; // [31:0]
|
||||
uint32_t reserved_19a : 32; // [31:0]
|
||||
uint32_t reserved_20a : 32; // [31:0]
|
||||
uint32_t reserved_21a : 32; // [31:0]
|
||||
uint32_t reserved_22a : 32; // [31:0]
|
||||
uint32_t reserved_23a : 32; // [31:0]
|
||||
uint32_t reserved_24a : 32; // [31:0]
|
||||
uint32_t reserved_25a : 28, // [27:0]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t reserved_2 : 30, // [31:2]
|
||||
threshold_index : 2; // [1:0]
|
||||
uint32_t reserved_3 : 8, // [31:24]
|
||||
link_descriptor_counter0 : 24; // [23:0]
|
||||
uint32_t reserved_4 : 8, // [31:24]
|
||||
link_descriptor_counter1 : 24; // [23:0]
|
||||
uint32_t reserved_5 : 8, // [31:24]
|
||||
link_descriptor_counter2 : 24; // [23:0]
|
||||
uint32_t reserved_6 : 6, // [31:26]
|
||||
link_descriptor_counter_sum : 26; // [25:0]
|
||||
uint32_t reserved_7 : 32; // [31:0]
|
||||
uint32_t reserved_8 : 32; // [31:0]
|
||||
uint32_t reserved_9a : 32; // [31:0]
|
||||
uint32_t reserved_10a : 32; // [31:0]
|
||||
uint32_t reserved_11a : 32; // [31:0]
|
||||
uint32_t reserved_12a : 32; // [31:0]
|
||||
uint32_t reserved_13a : 32; // [31:0]
|
||||
uint32_t reserved_14a : 32; // [31:0]
|
||||
uint32_t reserved_15a : 32; // [31:0]
|
||||
uint32_t reserved_16a : 32; // [31:0]
|
||||
uint32_t reserved_17a : 32; // [31:0]
|
||||
uint32_t reserved_18a : 32; // [31:0]
|
||||
uint32_t reserved_19a : 32; // [31:0]
|
||||
uint32_t reserved_20a : 32; // [31:0]
|
||||
uint32_t reserved_21a : 32; // [31:0]
|
||||
uint32_t reserved_22a : 32; // [31:0]
|
||||
uint32_t reserved_23a : 32; // [31:0]
|
||||
uint32_t reserved_24a : 32; // [31:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
reserved_25a : 28; // [27:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STATUS_HEADER
|
||||
|
||||
Consumer: SW
|
||||
Producer: REO
|
||||
|
||||
Details that can link this status with the original command.
|
||||
It also contains info on how long REO took to execute this
|
||||
command.
|
||||
*/
|
||||
|
||||
|
||||
/* Description REO_STATUS_NUMBER
|
||||
|
||||
Consumer: SW , DEBUG
|
||||
Producer: REO
|
||||
|
||||
The value in this field is equal to value of the 'REO_CMD_Number'
|
||||
field the REO command
|
||||
|
||||
This field helps to correlate the statuses with the REO
|
||||
commands.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description CMD_EXECUTION_TIME
|
||||
|
||||
Consumer: DEBUG
|
||||
Producer: REO
|
||||
|
||||
The amount of time REO took to excecute the command. Note
|
||||
that this time does not include the duration of the command
|
||||
waiting in the command ring, before the execution started.
|
||||
|
||||
|
||||
In us.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
|
||||
|
||||
|
||||
/* Description REO_CMD_EXECUTION_STATUS
|
||||
|
||||
Consumer: DEBUG
|
||||
Producer: REO
|
||||
|
||||
Execution status of the command.
|
||||
|
||||
<enum 0 reo_successful_execution> Command has successfully
|
||||
be executed
|
||||
<enum 1 reo_blocked_execution> Command could not be executed
|
||||
as the queue or cache was blocked
|
||||
<enum 2 reo_failed_execution> Command has encountered problems
|
||||
when executing, like the queue descriptor not being valid.
|
||||
None of the status fields in the entire STATUS TLV are valid.
|
||||
|
||||
<enum 3 reo_resource_blocked> Command is NOT executed because
|
||||
one or more descriptors were blocked. This is SW programming
|
||||
mistake.
|
||||
None of the status fields in the entire STATUS TLV are valid.
|
||||
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
|
||||
|
||||
|
||||
/* Description TIMESTAMP
|
||||
|
||||
Timestamp at the moment that this status report is written.
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description THRESHOLD_INDEX
|
||||
|
||||
The index of the threshold register whose value got reached
|
||||
|
||||
|
||||
<enum 0 reo_desc_counter0_threshold>
|
||||
<enum 1 reo_desc_counter1_threshold>
|
||||
<enum 2 reo_desc_counter2_threshold>
|
||||
<enum 3 reo_desc_counter_sum_threshold>
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003
|
||||
|
||||
|
||||
/* Description RESERVED_2
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc
|
||||
|
||||
|
||||
/* Description LINK_DESCRIPTOR_COUNTER0
|
||||
|
||||
Value of this counter at generation of this message
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_3
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000
|
||||
|
||||
|
||||
/* Description LINK_DESCRIPTOR_COUNTER1
|
||||
|
||||
Value of this counter at generation of this message
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff
|
||||
|
||||
|
||||
/* Description RESERVED_4
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000
|
||||
|
||||
|
||||
/* Description LINK_DESCRIPTOR_COUNTER2
|
||||
|
||||
Value of this counter at generation of this message
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_5
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000
|
||||
|
||||
|
||||
/* Description LINK_DESCRIPTOR_COUNTER_SUM
|
||||
|
||||
Value of this counter at generation of this message
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff
|
||||
|
||||
|
||||
/* Description RESERVED_6
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000
|
||||
|
||||
|
||||
/* Description RESERVED_7
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_8
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_25A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into this Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63
|
||||
#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS
|
||||
945
hw/qcn6432/reo_destination_ring.h
Archivo normal
945
hw/qcn6432/reo_destination_ring.h
Archivo normal
@@ -0,0 +1,945 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_DESTINATION_RING_H_
|
||||
#define _REO_DESTINATION_RING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "rx_msdu_desc_info.h"
|
||||
#include "rx_mpdu_desc_info.h"
|
||||
#include "buffer_addr_info.h"
|
||||
#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
|
||||
|
||||
|
||||
struct reo_destination_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct buffer_addr_info buf_or_link_desc_addr_info;
|
||||
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
|
||||
struct rx_msdu_desc_info rx_msdu_desc_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t buffer_virt_addr_63_32 : 32; // [31:0]
|
||||
uint32_t reo_dest_buffer_type : 1, // [0:0]
|
||||
reo_push_reason : 2, // [2:1]
|
||||
reo_error_code : 5, // [7:3]
|
||||
captured_msdu_data_size : 4, // [11:8]
|
||||
sw_exception : 1, // [12:12]
|
||||
src_link_id : 3, // [15:13]
|
||||
reo_destination_struct_signature : 4, // [19:16]
|
||||
ring_id : 8, // [27:20]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
struct buffer_addr_info buf_or_link_desc_addr_info;
|
||||
struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
|
||||
struct rx_msdu_desc_info rx_msdu_desc_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32; // [31:0]
|
||||
uint32_t buffer_virt_addr_63_32 : 32; // [31:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
ring_id : 8, // [27:20]
|
||||
reo_destination_struct_signature : 4, // [19:16]
|
||||
src_link_id : 3, // [15:13]
|
||||
sw_exception : 1, // [12:12]
|
||||
captured_msdu_data_size : 4, // [11:8]
|
||||
reo_error_code : 5, // [7:3]
|
||||
reo_push_reason : 2, // [2:1]
|
||||
reo_dest_buffer_type : 1; // [0:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description BUF_OR_LINK_DESC_ADDR_INFO
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
Details of the physical address of the a buffer or MSDU
|
||||
link descriptor
|
||||
*/
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_31_0
|
||||
|
||||
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_39_32
|
||||
|
||||
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RETURN_BUFFER_MANAGER
|
||||
|
||||
Consumer: WBM
|
||||
Producer: SW/FW
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
||||
descriptor OR link descriptor that is being pointed to
|
||||
shall be returned after the frame has been processed. It
|
||||
is used by WBM for routing purposes.
|
||||
|
||||
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
||||
to the WMB buffer idle list
|
||||
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the WBM idle link descriptor idle list, where the chip
|
||||
0 WBM is chosen in case of a multi-chip config
|
||||
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 1 WBM idle link descriptor idle list
|
||||
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 2 WBM idle link descriptor idle list
|
||||
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
||||
returned to chip 3 WBM idle link descriptor idle list
|
||||
<enum 4 FW_BM> This buffer shall be returned to the FW
|
||||
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
||||
ring 0
|
||||
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
||||
ring 1
|
||||
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
||||
ring 2
|
||||
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
||||
ring 3
|
||||
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
||||
ring 4
|
||||
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
||||
ring 5
|
||||
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
||||
ring 6
|
||||
|
||||
<legal 0-12>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
||||
|
||||
|
||||
/* Description SW_BUFFER_COOKIE
|
||||
|
||||
Cookie field exclusively used by SW.
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
HW ignores the contents, accept that it passes the programmed
|
||||
value on to other descriptors together with the physical
|
||||
address
|
||||
|
||||
Field can be used by SW to for example associate the buffers
|
||||
physical address with the virtual address
|
||||
The bit definitions as used by SW are within SW HLD specification
|
||||
|
||||
|
||||
NOTE1:
|
||||
The three most significant bits can have a special meaning
|
||||
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
||||
and field transmit_bw_restriction is set
|
||||
|
||||
In case of NON punctured transmission:
|
||||
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
In case of punctured transmission:
|
||||
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
Note: a punctured transmission is indicated by the presence
|
||||
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
||||
#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
||||
|
||||
|
||||
/* Description RX_MPDU_DESC_INFO_DETAILS
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
General information related to the MPDU that is passed on
|
||||
from REO entrance ring to the REO destination ring
|
||||
|
||||
When enabled in REO, REO will overwrite this structure to
|
||||
have only the 'Msdu_count' field and 56 bits of the previous
|
||||
PN from 'RX_REO_QUEUE'
|
||||
*/
|
||||
|
||||
|
||||
/* Description MSDU_COUNT
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
The number of MSDUs within the MPDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description FRAGMENT_FLAG
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
When set, this MPDU is a fragment and REO should forward
|
||||
this fragment MPDU to the REO destination ring without
|
||||
any reorder checks, pn checks or bitmap update. This implies
|
||||
that REO is forwarding the pointer to the MSDU link descriptor.
|
||||
The destination ring is coming from a programmable register
|
||||
setting in REO
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
|
||||
|
||||
|
||||
/* Description MPDU_RETRY_BIT
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
The retry bit setting from the MPDU header of the received
|
||||
frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
|
||||
|
||||
|
||||
/* Description AMPDU_FLAG
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
When set, the MPDU was received as part of an A-MPDU.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
|
||||
|
||||
|
||||
/* Description BAR_FRAME
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
When set, the received frame is a BAR frame. After processing,
|
||||
this frame shall be pushed to SW or deleted.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
|
||||
|
||||
|
||||
/* Description PN_FIELDS_CONTAIN_VALID_INFO
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
Copied here by RXDMA from RX_MPDU_END
|
||||
When not set, REO will Not perform a PN sequence number
|
||||
check
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description RAW_MPDU
|
||||
|
||||
Field only valid when first_msdu_in_mpdu_flag is set.
|
||||
|
||||
When set, the contents in the MSDU buffer contains a 'RAW'
|
||||
MPDU. This 'RAW' MPDU might be spread out over multiple
|
||||
MSDU buffers.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
|
||||
|
||||
|
||||
/* Description MORE_FRAGMENT_FLAG
|
||||
|
||||
The More Fragment bit setting from the MPDU header of the
|
||||
received frame
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
|
||||
|
||||
|
||||
/* Description SRC_INFO
|
||||
|
||||
Source (virtual) device/interface info. associated with
|
||||
this peer
|
||||
|
||||
This field gets passed on by REO to PPE in the EDMA descriptor
|
||||
('REO_TO_PPE_RING').
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
|
||||
|
||||
|
||||
/* Description MPDU_QOS_CONTROL_VALID
|
||||
|
||||
When set, the MPDU has a QoS control field.
|
||||
|
||||
In case of ndp or phy_err, this field will never be set.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
|
||||
|
||||
|
||||
/* Description TID
|
||||
|
||||
Field only valid when mpdu_qos_control_valid is set
|
||||
|
||||
The TID field in the QoS control field
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description PEER_META_DATA
|
||||
|
||||
Meta data that SW has programmed in the Peer table entry
|
||||
of the transmitting STA.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
|
||||
#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description RX_MSDU_DESC_INFO_DETAILS
|
||||
|
||||
General information related to the MSDU that is passed on
|
||||
from RXDMA all the way to to the REO destination ring.
|
||||
*/
|
||||
|
||||
|
||||
/* Description FIRST_MSDU_IN_MPDU_FLAG
|
||||
|
||||
Parsed from RX_MSDU_END TLV . In the case MSDU spans over
|
||||
multiple buffers, this field will be valid in the Last
|
||||
buffer used by the MSDU
|
||||
|
||||
<enum 0 Not_first_msdu> This is not the first MSDU in the
|
||||
MPDU.
|
||||
<enum 1 first_msdu> This MSDU is the first one in the MPDU.
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
|
||||
|
||||
|
||||
/* Description LAST_MSDU_IN_MPDU_FLAG
|
||||
|
||||
Consumer: WBM/REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
Parsed from RX_MSDU_END TLV . In the case MSDU spans over
|
||||
multiple buffers, this field will be valid in the Last
|
||||
buffer used by the MSDU
|
||||
|
||||
<enum 0 Not_last_msdu> There are more MSDUs linked to this
|
||||
MSDU that belongs to this MPDU
|
||||
<enum 1 Last_msdu> this MSDU is the last one in the MPDU.
|
||||
This setting is only allowed in combination with 'Msdu_continuation'
|
||||
set to 0. This implies that when an msdu is spread out over
|
||||
multiple buffers and thus msdu_continuation is set, only
|
||||
for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag'
|
||||
be set.
|
||||
|
||||
When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag
|
||||
are set, the MPDU that this MSDU belongs to only contains
|
||||
a single MSDU.
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
|
||||
|
||||
|
||||
/* Description MSDU_CONTINUATION
|
||||
|
||||
When set, this MSDU buffer was not able to hold the entire
|
||||
MSDU. The next buffer will therefor contain additional
|
||||
information related to this MSDU.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
|
||||
|
||||
|
||||
/* Description MSDU_LENGTH
|
||||
|
||||
Parsed from RX_MSDU_START TLV . In the case MSDU spans over
|
||||
multiple buffers, this field will be valid in the First
|
||||
buffer used by MSDU.
|
||||
|
||||
Full MSDU length in bytes after decapsulation.
|
||||
|
||||
This field is still valid for MPDU frames without A-MSDU.
|
||||
It still represents MSDU length after decapsulation
|
||||
|
||||
Or in case of RAW MPDUs, it indicates the length of the
|
||||
entire MPDU (without FCS field)
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
|
||||
|
||||
|
||||
/* Description MSDU_DROP
|
||||
|
||||
Parsed from RX_MSDU_END TLV . In the case MSDU spans over
|
||||
multiple buffers, this field will be valid in the Last
|
||||
buffer used by the MSDU
|
||||
|
||||
When set, REO shall drop this MSDU and not forward it to
|
||||
any other ring...
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
|
||||
|
||||
|
||||
/* Description SA_IS_VALID
|
||||
|
||||
Parsed from RX_MSDU_END TLV . In the case MSDU spans over
|
||||
multiple buffers, this field will be valid in the Last
|
||||
buffer used by the MSDU
|
||||
|
||||
Indicates that OLE found a valid SA entry for this MSDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
|
||||
|
||||
|
||||
/* Description DA_IS_VALID
|
||||
|
||||
Parsed from RX_MSDU_END TLV . In the case MSDU spans over
|
||||
multiple buffers, this field will be valid in the Last
|
||||
buffer used by the MSDU
|
||||
|
||||
Indicates that OLE found a valid DA entry for this MSDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
|
||||
|
||||
|
||||
/* Description DA_IS_MCBC
|
||||
|
||||
Field Only valid if "da_is_valid" is set
|
||||
|
||||
Indicates the DA address was a Multicast of Broadcast address
|
||||
for this MSDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
|
||||
|
||||
|
||||
/* Description L3_HEADER_PADDING_MSB
|
||||
|
||||
Passed on from 'RX_MSDU_END' TLV (only the MSB is reported
|
||||
as the LSB is always zero)
|
||||
Number of bytes padded to make sure that the L3 header will
|
||||
always start of a Dword boundary
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
|
||||
|
||||
|
||||
/* Description TCP_UDP_CHKSUM_FAIL
|
||||
|
||||
Passed on from 'RX_ATTENTION' TLV
|
||||
Indicates that the computed checksum did not match the checksum
|
||||
in the TCP/UDP header.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
|
||||
|
||||
|
||||
/* Description IP_CHKSUM_FAIL
|
||||
|
||||
Passed on from 'RX_ATTENTION' TLV
|
||||
Indicates that the computed checksum did not match the checksum
|
||||
in the IP header.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
|
||||
|
||||
|
||||
/* Description FR_DS
|
||||
|
||||
Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START'
|
||||
TLV
|
||||
Set if the 'from DS' bit is set in the frame control.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
|
||||
|
||||
|
||||
/* Description TO_DS
|
||||
|
||||
Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START'
|
||||
TLV
|
||||
Set if the 'to DS' bit is set in the frame control.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
|
||||
|
||||
|
||||
/* Description INTRA_BSS
|
||||
|
||||
This packet needs intra-BSS routing by SW as the 'vdev_id'
|
||||
for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START')
|
||||
that this MSDU was got in.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
|
||||
|
||||
|
||||
/* Description DEST_CHIP_ID
|
||||
|
||||
If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
|
||||
to support intra-BSS routing with multi-chip multi-link
|
||||
operation.
|
||||
|
||||
This indicates into which chip's TCL the packet should be
|
||||
queued.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
|
||||
|
||||
|
||||
/* Description DECAP_FORMAT
|
||||
|
||||
Indicates the format after decapsulation:
|
||||
|
||||
<enum 0 RAW> No encapsulation
|
||||
<enum 1 Native_WiFi>
|
||||
<enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC)
|
||||
|
||||
<enum 3 802_3> Indicate Ethernet
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
|
||||
|
||||
|
||||
/* Description DEST_CHIP_PMAC_ID
|
||||
|
||||
If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY'
|
||||
to support intra-BSS routing with multi-chip multi-link
|
||||
operation.
|
||||
|
||||
This indicates into which link/'vdev' the packet should
|
||||
be queued in TCL.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000010
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31
|
||||
#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000
|
||||
|
||||
|
||||
/* Description BUFFER_VIRT_ADDR_31_0
|
||||
|
||||
Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address
|
||||
|
||||
|
||||
Lower 32 bits of the 64-bit virtual address corresponding
|
||||
to Buf_or_link_desc_addr_info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description BUFFER_VIRT_ADDR_63_32
|
||||
|
||||
Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address
|
||||
|
||||
|
||||
Upper 32 bits of the 64-bit virtual address corresponding
|
||||
to Buf_or_link_desc_addr_info
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
|
||||
#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description REO_DEST_BUFFER_TYPE
|
||||
|
||||
Indicates the type of address provided in the 'Buf_or_link_desc_addr_info'
|
||||
|
||||
|
||||
<enum 0 MSDU_buf_address> The address of an MSDU buffer
|
||||
<enum 1 MSDU_link_desc_address> The address of the MSDU
|
||||
link descriptor.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0
|
||||
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0
|
||||
#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001
|
||||
|
||||
|
||||
/* Description REO_PUSH_REASON
|
||||
|
||||
Indicates why REO pushed the frame to this exit ring
|
||||
|
||||
<enum 0 reo_error_detected> Reo detected an error an pushed
|
||||
this frame to this queue
|
||||
<enum 1 reo_routing_instruction> Reo pushed the frame to
|
||||
this queue per received routing instructions. No error
|
||||
within REO was detected
|
||||
|
||||
|
||||
<legal 0 - 1>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1
|
||||
#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2
|
||||
#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006
|
||||
|
||||
|
||||
/* Description REO_ERROR_CODE
|
||||
|
||||
Field only valid when 'Reo_push_reason' set to 'reo_error_detected'.
|
||||
|
||||
|
||||
<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor provided
|
||||
in the REO_ENTRANCE ring is set to 0
|
||||
<enum 1 reo_queue_desc_not_valid> Reo queue descriptor valid
|
||||
bit is NOT set
|
||||
<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
|
||||
session having been setup.
|
||||
<enum 3 non_ba_duplicate> Non-BA session, SN equal to SSN,
|
||||
Retry bit set: duplicate frame
|
||||
<enum 4 ba_duplicate> BA session, duplicate frame
|
||||
<enum 5 regular_frame_2k_jump> A normal (management/data
|
||||
frame) received with 2K jump in SN
|
||||
<enum 6 bar_frame_2k_jump> A bar received with 2K jump in
|
||||
SSN
|
||||
<enum 7 regular_frame_OOR> A normal (management/data frame)
|
||||
received with SN falling within the OOR window
|
||||
<enum 8 bar_frame_OOR> A bar received with SSN falling within
|
||||
the OOR window
|
||||
<enum 9 bar_frame_no_ba_session> A bar received without
|
||||
a BA session
|
||||
<enum 10 bar_frame_sn_equals_ssn> A bar received with SSN
|
||||
equal to SN
|
||||
<enum 11 pn_check_failed> PN Check Failed packet.
|
||||
<enum 12 2k_error_handling_flag_set> Frame is forwarded
|
||||
as a result of the 'Seq_2k_error_detected_flag' been set
|
||||
in the REO Queue descriptor
|
||||
<enum 13 pn_error_handling_flag_set> Frame is forwarded
|
||||
as a result of the 'pn_error_detected_flag' been set in
|
||||
the REO Queue descriptor
|
||||
<enum 14 queue_descriptor_blocked_set> Frame is forwarded
|
||||
as a result of the queue descriptor(address) being blocked
|
||||
as SW/FW seems to be currently in the process of making
|
||||
updates to this descriptor...
|
||||
|
||||
<legal 0-14>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3
|
||||
#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7
|
||||
#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8
|
||||
|
||||
|
||||
/* Description CAPTURED_MSDU_DATA_SIZE
|
||||
|
||||
The number of following REO_DESTINATION STRUCTs that have
|
||||
been replaced with msdu_data extracted from the msdu_buffer
|
||||
and copied into the ring for easy FW/SW access.
|
||||
Note that it is possible that these STRUCTs wrap around
|
||||
the end of the ring.
|
||||
<legal 0-4>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8
|
||||
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11
|
||||
#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
|
||||
|
||||
|
||||
/* Description SW_EXCEPTION
|
||||
|
||||
This field has the same setting as the SW_exception field
|
||||
in the corresponding REO_entrance_ring descriptor.
|
||||
When set, the REO entrance descriptor is generated by FW,
|
||||
and the MPDU was processed in the following way:
|
||||
- NO re-order function is needed.
|
||||
- MPDU delinking is determined by the setting of Entrance
|
||||
ring field: SW_excection_mpdu_delink
|
||||
- Destination ring selection is based on the setting of
|
||||
the Entrance ring field SW_exception_destination _ring_valid
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12
|
||||
#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12
|
||||
#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description SRC_LINK_ID
|
||||
|
||||
Consumer: SW
|
||||
Producer: RXDMA
|
||||
|
||||
Set to the link ID of the PMAC that received the frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13
|
||||
#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15
|
||||
#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000
|
||||
|
||||
|
||||
/* Description REO_DESTINATION_STRUCT_SIGNATURE
|
||||
|
||||
Set to value 0x8 when msdu capture mode is enabled for this
|
||||
ring <legal 0, 8 >
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
|
||||
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
|
||||
#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
|
||||
|
||||
|
||||
/* Description RING_ID
|
||||
|
||||
The buffer pointer ring ID.
|
||||
0 refers to the IDLE ring
|
||||
1 - N refers to other rings
|
||||
|
||||
Helps with debugging when dumping ring contents.
|
||||
|
||||
This can be used in conjunction with the Reo_destination_struct_signature.
|
||||
|
||||
|
||||
For debugging, if enabled, REO may fill the Rx MPDU sequence
|
||||
number in {Looping_count, ring_id}.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_RING_ID_LSB 20
|
||||
#define REO_DESTINATION_RING_RING_ID_MSB 27
|
||||
#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into this Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
|
||||
For debugging, if enabled, REO may fill the Rx MPDU sequence
|
||||
number in {Looping_count, ring_id}.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c
|
||||
#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28
|
||||
#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31
|
||||
#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_DESTINATION_RING
|
||||
933
hw/qcn6432/reo_entrance_ring.h
Archivo normal
933
hw/qcn6432/reo_entrance_ring.h
Archivo normal
@@ -0,0 +1,933 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_ENTRANCE_RING_H_
|
||||
#define _REO_ENTRANCE_RING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "rx_mpdu_details.h"
|
||||
#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
|
||||
|
||||
|
||||
struct reo_entrance_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct rx_mpdu_details reo_level_mpdu_frame_info;
|
||||
uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
|
||||
uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0]
|
||||
rounded_mpdu_byte_count : 14, // [21:8]
|
||||
reo_destination_indication : 5, // [26:22]
|
||||
frameless_bar : 1, // [27:27]
|
||||
reserved_5a : 4; // [31:28]
|
||||
uint32_t rxdma_push_reason : 2, // [1:0]
|
||||
rxdma_error_code : 5, // [6:2]
|
||||
mpdu_fragment_number : 4, // [10:7]
|
||||
sw_exception : 1, // [11:11]
|
||||
sw_exception_mpdu_delink : 1, // [12:12]
|
||||
sw_exception_destination_ring_valid : 1, // [13:13]
|
||||
sw_exception_destination_ring : 5, // [18:14]
|
||||
mpdu_sequence_number : 12, // [30:19]
|
||||
reserved_6a : 1; // [31:31]
|
||||
uint32_t phy_ppdu_id : 16, // [15:0]
|
||||
src_link_id : 3, // [18:16]
|
||||
reserved_7a : 1, // [19:19]
|
||||
ring_id : 8, // [27:20]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
struct rx_mpdu_details reo_level_mpdu_frame_info;
|
||||
uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0]
|
||||
uint32_t reserved_5a : 4, // [31:28]
|
||||
frameless_bar : 1, // [27:27]
|
||||
reo_destination_indication : 5, // [26:22]
|
||||
rounded_mpdu_byte_count : 14, // [21:8]
|
||||
rx_reo_queue_desc_addr_39_32 : 8; // [7:0]
|
||||
uint32_t reserved_6a : 1, // [31:31]
|
||||
mpdu_sequence_number : 12, // [30:19]
|
||||
sw_exception_destination_ring : 5, // [18:14]
|
||||
sw_exception_destination_ring_valid : 1, // [13:13]
|
||||
sw_exception_mpdu_delink : 1, // [12:12]
|
||||
sw_exception : 1, // [11:11]
|
||||
mpdu_fragment_number : 4, // [10:7]
|
||||
rxdma_error_code : 5, // [6:2]
|
||||
rxdma_push_reason : 2; // [1:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
ring_id : 8, // [27:20]
|
||||
reserved_7a : 1, // [19:19]
|
||||
src_link_id : 3, // [18:16]
|
||||
phy_ppdu_id : 16; // [15:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description REO_LEVEL_MPDU_FRAME_INFO
|
||||
|
||||
Consumer: REO
|
||||
Producer: RXDMA
|
||||
|
||||
Details related to the MPDU being pushed into the REO
|
||||
*/
|
||||
|
||||
|
||||
/* Description MSDU_LINK_DESC_ADDR_INFO
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
Details of the physical address of the MSDU link descriptor
|
||||
that contains pointers to MSDUs related to this MPDU
|
||||
*/
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_31_0
|
||||
|
||||
Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description BUFFER_ADDR_39_32
|
||||
|
||||
Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION
|
||||
descriptor OR Link Descriptor
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description RETURN_BUFFER_MANAGER
|
||||
|
||||
Consumer: WBM
|
||||
Producer: SW/FW
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
Indicates to which buffer manager the buffer OR MSDU_EXTENSION
|
||||
descriptor OR link descriptor that is being pointed to
|
||||
shall be returned after the frame has been processed. It
|
||||
is used by WBM for routing purposes.
|
||||
|
||||
<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
|
||||
to the WMB buffer idle list
|
||||
<enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the WBM idle link descriptor idle list, where the chip
|
||||
0 WBM is chosen in case of a multi-chip config
|
||||
<enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 1 WBM idle link descriptor idle list
|
||||
<enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned
|
||||
to the chip 2 WBM idle link descriptor idle list
|
||||
<enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be
|
||||
returned to chip 3 WBM idle link descriptor idle list
|
||||
<enum 4 FW_BM> This buffer shall be returned to the FW
|
||||
<enum 5 SW0_BM> This buffer shall be returned to the SW,
|
||||
ring 0
|
||||
<enum 6 SW1_BM> This buffer shall be returned to the SW,
|
||||
ring 1
|
||||
<enum 7 SW2_BM> This buffer shall be returned to the SW,
|
||||
ring 2
|
||||
<enum 8 SW3_BM> This buffer shall be returned to the SW,
|
||||
ring 3
|
||||
<enum 9 SW4_BM> This buffer shall be returned to the SW,
|
||||
ring 4
|
||||
<enum 10 SW5_BM> This buffer shall be returned to the SW,
|
||||
ring 5
|
||||
<enum 11 SW6_BM> This buffer shall be returned to the SW,
|
||||
ring 6
|
||||
|
||||
<legal 0-12>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
||||
|
||||
|
||||
/* Description SW_BUFFER_COOKIE
|
||||
|
||||
Cookie field exclusively used by SW.
|
||||
|
||||
In case of 'NULL' pointer, this field is set to 0
|
||||
|
||||
HW ignores the contents, accept that it passes the programmed
|
||||
value on to other descriptors together with the physical
|
||||
address
|
||||
|
||||
Field can be used by SW to for example associate the buffers
|
||||
physical address with the virtual address
|
||||
The bit definitions as used by SW are within SW HLD specification
|
||||
|
||||
|
||||
NOTE1:
|
||||
The three most significant bits can have a special meaning
|
||||
in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
|
||||
and field transmit_bw_restriction is set
|
||||
|
||||
In case of NON punctured transmission:
|
||||
Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only
|
||||
Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
In case of punctured transmission:
|
||||
Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only
|
||||
Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only
|
||||
Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only
|
||||
Sw_buffer_cookie[19:18] = 2'b11: reserved
|
||||
|
||||
Note: a punctured transmission is indicated by the presence
|
||||
of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
|
||||
|
||||
|
||||
/* Description RX_MPDU_DESC_INFO_DETAILS
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
General information related to the MPDU that should be passed
|
||||
on from REO entrance ring to the REO destination ring
|
||||
*/
|
||||
|
||||
|
||||
/* Description MSDU_COUNT
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
The number of MSDUs within the MPDU
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description FRAGMENT_FLAG
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
When set, this MPDU is a fragment and REO should forward
|
||||
this fragment MPDU to the REO destination ring without
|
||||
any reorder checks, pn checks or bitmap update. This implies
|
||||
that REO is forwarding the pointer to the MSDU link descriptor.
|
||||
The destination ring is coming from a programmable register
|
||||
setting in REO
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
|
||||
|
||||
|
||||
/* Description MPDU_RETRY_BIT
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
The retry bit setting from the MPDU header of the received
|
||||
frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
|
||||
|
||||
|
||||
/* Description AMPDU_FLAG
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
When set, the MPDU was received as part of an A-MPDU.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
|
||||
|
||||
|
||||
/* Description BAR_FRAME
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
When set, the received frame is a BAR frame. After processing,
|
||||
this frame shall be pushed to SW or deleted.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
|
||||
|
||||
|
||||
/* Description PN_FIELDS_CONTAIN_VALID_INFO
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
Copied here by RXDMA from RX_MPDU_END
|
||||
When not set, REO will Not perform a PN sequence number
|
||||
check
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description RAW_MPDU
|
||||
|
||||
Field only valid when first_msdu_in_mpdu_flag is set.
|
||||
|
||||
When set, the contents in the MSDU buffer contains a 'RAW'
|
||||
MPDU. This 'RAW' MPDU might be spread out over multiple
|
||||
MSDU buffers.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
|
||||
|
||||
|
||||
/* Description MORE_FRAGMENT_FLAG
|
||||
|
||||
The More Fragment bit setting from the MPDU header of the
|
||||
received frame
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
|
||||
|
||||
|
||||
/* Description SRC_INFO
|
||||
|
||||
Source (virtual) device/interface info. associated with
|
||||
this peer
|
||||
|
||||
This field gets passed on by REO to PPE in the EDMA descriptor
|
||||
('REO_TO_PPE_RING').
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
|
||||
|
||||
|
||||
/* Description MPDU_QOS_CONTROL_VALID
|
||||
|
||||
When set, the MPDU has a QoS control field.
|
||||
|
||||
In case of ndp or phy_err, this field will never be set.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
|
||||
|
||||
|
||||
/* Description TID
|
||||
|
||||
Field only valid when mpdu_qos_control_valid is set
|
||||
|
||||
The TID field in the QoS control field
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description PEER_META_DATA
|
||||
|
||||
Meta data that SW has programmed in the Peer table entry
|
||||
of the transmitting STA.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
|
||||
#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description RX_REO_QUEUE_DESC_ADDR_31_0
|
||||
|
||||
Consumer: REO
|
||||
Producer: RXDMA
|
||||
|
||||
Address (lower 32 bits) of the REO queue descriptor
|
||||
|
||||
Alternatively, REO internally looks up the
|
||||
queue descriptor address from 'Sw_peer_id' and 'Tid.' In
|
||||
this mode, RXDMA fills 'Sw_peer_id' from 'RX_MPDU_START'
|
||||
in the LSB 16 bits. 'Tid' is available in 'RX_MPDU_DETAILS.'
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
|
||||
/* Description RX_REO_QUEUE_DESC_ADDR_39_32
|
||||
|
||||
Consumer: REO
|
||||
Producer: RXDMA
|
||||
|
||||
Address (upper 8 bits) of the REO queue descriptor
|
||||
Alternatively, REO internally looks up the
|
||||
queue descriptor address from 'Sw_peer_id' and 'Tid.' In
|
||||
this mode, this field is unused.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
|
||||
#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
|
||||
/* Description ROUNDED_MPDU_BYTE_COUNT
|
||||
|
||||
An approximation of the number of bytes received in this
|
||||
MPDU.
|
||||
Used to keeps stats on the amount of data flowing through
|
||||
a queue.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
|
||||
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8
|
||||
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21
|
||||
#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
|
||||
|
||||
|
||||
/* Description REO_DESTINATION_INDICATION
|
||||
|
||||
RXDMA copy the MPDU's first MSDU's destination indication
|
||||
field here. This is used for REO to be able to re-route
|
||||
the packet to a different SW destination ring if the packet
|
||||
is detected as error in REO.
|
||||
|
||||
The ID of the REO exit ring where the MSDU frame shall push
|
||||
after (MPDU level) reordering has finished.
|
||||
|
||||
<enum 0 reo_destination_sw0> Reo will push the frame into
|
||||
the REO2SW0 ring
|
||||
<enum 1 reo_destination_sw1> Reo will push the frame into
|
||||
the REO2SW1 ring
|
||||
<enum 2 reo_destination_sw2> Reo will push the frame into
|
||||
the REO2SW2 ring
|
||||
<enum 3 reo_destination_sw3> Reo will push the frame into
|
||||
the REO2SW3 ring
|
||||
<enum 4 reo_destination_sw4> Reo will push the frame into
|
||||
the REO2SW4 ring
|
||||
<enum 5 reo_destination_release> Reo will push the frame
|
||||
into the REO_release ring
|
||||
<enum 6 reo_destination_fw> Reo will push the frame into
|
||||
the REO2FW ring
|
||||
<enum 7 reo_destination_sw5> Reo will push the frame into
|
||||
the REO2SW5 ring (REO remaps this in chips without REO2SW5
|
||||
ring)
|
||||
<enum 8 reo_destination_sw6> Reo will push the frame into
|
||||
the REO2SW6 ring (REO remaps this in chips without REO2SW6
|
||||
ring)
|
||||
<enum 9 reo_destination_sw7> Reo will push the frame into
|
||||
the REO2SW7 ring (REO remaps this in chips without REO2SW7
|
||||
ring)
|
||||
<enum 10 reo_destination_sw8> Reo will push the frame into
|
||||
the REO2SW8 ring (REO remaps this in chips without REO2SW8
|
||||
ring)
|
||||
<enum 11 reo_destination_11> REO remaps this
|
||||
<enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13>
|
||||
REO remaps this
|
||||
<enum 14 reo_destination_14> REO remaps this
|
||||
<enum 15 reo_destination_15> REO remaps this
|
||||
<enum 16 reo_destination_16> REO remaps this
|
||||
<enum 17 reo_destination_17> REO remaps this
|
||||
<enum 18 reo_destination_18> REO remaps this
|
||||
<enum 19 reo_destination_19> REO remaps this
|
||||
<enum 20 reo_destination_20> REO remaps this
|
||||
<enum 21 reo_destination_21> REO remaps this
|
||||
<enum 22 reo_destination_22> REO remaps this
|
||||
<enum 23 reo_destination_23> REO remaps this
|
||||
<enum 24 reo_destination_24> REO remaps this
|
||||
<enum 25 reo_destination_25> REO remaps this
|
||||
<enum 26 reo_destination_26> REO remaps this
|
||||
<enum 27 reo_destination_27> REO remaps this
|
||||
<enum 28 reo_destination_28> REO remaps this
|
||||
<enum 29 reo_destination_29> REO remaps this
|
||||
<enum 30 reo_destination_30> REO remaps this
|
||||
<enum 31 reo_destination_31> REO remaps this
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014
|
||||
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22
|
||||
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26
|
||||
#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000
|
||||
|
||||
|
||||
/* Description FRAMELESS_BAR
|
||||
|
||||
When set, this REO entrance ring struct contains BAR info
|
||||
from a multi TID BAR frame. The original multi TID BAR
|
||||
frame itself contained all the REO info for the first TID,
|
||||
but all the subsequent TID info and their linkage to the
|
||||
REO descriptors is passed down as 'frameless' BAR info.
|
||||
|
||||
|
||||
The only fields valid in this descriptor when this bit is
|
||||
set are:
|
||||
Rx_reo_queue_desc_addr_31_0
|
||||
RX_reo_queue_desc_addr_39_32
|
||||
|
||||
And within the
|
||||
Reo_level_mpdu_frame_info:
|
||||
Within Rx_mpdu_desc_info_details:
|
||||
Mpdu_Sequence_number
|
||||
BAR_frame
|
||||
Peer_meta_data
|
||||
All other fields shall be set to 0
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014
|
||||
#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27
|
||||
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27
|
||||
#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000
|
||||
|
||||
|
||||
/* Description RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014
|
||||
#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28
|
||||
#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31
|
||||
#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000
|
||||
|
||||
|
||||
/* Description RXDMA_PUSH_REASON
|
||||
|
||||
Indicates why rxdma pushed the frame to this ring
|
||||
|
||||
This field is ignored by REO.
|
||||
|
||||
<enum 0 rxdma_error_detected> RXDMA detected an error an
|
||||
pushed this frame to this queue
|
||||
<enum 1 rxdma_routing_instruction> RXDMA pushed the frame
|
||||
to this queue per received routing instructions. No error
|
||||
within RXDMA was detected
|
||||
<enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
|
||||
result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag"
|
||||
set, but instead WBM might just see a NULL pointer in the
|
||||
MSDU link descriptor. This is to be considered a normal
|
||||
condition for this scenario.
|
||||
|
||||
<legal 0 - 2>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0
|
||||
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1
|
||||
#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003
|
||||
|
||||
|
||||
/* Description RXDMA_ERROR_CODE
|
||||
|
||||
Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'.
|
||||
|
||||
|
||||
This field is ignored by REO.
|
||||
|
||||
<enum 0 rxdma_overflow_err>MPDU frame is not complete due
|
||||
to a FIFO overflow error in RXPCU.
|
||||
<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
|
||||
due to receiving incomplete MPDU from the PHY
|
||||
<enum 2 rxdma_fcs_err>FCS check on the MPDU frame failed
|
||||
|
||||
<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption error
|
||||
or CRYPTO received an encrypted frame, but did not get
|
||||
a valid corresponding key id in the peer entry.
|
||||
<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC error
|
||||
|
||||
<enum 5 rxdma_unecrypted_err>CRYPTO reported an unencrypted
|
||||
frame error when encrypted was expected
|
||||
<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU length
|
||||
error
|
||||
<enum 7 rxdma_msdu_limit_err>RX OLE reported that max number
|
||||
of MSDUs allowed in an MPDU got exceeded
|
||||
<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing error
|
||||
|
||||
<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
|
||||
parsing error
|
||||
<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
|
||||
during SA search
|
||||
<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
|
||||
during DA search
|
||||
<enum 12 rxdma_flow_timeout_err>RX OLE reported a timeout
|
||||
during flow search
|
||||
<enum 13 rxdma_flush_request>RXDMA received a flush request
|
||||
|
||||
<enum 15 rxdma_multicast_echo_err>RX OLE reported a multicast
|
||||
echo
|
||||
<enum 16 rxdma_amsdu_addr_mismatch_err>RX OLE reported an
|
||||
A-MSDU with either 'from DS = 0' with an SA mismatching
|
||||
TA or 'to DS = 0' with a DA mismatching RA.
|
||||
<enum 17 rxdma_unauthorized_wds_err>RX PCU reported that
|
||||
Rx peer entry did not indicate 'authorized_to_send_WDS'
|
||||
and also indicated 'from DS = to DS = 1.'
|
||||
<enum 18 rxdma_groupcast_amsdu_or_wds_err>RX PCU reported
|
||||
a broadcast or multicast RA as well as either A-MSDU present
|
||||
or 'from DS = to DS = 1.'
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2
|
||||
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6
|
||||
#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c
|
||||
|
||||
|
||||
/* Description MPDU_FRAGMENT_NUMBER
|
||||
|
||||
Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag
|
||||
is set.
|
||||
|
||||
The fragment number from the 802.11 header.
|
||||
|
||||
Note that the sequence number is embedded in the field:
|
||||
Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7
|
||||
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10
|
||||
#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
|
||||
|
||||
|
||||
/* Description SW_EXCEPTION
|
||||
|
||||
When not set, REO is performing all its default MPDU processing
|
||||
operations,
|
||||
When set, this REO entrance descriptor is generated by FW,
|
||||
and should be processed as an exception. This implies:
|
||||
NO re-order function is needed.
|
||||
MPDU delinking is determined by the setting of field SW_excection_mpdu_delink
|
||||
|
||||
Destination ring selection is based on the setting of the
|
||||
field SW_exception_destination_ring_valid
|
||||
In the destination ring descriptor set bit: SW_exception_entry
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800
|
||||
|
||||
|
||||
/* Description SW_EXCEPTION_MPDU_DELINK
|
||||
|
||||
Field only valid when SW_exception is set.
|
||||
1'b0: REO should NOT delink the MPDU, and thus pass this
|
||||
MPDU on to the destination ring as is. This implies that
|
||||
in the REO_DESTINATION_RING struct field Buf_or_link_desc_addr_info
|
||||
should point to an MSDU link descriptor
|
||||
1'b1: REO should perform the normal MPDU delink into MSDU
|
||||
operations.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
|
||||
|
||||
|
||||
/* Description SW_EXCEPTION_DESTINATION_RING_VALID
|
||||
|
||||
Field only valid when SW_exception is set.
|
||||
1'b0: REO shall push the MPDU (or delinked MPDU based on
|
||||
the setting of SW_exception_mpdu_delink) to the destination
|
||||
ring according to field reo_destination_indication.
|
||||
1'b1: REO shall push the MPDU (or delinked MPDU based on
|
||||
the setting of SW_exception_mpdu_delink) to the destination
|
||||
ring according to field SW_exception_destination_ring.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
|
||||
|
||||
|
||||
/* Description SW_EXCEPTION_DESTINATION_RING
|
||||
|
||||
Field only valid when fields SW_exception and SW_exception_destination_ring_valid
|
||||
are set.
|
||||
The ID of the ring where REO shall push this frame.
|
||||
<enum 0 reo_destination_sw0> Reo will push the frame into
|
||||
the REO2SW0 ring
|
||||
<enum 1 reo_destination_sw1> Reo will push the frame into
|
||||
the REO2SW1 ring
|
||||
<enum 2 reo_destination_sw2> Reo will push the frame into
|
||||
the REO2SW1 ring
|
||||
<enum 3 reo_destination_sw3> Reo will push the frame into
|
||||
the REO2SW1 ring
|
||||
<enum 4 reo_destination_sw4> Reo will push the frame into
|
||||
the REO2SW1 ring
|
||||
<enum 5 reo_destination_release> Reo will push the frame
|
||||
into the REO_release ring
|
||||
<enum 6 reo_destination_fw> Reo will push the frame into
|
||||
the REO2FW ring
|
||||
<enum 7 reo_destination_sw5> REO remaps this
|
||||
<enum 8 reo_destination_sw6> REO remaps this
|
||||
<enum 9 reo_destination_sw7> REO remaps this
|
||||
<enum 10 reo_destination_sw8> REO remaps this
|
||||
<enum 11 reo_destination_11> REO remaps this
|
||||
<enum 12 reo_destination_12> REO remaps this <enum 13 reo_destination_13>
|
||||
REO remaps this
|
||||
<enum 14 reo_destination_14> REO remaps this
|
||||
<enum 15 reo_destination_15> REO remaps this
|
||||
<enum 16 reo_destination_16> REO remaps this
|
||||
<enum 17 reo_destination_17> REO remaps this
|
||||
<enum 18 reo_destination_18> REO remaps this
|
||||
<enum 19 reo_destination_19> REO remaps this
|
||||
<enum 20 reo_destination_20> REO remaps this
|
||||
<enum 21 reo_destination_21> REO remaps this
|
||||
<enum 22 reo_destination_22> REO remaps this
|
||||
<enum 23 reo_destination_23> REO remaps this
|
||||
<enum 24 reo_destination_24> REO remaps this
|
||||
<enum 25 reo_destination_25> REO remaps this
|
||||
<enum 26 reo_destination_26> REO remaps this
|
||||
<enum 27 reo_destination_27> REO remaps this
|
||||
<enum 28 reo_destination_28> REO remaps this
|
||||
<enum 29 reo_destination_29> REO remaps this
|
||||
<enum 30 reo_destination_30> REO remaps this
|
||||
<enum 31 reo_destination_31> REO remaps this
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18
|
||||
#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
|
||||
|
||||
|
||||
/* Description MPDU_SEQUENCE_NUMBER
|
||||
|
||||
Consumer: REO/SW/FW
|
||||
Producer: RXDMA
|
||||
|
||||
The field can have two different meanings based on the setting
|
||||
of sub-field Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.BAR_frame:
|
||||
|
||||
|
||||
'BAR_frame' is NOT set:
|
||||
The MPDU sequence number of the received frame.
|
||||
|
||||
'BAR_frame' is set.
|
||||
The MPDU Start sequence number from the BAR frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19
|
||||
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30
|
||||
#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000
|
||||
|
||||
|
||||
/* Description RESERVED_6A
|
||||
|
||||
Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.
|
||||
Mpdu_qos_control_valid is set
|
||||
|
||||
This indicates whether the 'Ack policy' field within the
|
||||
QoS control field of the MPDU indicates 'no-Ack.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018
|
||||
#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31
|
||||
#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31
|
||||
#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000
|
||||
|
||||
|
||||
/* Description PHY_PPDU_ID
|
||||
|
||||
A PPDU counter value that PHY increments for every PPDU
|
||||
received
|
||||
The counter value wraps around. RXDMA can be configured
|
||||
to copy this from the RX_PPDU_START TLV for every output
|
||||
descriptor.
|
||||
|
||||
This field is ignored by REO.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c
|
||||
#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0
|
||||
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15
|
||||
#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff
|
||||
|
||||
|
||||
/* Description SRC_LINK_ID
|
||||
|
||||
Consumer: SW
|
||||
Producer: RXDMA
|
||||
|
||||
Set to the link ID of the PMAC that received the frame
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c
|
||||
#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16
|
||||
#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18
|
||||
#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000
|
||||
|
||||
|
||||
|
||||
#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c
|
||||
#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19
|
||||
#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19
|
||||
#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000
|
||||
|
||||
|
||||
/* Description RING_ID
|
||||
|
||||
Consumer: SW/REO/DEBUG
|
||||
Producer: SRNG (of RXDMA)
|
||||
|
||||
For debugging.
|
||||
This field is filled in by the SRNG module.
|
||||
It help to identify the ring that is being looked <legal
|
||||
all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c
|
||||
#define REO_ENTRANCE_RING_RING_ID_LSB 20
|
||||
#define REO_ENTRANCE_RING_RING_ID_MSB 27
|
||||
#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
Consumer: SW/REO/DEBUG
|
||||
Producer: SRNG (of RXDMA)
|
||||
|
||||
For debugging.
|
||||
This field is filled in by the SRNG module.
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into this Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c
|
||||
#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28
|
||||
#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31
|
||||
#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_ENTRANCE_RING
|
||||
394
hw/qcn6432/reo_flush_cache.h
Archivo normal
394
hw/qcn6432/reo_flush_cache.h
Archivo normal
@@ -0,0 +1,394 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_FLUSH_CACHE_H_
|
||||
#define _REO_FLUSH_CACHE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_cmd_header.h"
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10
|
||||
|
||||
#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5
|
||||
|
||||
|
||||
struct reo_flush_cache {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t flush_addr_31_0 : 32; // [31:0]
|
||||
uint32_t flush_addr_39_32 : 8, // [7:0]
|
||||
forward_all_mpdus_in_queue : 1, // [8:8]
|
||||
release_cache_block_index : 1, // [9:9]
|
||||
cache_block_resource_index : 2, // [11:10]
|
||||
flush_without_invalidate : 1, // [12:12]
|
||||
block_cache_usage_after_flush : 1, // [13:13]
|
||||
flush_entire_cache : 1, // [14:14]
|
||||
flush_queue_1k_desc : 1, // [15:15]
|
||||
reserved_2b : 16; // [31:16]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t flush_addr_31_0 : 32; // [31:0]
|
||||
uint32_t reserved_2b : 16, // [31:16]
|
||||
flush_queue_1k_desc : 1, // [15:15]
|
||||
flush_entire_cache : 1, // [14:14]
|
||||
block_cache_usage_after_flush : 1, // [13:13]
|
||||
flush_without_invalidate : 1, // [12:12]
|
||||
cache_block_resource_index : 2, // [11:10]
|
||||
release_cache_block_index : 1, // [9:9]
|
||||
forward_all_mpdus_in_queue : 1, // [8:8]
|
||||
flush_addr_39_32 : 8; // [7:0]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description CMD_HEADER
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
Details for command execution tracking purposes.
|
||||
*/
|
||||
|
||||
|
||||
/* Description REO_CMD_NUMBER
|
||||
|
||||
Consumer: REO/SW/DEBUG
|
||||
Producer: SW
|
||||
|
||||
This number can be used by SW to track, identify and link
|
||||
the created commands with the command statusses
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description REO_STATUS_REQUIRED
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
<enum 0 NoStatus> REO does not need to generate a status
|
||||
TLV for the execution of this command
|
||||
<enum 1 StatusRequired> REO shall generate a status TLV
|
||||
for the execution of this command
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
|
||||
#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
|
||||
|
||||
|
||||
/* Description FLUSH_ADDR_31_0
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
Address (lower 32 bits) of the descriptor to flush
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description FLUSH_ADDR_39_32
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
Address (upper 8 bits) of the descriptor to flush
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7
|
||||
#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description FORWARD_ALL_MPDUS_IN_QUEUE
|
||||
|
||||
Is only allowed to be set when the flush address corresponds
|
||||
with a REO descriptor.
|
||||
|
||||
When set, REO shall first forward all the MPDUs held in
|
||||
the indicated re-order queue, before flushing the descriptor
|
||||
from the cache.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
|
||||
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8
|
||||
#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100
|
||||
|
||||
|
||||
/* Description RELEASE_CACHE_BLOCK_INDEX
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
If SW has previously used a blocking resource that it now
|
||||
wants to re-use for this command, this bit shall be set.
|
||||
It prevents SW from having to send a separate REO_UNBLOCK_CACHE
|
||||
command.
|
||||
|
||||
When set, HW will first release the blocking resource (indicated
|
||||
in field 'Cache_block_resouce_index') before this command
|
||||
gets executed.
|
||||
If that resource was already unblocked, this will be considered
|
||||
an error. This command will not be executed, and an error
|
||||
shall be returned.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9
|
||||
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9
|
||||
#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200
|
||||
|
||||
|
||||
/* Description CACHE_BLOCK_RESOURCE_INDEX
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
Indicates which of the four blocking resources in REO will
|
||||
be assigned for managing the blocking of this (descriptor)
|
||||
address
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
|
||||
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11
|
||||
#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00
|
||||
|
||||
|
||||
/* Description FLUSH_WITHOUT_INVALIDATE
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
When set, REO shall flush the cache line contents from the
|
||||
cache, but there is NO need to invalidate the cache line
|
||||
entry... The contents in the cache can be maintained. This
|
||||
feature can be used by SW (and DV) to get a current snapshot
|
||||
of the contents in the cache
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12
|
||||
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12
|
||||
#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000
|
||||
|
||||
|
||||
/* Description BLOCK_CACHE_USAGE_AFTER_FLUSH
|
||||
|
||||
Field not valid when Flush_entire_cache is set.
|
||||
|
||||
When set, REO shall block any cache accesses to this address
|
||||
till explicitly unblocked.
|
||||
|
||||
Whenever SW sets this bit, SW shall also set bit 'Forward_all_mpdus_in_queue'
|
||||
to ensure all packets are flushed out in order to make sure
|
||||
this queue desc is not in one of the aging link lists.
|
||||
In case SW does not want to flush the MPDUs in the queue,
|
||||
see the recipe description below this TLV definition.
|
||||
|
||||
The 'blocking' index to be used for this is indicated in
|
||||
field 'cache_block_resource_index'. If SW had previously
|
||||
used this blocking resource and was not freed up yet, SW
|
||||
shall first unblock that index (by setting bit Release_cache_block_index)
|
||||
or use an unblock command.
|
||||
|
||||
If the resource indicated here was already blocked (and
|
||||
did not get unblocked in this command), it is considered
|
||||
an error scenario...
|
||||
No flush shall happen. The status for this command shall
|
||||
indicate error.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
|
||||
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13
|
||||
#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000
|
||||
|
||||
|
||||
/* Description FLUSH_ENTIRE_CACHE
|
||||
|
||||
When set, the entire cache shall be flushed. The entire
|
||||
cache will also remain blocked, till the 'REO_UNBLOCK_COMMAND'
|
||||
is received with bit unblock type set to unblock_cache.
|
||||
All other fields in this command are to be ignored.
|
||||
|
||||
Note that flushing the entire cache has no changes to the
|
||||
current settings of the blocking resource settings
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14
|
||||
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14
|
||||
#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000
|
||||
|
||||
|
||||
/* Description FLUSH_QUEUE_1K_DESC
|
||||
|
||||
When set, REO will flush the 'RX_REO_QUEUE_1K' descriptor
|
||||
after flushing the 'RX_REO_QUEUE' descriptor.
|
||||
|
||||
This bit shall only be set when the BA_window_size > 255
|
||||
in 'RX_REO_QUEUE.'
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15
|
||||
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15
|
||||
#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000
|
||||
|
||||
|
||||
/* Description RESERVED_2B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16
|
||||
#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31
|
||||
#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32
|
||||
#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63
|
||||
#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31
|
||||
#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32
|
||||
#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63
|
||||
#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31
|
||||
#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32
|
||||
#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63
|
||||
#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31
|
||||
#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32
|
||||
#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63
|
||||
#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_FLUSH_CACHE
|
||||
646
hw/qcn6432/reo_flush_cache_status.h
Archivo normal
646
hw/qcn6432/reo_flush_cache_status.h
Archivo normal
@@ -0,0 +1,646 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_FLUSH_CACHE_STATUS_H_
|
||||
#define _REO_FLUSH_CACHE_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26
|
||||
|
||||
#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13
|
||||
|
||||
|
||||
struct reo_flush_cache_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t error_detected : 1, // [0:0]
|
||||
block_error_details : 2, // [2:1]
|
||||
reserved_2a : 5, // [7:3]
|
||||
cache_controller_flush_status_hit : 1, // [8:8]
|
||||
cache_controller_flush_status_desc_type : 3, // [11:9]
|
||||
cache_controller_flush_status_client_id : 4, // [15:12]
|
||||
cache_controller_flush_status_error : 2, // [17:16]
|
||||
cache_controller_flush_count : 8, // [25:18]
|
||||
flush_queue_1k_desc : 1, // [26:26]
|
||||
reserved_2b : 5; // [31:27]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t reserved_9a : 32; // [31:0]
|
||||
uint32_t reserved_10a : 32; // [31:0]
|
||||
uint32_t reserved_11a : 32; // [31:0]
|
||||
uint32_t reserved_12a : 32; // [31:0]
|
||||
uint32_t reserved_13a : 32; // [31:0]
|
||||
uint32_t reserved_14a : 32; // [31:0]
|
||||
uint32_t reserved_15a : 32; // [31:0]
|
||||
uint32_t reserved_16a : 32; // [31:0]
|
||||
uint32_t reserved_17a : 32; // [31:0]
|
||||
uint32_t reserved_18a : 32; // [31:0]
|
||||
uint32_t reserved_19a : 32; // [31:0]
|
||||
uint32_t reserved_20a : 32; // [31:0]
|
||||
uint32_t reserved_21a : 32; // [31:0]
|
||||
uint32_t reserved_22a : 32; // [31:0]
|
||||
uint32_t reserved_23a : 32; // [31:0]
|
||||
uint32_t reserved_24a : 32; // [31:0]
|
||||
uint32_t reserved_25a : 28, // [27:0]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t reserved_2b : 5, // [31:27]
|
||||
flush_queue_1k_desc : 1, // [26:26]
|
||||
cache_controller_flush_count : 8, // [25:18]
|
||||
cache_controller_flush_status_error : 2, // [17:16]
|
||||
cache_controller_flush_status_client_id : 4, // [15:12]
|
||||
cache_controller_flush_status_desc_type : 3, // [11:9]
|
||||
cache_controller_flush_status_hit : 1, // [8:8]
|
||||
reserved_2a : 5, // [7:3]
|
||||
block_error_details : 2, // [2:1]
|
||||
error_detected : 1; // [0:0]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t reserved_9a : 32; // [31:0]
|
||||
uint32_t reserved_10a : 32; // [31:0]
|
||||
uint32_t reserved_11a : 32; // [31:0]
|
||||
uint32_t reserved_12a : 32; // [31:0]
|
||||
uint32_t reserved_13a : 32; // [31:0]
|
||||
uint32_t reserved_14a : 32; // [31:0]
|
||||
uint32_t reserved_15a : 32; // [31:0]
|
||||
uint32_t reserved_16a : 32; // [31:0]
|
||||
uint32_t reserved_17a : 32; // [31:0]
|
||||
uint32_t reserved_18a : 32; // [31:0]
|
||||
uint32_t reserved_19a : 32; // [31:0]
|
||||
uint32_t reserved_20a : 32; // [31:0]
|
||||
uint32_t reserved_21a : 32; // [31:0]
|
||||
uint32_t reserved_22a : 32; // [31:0]
|
||||
uint32_t reserved_23a : 32; // [31:0]
|
||||
uint32_t reserved_24a : 32; // [31:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
reserved_25a : 28; // [27:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STATUS_HEADER
|
||||
|
||||
Consumer: SW
|
||||
Producer: REO
|
||||
|
||||
Details that can link this status with the original command.
|
||||
It also contains info on how long REO took to execute this
|
||||
command.
|
||||
*/
|
||||
|
||||
|
||||
/* Description REO_STATUS_NUMBER
|
||||
|
||||
Consumer: SW , DEBUG
|
||||
Producer: REO
|
||||
|
||||
The value in this field is equal to value of the 'REO_CMD_Number'
|
||||
field the REO command
|
||||
|
||||
This field helps to correlate the statuses with the REO
|
||||
commands.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description CMD_EXECUTION_TIME
|
||||
|
||||
Consumer: DEBUG
|
||||
Producer: REO
|
||||
|
||||
The amount of time REO took to excecute the command. Note
|
||||
that this time does not include the duration of the command
|
||||
waiting in the command ring, before the execution started.
|
||||
|
||||
|
||||
In us.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
|
||||
|
||||
|
||||
/* Description REO_CMD_EXECUTION_STATUS
|
||||
|
||||
Consumer: DEBUG
|
||||
Producer: REO
|
||||
|
||||
Execution status of the command.
|
||||
|
||||
<enum 0 reo_successful_execution> Command has successfully
|
||||
be executed
|
||||
<enum 1 reo_blocked_execution> Command could not be executed
|
||||
as the queue or cache was blocked
|
||||
<enum 2 reo_failed_execution> Command has encountered problems
|
||||
when executing, like the queue descriptor not being valid.
|
||||
None of the status fields in the entire STATUS TLV are valid.
|
||||
|
||||
<enum 3 reo_resource_blocked> Command is NOT executed because
|
||||
one or more descriptors were blocked. This is SW programming
|
||||
mistake.
|
||||
None of the status fields in the entire STATUS TLV are valid.
|
||||
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
|
||||
|
||||
|
||||
/* Description TIMESTAMP
|
||||
|
||||
Timestamp at the moment that this status report is written.
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description ERROR_DETECTED
|
||||
|
||||
Status for blocking resource handling
|
||||
|
||||
0: No error has been detected while executing this command
|
||||
|
||||
1: an error in the blocking resource management was detected
|
||||
|
||||
See field 'Block_error_details'
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description BLOCK_ERROR_DETAILS
|
||||
|
||||
Field only valid when 'Error_detected' is set.
|
||||
0: no blocking related error found
|
||||
1: blocking resource was already in use
|
||||
2: resource that was asked to be unblocked, was not blocked
|
||||
|
||||
<legal 0-2>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1
|
||||
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2
|
||||
#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006
|
||||
|
||||
|
||||
/* Description RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8
|
||||
|
||||
|
||||
/* Description CACHE_CONTROLLER_FLUSH_STATUS_HIT
|
||||
|
||||
The status that the cache controller returned for executing
|
||||
the flush command
|
||||
|
||||
descriptor hit
|
||||
1 = hit
|
||||
0 = miss
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100
|
||||
|
||||
|
||||
/* Description CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE
|
||||
|
||||
The status that the cache controller returned for executing
|
||||
the flush command
|
||||
Descriptor type
|
||||
FLOW_QUEUE_DESCRIPTOR 3'd0
|
||||
MPDU_LINK_DESCRIPTOR 3'd4
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00
|
||||
|
||||
|
||||
/* Description CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID
|
||||
|
||||
The status that the cache controller returned for executing
|
||||
the flush command
|
||||
|
||||
client ID
|
||||
Module who made flush the request
|
||||
|
||||
In REO, this is always set to 0
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000
|
||||
|
||||
|
||||
/* Description CACHE_CONTROLLER_FLUSH_STATUS_ERROR
|
||||
|
||||
The status that the cache controller returned for executing
|
||||
the flush command
|
||||
|
||||
Error condition
|
||||
2'b00: No error found
|
||||
2'b01: HW IF still busy
|
||||
2'b10: Line is currently locked. Used for the one line flush
|
||||
command.
|
||||
2'b11: At least one line is currently still locked. Used
|
||||
for the cache flush command.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000
|
||||
|
||||
|
||||
/* Description CACHE_CONTROLLER_FLUSH_COUNT
|
||||
|
||||
The number of lines that were actually flushed out.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25
|
||||
#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000
|
||||
|
||||
|
||||
/* Description FLUSH_QUEUE_1K_DESC
|
||||
|
||||
When set, REO has flushed the 'RX_REO_QUEUE_1K' descriptor
|
||||
after flushing the 'RX_REO_QUEUE' descriptor.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26
|
||||
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26
|
||||
#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000
|
||||
|
||||
|
||||
/* Description RESERVED_2B
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_25A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59
|
||||
#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into this Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
|
||||
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60
|
||||
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63
|
||||
#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_FLUSH_CACHE_STATUS
|
||||
272
hw/qcn6432/reo_flush_queue.h
Archivo normal
272
hw/qcn6432/reo_flush_queue.h
Archivo normal
@@ -0,0 +1,272 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_FLUSH_QUEUE_H_
|
||||
#define _REO_FLUSH_QUEUE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_cmd_header.h"
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10
|
||||
|
||||
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5
|
||||
|
||||
|
||||
struct reo_flush_queue {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t flush_desc_addr_31_0 : 32; // [31:0]
|
||||
uint32_t flush_desc_addr_39_32 : 8, // [7:0]
|
||||
block_desc_addr_usage_after_flush : 1, // [8:8]
|
||||
block_resource_index : 2, // [10:9]
|
||||
reserved_2a : 21; // [31:11]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t flush_desc_addr_31_0 : 32; // [31:0]
|
||||
uint32_t reserved_2a : 21, // [31:11]
|
||||
block_resource_index : 2, // [10:9]
|
||||
block_desc_addr_usage_after_flush : 1, // [8:8]
|
||||
flush_desc_addr_39_32 : 8; // [7:0]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description CMD_HEADER
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
Details for command execution tracking purposes.
|
||||
*/
|
||||
|
||||
|
||||
/* Description REO_CMD_NUMBER
|
||||
|
||||
Consumer: REO/SW/DEBUG
|
||||
Producer: SW
|
||||
|
||||
This number can be used by SW to track, identify and link
|
||||
the created commands with the command statusses
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description REO_STATUS_REQUIRED
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
<enum 0 NoStatus> REO does not need to generate a status
|
||||
TLV for the execution of this command
|
||||
<enum 1 StatusRequired> REO shall generate a status TLV
|
||||
for the execution of this command
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
|
||||
|
||||
|
||||
/* Description FLUSH_DESC_ADDR_31_0
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
Address (lower 32 bits) of the descriptor to flush
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description FLUSH_DESC_ADDR_39_32
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
Address (upper 8 bits) of the descriptor to flush
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7
|
||||
#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff
|
||||
|
||||
|
||||
/* Description BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
|
||||
|
||||
When set, REO shall not re-fetch this address till SW explicitly
|
||||
unblocked this address
|
||||
|
||||
If the blocking resource was already used, this command
|
||||
shall fail and an error is reported
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
|
||||
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8
|
||||
#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100
|
||||
|
||||
|
||||
/* Description BLOCK_RESOURCE_INDEX
|
||||
|
||||
Field only valid when 'Block_desc_addr_usage_after_flush
|
||||
' is set.
|
||||
|
||||
Indicates which of the four blocking resources in REO will
|
||||
be assigned for managing the blocking of this address.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9
|
||||
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10
|
||||
#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600
|
||||
|
||||
|
||||
/* Description RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11
|
||||
#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32
|
||||
#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63
|
||||
#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_FLUSH_QUEUE
|
||||
503
hw/qcn6432/reo_flush_queue_status.h
Archivo normal
503
hw/qcn6432/reo_flush_queue_status.h
Archivo normal
@@ -0,0 +1,503 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_FLUSH_QUEUE_STATUS_H_
|
||||
#define _REO_FLUSH_QUEUE_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_status_header.h"
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26
|
||||
|
||||
#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13
|
||||
|
||||
|
||||
struct reo_flush_queue_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t error_detected : 1, // [0:0]
|
||||
reserved_2a : 31; // [31:1]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t reserved_9a : 32; // [31:0]
|
||||
uint32_t reserved_10a : 32; // [31:0]
|
||||
uint32_t reserved_11a : 32; // [31:0]
|
||||
uint32_t reserved_12a : 32; // [31:0]
|
||||
uint32_t reserved_13a : 32; // [31:0]
|
||||
uint32_t reserved_14a : 32; // [31:0]
|
||||
uint32_t reserved_15a : 32; // [31:0]
|
||||
uint32_t reserved_16a : 32; // [31:0]
|
||||
uint32_t reserved_17a : 32; // [31:0]
|
||||
uint32_t reserved_18a : 32; // [31:0]
|
||||
uint32_t reserved_19a : 32; // [31:0]
|
||||
uint32_t reserved_20a : 32; // [31:0]
|
||||
uint32_t reserved_21a : 32; // [31:0]
|
||||
uint32_t reserved_22a : 32; // [31:0]
|
||||
uint32_t reserved_23a : 32; // [31:0]
|
||||
uint32_t reserved_24a : 32; // [31:0]
|
||||
uint32_t reserved_25a : 28, // [27:0]
|
||||
looping_count : 4; // [31:28]
|
||||
#else
|
||||
struct uniform_reo_status_header status_header;
|
||||
uint32_t reserved_2a : 31, // [31:1]
|
||||
error_detected : 1; // [0:0]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t reserved_9a : 32; // [31:0]
|
||||
uint32_t reserved_10a : 32; // [31:0]
|
||||
uint32_t reserved_11a : 32; // [31:0]
|
||||
uint32_t reserved_12a : 32; // [31:0]
|
||||
uint32_t reserved_13a : 32; // [31:0]
|
||||
uint32_t reserved_14a : 32; // [31:0]
|
||||
uint32_t reserved_15a : 32; // [31:0]
|
||||
uint32_t reserved_16a : 32; // [31:0]
|
||||
uint32_t reserved_17a : 32; // [31:0]
|
||||
uint32_t reserved_18a : 32; // [31:0]
|
||||
uint32_t reserved_19a : 32; // [31:0]
|
||||
uint32_t reserved_20a : 32; // [31:0]
|
||||
uint32_t reserved_21a : 32; // [31:0]
|
||||
uint32_t reserved_22a : 32; // [31:0]
|
||||
uint32_t reserved_23a : 32; // [31:0]
|
||||
uint32_t reserved_24a : 32; // [31:0]
|
||||
uint32_t looping_count : 4, // [31:28]
|
||||
reserved_25a : 28; // [27:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description STATUS_HEADER
|
||||
|
||||
Consumer: SW
|
||||
Producer: REO
|
||||
|
||||
Details that can link this status with the original command.
|
||||
It also contains info on how long REO took to execute this
|
||||
command.
|
||||
*/
|
||||
|
||||
|
||||
/* Description REO_STATUS_NUMBER
|
||||
|
||||
Consumer: SW , DEBUG
|
||||
Producer: REO
|
||||
|
||||
The value in this field is equal to value of the 'REO_CMD_Number'
|
||||
field the REO command
|
||||
|
||||
This field helps to correlate the statuses with the REO
|
||||
commands.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description CMD_EXECUTION_TIME
|
||||
|
||||
Consumer: DEBUG
|
||||
Producer: REO
|
||||
|
||||
The amount of time REO took to excecute the command. Note
|
||||
that this time does not include the duration of the command
|
||||
waiting in the command ring, before the execution started.
|
||||
|
||||
|
||||
In us.
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000
|
||||
|
||||
|
||||
/* Description REO_CMD_EXECUTION_STATUS
|
||||
|
||||
Consumer: DEBUG
|
||||
Producer: REO
|
||||
|
||||
Execution status of the command.
|
||||
|
||||
<enum 0 reo_successful_execution> Command has successfully
|
||||
be executed
|
||||
<enum 1 reo_blocked_execution> Command could not be executed
|
||||
as the queue or cache was blocked
|
||||
<enum 2 reo_failed_execution> Command has encountered problems
|
||||
when executing, like the queue descriptor not being valid.
|
||||
None of the status fields in the entire STATUS TLV are valid.
|
||||
|
||||
<enum 3 reo_resource_blocked> Command is NOT executed because
|
||||
one or more descriptors were blocked. This is SW programming
|
||||
mistake.
|
||||
None of the status fields in the entire STATUS TLV are valid.
|
||||
|
||||
|
||||
<legal 0-3>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000
|
||||
|
||||
|
||||
/* Description TIMESTAMP
|
||||
|
||||
Timestamp at the moment that this status report is written.
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description ERROR_DETECTED
|
||||
|
||||
Status of the blocking resource
|
||||
0: No error has been detected while executing this command
|
||||
|
||||
1: Error detected: The resource to be used for blocking
|
||||
was already in use.
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001
|
||||
|
||||
|
||||
/* Description RESERVED_2A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_9A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_10A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_11A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_12A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_13A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_14A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_15A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_16A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_17A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_18A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_19A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_20A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_21A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_22A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_23A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_24A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_25A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59
|
||||
#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000
|
||||
|
||||
|
||||
/* Description LOOPING_COUNT
|
||||
|
||||
A count value that indicates the number of times the producer
|
||||
of entries into this Ring has looped around the ring.
|
||||
At initialization time, this value is set to 0. On the first
|
||||
loop, this value is set to 1. After the max value is reached
|
||||
allowed by the number of bits for this field, the count
|
||||
value continues with 0 again.
|
||||
|
||||
In case SW is the consumer of the ring entries, it can use
|
||||
this field to figure out up to where the producer of entries
|
||||
has created new entries. This eliminates the need to check
|
||||
where the "head pointer' of the ring is located once the
|
||||
SW starts processing an interrupt indicating that new entries
|
||||
have been put into this ring...
|
||||
|
||||
Also note that SW if it wants only needs to look at the
|
||||
LSB bit of this count value.
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060
|
||||
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60
|
||||
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63
|
||||
#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_FLUSH_QUEUE_STATUS
|
||||
279
hw/qcn6432/reo_flush_timeout_list.h
Archivo normal
279
hw/qcn6432/reo_flush_timeout_list.h
Archivo normal
@@ -0,0 +1,279 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
|
||||
#define _REO_FLUSH_TIMEOUT_LIST_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "uniform_reo_cmd_header.h"
|
||||
#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10
|
||||
|
||||
#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5
|
||||
|
||||
|
||||
struct reo_flush_timeout_list {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t ac_timout_list : 2, // [1:0]
|
||||
reserved_1 : 30; // [31:2]
|
||||
uint32_t minimum_release_desc_count : 16, // [15:0]
|
||||
minimum_forward_buf_count : 16; // [31:16]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#else
|
||||
struct uniform_reo_cmd_header cmd_header;
|
||||
uint32_t reserved_1 : 30, // [31:2]
|
||||
ac_timout_list : 2; // [1:0]
|
||||
uint32_t minimum_forward_buf_count : 16, // [31:16]
|
||||
minimum_release_desc_count : 16; // [15:0]
|
||||
uint32_t reserved_3a : 32; // [31:0]
|
||||
uint32_t reserved_4a : 32; // [31:0]
|
||||
uint32_t reserved_5a : 32; // [31:0]
|
||||
uint32_t reserved_6a : 32; // [31:0]
|
||||
uint32_t reserved_7a : 32; // [31:0]
|
||||
uint32_t reserved_8a : 32; // [31:0]
|
||||
uint32_t tlv64_padding : 32; // [31:0]
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
/* Description CMD_HEADER
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
Details for command execution tracking purposes.
|
||||
*/
|
||||
|
||||
|
||||
/* Description REO_CMD_NUMBER
|
||||
|
||||
Consumer: REO/SW/DEBUG
|
||||
Producer: SW
|
||||
|
||||
This number can be used by SW to track, identify and link
|
||||
the created commands with the command statusses
|
||||
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description REO_STATUS_REQUIRED
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
<enum 0 NoStatus> REO does not need to generate a status
|
||||
TLV for the execution of this command
|
||||
<enum 1 StatusRequired> REO shall generate a status TLV
|
||||
for the execution of this command
|
||||
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000
|
||||
|
||||
|
||||
/* Description RESERVED_0A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31
|
||||
#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000
|
||||
|
||||
|
||||
/* Description AC_TIMOUT_LIST
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
The AC_timeout list to be used for this command
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32
|
||||
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33
|
||||
#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000
|
||||
|
||||
|
||||
/* Description RESERVED_1
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000
|
||||
|
||||
|
||||
/* Description MINIMUM_RELEASE_DESC_COUNT
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
The minimum number of link descriptors requested to be released.
|
||||
If set to 0, only buffer release counts seems to be important...
|
||||
When set to very high value, likely the entire timeout list
|
||||
will be exhausted before this count is reached or maybe
|
||||
this count will not get reached. REO however will stop
|
||||
here as it can not do anything else.
|
||||
|
||||
When both this field and field Minimum_forward_buf_count
|
||||
are > 0, REO needs to meet both requirements. When both
|
||||
entries are 0 (which should be a programming error), REO
|
||||
does not need to do anything.
|
||||
|
||||
Note that this includes counts of MPDU link Desc as well
|
||||
as MSDU link Desc. Where the count of MSDU link Desc is
|
||||
not known to REO it's approximated by deriving from MSDU
|
||||
count
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff
|
||||
|
||||
|
||||
/* Description MINIMUM_FORWARD_BUF_COUNT
|
||||
|
||||
Consumer: REO
|
||||
Producer: SW
|
||||
|
||||
The minimum number of buffer descriptors requested to be
|
||||
passed on to the REO destination rings.
|
||||
|
||||
If set to 0, only descriptor release counts seems to be
|
||||
important...
|
||||
|
||||
When set to very high value, likely the entire timeout list
|
||||
will be exhausted before this count is reached or maybe
|
||||
this count will not get reached. REO however will stop
|
||||
here as it can not do anything else.
|
||||
|
||||
Note that REO does not know the exact buffer count. This
|
||||
can be approximated by using the MSDU_COUNT
|
||||
<legal all>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31
|
||||
#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000
|
||||
|
||||
|
||||
/* Description RESERVED_3A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_4A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_5A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_6A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description RESERVED_7A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
/* Description RESERVED_8A
|
||||
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31
|
||||
#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff
|
||||
|
||||
|
||||
/* Description TLV64_PADDING
|
||||
|
||||
Automatic DWORD padding inserted while converting TLV32
|
||||
to TLV64 for 64 bit ARCH
|
||||
<legal 0>
|
||||
*/
|
||||
|
||||
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020
|
||||
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32
|
||||
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63
|
||||
#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
|
||||
|
||||
#endif // REO_FLUSH_TIMEOUT_LIST
|
||||
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