samsung-sm8650/android_kernel_samsung_sm8650-modules
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UPSTREAM: 11/12/19: Merge 'quic/camera-kernel.lnx.1.0' into 'quic/camera-kernel.lnx.4.0'

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* quic/camera-kernel.lnx.1.0:
  msm: camera: common: Update uapi to support custom hw features
  msm: camera: ife: calculate accurate boot timestamp at CSID SOF
  msm: camera: cpas: Update ife_rd safe lut value
  msm: camera: sensor: Remove true/false redefinitions
  msm: camera: reqmgr: Add support to modify timer for long exposure
  msm: camera: reqmgr: Add provision to obtain exposure time
  msm: camera: cpas: Fix TCSR Register programming
  msm: camera: cci: Fix cam_cci_get_subdev for conditional compilation
  msm: camera: utils: Remove deprecated clk_set_flag functions
  msm: camera: csiphy: Update DPHY combo mode sequence
  msm: camera: csiphy: Correct Dphy mission mode sequence
  msm: camera: core: Fix extraneous variable declaration
  msm: camera: icp: Remove qcom soc dependency
  msm: camera: sync: Dump fence info in case of fence exhaust
  msm: camera: icp: Use CAM_PERF for clock, bw related logs
  msm: camera: common: va_end should follow va_start
  msm: camera: common: Fix integer overflow in shift
  msm: camera: reqmgr: Remove division on uint64_t
  msm: camera: isp: Improve isp substate logging
  msm: camera: isp: Limit sof_in_epoch log to first frame
  msm: camera: jpeg: Add plane stride & slice height debug info
  msm: camera: isp: Change state immediately in flush
  msm: camera: isp: Dump isp req for cdm timeout
  msm: camera: ife: Add packing format support
  msm: camera: icp: Fix AHB, AXI voting in icp
  msm: camera: ife: Remove duplicate add to port counters
  msm: camera: csiphy: Update CPHY 3-phase registers for CSIPHY v1.2

Change-Id: I93948d5cfcf2c8dea921d34696456490abd6f1e5
Signed-off-by: Abhijit Trivedi <abhijitt@codeaurora.org>
This commit is contained in:
Abhijit Trivedi
2019-11-12 12:51:16 -08:00
parent 524b1ab1d4 f45e3dda5c
commit 9b6110b579
34 changed files with 680 additions and 503 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/cam_core/cam_context_utils.c
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@@ -481,7 +481,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx,
return rc; return rc;
put_ctx_ref: put_ctx_ref:
for (j; j >= 0; j--) for (; j >= 0; j--)
cam_context_putref(ctx); cam_context_putref(ctx);
put_ref: put_ref:
for (--i; i >= 0; i--) { for (--i; i >= 0; i--) {

7
drivers/cam_cpas/cpas_top/cam_cpastop_hw.c
View File

@@ -514,7 +514,7 @@ done:
static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
{ {
int i; int i, reg_val;
struct cam_cpas_hw_errata_wa_list *errata_wa_list = struct cam_cpas_hw_errata_wa_list *errata_wa_list =
camnoc_info->errata_wa_list; camnoc_info->errata_wa_list;
struct cam_cpas_hw_errata_wa *errata_wa = struct cam_cpas_hw_errata_wa *errata_wa =
@@ -541,8 +541,9 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
} }
if (errata_wa->enable) { if (errata_wa->enable) {
scm_io_write(errata_wa->data.reg_info.offset, reg_val = scm_io_read(errata_wa->data.reg_info.offset);
errata_wa->data.reg_info.value); reg_val |= errata_wa->data.reg_info.value;
scm_io_write(errata_wa->data.reg_info.offset, reg_val);
} }
return 0; return 0;

2
drivers/cam_cpas/cpas_top/cpastop_v480_100.h
View File

@@ -357,7 +357,7 @@ static struct cam_camnoc_specific
.value = 0x0, .value = 0x0,
}, },
.safe_lut = { .safe_lut = {
.enable = true, .enable = false,
.access_type = CAM_REG_TYPE_READ_WRITE, .access_type = CAM_REG_TYPE_READ_WRITE,
.offset = 0x1048, /* IFE_RDI_RD_SAFELUT_LOW */ .offset = 0x1048, /* IFE_RDI_RD_SAFELUT_LOW */
.value = 0x0, .value = 0x0,

39
drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c
View File

@@ -71,39 +71,6 @@ static int cam_fd_hw_soc_util_setup_regbase_indices(
return 0; return 0;
} }
static int cam_fd_soc_set_clk_flags(struct cam_hw_soc_info *soc_info)
{
int i, rc = 0;
if (soc_info->num_clk > CAM_SOC_MAX_CLK) {
CAM_ERR(CAM_FD, "Invalid num clk %d", soc_info->num_clk);
return -EINVAL;
}
/* set memcore and mem periphery logic flags to 0 */
for (i = 0; i < soc_info->num_clk; i++) {
if ((strcmp(soc_info->clk_name[i], "fd_core_clk") == 0) ||
(strcmp(soc_info->clk_name[i], "fd_core_uar_clk") ==
0)) {
rc = cam_soc_util_set_clk_flags(soc_info, i,
CLKFLAG_NORETAIN_MEM);
if (rc)
CAM_ERR(CAM_FD,
"Failed in NORETAIN_MEM i=%d, rc=%d",
i, rc);
cam_soc_util_set_clk_flags(soc_info, i,
CLKFLAG_NORETAIN_PERIPH);
if (rc)
CAM_ERR(CAM_FD,
"Failed in NORETAIN_PERIPH i=%d, rc=%d",
i, rc);
}
}
return rc;
}
void cam_fd_soc_register_write(struct cam_hw_soc_info *soc_info, void cam_fd_soc_register_write(struct cam_hw_soc_info *soc_info,
enum cam_fd_reg_base reg_base, uint32_t reg_offset, uint32_t reg_value) enum cam_fd_reg_base reg_base, uint32_t reg_offset, uint32_t reg_value)
{ {
@@ -228,12 +195,6 @@ int cam_fd_soc_init_resources(struct cam_hw_soc_info *soc_info,
return rc; return rc;
} }
rc = cam_fd_soc_set_clk_flags(soc_info);
if (rc) {
CAM_ERR(CAM_FD, "failed in set_clk_flags rc=%d", rc);
goto release_res;
}
soc_private = kzalloc(sizeof(struct cam_fd_soc_private), GFP_KERNEL); soc_private = kzalloc(sizeof(struct cam_fd_soc_private), GFP_KERNEL);
if (!soc_private) { if (!soc_private) {
rc = -ENOMEM; rc = -ENOMEM;

5
drivers/cam_icp/hfi.c
View File

@@ -11,7 +11,6 @@
#include <linux/timer.h> #include <linux/timer.h>
#include <media/cam_icp.h> #include <media/cam_icp.h>
#include <linux/iopoll.h> #include <linux/iopoll.h>
#include <soc/qcom/socinfo.h>
#include "cam_io_util.h" #include "cam_io_util.h"
#include "hfi_reg.h" #include "hfi_reg.h"
@@ -20,7 +19,6 @@
#include "hfi_intf.h" #include "hfi_intf.h"
#include "cam_icp_hw_mgr_intf.h" #include "cam_icp_hw_mgr_intf.h"
#include "cam_debug_util.h" #include "cam_debug_util.h"
#include "cam_soc_util.h"
#define HFI_VERSION_INFO_MAJOR_VAL 1 #define HFI_VERSION_INFO_MAJOR_VAL 1
#define HFI_VERSION_INFO_MINOR_VAL 1 #define HFI_VERSION_INFO_MINOR_VAL 1
@@ -681,7 +679,7 @@ int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem,
struct hfi_qtbl *qtbl; struct hfi_qtbl *qtbl;
struct hfi_qtbl_hdr *qtbl_hdr; struct hfi_qtbl_hdr *qtbl_hdr;
struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr; struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr;
uint32_t hw_version, soc_version, fw_version, status = 0; uint32_t hw_version, fw_version, status = 0;
uint32_t retry_cnt = 0; uint32_t retry_cnt = 0;
struct sfr_buf *sfr_buffer; struct sfr_buf *sfr_buffer;
@@ -703,7 +701,6 @@ int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem,
memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map)); memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map));
g_hfi->hfi_state = HFI_DEINIT; g_hfi->hfi_state = HFI_DEINIT;
soc_version = socinfo_get_version();
if (debug) { if (debug) {
cam_io_w_mb( cam_io_w_mb(
(uint32_t)(ICP_FLAG_CSR_A5_EN | ICP_FLAG_CSR_WAKE_UP_EN | (uint32_t)(ICP_FLAG_CSR_A5_EN | ICP_FLAG_CSR_WAKE_UP_EN |

16
drivers/cam_icp/icp_hw/bps_hw/bps_core.c
View File

@@ -40,7 +40,7 @@ static int cam_bps_cpas_vote(struct cam_bps_device_core_info *core_info,
&cpas_vote->axi_vote); &cpas_vote->axi_vote);
if (rc < 0) if (rc < 0)
CAM_ERR(CAM_ICP, "cpas vote is failed: %d", rc); CAM_ERR(CAM_PERF, "cpas vote is failed: %d", rc);
return rc; return rc;
} }
@@ -171,7 +171,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
hw_info->pwr_ctrl, true, 0x1); hw_info->pwr_ctrl, true, 0x1);
if ((pwr_status >> BPS_PWR_ON_MASK)) if ((pwr_status >> BPS_PWR_ON_MASK))
CAM_WARN(CAM_ICP, "BPS: pwr_status(%x):pwr_ctrl(%x)", CAM_WARN(CAM_PERF, "BPS: pwr_status(%x):pwr_ctrl(%x)",
pwr_status, pwr_ctrl); pwr_status, pwr_ctrl);
} }
cam_bps_get_gdsc_control(soc_info); cam_bps_get_gdsc_control(soc_info);
@@ -181,7 +181,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev)
cam_cpas_reg_read(core_info->cpas_handle, cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status); true, &pwr_status);
CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status); pwr_ctrl, pwr_status);
return 0; return 0;
@@ -203,7 +203,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
cam_cpas_reg_read(core_info->cpas_handle, cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl);
if (pwr_ctrl & BPS_COLLAPSE_MASK) { if (pwr_ctrl & BPS_COLLAPSE_MASK) {
CAM_DBG(CAM_ICP, "BPS: pwr_ctrl set(%x)", pwr_ctrl); CAM_DBG(CAM_PERF, "BPS: pwr_ctrl set(%x)", pwr_ctrl);
cam_cpas_reg_write(core_info->cpas_handle, cam_cpas_reg_write(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, CAM_CPAS_REG_CPASTOP,
hw_info->pwr_ctrl, true, 0); hw_info->pwr_ctrl, true, 0);
@@ -214,7 +214,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev)
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl);
cam_cpas_reg_read(core_info->cpas_handle, cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status); CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status);
CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status); pwr_ctrl, pwr_status);
return rc; return rc;
@@ -370,7 +370,7 @@ int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type,
uint32_t clk_rate = clk_upd_cmd->curr_clk_rate; uint32_t clk_rate = clk_upd_cmd->curr_clk_rate;
int32_t clk_level = 0, err = 0; int32_t clk_level = 0, err = 0;
CAM_DBG(CAM_ICP, "bps_src_clk rate = %d", (int)clk_rate); CAM_DBG(CAM_PERF, "bps_src_clk rate = %d", (int)clk_rate);
if (!core_info->clk_enable) { if (!core_info->clk_enable) {
if (clk_upd_cmd->ipe_bps_pc_enable) { if (clk_upd_cmd->ipe_bps_pc_enable) {
@@ -390,10 +390,10 @@ int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type,
CAM_ERR(CAM_ICP, "BPS resume failed"); CAM_ERR(CAM_ICP, "BPS resume failed");
} }
} }
CAM_DBG(CAM_ICP, "clock rate %d", clk_rate); CAM_DBG(CAM_PERF, "clock rate %d", clk_rate);
rc = cam_bps_update_clk_rate(soc_info, clk_rate); rc = cam_bps_update_clk_rate(soc_info, clk_rate);
if (rc) if (rc)
CAM_ERR(CAM_ICP, "Failed to update clk"); CAM_ERR(CAM_PERF, "Failed to update clk %d", clk_rate);
err = cam_soc_util_get_clk_level(soc_info, err = cam_soc_util_get_clk_level(soc_info,
clk_rate, soc_info->src_clk_idx, clk_rate, soc_info->src_clk_idx,

2
drivers/cam_icp/icp_hw/bps_hw/bps_soc.c
View File

@@ -140,7 +140,7 @@ int cam_bps_update_clk_rate(struct cam_hw_soc_info *soc_info,
if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) &&
(soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) &&
(clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) {
CAM_DBG(CAM_ICP, "clk_rate %d greater than max, reset to %d", CAM_DBG(CAM_PERF, "clk_rate %d greater than max, reset to %d",
clk_rate, clk_rate,
soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]);
clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx];

135
drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c
View File

@@ -182,7 +182,7 @@ static bool cam_icp_is_over_clk(struct cam_icp_hw_mgr *hw_mgr,
curr_clk_idx = cam_icp_get_actual_clk_rate_idx(ctx_data, curr_clk_idx = cam_icp_get_actual_clk_rate_idx(ctx_data,
hw_mgr_clk_info->curr_clk); hw_mgr_clk_info->curr_clk);
CAM_DBG(CAM_ICP, "bc_idx = %d cc_idx = %d %d %d", CAM_DBG(CAM_PERF, "bc_idx = %d cc_idx = %d %d %d",
base_clk_idx, curr_clk_idx, hw_mgr_clk_info->base_clk, base_clk_idx, curr_clk_idx, hw_mgr_clk_info->base_clk,
hw_mgr_clk_info->curr_clk); hw_mgr_clk_info->curr_clk);
@@ -202,7 +202,7 @@ static int cam_icp_get_lower_clk_rate(struct cam_icp_hw_mgr *hw_mgr,
if (i > 0) if (i > 0)
return ctx_data->clk_info.clk_rate[i - 1]; return ctx_data->clk_info.clk_rate[i - 1];
CAM_DBG(CAM_ICP, "Already clk at lower level"); CAM_DBG(CAM_PERF, "Already clk at lower level");
return base_clk; return base_clk;
} }
@@ -216,7 +216,7 @@ static int cam_icp_get_next_clk_rate(struct cam_icp_hw_mgr *hw_mgr,
if (i < CAM_MAX_VOTE - 1) if (i < CAM_MAX_VOTE - 1)
return ctx_data->clk_info.clk_rate[i + 1]; return ctx_data->clk_info.clk_rate[i + 1];
CAM_DBG(CAM_ICP, "Already clk at higher level"); CAM_DBG(CAM_PERF, "Already clk at higher level");
return base_clk; return base_clk;
} }
@@ -256,7 +256,7 @@ static int cam_icp_supported_clk_rates(struct cam_icp_hw_mgr *hw_mgr,
for (i = 0; i < CAM_MAX_VOTE; i++) { for (i = 0; i < CAM_MAX_VOTE; i++) {
ctx_data->clk_info.clk_rate[i] = ctx_data->clk_info.clk_rate[i] =
soc_info->clk_rate[i][soc_info->src_clk_idx]; soc_info->clk_rate[i][soc_info->src_clk_idx];
CAM_DBG(CAM_ICP, "clk_info[%d] = %d", CAM_DBG(CAM_PERF, "clk_info[%d] = %d",
i, ctx_data->clk_info.clk_rate[i]); i, ctx_data->clk_info.clk_rate[i]);
} }
@@ -307,7 +307,7 @@ static int cam_icp_ctx_timer_reset(struct cam_icp_hw_ctx_data *ctx_data)
{ {
if (ctx_data && ctx_data->watch_dog) { if (ctx_data && ctx_data->watch_dog) {
ctx_data->watch_dog_reset_counter++; ctx_data->watch_dog_reset_counter++;
CAM_DBG(CAM_ICP, "reset timer : ctx_id = %d, counter=%d", CAM_DBG(CAM_PERF, "reset timer : ctx_id = %d, counter=%d",
ctx_data->ctx_id, ctx_data->watch_dog_reset_counter); ctx_data->ctx_id, ctx_data->watch_dog_reset_counter);
crm_timer_reset(ctx_data->watch_dog); crm_timer_reset(ctx_data->watch_dog);
} }
@@ -322,7 +322,7 @@ static void cam_icp_device_timer_reset(struct cam_icp_hw_mgr *hw_mgr,
return; return;
if (hw_mgr->clk_info[device_index].watch_dog) { if (hw_mgr->clk_info[device_index].watch_dog) {
CAM_DBG(CAM_ICP, "reset timer : device_index = %d", CAM_DBG(CAM_PERF, "reset timer : device_index = %d",
device_index); device_index);
crm_timer_reset(hw_mgr->clk_info[device_index].watch_dog); crm_timer_reset(hw_mgr->clk_info[device_index].watch_dog);
hw_mgr->clk_info[device_index].watch_dog_reset_counter++; hw_mgr->clk_info[device_index].watch_dog_reset_counter++;
@@ -396,7 +396,7 @@ static int32_t cam_icp_deinit_idle_clk(void *priv, void *data)
goto done; goto done;
} }
CAM_DBG(CAM_ICP, "Disable %d", clk_info->hw_type); CAM_DBG(CAM_PERF, "Disable %d", clk_info->hw_type);
clk_upd_cmd.ipe_bps_pc_enable = icp_hw_mgr.ipe_bps_pc_flag; clk_upd_cmd.ipe_bps_pc_enable = icp_hw_mgr.ipe_bps_pc_flag;
@@ -431,6 +431,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
struct cam_icp_cpas_vote clk_update; struct cam_icp_cpas_vote clk_update;
int i = 0; int i = 0;
int device_share_ratio = 1; int device_share_ratio = 1;
uint64_t total_ab_bw = 0;
if (!ctx_data) { if (!ctx_data) {
CAM_ERR(CAM_ICP, "ctx_data is NULL, failed to update clk"); CAM_ERR(CAM_ICP, "ctx_data is NULL, failed to update clk");
@@ -440,7 +441,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
mutex_lock(&ctx_data->ctx_mutex); mutex_lock(&ctx_data->ctx_mutex);
if ((ctx_data->state != CAM_ICP_CTX_STATE_ACQUIRED) || if ((ctx_data->state != CAM_ICP_CTX_STATE_ACQUIRED) ||
(ctx_data->watch_dog_reset_counter == 0)) { (ctx_data->watch_dog_reset_counter == 0)) {
CAM_DBG(CAM_ICP, "state %d, counter=%d", CAM_DBG(CAM_PERF, "state %d, counter=%d",
ctx_data->state, ctx_data->watch_dog_reset_counter); ctx_data->state, ctx_data->watch_dog_reset_counter);
mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&ctx_data->ctx_mutex);
return 0; return 0;
@@ -452,7 +453,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
return -EBUSY; return -EBUSY;
} }
CAM_DBG(CAM_ICP, CAM_DBG(CAM_PERF,
"E :ctx_id = %d ubw = %lld cbw = %lld curr_fc = %u bc = %u", "E :ctx_id = %d ubw = %lld cbw = %lld curr_fc = %u bc = %u",
ctx_data->ctx_id, ctx_data->ctx_id,
ctx_data->clk_info.uncompressed_bw, ctx_data->clk_info.uncompressed_bw,
@@ -494,10 +495,6 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
CAM_ICP_RES_TYPE_BPS) && (ipe1_dev_intf)) CAM_ICP_RES_TYPE_BPS) && (ipe1_dev_intf))
device_share_ratio = 2; device_share_ratio = 2;
clk_update.ahb_vote.type = CAM_VOTE_DYNAMIC;
clk_update.ahb_vote.vote.freq = 0;
clk_update.ahb_vote_valid = false;
if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) { if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) {
clk_update.axi_vote.num_paths = 1; clk_update.axi_vote.num_paths = 1;
if (ctx_data->icp_dev_acquire_info->dev_type == if (ctx_data->icp_dev_acquire_info->dev_type ==
@@ -516,6 +513,8 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
clk_info->compressed_bw -= ctx_data->clk_info.compressed_bw; clk_info->compressed_bw -= ctx_data->clk_info.compressed_bw;
clk_info->uncompressed_bw -= ctx_data->clk_info.uncompressed_bw; clk_info->uncompressed_bw -= ctx_data->clk_info.uncompressed_bw;
total_ab_bw = clk_info->compressed_bw;
ctx_data->clk_info.uncompressed_bw = 0; ctx_data->clk_info.uncompressed_bw = 0;
ctx_data->clk_info.compressed_bw = 0; ctx_data->clk_info.compressed_bw = 0;
ctx_data->clk_info.curr_fc = 0; ctx_data->clk_info.curr_fc = 0;
@@ -561,7 +560,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
} }
if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) {
CAM_WARN(CAM_ICP, CAM_WARN(CAM_PERF,
"Invalid path %d, start offset=%d, max=%d", "Invalid path %d, start offset=%d, max=%d",
ctx_data->clk_info.axi_path[i] ctx_data->clk_info.axi_path[i]
.path_data_type, .path_data_type,
@@ -580,6 +579,9 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
ctx_data->clk_info.axi_path[i].ddr_ab_bw; ctx_data->clk_info.axi_path[i].ddr_ab_bw;
clk_info->axi_path[path_index].ddr_ib_bw -= clk_info->axi_path[path_index].ddr_ib_bw -=
ctx_data->clk_info.axi_path[i].ddr_ib_bw; ctx_data->clk_info.axi_path[i].ddr_ib_bw;
total_ab_bw +=
clk_info->axi_path[path_index].mnoc_ab_bw;
} }
memset(&ctx_data->clk_info.axi_path[0], 0, memset(&ctx_data->clk_info.axi_path[0], 0,
@@ -616,6 +618,16 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
} }
clk_update.axi_vote_valid = true; clk_update.axi_vote_valid = true;
if (total_ab_bw == 0) {
/* If no more contexts are active, reduce AHB vote to minimum */
clk_update.ahb_vote.type = CAM_VOTE_ABSOLUTE;
clk_update.ahb_vote.vote.level = CAM_LOWSVS_VOTE;
clk_update.ahb_vote_valid = true;
} else {
clk_update.ahb_vote_valid = false;
}
dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id,
&clk_update, sizeof(clk_update)); &clk_update, sizeof(clk_update));
@@ -629,7 +641,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data)
ipe1_dev_intf->hw_ops.process_cmd(ipe1_dev_intf->hw_priv, id, ipe1_dev_intf->hw_ops.process_cmd(ipe1_dev_intf->hw_priv, id,
&clk_update, sizeof(clk_update)); &clk_update, sizeof(clk_update));
CAM_DBG(CAM_ICP, "X :ctx_id = %d curr_fc = %u bc = %u", CAM_DBG(CAM_PERF, "X :ctx_id = %d curr_fc = %u bc = %u",
ctx_data->ctx_id, ctx_data->clk_info.curr_fc, ctx_data->ctx_id, ctx_data->clk_info.curr_fc,
ctx_data->clk_info.base_clk); ctx_data->clk_info.base_clk);
mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&ctx_data->ctx_mutex);
@@ -727,7 +739,7 @@ static int cam_icp_ctx_timer_start(struct cam_icp_hw_ctx_data *ctx_data)
ctx_data->watch_dog_reset_counter = 0; ctx_data->watch_dog_reset_counter = 0;
CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); CAM_DBG(CAM_PERF, "start timer : ctx_id = %d", ctx_data->ctx_id);
return rc; return rc;
} }
@@ -755,7 +767,7 @@ static int cam_icp_device_timer_start(struct cam_icp_hw_mgr *hw_mgr)
static int cam_icp_ctx_timer_stop(struct cam_icp_hw_ctx_data *ctx_data) static int cam_icp_ctx_timer_stop(struct cam_icp_hw_ctx_data *ctx_data)
{ {
if (ctx_data->watch_dog) { if (ctx_data->watch_dog) {
CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); CAM_DBG(CAM_PERF, "stop timer : ctx_id = %d", ctx_data->ctx_id);
ctx_data->watch_dog_reset_counter = 0; ctx_data->watch_dog_reset_counter = 0;
crm_timer_exit(&ctx_data->watch_dog); crm_timer_exit(&ctx_data->watch_dog);
ctx_data->watch_dog = NULL; ctx_data->watch_dog = NULL;
@@ -790,7 +802,7 @@ static uint32_t cam_icp_mgr_calc_base_clk(uint32_t frame_cycles,
base_clk = frame_cycles * mul; base_clk = frame_cycles * mul;
do_div(base_clk, budget); do_div(base_clk, budget);
CAM_DBG(CAM_ICP, "budget = %lld fc = %d ib = %lld base_clk = %lld", CAM_DBG(CAM_PERF, "budget = %lld fc = %d ib = %lld base_clk = %lld",
budget, frame_cycles, budget, frame_cycles,
(long long)(frame_cycles * mul), base_clk); (long long)(frame_cycles * mul), base_clk);
@@ -806,7 +818,7 @@ static bool cam_icp_busy_prev_reqs(struct hfi_frame_process_info *frm_process,
for (i = 0, cnt = 0; i < CAM_FRAME_CMD_MAX; i++) { for (i = 0, cnt = 0; i < CAM_FRAME_CMD_MAX; i++) {
if (frm_process->request_id[i]) { if (frm_process->request_id[i]) {
if (frm_process->fw_process_flag[i]) { if (frm_process->fw_process_flag[i]) {
CAM_DBG(CAM_ICP, "r id = %lld busy = %d", CAM_DBG(CAM_PERF, "r id = %lld busy = %d",
frm_process->request_id[i], frm_process->request_id[i],
frm_process->fw_process_flag[i]); frm_process->fw_process_flag[i]);
cnt++; cnt++;
@@ -998,7 +1010,7 @@ static bool cam_icp_debug_clk_update(struct cam_icp_clk_info *hw_mgr_clk_info)
hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_debug_clk; hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_debug_clk;
hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_debug_clk; hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_debug_clk;
hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_debug_clk; hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_debug_clk;
CAM_DBG(CAM_ICP, "bc = %d cc = %d", CAM_DBG(CAM_PERF, "bc = %d cc = %d",
hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk); hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk);
return true; return true;
} }
@@ -1013,7 +1025,7 @@ static bool cam_icp_default_clk_update(struct cam_icp_clk_info *hw_mgr_clk_info)
hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_default_clk; hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_default_clk;
hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_default_clk; hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_default_clk;
hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_default_clk; hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_default_clk;
CAM_DBG(CAM_ICP, "bc = %d cc = %d", CAM_DBG(CAM_PERF, "bc = %d cc = %d",
hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk); hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk);
return true; return true;
} }
@@ -1037,7 +1049,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr,
*/ */
for (i = 0; i < clk_info->num_paths; i++) for (i = 0; i < clk_info->num_paths; i++)
CAM_DBG(CAM_ICP, "clk_info camnoc = %lld busy = %d", CAM_DBG(CAM_PERF, "clk_info camnoc = %lld busy = %d",
clk_info->axi_path[i].camnoc_bw, busy); clk_info->axi_path[i].camnoc_bw, busy);
if (clk_info->num_paths == ctx_data->clk_info.num_paths) { if (clk_info->num_paths == ctx_data->clk_info.num_paths) {
@@ -1060,8 +1072,9 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr,
} }
if (!update_required) { if (!update_required) {
CAM_DBG(CAM_ICP, CAM_DBG(CAM_PERF,
"Incoming BW hasn't changed, no update required"); "Incoming BW hasn't changed, no update required, num_paths=%d",
clk_info->num_paths);
return false; return false;
} }
@@ -1091,7 +1104,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr,
} }
if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) {
CAM_WARN(CAM_ICP, CAM_WARN(CAM_PERF,
"Invalid path %d, start offset=%d, max=%d", "Invalid path %d, start offset=%d, max=%d",
ctx_data->clk_info.axi_path[i].path_data_type, ctx_data->clk_info.axi_path[i].path_data_type,
CAM_AXI_PATH_DATA_IPE_START_OFFSET, CAM_AXI_PATH_DATA_IPE_START_OFFSET,
@@ -1135,7 +1148,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr,
} }
if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) {
CAM_WARN(CAM_ICP, CAM_WARN(CAM_PERF,
"Invalid path %d, start offset=%d, max=%d", "Invalid path %d, start offset=%d, max=%d",
ctx_data->clk_info.axi_path[i].path_data_type, ctx_data->clk_info.axi_path[i].path_data_type,
CAM_AXI_PATH_DATA_IPE_START_OFFSET, CAM_AXI_PATH_DATA_IPE_START_OFFSET,
@@ -1158,7 +1171,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr,
hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw += hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw +=
ctx_data->clk_info.axi_path[i].ddr_ib_bw; ctx_data->clk_info.axi_path[i].ddr_ib_bw;
CAM_DBG(CAM_ICP, CAM_DBG(CAM_PERF,
"Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]", "Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]",
cam_icp_dev_type_to_name( cam_icp_dev_type_to_name(
ctx_data->icp_dev_acquire_info->dev_type), ctx_data->icp_dev_acquire_info->dev_type),
@@ -1191,14 +1204,14 @@ static bool cam_icp_update_bw(struct cam_icp_hw_mgr *hw_mgr,
* recalculate bandwidth of all contexts of same hardware and update * recalculate bandwidth of all contexts of same hardware and update
* voting of bandwidth * voting of bandwidth
*/ */
CAM_DBG(CAM_ICP, "ubw ctx = %lld clk_info ubw = %lld busy = %d", CAM_DBG(CAM_PERF, "ubw ctx = %lld clk_info ubw = %lld busy = %d",
ctx_data->clk_info.uncompressed_bw, ctx_data->clk_info.uncompressed_bw,
clk_info->uncompressed_bw, busy); clk_info->uncompressed_bw, busy);
if ((clk_info->uncompressed_bw == ctx_data->clk_info.uncompressed_bw) && if ((clk_info->uncompressed_bw == ctx_data->clk_info.uncompressed_bw) &&
(ctx_data->clk_info.uncompressed_bw == (ctx_data->clk_info.uncompressed_bw ==
hw_mgr_clk_info->uncompressed_bw)) { hw_mgr_clk_info->uncompressed_bw)) {
CAM_DBG(CAM_ICP, "Update not required bw=%lld", CAM_DBG(CAM_PERF, "Update not required bw=%lld",
ctx_data->clk_info.uncompressed_bw); ctx_data->clk_info.uncompressed_bw);
return false; return false;
} }
@@ -1206,7 +1219,8 @@ static bool cam_icp_update_bw(struct cam_icp_hw_mgr *hw_mgr,
if (busy && if (busy &&
(ctx_data->clk_info.uncompressed_bw > (ctx_data->clk_info.uncompressed_bw >
clk_info->uncompressed_bw)) { clk_info->uncompressed_bw)) {
CAM_DBG(CAM_ICP, "Busy, Update not req existing=%lld, new=%lld", CAM_DBG(CAM_PERF,
"Busy, Update not req existing=%lld, new=%lld",
ctx_data->clk_info.uncompressed_bw, ctx_data->clk_info.uncompressed_bw,
clk_info->uncompressed_bw); clk_info->uncompressed_bw);
return false; return false;
@@ -1227,7 +1241,7 @@ static bool cam_icp_update_bw(struct cam_icp_hw_mgr *hw_mgr,
ctx->clk_info.uncompressed_bw; ctx->clk_info.uncompressed_bw;
hw_mgr_clk_info->compressed_bw += hw_mgr_clk_info->compressed_bw +=
ctx->clk_info.compressed_bw; ctx->clk_info.compressed_bw;
CAM_DBG(CAM_ICP, CAM_DBG(CAM_PERF,
"Current context=[%lld %lld] Total=[%lld %lld]", "Current context=[%lld %lld] Total=[%lld %lld]",
ctx->clk_info.uncompressed_bw, ctx->clk_info.uncompressed_bw,
ctx->clk_info.compressed_bw, ctx->clk_info.compressed_bw,
@@ -1253,11 +1267,11 @@ static bool cam_icp_check_clk_update(struct cam_icp_hw_mgr *hw_mgr,
if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) { if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) {
cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_BPS); cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_BPS);
hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS]; hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS];
CAM_DBG(CAM_ICP, "Reset bps timer"); CAM_DBG(CAM_PERF, "Reset bps timer");
} else { } else {
cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_IPE); cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_IPE);
hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE]; hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE];
CAM_DBG(CAM_ICP, "Reset ipe timer"); CAM_DBG(CAM_PERF, "Reset ipe timer");
} }
if (icp_hw_mgr.icp_debug_clk) if (icp_hw_mgr.icp_debug_clk)
@@ -1267,7 +1281,7 @@ static bool cam_icp_check_clk_update(struct cam_icp_hw_mgr *hw_mgr,
frame_info = &ctx_data->hfi_frame_process; frame_info = &ctx_data->hfi_frame_process;
req_id = frame_info->request_id[idx]; req_id = frame_info->request_id[idx];
busy = cam_icp_busy_prev_reqs(frame_info, req_id); busy = cam_icp_busy_prev_reqs(frame_info, req_id);
CAM_DBG(CAM_ICP, "busy = %d req_id = %lld", busy, req_id); CAM_DBG(CAM_PERF, "busy = %d req_id = %lld", busy, req_id);
clk_info = &ctx_data->hfi_frame_process.clk_info[idx]; clk_info = &ctx_data->hfi_frame_process.clk_info[idx];
if (!clk_info->frame_cycles) if (!clk_info->frame_cycles)
@@ -1285,7 +1299,7 @@ static bool cam_icp_check_clk_update(struct cam_icp_hw_mgr *hw_mgr,
rc = cam_icp_update_clk_free(hw_mgr, ctx_data, rc = cam_icp_update_clk_free(hw_mgr, ctx_data,
hw_mgr_clk_info, clk_info, base_clk); hw_mgr_clk_info, clk_info, base_clk);
CAM_DBG(CAM_ICP, "bc = %d cc = %d busy = %d overclk = %d uc = %d", CAM_DBG(CAM_PERF, "bc = %d cc = %d busy = %d overclk = %d uc = %d",
hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk, hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk,
busy, hw_mgr_clk_info->over_clked, rc); busy, hw_mgr_clk_info->over_clked, rc);
@@ -1315,7 +1329,7 @@ static bool cam_icp_check_bw_update(struct cam_icp_hw_mgr *hw_mgr,
if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) { if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) {
clk_info = &ctx_data->hfi_frame_process.clk_info[idx]; clk_info = &ctx_data->hfi_frame_process.clk_info[idx];
CAM_DBG(CAM_ICP, CAM_DBG(CAM_PERF,
"Ctx[%pK][%d] Req[%lld] Current camno=%lld, mnoc=%lld", "Ctx[%pK][%d] Req[%lld] Current camno=%lld, mnoc=%lld",
ctx_data, ctx_data->ctx_id, req_id, ctx_data, ctx_data->ctx_id, req_id,
hw_mgr_clk_info->uncompressed_bw, hw_mgr_clk_info->uncompressed_bw,
@@ -1326,11 +1340,14 @@ static bool cam_icp_check_bw_update(struct cam_icp_hw_mgr *hw_mgr,
} else if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V2) { } else if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V2) {
clk_info_v2 = &ctx_data->hfi_frame_process.clk_info_v2[idx]; clk_info_v2 = &ctx_data->hfi_frame_process.clk_info_v2[idx];
CAM_DBG(CAM_PERF, "index=%d, num_paths=%d, ctx_data=%pK",
idx, clk_info_v2->num_paths, ctx_data);
bw_updated = cam_icp_update_bw_v2(hw_mgr, ctx_data, bw_updated = cam_icp_update_bw_v2(hw_mgr, ctx_data,
hw_mgr_clk_info, clk_info_v2, busy); hw_mgr_clk_info, clk_info_v2, busy);
for (i = 0; i < hw_mgr_clk_info->num_paths; i++) { for (i = 0; i < hw_mgr_clk_info->num_paths; i++) {
CAM_DBG(CAM_ICP, CAM_DBG(CAM_PERF,
"Final path_type: %s, transac_type: %s, camnoc_bw = %lld mnoc_ab_bw = %lld, mnoc_ib_bw = %lld, device: %s", "Final path_type: %s, transac_type: %s, camnoc_bw = %lld mnoc_ab_bw = %lld, mnoc_ib_bw = %lld, device: %s",
cam_cpas_axi_util_path_type_to_string( cam_cpas_axi_util_path_type_to_string(
hw_mgr_clk_info->axi_path[i].path_data_type), hw_mgr_clk_info->axi_path[i].path_data_type),
@@ -1343,7 +1360,7 @@ static bool cam_icp_check_bw_update(struct cam_icp_hw_mgr *hw_mgr,
ctx_data->icp_dev_acquire_info->dev_type)); ctx_data->icp_dev_acquire_info->dev_type));
} }
} else { } else {
CAM_ERR(CAM_ICP, "Invalid bw config version: %d", CAM_ERR(CAM_PERF, "Invalid bw config version: %d",
ctx_data->bw_config_version); ctx_data->bw_config_version);
return false; return false;
} }
@@ -1402,7 +1419,7 @@ static int cam_icp_update_clk_rate(struct cam_icp_hw_mgr *hw_mgr,
} }
/* update a5 clock */ /* update a5 clock */
CAM_DBG(CAM_ICP, "Update ICP clk to level [%d]", CAM_DBG(CAM_PERF, "Update ICP clk to level [%d]",
clk_upd_cmd.clk_level); clk_upd_cmd.clk_level);
a5_dev_intf->hw_ops.process_cmd(a5_dev_intf->hw_priv, a5_dev_intf->hw_ops.process_cmd(a5_dev_intf->hw_priv,
CAM_ICP_A5_CMD_CLK_UPDATE, &clk_upd_cmd.clk_level, CAM_ICP_A5_CMD_CLK_UPDATE, &clk_upd_cmd.clk_level,
@@ -1609,7 +1626,7 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr,
core_info_mask = ICP_PWR_CLP_IPE0; core_info_mask = ICP_PWR_CLP_IPE0;
} }
CAM_DBG(CAM_ICP, "core_info %X", core_info_mask); CAM_DBG(CAM_PERF, "core_info %X", core_info_mask);
if (icp_hw_mgr.ipe_bps_pc_flag) if (icp_hw_mgr.ipe_bps_pc_flag)
rc = hfi_enable_ipe_bps_pc(true, core_info_mask); rc = hfi_enable_ipe_bps_pc(true, core_info_mask);
else else
@@ -1641,7 +1658,7 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr,
dev = ctx_data->icp_dev_acquire_info->dev_type; dev = ctx_data->icp_dev_acquire_info->dev_type;
if (dev == CAM_ICP_RES_TYPE_BPS) { if (dev == CAM_ICP_RES_TYPE_BPS) {
CAM_DBG(CAM_ICP, "bps ctx cnt %d", hw_mgr->bps_ctxt_cnt); CAM_DBG(CAM_PERF, "bps ctx cnt %d", hw_mgr->bps_ctxt_cnt);
if (ctx_data) if (ctx_data)
--hw_mgr->bps_ctxt_cnt; --hw_mgr->bps_ctxt_cnt;
@@ -1662,7 +1679,7 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr,
hw_mgr->bps_clk_state = false; hw_mgr->bps_clk_state = false;
} }
} else { } else {
CAM_DBG(CAM_ICP, "ipe ctx cnt %d", hw_mgr->ipe_ctxt_cnt); CAM_DBG(CAM_PERF, "ipe ctx cnt %d", hw_mgr->ipe_ctxt_cnt);
if (ctx_data) if (ctx_data)
--hw_mgr->ipe_ctxt_cnt; --hw_mgr->ipe_ctxt_cnt;
@@ -2919,7 +2936,7 @@ static int cam_icp_mgr_icp_power_collapse(struct cam_icp_hw_mgr *hw_mgr)
struct cam_hw_intf *a5_dev_intf = NULL; struct cam_hw_intf *a5_dev_intf = NULL;
struct cam_hw_info *a5_dev = NULL; struct cam_hw_info *a5_dev = NULL;
CAM_DBG(CAM_ICP, "ENTER"); CAM_DBG(CAM_PERF, "ENTER");
a5_dev_intf = hw_mgr->a5_dev_intf; a5_dev_intf = hw_mgr->a5_dev_intf;
if (!a5_dev_intf) { if (!a5_dev_intf) {
@@ -2939,7 +2956,7 @@ static int cam_icp_mgr_icp_power_collapse(struct cam_icp_hw_mgr *hw_mgr)
a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base);
} }
a5_dev_intf->hw_ops.deinit(a5_dev_intf->hw_priv, NULL, 0); a5_dev_intf->hw_ops.deinit(a5_dev_intf->hw_priv, NULL, 0);
CAM_DBG(CAM_ICP, "EXIT"); CAM_DBG(CAM_PERF, "EXIT");
return rc; return rc;
} }
@@ -4138,6 +4155,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data,
size_t io_buf_size, clk_update_size; size_t io_buf_size, clk_update_size;
int rc = 0; int rc = 0;
uintptr_t pResource; uintptr_t pResource;
uint32_t i = 0;
if (!blob_data || (blob_size == 0)) { if (!blob_data || (blob_size == 0)) {
CAM_ERR(CAM_ICP, "Invalid blob info %pK %d", blob_data, CAM_ERR(CAM_ICP, "Invalid blob info %pK %d", blob_data,
@@ -4151,7 +4169,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data,
switch (blob_type) { switch (blob_type) {
case CAM_ICP_CMD_GENERIC_BLOB_CLK: case CAM_ICP_CMD_GENERIC_BLOB_CLK:
CAM_WARN_RATE_LIMIT_CUSTOM(CAM_ICP, 300, 1, CAM_WARN_RATE_LIMIT_CUSTOM(CAM_PERF, 300, 1,
"Using deprecated blob type GENERIC_BLOB_CLK"); "Using deprecated blob type GENERIC_BLOB_CLK");
if (blob_size != sizeof(struct cam_icp_clk_bw_request)) { if (blob_size != sizeof(struct cam_icp_clk_bw_request)) {
CAM_ERR(CAM_ICP, "Mismatch blob size %d expected %lu", CAM_ERR(CAM_ICP, "Mismatch blob size %d expected %lu",
@@ -4175,7 +4193,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data,
soc_req = (struct cam_icp_clk_bw_request *)blob_data; soc_req = (struct cam_icp_clk_bw_request *)blob_data;
*clk_info = *soc_req; *clk_info = *soc_req;
CAM_DBG(CAM_ICP, "budget:%llu fc: %llu %d BW %lld %lld", CAM_DBG(CAM_PERF, "budget:%llu fc: %llu %d BW %lld %lld",
clk_info->budget_ns, clk_info->frame_cycles, clk_info->budget_ns, clk_info->frame_cycles,
clk_info->rt_flag, clk_info->uncompressed_bw, clk_info->rt_flag, clk_info->uncompressed_bw,
clk_info->compressed_bw); clk_info->compressed_bw);
@@ -4202,7 +4220,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data,
soc_req_v2 = (struct cam_icp_clk_bw_request_v2 *)blob_data; soc_req_v2 = (struct cam_icp_clk_bw_request_v2 *)blob_data;
if (soc_req_v2->num_paths > CAM_ICP_MAX_PER_PATH_VOTES) { if (soc_req_v2->num_paths > CAM_ICP_MAX_PER_PATH_VOTES) {
CAM_ERR(CAM_ICP, "Invalid num paths: %d", CAM_ERR(CAM_PERF, "Invalid num paths: %d",
soc_req_v2->num_paths); soc_req_v2->num_paths);
return -EINVAL; return -EINVAL;
} }
@@ -4241,9 +4259,26 @@ static int cam_icp_packet_generic_blob_handler(void *user_data,
clk_info->frame_cycles = clk_info_v2->frame_cycles; clk_info->frame_cycles = clk_info_v2->frame_cycles;
clk_info->rt_flag = clk_info_v2->rt_flag; clk_info->rt_flag = clk_info_v2->rt_flag;
CAM_DBG(CAM_ICP, "budget=%llu, frame_cycle=%llu, rt_flag=%d", CAM_DBG(CAM_PERF,
"budget=%llu, frame_cycle=%llu, rt_flag=%d, num_paths=%d, clk_update_size=%d, index=%d, ctx_data=%pK",
clk_info_v2->budget_ns, clk_info_v2->frame_cycles, clk_info_v2->budget_ns, clk_info_v2->frame_cycles,
clk_info_v2->rt_flag); clk_info_v2->rt_flag,
clk_info_v2->num_paths,
clk_update_size,
index,
ctx_data);
for (i = 0; i < clk_info_v2->num_paths; i++) {
CAM_DBG(CAM_PERF,
"[%d] : path_type=%d, trans_type=%d, camnoc=%lld, mnoc_ab=%lld, mnoc_ib=%lld",
i,
clk_info_v2->axi_path[i].path_data_type,
clk_info_v2->axi_path[i].transac_type,
clk_info_v2->axi_path[i].camnoc_bw,
clk_info_v2->axi_path[i].mnoc_ab_bw,
clk_info_v2->axi_path[i].mnoc_ib_bw);
}
break; break;
case CAM_ICP_CMD_GENERIC_BLOB_CFG_IO: case CAM_ICP_CMD_GENERIC_BLOB_CFG_IO:
@@ -4456,7 +4491,7 @@ static void cam_icp_mgr_print_io_bufs(struct cam_packet *packet,
"get src buf address fail rc %d", rc); "get src buf address fail rc %d", rc);
continue; continue;
} }
if (iova_addr >> 32) { if ((iova_addr & 0xFFFFFFFF) != iova_addr) {
CAM_ERR(CAM_ICP, "Invalid mapped address"); CAM_ERR(CAM_ICP, "Invalid mapped address");
rc = -EINVAL; rc = -EINVAL;
continue; continue;

2
drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h
View File

@@ -145,6 +145,7 @@ struct icp_frame_info {
* @budget_ns: Time required to process frame * @budget_ns: Time required to process frame
* @frame_cycles: Frame cycles needed to process the frame * @frame_cycles: Frame cycles needed to process the frame
* @rt_flag: Flag to indicate real time stream * @rt_flag: Flag to indicate real time stream
* @reserved: Reserved filed.
* @num_paths: Number of paths for per path bw vote * @num_paths: Number of paths for per path bw vote
* @axi_path: Per path vote info for IPE/BPS * @axi_path: Per path vote info for IPE/BPS
*/ */
@@ -152,6 +153,7 @@ struct cam_icp_clk_bw_req_internal_v2 {
uint64_t budget_ns; uint64_t budget_ns;
uint32_t frame_cycles; uint32_t frame_cycles;
uint32_t rt_flag; uint32_t rt_flag;
uint32_t reserved;
uint32_t num_paths; uint32_t num_paths;
struct cam_axi_per_path_bw_vote axi_path[CAM_ICP_MAX_PER_PATH_VOTES]; struct cam_axi_per_path_bw_vote axi_path[CAM_ICP_MAX_PER_PATH_VOTES];
}; };

16
drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c
View File

@@ -39,7 +39,7 @@ static int cam_ipe_cpas_vote(struct cam_ipe_device_core_info *core_info,
&cpas_vote->axi_vote); &cpas_vote->axi_vote);
if (rc) if (rc)
CAM_ERR(CAM_ICP, "cpas vote is failed: %d", rc); CAM_ERR(CAM_PERF, "cpas vote is failed: %d", rc);
return rc; return rc;
} }
@@ -168,7 +168,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
hw_info->pwr_ctrl, true, 0x1); hw_info->pwr_ctrl, true, 0x1);
if (pwr_status >> IPE_PWR_ON_MASK) if (pwr_status >> IPE_PWR_ON_MASK)
CAM_WARN(CAM_ICP, "BPS: pwr_status(%x):pwr_ctrl(%x)", CAM_WARN(CAM_PERF, "BPS: pwr_status(%x):pwr_ctrl(%x)",
pwr_status, pwr_ctrl); pwr_status, pwr_ctrl);
} }
@@ -179,7 +179,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev)
cam_cpas_reg_read(core_info->cpas_handle, cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status); true, &pwr_status);
CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status); pwr_ctrl, pwr_status);
return 0; return 0;
@@ -202,7 +202,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl,
true, &pwr_ctrl); true, &pwr_ctrl);
if (pwr_ctrl & IPE_COLLAPSE_MASK) { if (pwr_ctrl & IPE_COLLAPSE_MASK) {
CAM_DBG(CAM_ICP, "IPE pwr_ctrl set(%x)", pwr_ctrl); CAM_DBG(CAM_PERF, "IPE pwr_ctrl set(%x)", pwr_ctrl);
cam_cpas_reg_write(core_info->cpas_handle, cam_cpas_reg_write(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, CAM_CPAS_REG_CPASTOP,
hw_info->pwr_ctrl, true, 0); hw_info->pwr_ctrl, true, 0);
@@ -214,7 +214,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev)
cam_cpas_reg_read(core_info->cpas_handle, cam_cpas_reg_read(core_info->cpas_handle,
CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, CAM_CPAS_REG_CPASTOP, hw_info->pwr_status,
true, &pwr_status); true, &pwr_status);
CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x",
pwr_ctrl, pwr_status); pwr_ctrl, pwr_status);
return rc; return rc;
@@ -364,7 +364,7 @@ int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type,
uint32_t clk_rate = clk_upd_cmd->curr_clk_rate; uint32_t clk_rate = clk_upd_cmd->curr_clk_rate;
int32_t clk_level = 0, err = 0; int32_t clk_level = 0, err = 0;
CAM_DBG(CAM_ICP, "ipe_src_clk rate = %d", (int)clk_rate); CAM_DBG(CAM_PERF, "ipe_src_clk rate = %d", (int)clk_rate);
if (!core_info->clk_enable) { if (!core_info->clk_enable) {
if (clk_upd_cmd->ipe_bps_pc_enable) { if (clk_upd_cmd->ipe_bps_pc_enable) {
cam_ipe_handle_pc(ipe_dev); cam_ipe_handle_pc(ipe_dev);
@@ -383,11 +383,11 @@ int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type,
CAM_ERR(CAM_ICP, "bps resume failed"); CAM_ERR(CAM_ICP, "bps resume failed");
} }
} }
CAM_DBG(CAM_ICP, "clock rate %d", clk_rate); CAM_DBG(CAM_PERF, "clock rate %d", clk_rate);
rc = cam_ipe_update_clk_rate(soc_info, clk_rate); rc = cam_ipe_update_clk_rate(soc_info, clk_rate);
if (rc) if (rc)
CAM_ERR(CAM_ICP, "Failed to update clk"); CAM_ERR(CAM_PERF, "Failed to update clk %d", clk_rate);
err = cam_soc_util_get_clk_level(soc_info, err = cam_soc_util_get_clk_level(soc_info,
clk_rate, soc_info->src_clk_idx, clk_rate, soc_info->src_clk_idx,

2
drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c
View File

@@ -143,7 +143,7 @@ int cam_ipe_update_clk_rate(struct cam_hw_soc_info *soc_info,
if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) &&
(soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) &&
(clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) {
CAM_DBG(CAM_ICP, "clk_rate %d greater than max, reset to %d", CAM_DBG(CAM_PERF, "clk_rate %d greater than max, reset to %d",
clk_rate, clk_rate,
soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]);
clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx];

234
drivers/cam_isp/cam_isp_context.c
View File

@@ -56,7 +56,7 @@ static void __cam_isp_ctx_update_state_monitor_array(
} }
static const char *__cam_isp_ctx_substate_val_to_type( static const char *__cam_isp_ctx_substate_val_to_type(
uint32_t type) enum cam_isp_ctx_activated_substate type)
{ {
switch (type) { switch (type) {
case CAM_ISP_CTX_ACTIVATED_SOF: case CAM_ISP_CTX_ACTIVATED_SOF:
@@ -74,7 +74,7 @@ static const char *__cam_isp_ctx_substate_val_to_type(
case CAM_ISP_CTX_ACTIVATED_HALT: case CAM_ISP_CTX_ACTIVATED_HALT:
return "HALT"; return "HALT";
default: default:
return "CAM_ISP_CTX_INVALID_STATE"; return "INVALID";
} }
} }
@@ -130,7 +130,7 @@ static void __cam_isp_ctx_dump_state_monitor_array(
for (i = 0; i < num_entries; i++) { for (i = 0; i < num_entries; i++) {
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
"Index[%d] time[%d] : State[%s] Frame[%lld] ReqId[%llu] evt_type[%s]", "Index[%d] time[%d] : Substate[%s] Frame[%lld] ReqId[%llu] evt_type[%s]",
index, index,
ctx_isp->cam_isp_ctx_state_monitor[index].evt_time_stamp, ctx_isp->cam_isp_ctx_state_monitor[index].evt_time_stamp,
__cam_isp_ctx_substate_val_to_type( __cam_isp_ctx_substate_val_to_type(
@@ -689,9 +689,10 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state(
if (done_next_req.num_handles) { if (done_next_req.num_handles) {
struct cam_isp_hw_done_event_data unhandled_res; struct cam_isp_hw_done_event_data unhandled_res;
struct cam_ctx_request *next_req = list_next_entry(req, list); struct cam_ctx_request *next_req = list_last_entry(
&ctx->active_req_list, struct cam_ctx_request, list);
if (next_req) { if (next_req->request_id != req->request_id) {
/* /*
* Few resource handles are already signalled in the * Few resource handles are already signalled in the
* current request, lets check if there is another * current request, lets check if there is another
@@ -719,21 +720,29 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state(
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
"BUF Done not handled for next request %lld", "BUF Done not handled for next request %lld",
next_req->request_id); next_req->request_id);
} else {
CAM_WARN(CAM_ISP,
"Req %lld only active request, spurious buf_done rxd",
req->request_id);
} }
} }
return rc; return rc;
} }
static int __cam_isp_ctx_reg_upd_in_epoch_state( static int __cam_isp_ctx_reg_upd_in_epoch_bubble_state(
struct cam_isp_context *ctx_isp, void *evt_data) struct cam_isp_context *ctx_isp, void *evt_data)
{ {
if (ctx_isp->frame_id == 1) if (ctx_isp->frame_id == 1)
CAM_DBG(CAM_ISP, "Reg update for early PCR"); CAM_DBG(CAM_ISP, "Reg update in Substate[%s] for early PCR",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
else else
CAM_WARN(CAM_ISP, CAM_WARN(CAM_ISP,
"Unexpected reg update in activated substate:%d for frame_id:%lld", "Unexpected reg update in activated Substate[%s] for frame_id:%lld",
ctx_isp->substate_activated, ctx_isp->frame_id); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated),
ctx_isp->frame_id);
return 0; return 0;
} }
@@ -775,7 +784,9 @@ static int __cam_isp_ctx_reg_upd_in_applied_state(
* state so change substate here. * state so change substate here.
*/ */
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH; ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH;
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "next Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
__cam_isp_ctx_update_state_monitor_array(ctx_isp, __cam_isp_ctx_update_state_monitor_array(ctx_isp,
CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, request_id); CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, request_id);
@@ -1068,8 +1079,9 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp,
CAM_REQ_MGR_SOF_EVENT_ERROR); CAM_REQ_MGR_SOF_EVENT_ERROR);
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE;
CAM_DBG(CAM_ISP, "next substate %d", CAM_DBG(CAM_ISP, "next Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
end: end:
if (request_id == 0) { if (request_id == 0) {
req = list_last_entry(&ctx->active_req_list, req = list_last_entry(&ctx->active_req_list,
@@ -1125,9 +1137,17 @@ static int __cam_isp_ctx_sof_in_epoch(struct cam_isp_context *ctx_isp,
CAM_ISP_STATE_CHANGE_TRIGGER_SOF, CAM_ISP_STATE_CHANGE_TRIGGER_SOF,
req->request_id); req->request_id);
if (ctx_isp->frame_id == 1)
CAM_INFO(CAM_ISP, CAM_INFO(CAM_ISP,
"First SOF in EPCR ctx:%d frame_id:%lld next substate %d", "First SOF in EPCR ctx:%d frame_id:%lld next substate %s",
ctx->ctx_id, ctx_isp->frame_id, ctx_isp->substate_activated); ctx->ctx_id, ctx_isp->frame_id,
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
CAM_DBG(CAM_ISP, "SOF in epoch ctx:%d frame_id:%lld next substate:%s",
ctx->ctx_id, ctx_isp->frame_id,
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
return rc; return rc;
} }
@@ -1227,7 +1247,9 @@ static int __cam_isp_ctx_epoch_in_bubble_applied(
CAM_REQ_MGR_SOF_EVENT_SUCCESS); CAM_REQ_MGR_SOF_EVENT_SUCCESS);
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE;
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "next Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
end: end:
req = list_last_entry(&ctx->active_req_list, struct cam_ctx_request, req = list_last_entry(&ctx->active_req_list, struct cam_ctx_request,
list); list);
@@ -1708,7 +1730,9 @@ static int __cam_isp_ctx_fs2_reg_upd_in_applied_state(
rc = -EFAULT; rc = -EFAULT;
} }
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "next Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
end: end:
if (req != NULL && !rc) { if (req != NULL && !rc) {
__cam_isp_ctx_update_state_monitor_array(ctx_isp, __cam_isp_ctx_update_state_monitor_array(ctx_isp,
@@ -1747,7 +1771,7 @@ static struct cam_isp_ctx_irq_ops
.irq_ops = { .irq_ops = {
__cam_isp_ctx_handle_error, __cam_isp_ctx_handle_error,
__cam_isp_ctx_sof_in_epoch, __cam_isp_ctx_sof_in_epoch,
__cam_isp_ctx_reg_upd_in_epoch_state, __cam_isp_ctx_reg_upd_in_epoch_bubble_state,
__cam_isp_ctx_notify_sof_in_activated_state, __cam_isp_ctx_notify_sof_in_activated_state,
__cam_isp_ctx_notify_eof_in_activated_state, __cam_isp_ctx_notify_eof_in_activated_state,
__cam_isp_ctx_buf_done_in_epoch, __cam_isp_ctx_buf_done_in_epoch,
@@ -1758,7 +1782,7 @@ static struct cam_isp_ctx_irq_ops
.irq_ops = { .irq_ops = {
__cam_isp_ctx_handle_error, __cam_isp_ctx_handle_error,
__cam_isp_ctx_sof_in_activated_state, __cam_isp_ctx_sof_in_activated_state,
NULL, __cam_isp_ctx_reg_upd_in_epoch_bubble_state,
__cam_isp_ctx_notify_sof_in_activated_state, __cam_isp_ctx_notify_sof_in_activated_state,
__cam_isp_ctx_notify_eof_in_activated_state, __cam_isp_ctx_notify_eof_in_activated_state,
__cam_isp_ctx_buf_done_in_bubble, __cam_isp_ctx_buf_done_in_bubble,
@@ -1820,7 +1844,7 @@ static struct cam_isp_ctx_irq_ops
.irq_ops = { .irq_ops = {
__cam_isp_ctx_handle_error, __cam_isp_ctx_handle_error,
__cam_isp_ctx_sof_in_epoch, __cam_isp_ctx_sof_in_epoch,
__cam_isp_ctx_reg_upd_in_epoch_state, __cam_isp_ctx_reg_upd_in_epoch_bubble_state,
__cam_isp_ctx_notify_sof_in_activated_state, __cam_isp_ctx_notify_sof_in_activated_state,
__cam_isp_ctx_notify_eof_in_activated_state, __cam_isp_ctx_notify_eof_in_activated_state,
__cam_isp_ctx_fs2_buf_done_in_epoch, __cam_isp_ctx_fs2_buf_done_in_epoch,
@@ -1831,7 +1855,7 @@ static struct cam_isp_ctx_irq_ops
.irq_ops = { .irq_ops = {
__cam_isp_ctx_handle_error, __cam_isp_ctx_handle_error,
__cam_isp_ctx_sof_in_activated_state, __cam_isp_ctx_sof_in_activated_state,
NULL, __cam_isp_ctx_reg_upd_in_epoch_bubble_state,
__cam_isp_ctx_notify_sof_in_activated_state, __cam_isp_ctx_notify_sof_in_activated_state,
__cam_isp_ctx_notify_eof_in_activated_state, __cam_isp_ctx_notify_eof_in_activated_state,
__cam_isp_ctx_buf_done_in_bubble, __cam_isp_ctx_buf_done_in_bubble,
@@ -1866,7 +1890,7 @@ static struct cam_isp_ctx_irq_ops
static int __cam_isp_ctx_apply_req_in_activated_state( static int __cam_isp_ctx_apply_req_in_activated_state(
struct cam_context *ctx, struct cam_req_mgr_apply_request *apply, struct cam_context *ctx, struct cam_req_mgr_apply_request *apply,
uint32_t next_state) enum cam_isp_ctx_activated_substate next_state)
{ {
int rc = 0; int rc = 0;
struct cam_ctx_request *req; struct cam_ctx_request *req;
@@ -1916,8 +1940,10 @@ static int __cam_isp_ctx_apply_req_in_activated_state(
goto end; goto end;
} }
CAM_DBG(CAM_REQ, "Apply request %lld in substate %d ctx %u", CAM_DBG(CAM_REQ, "Apply request %lld in Substate[%s] ctx %u",
req->request_id, ctx_isp->substate_activated, ctx->ctx_id); req->request_id,
__cam_isp_ctx_substate_val_to_type(ctx_isp->substate_activated),
ctx->ctx_id);
req_isp = (struct cam_isp_ctx_req *) req->req_priv; req_isp = (struct cam_isp_ctx_req *) req->req_priv;
if (ctx_isp->active_req_cnt >= 2) { if (ctx_isp->active_req_cnt >= 2) {
@@ -1966,8 +1992,9 @@ static int __cam_isp_ctx_apply_req_in_activated_state(
ctx_isp->last_applied_req_id = apply->request_id; ctx_isp->last_applied_req_id = apply->request_id;
list_del_init(&req->list); list_del_init(&req->list);
list_add_tail(&req->list, &ctx->wait_req_list); list_add_tail(&req->list, &ctx->wait_req_list);
CAM_DBG(CAM_ISP, "new substate state %d, applied req %lld", CAM_DBG(CAM_ISP, "new substate Substate[%s], applied req %lld",
next_state, ctx_isp->last_applied_req_id); __cam_isp_ctx_substate_val_to_type(next_state),
ctx_isp->last_applied_req_id);
spin_unlock_bh(&ctx->lock); spin_unlock_bh(&ctx->lock);
__cam_isp_ctx_update_state_monitor_array(ctx_isp, __cam_isp_ctx_update_state_monitor_array(ctx_isp,
@@ -1985,15 +2012,19 @@ static int __cam_isp_ctx_apply_req_in_sof(
struct cam_isp_context *ctx_isp = struct cam_isp_context *ctx_isp =
(struct cam_isp_context *) ctx->ctx_priv; (struct cam_isp_context *) ctx->ctx_priv;
CAM_DBG(CAM_ISP, "current substate %d", CAM_DBG(CAM_ISP, "current Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply,
CAM_ISP_CTX_ACTIVATED_APPLIED); CAM_ISP_CTX_ACTIVATED_APPLIED);
CAM_DBG(CAM_ISP, "new substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "new Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
if (rc) if (rc)
CAM_DBG(CAM_ISP, "Apply failed in state %d, rc %d", CAM_DBG(CAM_ISP, "Apply failed in Substate[%s], rc %d",
ctx_isp->substate_activated, rc); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated), rc);
return rc; return rc;
} }
@@ -2005,15 +2036,19 @@ static int __cam_isp_ctx_apply_req_in_epoch(
struct cam_isp_context *ctx_isp = struct cam_isp_context *ctx_isp =
(struct cam_isp_context *) ctx->ctx_priv; (struct cam_isp_context *) ctx->ctx_priv;
CAM_DBG(CAM_ISP, "current substate %d", CAM_DBG(CAM_ISP, "current Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply,
CAM_ISP_CTX_ACTIVATED_APPLIED); CAM_ISP_CTX_ACTIVATED_APPLIED);
CAM_DBG(CAM_ISP, "new substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "new Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
if (rc) if (rc)
CAM_DBG(CAM_ISP, "Apply failed in state %d, rc %d", CAM_DBG(CAM_ISP, "Apply failed in Substate[%s], rc %d",
ctx_isp->substate_activated, rc); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated), rc);
return rc; return rc;
} }
@@ -2025,15 +2060,19 @@ static int __cam_isp_ctx_apply_req_in_bubble(
struct cam_isp_context *ctx_isp = struct cam_isp_context *ctx_isp =
(struct cam_isp_context *) ctx->ctx_priv; (struct cam_isp_context *) ctx->ctx_priv;
CAM_DBG(CAM_ISP, "current substate %d", CAM_DBG(CAM_ISP, "current Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply,
CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED); CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED);
CAM_DBG(CAM_ISP, "new substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "new Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
if (rc) if (rc)
CAM_DBG(CAM_ISP, "Apply failed in state %d, rc %d", CAM_DBG(CAM_ISP, "Apply failed in Substate[%s], rc %d",
ctx_isp->substate_activated, rc); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated), rc);
return rc; return rc;
} }
@@ -2103,6 +2142,7 @@ static int __cam_isp_ctx_flush_req(struct cam_context *ctx,
} }
} }
req_isp->reapply = false; req_isp->reapply = false;
list_del_init(&req->list);
list_add_tail(&req->list, &ctx->free_req_list); list_add_tail(&req->list, &ctx->free_req_list);
} }
@@ -2127,17 +2167,27 @@ static int __cam_isp_ctx_flush_req_in_top_state(
struct cam_hw_cmd_args hw_cmd_args; struct cam_hw_cmd_args hw_cmd_args;
ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; ctx_isp = (struct cam_isp_context *) ctx->ctx_priv;
if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) {
CAM_INFO(CAM_ISP, "Last request id to flush is %lld",
flush_req->req_id);
ctx->last_flush_req = flush_req->req_id;
}
CAM_DBG(CAM_ISP, "Flush pending list"); CAM_DBG(CAM_ISP, "Flush pending list");
spin_lock_bh(&ctx->lock); spin_lock_bh(&ctx->lock);
rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); rc = __cam_isp_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req);
spin_unlock_bh(&ctx->lock); spin_unlock_bh(&ctx->lock);
if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) {
if (ctx->state <= CAM_CTX_READY) {
ctx->state = CAM_CTX_ACQUIRED;
goto end;
}
spin_lock_bh(&ctx->lock);
ctx->state = CAM_CTX_FLUSHED;
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HALT;
spin_unlock_bh(&ctx->lock);
CAM_INFO(CAM_ISP, "Last request id to flush is %lld",
flush_req->req_id);
ctx->last_flush_req = flush_req->req_id;
memset(&hw_cmd_args, 0, sizeof(hw_cmd_args)); memset(&hw_cmd_args, 0, sizeof(hw_cmd_args));
hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; hw_cmd_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map;
hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH; hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH;
@@ -2148,12 +2198,6 @@ static int __cam_isp_ctx_flush_req_in_top_state(
rc = 0; rc = 0;
} }
if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) {
if (ctx->state <= CAM_CTX_READY) {
ctx->state = CAM_CTX_ACQUIRED;
goto end;
}
stop_args.ctxt_to_hw_map = ctx_isp->hw_ctx; stop_args.ctxt_to_hw_map = ctx_isp->hw_ctx;
stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY; stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY;
stop_isp.stop_only = true; stop_isp.stop_only = true;
@@ -2184,8 +2228,6 @@ static int __cam_isp_ctx_flush_req_in_top_state(
if (rc) if (rc)
CAM_ERR(CAM_ISP, "Failed to reset HW rc: %d", rc); CAM_ERR(CAM_ISP, "Failed to reset HW rc: %d", rc);
ctx->state = CAM_CTX_FLUSHED;
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HALT;
ctx_isp->init_received = false; ctx_isp->init_received = false;
} }
@@ -2376,8 +2418,9 @@ static int __cam_isp_ctx_rdi_only_sof_in_top_state(
else else
CAM_DBG(CAM_ISP, "Still need to wait for the buf done"); CAM_DBG(CAM_ISP, "Still need to wait for the buf done");
CAM_DBG(CAM_ISP, "next substate %d", CAM_DBG(CAM_ISP, "next Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
return rc; return rc;
} }
@@ -2398,7 +2441,9 @@ static int __cam_isp_ctx_rdi_only_sof_in_applied_state(
ctx_isp->frame_id, ctx_isp->sof_timestamp_val); ctx_isp->frame_id, ctx_isp->sof_timestamp_val);
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED; ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED;
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "next Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
return 0; return 0;
} }
@@ -2494,7 +2539,9 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied(
/* change the state to bubble, as reg update has not come */ /* change the state to bubble, as reg update has not come */
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE;
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "next Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
end: end:
return 0; return 0;
} }
@@ -2566,8 +2613,9 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state(
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF;
CAM_DBG(CAM_ISP, "next substate %d", CAM_DBG(CAM_ISP, "next Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
return 0; return 0;
} }
@@ -2631,7 +2679,9 @@ static int __cam_isp_ctx_rdi_only_reg_upd_in_bubble_applied_state(
__cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id,
CAM_REQ_MGR_SOF_EVENT_SUCCESS); CAM_REQ_MGR_SOF_EVENT_SUCCESS);
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "next Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
return 0; return 0;
error: error:
@@ -2721,15 +2771,19 @@ static int __cam_isp_ctx_rdi_only_apply_req_top_state(
struct cam_isp_context *ctx_isp = struct cam_isp_context *ctx_isp =
(struct cam_isp_context *) ctx->ctx_priv; (struct cam_isp_context *) ctx->ctx_priv;
CAM_DBG(CAM_ISP, "current substate %d", CAM_DBG(CAM_ISP, "current Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply, rc = __cam_isp_ctx_apply_req_in_activated_state(ctx, apply,
CAM_ISP_CTX_ACTIVATED_APPLIED); CAM_ISP_CTX_ACTIVATED_APPLIED);
CAM_DBG(CAM_ISP, "new substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "new Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
if (rc) if (rc)
CAM_ERR(CAM_ISP, "Apply failed in state %d, rc %d", CAM_ERR(CAM_ISP, "Apply failed in Substate[%s], rc %d",
ctx_isp->substate_activated, rc); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated), rc);
return rc; return rc;
} }
@@ -3025,10 +3079,12 @@ static int __cam_isp_ctx_config_dev_in_top_state(
ctx_isp->init_received = true; ctx_isp->init_received = true;
} else { } else {
rc = -EINVAL; rc = -EINVAL;
CAM_ERR(CAM_ISP, "Recevied INIT pkt in wrong state"); CAM_ERR(CAM_ISP, "Recevied INIT pkt in wrong state:%d",
ctx->state);
} }
} else { } else {
if (ctx->state >= CAM_CTX_READY && ctx->ctx_crm_intf->add_req) { if (ctx->state != CAM_CTX_FLUSHED && ctx->state >= CAM_CTX_READY
&& ctx->ctx_crm_intf->add_req) {
add_req.link_hdl = ctx->link_hdl; add_req.link_hdl = ctx->link_hdl;
add_req.dev_hdl = ctx->dev_hdl; add_req.dev_hdl = ctx->dev_hdl;
add_req.req_id = req->request_id; add_req.req_id = req->request_id;
@@ -3043,7 +3099,9 @@ static int __cam_isp_ctx_config_dev_in_top_state(
} }
} else { } else {
rc = -EINVAL; rc = -EINVAL;
CAM_ERR(CAM_ISP, "Recevied Update in wrong state"); CAM_ERR(CAM_ISP,
"Recevied update req %lld in wrong state:%d",
req->request_id, ctx->state);
} }
} }
if (rc) if (rc)
@@ -3734,6 +3792,8 @@ static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx,
CAM_ERR(CAM_ISP, "Start HW failed"); CAM_ERR(CAM_ISP, "Start HW failed");
ctx->state = CAM_CTX_READY; ctx->state = CAM_CTX_READY;
trace_cam_context_state("ISP", ctx); trace_cam_context_state("ISP", ctx);
if (rc == -ETIMEDOUT)
cam_isp_ctx_dump_req(req_isp);
list_del_init(&req->list); list_del_init(&req->list);
list_add(&req->list, &ctx->pending_req_list); list_add(&req->list, &ctx->pending_req_list);
goto end; goto end;
@@ -3789,7 +3849,9 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock(
spin_lock_bh(&ctx->lock); spin_lock_bh(&ctx->lock);
ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HALT; ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_HALT;
spin_unlock_bh(&ctx->lock); spin_unlock_bh(&ctx->lock);
CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); CAM_DBG(CAM_ISP, "next Substate[%s]",
__cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
while (!list_empty(&ctx->pending_req_list)) { while (!list_empty(&ctx->pending_req_list)) {
req = list_first_entry(&ctx->pending_req_list, req = list_first_entry(&ctx->pending_req_list,
@@ -4013,22 +4075,25 @@ static int __cam_isp_ctx_apply_req(struct cam_context *ctx,
(struct cam_isp_context *) ctx->ctx_priv; (struct cam_isp_context *) ctx->ctx_priv;
trace_cam_apply_req("ISP", apply->request_id); trace_cam_apply_req("ISP", apply->request_id);
CAM_DBG(CAM_ISP, "Enter: apply req in Substate %d request _id:%lld", CAM_DBG(CAM_ISP, "Enter: apply req in Substate[%s] request_id:%lld",
ctx_isp->substate_activated, apply->request_id); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated), apply->request_id);
ctx_ops = &ctx_isp->substate_machine[ctx_isp->substate_activated]; ctx_ops = &ctx_isp->substate_machine[ctx_isp->substate_activated];
if (ctx_ops->crm_ops.apply_req) { if (ctx_ops->crm_ops.apply_req) {
rc = ctx_ops->crm_ops.apply_req(ctx, apply); rc = ctx_ops->crm_ops.apply_req(ctx, apply);
} else { } else {
CAM_WARN_RATE_LIMIT(CAM_ISP, CAM_WARN_RATE_LIMIT(CAM_ISP,
"No handle function in activated substate %d", "No handle function in activated Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
rc = -EFAULT; rc = -EFAULT;
} }
if (rc) if (rc)
CAM_WARN_RATE_LIMIT(CAM_ISP, CAM_WARN_RATE_LIMIT(CAM_ISP,
"Apply failed in active substate %d rc %d", "Apply failed in active Substate[%s] rc %d",
ctx_isp->substate_activated, rc); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated), rc);
return rc; return rc;
} }
@@ -4048,20 +4113,23 @@ static int __cam_isp_ctx_handle_irq_in_activated(void *context,
trace_cam_isp_activated_irq(ctx, ctx_isp->substate_activated, evt_id, trace_cam_isp_activated_irq(ctx, ctx_isp->substate_activated, evt_id,
__cam_isp_ctx_get_event_ts(evt_id, evt_data)); __cam_isp_ctx_get_event_ts(evt_id, evt_data));
CAM_DBG(CAM_ISP, "Enter: State %d, Substate %d, evt id %d", CAM_DBG(CAM_ISP, "Enter: State %d, Substate[%s], evt id %d",
ctx->state, ctx_isp->substate_activated, evt_id); ctx->state, __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated), evt_id);
irq_ops = &ctx_isp->substate_machine_irq[ctx_isp->substate_activated]; irq_ops = &ctx_isp->substate_machine_irq[ctx_isp->substate_activated];
if (irq_ops->irq_ops[evt_id]) { if (irq_ops->irq_ops[evt_id]) {
rc = irq_ops->irq_ops[evt_id](ctx_isp, evt_data); rc = irq_ops->irq_ops[evt_id](ctx_isp, evt_data);
} else { } else {
CAM_DBG(CAM_ISP, "No handle function for substate %d", CAM_DBG(CAM_ISP, "No handle function for Substate[%s]",
ctx_isp->substate_activated); __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
if (isp_ctx_debug.enable_state_monitor_dump) if (isp_ctx_debug.enable_state_monitor_dump)
__cam_isp_ctx_dump_state_monitor_array(ctx_isp); __cam_isp_ctx_dump_state_monitor_array(ctx_isp);
} }
CAM_DBG(CAM_ISP, "Exit: State %d Substate %d", CAM_DBG(CAM_ISP, "Exit: State %d Substate[%s]",
ctx->state, ctx_isp->substate_activated); ctx->state, __cam_isp_ctx_substate_val_to_type(
ctx_isp->substate_activated));
spin_unlock(&ctx->lock); spin_unlock(&ctx->lock);
return rc; return rc;
} }
@@ -4339,7 +4407,9 @@ int cam_isp_context_deinit(struct cam_isp_context *ctx)
cam_context_deinit(ctx->base); cam_context_deinit(ctx->base);
if (ctx->substate_activated != CAM_ISP_CTX_ACTIVATED_SOF) if (ctx->substate_activated != CAM_ISP_CTX_ACTIVATED_SOF)
CAM_ERR(CAM_ISP, "ISP context substate is invalid"); CAM_ERR(CAM_ISP, "ISP context Substate[%s] is invalid",
__cam_isp_ctx_substate_val_to_type(
ctx->substate_activated));
memset(ctx, 0, sizeof(*ctx)); memset(ctx, 0, sizeof(*ctx));
return rc; return rc;

2
drivers/cam_isp/cam_isp_context.h
View File

@@ -183,7 +183,7 @@ struct cam_isp_context {
struct cam_context *base; struct cam_context *base;
int64_t frame_id; int64_t frame_id;
uint32_t substate_activated; enum cam_isp_ctx_activated_substate substate_activated;
atomic_t process_bubble; atomic_t process_bubble;
uint32_t bubble_frame_cnt; uint32_t bubble_frame_cnt;
struct cam_ctx_ops *substate_machine; struct cam_ctx_ops *substate_machine;

32
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
View File

@@ -2411,8 +2411,8 @@ static int cam_ife_mgr_acquire_hw_for_ctx(
goto err; goto err;
} }
*num_pix_port += ipp_count + ppp_count + ife_rd_count + lcr_count; *num_pix_port = ipp_count + ppp_count + ife_rd_count + lcr_count;
*num_rdi_port += rdi_count; *num_rdi_port = rdi_count;
return 0; return 0;
err: err:
@@ -3241,7 +3241,7 @@ static int cam_isp_blob_bw_update_v2(
sizeof( sizeof(
struct cam_vfe_bw_update_args_v2)); struct cam_vfe_bw_update_args_v2));
if (rc) if (rc)
CAM_ERR(CAM_ISP, CAM_ERR(CAM_PERF,
"BW Update failed rc: %d", rc); "BW Update failed rc: %d", rc);
} else { } else {
CAM_WARN(CAM_ISP, "NULL hw_intf!"); CAM_WARN(CAM_ISP, "NULL hw_intf!");
@@ -3340,7 +3340,7 @@ static int cam_isp_blob_bw_update(
&bw_upd_args, &bw_upd_args,
sizeof(struct cam_vfe_bw_update_args)); sizeof(struct cam_vfe_bw_update_args));
if (rc) if (rc)
CAM_ERR(CAM_ISP, "BW Update failed"); CAM_ERR(CAM_PERF, "BW Update failed");
} else } else
CAM_WARN(CAM_ISP, "NULL hw_intf!"); CAM_WARN(CAM_ISP, "NULL hw_intf!");
} }
@@ -3389,7 +3389,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv,
for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) {
if (hw_update_data->bw_config_valid[i] == true) { if (hw_update_data->bw_config_valid[i] == true) {
CAM_DBG(CAM_ISP, "idx=%d, bw_config_version=%d", CAM_DBG(CAM_PERF, "idx=%d, bw_config_version=%d",
ctx, ctx->ctx_index, i, ctx, ctx->ctx_index, i,
hw_update_data->bw_config_version); hw_update_data->bw_config_version);
@@ -3399,7 +3399,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv,
(struct cam_isp_bw_config *) (struct cam_isp_bw_config *)
&hw_update_data->bw_config[i], ctx); &hw_update_data->bw_config[i], ctx);
if (rc) if (rc)
CAM_ERR(CAM_ISP, CAM_ERR(CAM_PERF,
"Bandwidth Update Failed rc: %d", rc); "Bandwidth Update Failed rc: %d", rc);
} else if (hw_update_data->bw_config_version == } else if (hw_update_data->bw_config_version ==
CAM_ISP_BW_CONFIG_V2) { CAM_ISP_BW_CONFIG_V2) {
@@ -3407,11 +3407,11 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv,
(struct cam_isp_bw_config_v2 *) (struct cam_isp_bw_config_v2 *)
&hw_update_data->bw_config_v2[i], ctx); &hw_update_data->bw_config_v2[i], ctx);
if (rc) if (rc)
CAM_ERR(CAM_ISP, CAM_ERR(CAM_PERF,
"Bandwidth Update Failed rc: %d", rc); "Bandwidth Update Failed rc: %d", rc);
} else { } else {
CAM_ERR(CAM_ISP, CAM_ERR(CAM_PERF,
"Invalid bw config version: %d", "Invalid bw config version: %d",
hw_update_data->bw_config_version); hw_update_data->bw_config_version);
} }
@@ -4878,7 +4878,7 @@ static int cam_isp_blob_clock_update(
if (hw_intf && hw_intf->hw_ops.process_cmd) { if (hw_intf && hw_intf->hw_ops.process_cmd) {
clock_upd_args.node_res = clock_upd_args.node_res =
hw_mgr_res->hw_res[i]; hw_mgr_res->hw_res[i];
CAM_DBG(CAM_ISP, CAM_DBG(CAM_PERF,
"res_id=%u i= %d clk=%llu\n", "res_id=%u i= %d clk=%llu\n",
hw_mgr_res->res_id, i, clk_rate); hw_mgr_res->res_id, i, clk_rate);
@@ -4891,7 +4891,8 @@ static int cam_isp_blob_clock_update(
sizeof( sizeof(
struct cam_vfe_clock_update_args)); struct cam_vfe_clock_update_args));
if (rc) if (rc)
CAM_ERR(CAM_ISP, "Clock Update failed"); CAM_ERR(CAM_PERF,
"Clock Update failed");
} else } else
CAM_WARN(CAM_ISP, "NULL hw_intf!"); CAM_WARN(CAM_ISP, "NULL hw_intf!");
} }
@@ -5117,14 +5118,14 @@ static int cam_isp_packet_generic_blob_handler(void *user_data,
rc = cam_isp_blob_clock_update(blob_type, blob_info, rc = cam_isp_blob_clock_update(blob_type, blob_info,
clock_config, prepare); clock_config, prepare);
if (rc) if (rc)
CAM_ERR(CAM_ISP, "Clock Update Failed"); CAM_ERR(CAM_PERF, "Clock Update Failed, rc=%d", rc);
} }
break; break;
case CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG: { case CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG: {
struct cam_isp_bw_config *bw_config; struct cam_isp_bw_config *bw_config;
struct cam_isp_prepare_hw_update_data *prepare_hw_data; struct cam_isp_prepare_hw_update_data *prepare_hw_data;
CAM_WARN_RATE_LIMIT_CUSTOM(CAM_ISP, 300, 1, CAM_WARN_RATE_LIMIT_CUSTOM(CAM_PERF, 300, 1,
"Deprecated Blob TYPE_BW_CONFIG"); "Deprecated Blob TYPE_BW_CONFIG");
if (blob_size < sizeof(struct cam_isp_bw_config)) { if (blob_size < sizeof(struct cam_isp_bw_config)) {
CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size);
@@ -5742,7 +5743,7 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet,
io_cfg[i].mem_handle[j]); io_cfg[i].mem_handle[j]);
continue; continue;
} }
if (iova_addr >> 32) { if ((iova_addr & 0xFFFFFFFF) != iova_addr) {
CAM_ERR(CAM_ISP, "Invalid mapped address"); CAM_ERR(CAM_ISP, "Invalid mapped address");
rc = -EINVAL; rc = -EINVAL;
continue; continue;
@@ -5889,7 +5890,9 @@ static int cam_ife_mgr_cmd_get_sof_timestamp(
struct cam_hw_intf *hw_intf; struct cam_hw_intf *hw_intf;
struct cam_csid_get_time_stamp_args csid_get_time; struct cam_csid_get_time_stamp_args csid_get_time;
list_for_each_entry(hw_mgr_res, &ife_ctx->res_list_ife_csid, list) { hw_mgr_res = list_first_entry(&ife_ctx->res_list_ife_csid,
struct cam_ife_hw_mgr_res, list);
for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
if (!hw_mgr_res->hw_res[i]) if (!hw_mgr_res->hw_res[i])
continue; continue;
@@ -5926,7 +5929,6 @@ static int cam_ife_mgr_cmd_get_sof_timestamp(
} }
} }
} }
}
if (rc) if (rc)
CAM_ERR_RATE_LIMIT(CAM_ISP, "Getting sof time stamp failed"); CAM_ERR_RATE_LIMIT(CAM_ISP, "Getting sof time stamp failed");

18
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
View File

@@ -535,6 +535,7 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw)
CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d", CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d",
csid_hw->hw_intf->hw_idx, val); csid_hw->hw_intf->hw_idx, val);
csid_hw->error_irq_count = 0; csid_hw->error_irq_count = 0;
csid_hw->prev_boot_timestamp = 0;
return rc; return rc;
} }
@@ -1330,6 +1331,7 @@ static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw)
spin_unlock_irqrestore(&csid_hw->lock_state, flags); spin_unlock_irqrestore(&csid_hw->lock_state, flags);
csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN;
csid_hw->error_irq_count = 0; csid_hw->error_irq_count = 0;
csid_hw->prev_boot_timestamp = 0;
return rc; return rc;
} }
@@ -2929,6 +2931,7 @@ static int cam_ife_csid_get_time_stamp(
const struct cam_ife_csid_udi_reg_offset *udi_reg; const struct cam_ife_csid_udi_reg_offset *udi_reg;
struct timespec64 ts; struct timespec64 ts;
uint32_t time_32, id; uint32_t time_32, id;
uint64_t time_delta;
time_stamp = (struct cam_csid_get_time_stamp_args *)cmd_args; time_stamp = (struct cam_csid_get_time_stamp_args *)cmd_args;
res = time_stamp->node_res; res = time_stamp->node_res;
@@ -3000,9 +3003,22 @@ static int cam_ife_csid_get_time_stamp(
CAM_IFE_CSID_QTIMER_MUL_FACTOR, CAM_IFE_CSID_QTIMER_MUL_FACTOR,
CAM_IFE_CSID_QTIMER_DIV_FACTOR); CAM_IFE_CSID_QTIMER_DIV_FACTOR);
if (!csid_hw->prev_boot_timestamp) {
get_monotonic_boottime64(&ts); get_monotonic_boottime64(&ts);
time_stamp->boot_timestamp = (uint64_t)((ts.tv_sec * 1000000000) + time_stamp->boot_timestamp =
(uint64_t)((ts.tv_sec * 1000000000) +
ts.tv_nsec); ts.tv_nsec);
csid_hw->prev_qtimer_ts = 0;
CAM_DBG(CAM_ISP, "timestamp:%lld",
time_stamp->boot_timestamp);
} else {
time_delta = time_stamp->time_stamp_val -
csid_hw->prev_qtimer_ts;
time_stamp->boot_timestamp =
csid_hw->prev_boot_timestamp + time_delta;
}
csid_hw->prev_qtimer_ts = time_stamp->time_stamp_val;
csid_hw->prev_boot_timestamp = time_stamp->boot_timestamp;
return 0; return 0;
} }

4
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h
View File

@@ -550,6 +550,8 @@ struct cam_ife_csid_path_cfg {
* @binning_enable Flag is set if hardware supports QCFA binning * @binning_enable Flag is set if hardware supports QCFA binning
* @binning_supported Flag is set if sensor supports QCFA binning * @binning_supported Flag is set if sensor supports QCFA binning
* *
* @first_sof_ts first bootime stamp at the start
* @prev_qtimer_ts stores csid timestamp
*/ */
struct cam_ife_csid_hw { struct cam_ife_csid_hw {
struct cam_hw_intf *hw_intf; struct cam_hw_intf *hw_intf;
@@ -581,6 +583,8 @@ struct cam_ife_csid_hw {
spinlock_t lock_state; spinlock_t lock_state;
uint32_t binning_enable; uint32_t binning_enable;
uint32_t binning_supported; uint32_t binning_supported;
uint64_t prev_boot_timestamp;
uint64_t prev_qtimer_ts;
}; };
int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf,

3
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*/ */
#ifndef _CAM_IFE_CSID_LITE17X_H_ #ifndef _CAM_IFE_CSID_LITE17X_H_
@@ -286,6 +286,7 @@ static const struct cam_ife_csid_common_reg_offset
.path_rst_stb_all = 0x7f, .path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1, .path_rst_done_shift_val = 1,
.path_en_shift_val = 31, .path_en_shift_val = 31,
.packing_fmt_shift_val = 30,
.dt_id_shift_val = 27, .dt_id_shift_val = 27,
.vc_shift_val = 22, .vc_shift_val = 22,
.dt_shift_val = 16, .dt_shift_val = 16,

8
drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c
View File

@@ -656,22 +656,22 @@ static void cam_jpeg_mgr_print_io_bufs(struct cam_packet *packet,
CAM_ERR(CAM_UTIL, "get src buf address fail"); CAM_ERR(CAM_UTIL, "get src buf address fail");
continue; continue;
} }
if (iova_addr >> 32) { if ((iova_addr & 0xFFFFFFFF) != iova_addr) {
CAM_ERR(CAM_JPEG, "Invalid mapped address"); CAM_ERR(CAM_JPEG, "Invalid mapped address");
rc = -EINVAL; rc = -EINVAL;
continue; continue;
} }
CAM_INFO(CAM_JPEG, CAM_INFO(CAM_JPEG,
"pln %d w %d h %d size %d addr 0x%x offset 0x%x memh %x", "pln %u w %u h %u stride %u slice %u size %d addr 0x%x offset 0x%x memh %x",
j, io_cfg[i].planes[j].width, j, io_cfg[i].planes[j].width,
io_cfg[i].planes[j].height, io_cfg[i].planes[j].height,
io_cfg[i].planes[j].plane_stride,
io_cfg[i].planes[j].slice_height,
(int32_t)src_buf_size, (int32_t)src_buf_size,
(unsigned int)iova_addr, (unsigned int)iova_addr,
io_cfg[i].offsets[j], io_cfg[i].offsets[j],
io_cfg[i].mem_handle[j]); io_cfg[i].mem_handle[j]);
iova_addr += io_cfg[i].offsets[j];
} }
} }
} }

99
drivers/cam_req_mgr/cam_req_mgr_core.c
View File

@@ -443,6 +443,7 @@ static void __cam_req_mgr_flush_req_slot(
slot->req_id = -1; slot->req_id = -1;
slot->skip_idx = 1; slot->skip_idx = 1;
slot->recover = 0; slot->recover = 0;
slot->additional_timeout = 0;
slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC;
slot->status = CRM_SLOT_STATUS_NO_REQ; slot->status = CRM_SLOT_STATUS_NO_REQ;
@@ -486,6 +487,7 @@ static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link,
slot->req_id = -1; slot->req_id = -1;
slot->skip_idx = 0; slot->skip_idx = 0;
slot->recover = 0; slot->recover = 0;
slot->additional_timeout = 0;
slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC;
slot->status = CRM_SLOT_STATUS_NO_REQ; slot->status = CRM_SLOT_STATUS_NO_REQ;
@@ -499,6 +501,66 @@ static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link,
} }
} }
/**
* __cam_req_mgr_validate_crm_wd_timer()
*
* @brief : Validate/modify the wd timer based on associated
* timeout with the request
* @link : link pointer
*
*/
static void __cam_req_mgr_validate_crm_wd_timer(
struct cam_req_mgr_core_link *link)
{
int idx = 0;
int next_frame_timeout = 0, current_frame_timeout = 0;
struct cam_req_mgr_req_queue *in_q = link->req.in_q;
idx = in_q->rd_idx;
__cam_req_mgr_dec_idx(
&idx, (link->max_delay - 1),
in_q->num_slots);
next_frame_timeout = in_q->slot[idx].additional_timeout;
CAM_DBG(CAM_CRM,
"rd_idx: %d idx: %d next_frame_timeout: %d ms",
in_q->rd_idx, idx, next_frame_timeout);
idx = in_q->rd_idx;
__cam_req_mgr_dec_idx(
&idx, link->max_delay,
in_q->num_slots);
current_frame_timeout = in_q->slot[idx].additional_timeout;
CAM_DBG(CAM_CRM,
"rd_idx: %d idx: %d current_frame_timeout: %d ms",
in_q->rd_idx, idx, current_frame_timeout);
if ((next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT) >
link->watchdog->expires) {
CAM_DBG(CAM_CRM,
"Modifying wd timer expiry from %d ms to %d ms",
link->watchdog->expires,
(next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT));
crm_timer_modify(link->watchdog,
next_frame_timeout +
CAM_REQ_MGR_WATCHDOG_TIMEOUT);
} else if (current_frame_timeout) {
CAM_DBG(CAM_CRM,
"Reset wd timer to current frame from %d ms to %d ms",
link->watchdog->expires,
(current_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT));
crm_timer_modify(link->watchdog,
current_frame_timeout +
CAM_REQ_MGR_WATCHDOG_TIMEOUT);
} else if (link->watchdog->expires >
CAM_REQ_MGR_WATCHDOG_TIMEOUT) {
CAM_DBG(CAM_CRM,
"Reset wd timer to default from %d ms to %d ms",
link->watchdog->expires, CAM_REQ_MGR_WATCHDOG_TIMEOUT);
crm_timer_modify(link->watchdog,
CAM_REQ_MGR_WATCHDOG_TIMEOUT);
}
}
/** /**
* __cam_req_mgr_check_for_lower_pd_devices() * __cam_req_mgr_check_for_lower_pd_devices()
* *
@@ -1198,10 +1260,11 @@ static int __cam_req_mgr_check_sync_req_is_ready(
* difference of two SOF timestamp less than * difference of two SOF timestamp less than
* (sync_frame_duration / 5). * (sync_frame_duration / 5).
*/ */
do_div(sync_frame_duration, 5);
if ((link->sof_timestamp > sync_link->sof_timestamp) && if ((link->sof_timestamp > sync_link->sof_timestamp) &&
(sync_link->sof_timestamp > 0) && (sync_link->sof_timestamp > 0) &&
(link->sof_timestamp - sync_link->sof_timestamp < (link->sof_timestamp - sync_link->sof_timestamp <
sync_frame_duration / 5) && sync_frame_duration) &&
(sync_rd_slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC)) { (sync_rd_slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC)) {
/* /*
@@ -1274,9 +1337,11 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link,
* - if in applied_state, somthign wrong. * - if in applied_state, somthign wrong.
* - if in no_req state, no new req * - if in no_req state, no new req
*/ */
CAM_DBG(CAM_REQ, "SOF Req[%lld] idx %d req_status %d link_hdl %x", CAM_DBG(CAM_REQ,
"SOF Req[%lld] idx %d req_status %d link_hdl %x wd_timeout %d ms",
in_q->slot[in_q->rd_idx].req_id, in_q->rd_idx, in_q->slot[in_q->rd_idx].req_id, in_q->rd_idx,
in_q->slot[in_q->rd_idx].status, link->link_hdl); in_q->slot[in_q->rd_idx].status, link->link_hdl,
in_q->slot[in_q->rd_idx].additional_timeout);
slot = &in_q->slot[in_q->rd_idx]; slot = &in_q->slot[in_q->rd_idx];
if (slot->status == CRM_SLOT_STATUS_NO_REQ) { if (slot->status == CRM_SLOT_STATUS_NO_REQ) {
@@ -1392,6 +1457,9 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link,
link->trigger_mask |= trigger; link->trigger_mask |= trigger;
/* Check for any long exposure settings */
__cam_req_mgr_validate_crm_wd_timer(link);
CAM_DBG(CAM_CRM, "Applied req[%lld] on link[%x] success", CAM_DBG(CAM_CRM, "Applied req[%lld] on link[%x] success",
slot->req_id, link->link_hdl); slot->req_id, link->link_hdl);
spin_lock_bh(&link->link_state_spin_lock); spin_lock_bh(&link->link_state_spin_lock);
@@ -1640,7 +1708,7 @@ static int __cam_req_mgr_process_sof_freeze(void *priv, void *data)
memset(&msg, 0, sizeof(msg)); memset(&msg, 0, sizeof(msg));
msg.session_hdl = session->session_hdl; msg.session_hdl = session->session_hdl;
msg.u.err_msg.error_type = CAM_REQ_MGR_ERROR_TYPE_RECOVERY; msg.u.err_msg.error_type = CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE;
msg.u.err_msg.request_id = 0; msg.u.err_msg.request_id = 0;
msg.u.err_msg.link_hdl = link->link_hdl; msg.u.err_msg.link_hdl = link->link_hdl;
@@ -2029,6 +2097,7 @@ int cam_req_mgr_process_flush_req(void *priv, void *data)
mutex_unlock(&link->req.lock); mutex_unlock(&link->req.lock);
return -EINVAL; return -EINVAL;
} }
slot->additional_timeout = 0;
__cam_req_mgr_in_q_skip_idx(in_q, idx); __cam_req_mgr_in_q_skip_idx(in_q, idx);
} }
} }
@@ -2080,10 +2149,11 @@ int cam_req_mgr_process_sched_req(void *priv, void *data)
in_q = link->req.in_q; in_q = link->req.in_q;
CAM_DBG(CAM_CRM, CAM_DBG(CAM_CRM,
"link_hdl %x req_id %lld at slot %d sync_mode %d is_master:%d", "link_hdl %x req_id %lld at slot %d sync_mode %d is_master %d exp_timeout_val %d ms",
sched_req->link_hdl, sched_req->req_id, sched_req->link_hdl, sched_req->req_id,
in_q->wr_idx, sched_req->sync_mode, in_q->wr_idx, sched_req->sync_mode,
link->is_master); link->is_master,
sched_req->additional_timeout);
mutex_lock(&link->req.lock); mutex_lock(&link->req.lock);
slot = &in_q->slot[in_q->wr_idx]; slot = &in_q->slot[in_q->wr_idx];
@@ -2097,6 +2167,22 @@ int cam_req_mgr_process_sched_req(void *priv, void *data)
slot->sync_mode = sched_req->sync_mode; slot->sync_mode = sched_req->sync_mode;
slot->skip_idx = 0; slot->skip_idx = 0;
slot->recover = sched_req->bubble_enable; slot->recover = sched_req->bubble_enable;
if (sched_req->additional_timeout < 0) {
CAM_WARN(CAM_CRM,
"Requested timeout is invalid [%dms]",
sched_req->additional_timeout);
slot->additional_timeout = 0;
} else if (sched_req->additional_timeout >
CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX) {
CAM_WARN(CAM_CRM,
"Requested timeout [%dms] max supported timeout [%dms] resetting to max",
sched_req->additional_timeout,
CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX);
slot->additional_timeout = CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX;
} else {
slot->additional_timeout = sched_req->additional_timeout;
}
link->open_req_cnt++; link->open_req_cnt++;
__cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots); __cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots);
@@ -3260,6 +3346,7 @@ int cam_req_mgr_schedule_request(
sched->req_id = sched_req->req_id; sched->req_id = sched_req->req_id;
sched->sync_mode = sched_req->sync_mode; sched->sync_mode = sched_req->sync_mode;
sched->link_hdl = sched_req->link_hdl; sched->link_hdl = sched_req->link_hdl;
sched->additional_timeout = sched_req->additional_timeout;
if (session->force_err_recovery == AUTO_RECOVERY) { if (session->force_err_recovery == AUTO_RECOVERY) {
sched->bubble_enable = sched_req->bubble_enable; sched->bubble_enable = sched_req->bubble_enable;
} else { } else {

6
drivers/cam_req_mgr/cam_req_mgr_core.h
View File

@@ -13,7 +13,8 @@
#define CAM_REQ_MGR_MAX_LINKED_DEV 16 #define CAM_REQ_MGR_MAX_LINKED_DEV 16
#define MAX_REQ_SLOTS 48 #define MAX_REQ_SLOTS 48
#define CAM_REQ_MGR_WATCHDOG_TIMEOUT 5000 #define CAM_REQ_MGR_WATCHDOG_TIMEOUT 1000
#define CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX 50000
#define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000 #define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000
#define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30 #define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30
@@ -233,6 +234,8 @@ struct cam_req_mgr_req_tbl {
* @recover : if user enabled recovery for this request. * @recover : if user enabled recovery for this request.
* @req_id : mask tracking which all devices have request ready * @req_id : mask tracking which all devices have request ready
* @sync_mode : Sync mode in which req id in this slot has to applied * @sync_mode : Sync mode in which req id in this slot has to applied
* @additional_timeout : Adjusted watchdog timeout value associated with
* this request
*/ */
struct cam_req_mgr_slot { struct cam_req_mgr_slot {
int32_t idx; int32_t idx;
@@ -241,6 +244,7 @@ struct cam_req_mgr_slot {
int32_t recover; int32_t recover;
int64_t req_id; int64_t req_id;
int32_t sync_mode; int32_t sync_mode;
int32_t additional_timeout;
}; };
/** /**

4
drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h
View File

@@ -30,16 +30,12 @@
#define NUM_MASTERS 2 #define NUM_MASTERS 2
#define NUM_QUEUES 2 #define NUM_QUEUES 2
#define TRUE 1
#define FALSE 0
#define ACTUATOR_DRIVER_I2C "i2c_actuator" #define ACTUATOR_DRIVER_I2C "i2c_actuator"
#define CAMX_ACTUATOR_DEV_NAME "cam-actuator-driver" #define CAMX_ACTUATOR_DEV_NAME "cam-actuator-driver"
#define MSM_ACTUATOR_MAX_VREGS (10) #define MSM_ACTUATOR_MAX_VREGS (10)
#define ACTUATOR_MAX_POLL_COUNT 10 #define ACTUATOR_MAX_POLL_COUNT 10
enum cam_actuator_apply_state_t { enum cam_actuator_apply_state_t {
ACT_APPLY_SETTINGS_NOW, ACT_APPLY_SETTINGS_NOW,
ACT_APPLY_SETTINGS_LATER, ACT_APPLY_SETTINGS_LATER,

4
drivers/cam_sensor_module/cam_cci/cam_cci_core.c
View File

@@ -49,8 +49,8 @@ static void cam_cci_flush_queue(struct cci_device *cci_dev,
} else if (rc == 0) { } else if (rc == 0) {
CAM_ERR(CAM_CCI, "wait timeout"); CAM_ERR(CAM_CCI, "wait timeout");
/* Set reset pending flag to TRUE */ /* Set reset pending flag to true */
cci_dev->cci_master_info[master].reset_pending = TRUE; cci_dev->cci_master_info[master].reset_pending = true;
/* Set proper mask to RESET CMD address based on MASTER */ /* Set proper mask to RESET CMD address based on MASTER */
if (master == MASTER_0) if (master == MASTER_0)

25
drivers/cam_sensor_module/cam_cci/cam_cci_dev.c
View File

@@ -14,9 +14,16 @@ static struct v4l2_subdev *g_cci_subdev[MAX_CCI];
struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index) struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index)
{ {
struct v4l2_subdev *sub_device = NULL;
if (cci_dev_index < MAX_CCI) if (cci_dev_index < MAX_CCI)
return g_cci_subdev[cci_dev_index]; sub_device = g_cci_subdev[cci_dev_index];
return NULL; else
CAM_WARN(CAM_CCI, "Index: %u is beyond max num CCI allowed: %u",
cci_dev_index,
MAX_CCI);
return sub_device;
} }
static long cam_cci_subdev_ioctl(struct v4l2_subdev *sd, static long cam_cci_subdev_ioctl(struct v4l2_subdev *sd,
@@ -69,18 +76,18 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) { if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) {
struct cam_cci_master_info *cci_master_info; struct cam_cci_master_info *cci_master_info;
if (cci_dev->cci_master_info[MASTER_0].reset_pending == TRUE) { if (cci_dev->cci_master_info[MASTER_0].reset_pending == true) {
cci_master_info = &cci_dev->cci_master_info[MASTER_0]; cci_master_info = &cci_dev->cci_master_info[MASTER_0];
cci_dev->cci_master_info[MASTER_0].reset_pending = cci_dev->cci_master_info[MASTER_0].reset_pending =
FALSE; false;
if (!cci_master_info->status) if (!cci_master_info->status)
complete(&cci_master_info->reset_complete); complete(&cci_master_info->reset_complete);
cci_master_info->status = 0; cci_master_info->status = 0;
} }
if (cci_dev->cci_master_info[MASTER_1].reset_pending == TRUE) { if (cci_dev->cci_master_info[MASTER_1].reset_pending == true) {
cci_master_info = &cci_dev->cci_master_info[MASTER_1]; cci_master_info = &cci_dev->cci_master_info[MASTER_1];
cci_dev->cci_master_info[MASTER_1].reset_pending = cci_dev->cci_master_info[MASTER_1].reset_pending =
FALSE; false;
if (!cci_master_info->status) if (!cci_master_info->status)
complete(&cci_master_info->reset_complete); complete(&cci_master_info->reset_complete);
cci_master_info->status = 0; cci_master_info->status = 0;
@@ -205,12 +212,12 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_1"); CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_1");
if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK) { if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK) {
cci_dev->cci_master_info[MASTER_0].reset_pending = TRUE; cci_dev->cci_master_info[MASTER_0].reset_pending = true;
cam_io_w_mb(CCI_M0_RESET_RMSK, cam_io_w_mb(CCI_M0_RESET_RMSK,
base + CCI_RESET_CMD_ADDR); base + CCI_RESET_CMD_ADDR);
} }
if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK) { if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK) {
cci_dev->cci_master_info[MASTER_1].reset_pending = TRUE; cci_dev->cci_master_info[MASTER_1].reset_pending = true;
cam_io_w_mb(CCI_M1_RESET_RMSK, cam_io_w_mb(CCI_M1_RESET_RMSK,
base + CCI_RESET_CMD_ADDR); base + CCI_RESET_CMD_ADDR);
} }
@@ -316,7 +323,7 @@ static int cam_cci_irq_routine(struct v4l2_subdev *sd, u32 status,
&cci_dev->soc_info; &cci_dev->soc_info;
ret = cam_cci_irq(soc_info->irq_line->start, cci_dev); ret = cam_cci_irq(soc_info->irq_line->start, cci_dev);
*handled = TRUE; *handled = true;
return 0; return 0;
} }

12
drivers/cam_sensor_module/cam_cci/cam_cci_dev.h
View File

@@ -42,9 +42,6 @@
#define NUM_MASTERS 2 #define NUM_MASTERS 2
#define NUM_QUEUES 2 #define NUM_QUEUES 2
#define TRUE 1
#define FALSE 0
#define CCI_PINCTRL_STATE_DEFAULT "cci_default" #define CCI_PINCTRL_STATE_DEFAULT "cci_default"
#define CCI_PINCTRL_STATE_SLEEP "cci_suspend" #define CCI_PINCTRL_STATE_SLEEP "cci_suspend"
@@ -298,14 +295,7 @@ struct cci_write_async {
irqreturn_t cam_cci_irq(int irq_num, void *data); irqreturn_t cam_cci_irq(int irq_num, void *data);
#ifdef CONFIG_SPECTRA_CAMERA struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index);
extern struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index);
#else
static inline struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index)
{
return NULL;
}
#endif
#define VIDIOC_MSM_CCI_CFG \ #define VIDIOC_MSM_CCI_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl *) _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl *)

6
drivers/cam_sensor_module/cam_cci/cam_cci_soc.c
View File

@@ -52,8 +52,8 @@ int cam_cci_init(struct v4l2_subdev *sd,
for (i = 0; i < NUM_QUEUES; i++) for (i = 0; i < NUM_QUEUES; i++)
reinit_completion( reinit_completion(
&cci_dev->cci_master_info[master].report_q[i]); &cci_dev->cci_master_info[master].report_q[i]);
/* Set reset pending flag to TRUE */ /* Set reset pending flag to true */
cci_dev->cci_master_info[master].reset_pending = TRUE; cci_dev->cci_master_info[master].reset_pending = true;
/* Set proper mask to RESET CMD address */ /* Set proper mask to RESET CMD address */
if (master == MASTER_0) if (master == MASTER_0)
cam_io_w_mb(CCI_M0_RESET_RMSK, cam_io_w_mb(CCI_M0_RESET_RMSK,
@@ -131,7 +131,7 @@ int cam_cci_init(struct v4l2_subdev *sd,
} }
} }
cci_dev->cci_master_info[master].reset_pending = TRUE; cci_dev->cci_master_info[master].reset_pending = true;
cam_io_w_mb(CCI_RESET_CMD_RMSK, base + cam_io_w_mb(CCI_RESET_CMD_RMSK, base +
CCI_RESET_CMD_ADDR); CCI_RESET_CMD_ADDR);
cam_io_w_mb(0x1, base + CCI_RESET_CMD_ADDR); cam_io_w_mb(0x1, base + CCI_RESET_CMD_ADDR);

284
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h
View File

@@ -14,7 +14,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = {
.mipi_csiphy_glbl_irq_cmd_addr = 0x828, .mipi_csiphy_glbl_irq_cmd_addr = 0x828,
.csiphy_common_array_size = 6, .csiphy_common_array_size = 6,
.csiphy_reset_array_size = 5, .csiphy_reset_array_size = 5,
.csiphy_2ph_config_array_size = 21, .csiphy_2ph_config_array_size = 20,
.csiphy_3ph_config_array_size = 34, .csiphy_3ph_config_array_size = 34,
.csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_clock_lane = 0x1,
.csiphy_2ph_combo_ck_ln = 0x10, .csiphy_2ph_combo_ck_ln = 0x10,
@@ -55,118 +55,113 @@ struct
csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{ {
{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
}, },
{ {
{0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
}, },
{ {
{0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
}, },
{ {
{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
}, },
{ {
{0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
}, },
}; };
@@ -174,118 +169,113 @@ struct csiphy_reg_t
csiphy_2ph_v1_2_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { csiphy_2ph_v1_2_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{ {
{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
}, },
{ {
{0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x070c, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
}, },
{ {
{0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
}, },
{ {
{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
}, },
{ {
{0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x060c, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
}, },
}; };

4
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h
View File

@@ -334,7 +334,7 @@ csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AB0, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0AB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -369,7 +369,7 @@ csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0BB0, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0BB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0BB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

3
drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h
View File

@@ -28,9 +28,6 @@
#define NUM_MASTERS 2 #define NUM_MASTERS 2
#define NUM_QUEUES 2 #define NUM_QUEUES 2
#define TRUE 1
#define FALSE 0
#undef CDBG #undef CDBG
#ifdef CAM_SENSOR_DEBUG #ifdef CAM_SENSOR_DEBUG
#define CDBG(fmt, args...) pr_err(fmt, ##args) #define CDBG(fmt, args...) pr_err(fmt, ##args)

25
drivers/cam_sync/cam_sync.c
View File

@@ -25,6 +25,24 @@ struct sync_device *sync_dev;
*/ */
static bool trigger_cb_without_switch; static bool trigger_cb_without_switch;
static void cam_sync_print_fence_table(void)
{
int idx;
for (idx = 0; idx < CAM_SYNC_MAX_OBJS; idx++) {
spin_lock_bh(&sync_dev->row_spinlocks[idx]);
CAM_INFO(CAM_SYNC,
"index[%u]: sync_id=%d, name=%s, type=%d, state=%d, ref_cnt=%d",
idx,
sync_dev->sync_table[idx].sync_id,
sync_dev->sync_table[idx].name,
sync_dev->sync_table[idx].type,
sync_dev->sync_table[idx].state,
sync_dev->sync_table[idx].ref_cnt);
spin_unlock_bh(&sync_dev->row_spinlocks[idx]);
}
}
int cam_sync_create(int32_t *sync_obj, const char *name) int cam_sync_create(int32_t *sync_obj, const char *name)
{ {
int rc; int rc;
@@ -33,8 +51,13 @@ int cam_sync_create(int32_t *sync_obj, const char *name)
do { do {
idx = find_first_zero_bit(sync_dev->bitmap, CAM_SYNC_MAX_OBJS); idx = find_first_zero_bit(sync_dev->bitmap, CAM_SYNC_MAX_OBJS);
if (idx >= CAM_SYNC_MAX_OBJS) if (idx >= CAM_SYNC_MAX_OBJS) {
CAM_ERR(CAM_SYNC,
"Error: Unable to create sync idx = %d reached max!",
idx);
cam_sync_print_fence_table();
return -ENOMEM; return -ENOMEM;
}
CAM_DBG(CAM_SYNC, "Index location available at idx: %ld", idx); CAM_DBG(CAM_SYNC, "Index location available at idx: %ld", idx);
bit = test_and_set_bit(idx, sync_dev->bitmap); bit = test_and_set_bit(idx, sync_dev->bitmap);
} while (bit); } while (bit);

5
drivers/cam_utils/cam_debug_util.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2017-2018, The Linux Foundataion. All rights reserved. * Copyright (c) 2017-2019, The Linux Foundataion. All rights reserved.
*/ */
#include <linux/io.h> #include <linux/io.h>
@@ -115,6 +115,7 @@ void cam_debug_log(unsigned int module_id, const char *func, const int line,
pr_info("CAM_DBG: %s: %s: %d: %s\n", pr_info("CAM_DBG: %s: %s: %d: %s\n",
cam_get_module_name(module_id), cam_get_module_name(module_id),
func, line, str_buffer); func, line, str_buffer);
va_end(args);
} }
va_end(args);
} }

12
drivers/cam_utils/cam_soc_util.c
View File

@@ -368,18 +368,6 @@ long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
return clk_round_rate(soc_info->clk[clk_index], clk_rate); return clk_round_rate(soc_info->clk[clk_index], clk_rate);
} }
int cam_soc_util_set_clk_flags(struct cam_hw_soc_info *soc_info,
uint32_t clk_index, unsigned long flags)
{
if (!soc_info || (clk_index >= soc_info->num_clk)) {
CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d",
soc_info, clk_index);
return -EINVAL;
}
return clk_set_flags(soc_info->clk[clk_index], flags);
}
/** /**
* cam_soc_util_set_clk_rate() * cam_soc_util_set_clk_rate()
* *

14
drivers/cam_utils/cam_soc_util.h
View File

@@ -371,20 +371,6 @@ int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info, long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
uint32_t clk_index, unsigned long clk_rate); uint32_t clk_index, unsigned long clk_rate);
/**
* cam_soc_util_set_clk_flags()
*
* @brief: Camera SOC util to set the flags for a specified clock
*
* @soc_info: Device soc information
* @clk_index: Clock index in soc_info for which flags are to be set
* @flags: Flags to set
*
* @return: Success or Failure
*/
int cam_soc_util_set_clk_flags(struct cam_hw_soc_info *soc_info,
uint32_t clk_index, unsigned long flags);
/** /**
* cam_soc_util_set_src_clk_rate() * cam_soc_util_set_src_clk_rate()
* *

5
include/uapi/camera/media/cam_isp.h
View File

@@ -126,6 +126,11 @@
#define CAM_ISP_USAGE_RIGHT_PX 2 #define CAM_ISP_USAGE_RIGHT_PX 2
#define CAM_ISP_USAGE_RDI 3 #define CAM_ISP_USAGE_RDI 3
/* Acquire with custom hw */
#define CAM_ISP_ACQ_CUSTOM_NONE 0
#define CAM_ISP_ACQ_CUSTOM_PRIMARY 1
#define CAM_ISP_ACQ_CUSTOM_SECONDARY 2
/* Query devices */ /* Query devices */
/** /**
* struct cam_isp_dev_cap_info - A cap info for particular hw type * struct cam_isp_dev_cap_info - A cap info for particular hw type

14
include/uapi/camera/media/cam_req_mgr.h
View File

@@ -183,6 +183,11 @@ struct cam_req_mgr_flush_info {
* @bubble_enable: Input Param - Cam req mgr will do bubble recovery if this * @bubble_enable: Input Param - Cam req mgr will do bubble recovery if this
* flag is set. * flag is set.
* @sync_mode: Type of Sync mode for this request * @sync_mode: Type of Sync mode for this request
* @additional_timeout: Additional timeout value (in ms) associated with
* this request. This value needs to be 0 in cases where long exposure is
* not configured for the sensor.The max timeout that will be supported
* is 50000 ms
* @reserved: Reserved
* @req_id: Input Param - Request Id from which all requests will be flushed * @req_id: Input Param - Request Id from which all requests will be flushed
*/ */
struct cam_req_mgr_sched_request { struct cam_req_mgr_sched_request {
@@ -190,6 +195,8 @@ struct cam_req_mgr_sched_request {
int32_t link_hdl; int32_t link_hdl;
int32_t bubble_enable; int32_t bubble_enable;
int32_t sync_mode; int32_t sync_mode;
int32_t additional_timeout;
int32_t reserved;
int64_t req_id; int64_t req_id;
}; };
@@ -406,11 +413,13 @@ struct cam_mem_cache_ops_cmd {
* @CAM_REQ_MGR_ERROR_TYPE_REQUEST: Error on a single request, not fatal * @CAM_REQ_MGR_ERROR_TYPE_REQUEST: Error on a single request, not fatal
* @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal * @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal
* @CAM_REQ_MGR_ERROR_TYPE_RECOVERY: Fatal error, can be recovered * @CAM_REQ_MGR_ERROR_TYPE_RECOVERY: Fatal error, can be recovered
* @CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE: SOF freeze, can be recovered
*/ */
#define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0 #define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0
#define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1 #define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1
#define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2 #define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2
#define CAM_REQ_MGR_ERROR_TYPE_RECOVERY 3 #define CAM_REQ_MGR_ERROR_TYPE_RECOVERY 3
#define CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE 4
/** /**
* struct cam_req_mgr_error_msg * struct cam_req_mgr_error_msg
@@ -435,6 +444,9 @@ struct cam_req_mgr_error_msg {
* @timestamp: timestamp of the frame * @timestamp: timestamp of the frame
* @link_hdl: link handle associated with this message * @link_hdl: link handle associated with this message
* @sof_status: sof status success or fail * @sof_status: sof status success or fail
* @frame_id_meta: refers to the meta for
* that frame in specific usecases
* @reserved: reserved
*/ */
struct cam_req_mgr_frame_msg { struct cam_req_mgr_frame_msg {
uint64_t request_id; uint64_t request_id;
@@ -442,6 +454,8 @@ struct cam_req_mgr_frame_msg {
uint64_t timestamp; uint64_t timestamp;
int32_t link_hdl; int32_t link_hdl;
uint32_t sof_status; uint32_t sof_status;
uint32_t frame_id_meta;
uint32_t reserved;
}; };
/** /**