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UPSTREAM: 11/12/19: Merge 'quic/camera-kernel.lnx.1.0' into 'quic/camera-kernel.lnx.4.0'

* quic/camera-kernel.lnx.1.0:
  msm: camera: common: Update uapi to support custom hw features
  msm: camera: ife: calculate accurate boot timestamp at CSID SOF
  msm: camera: cpas: Update ife_rd safe lut value
  msm: camera: sensor: Remove true/false redefinitions
  msm: camera: reqmgr: Add support to modify timer for long exposure
  msm: camera: reqmgr: Add provision to obtain exposure time
  msm: camera: cpas: Fix TCSR Register programming
  msm: camera: cci: Fix cam_cci_get_subdev for conditional compilation
  msm: camera: utils: Remove deprecated clk_set_flag functions
  msm: camera: csiphy: Update DPHY combo mode sequence
  msm: camera: csiphy: Correct Dphy mission mode sequence
  msm: camera: core: Fix extraneous variable declaration
  msm: camera: icp: Remove qcom soc dependency
  msm: camera: sync: Dump fence info in case of fence exhaust
  msm: camera: icp: Use CAM_PERF for clock, bw related logs
  msm: camera: common: va_end should follow va_start
  msm: camera: common: Fix integer overflow in shift
  msm: camera: reqmgr: Remove division on uint64_t
  msm: camera: isp: Improve isp substate logging
  msm: camera: isp: Limit sof_in_epoch log to first frame
  msm: camera: jpeg: Add plane stride & slice height debug info
  msm: camera: isp: Change state immediately in flush
  msm: camera: isp: Dump isp req for cdm timeout
  msm: camera: ife: Add packing format support
  msm: camera: icp: Fix AHB, AXI voting in icp
  msm: camera: ife: Remove duplicate add to port counters
  msm: camera: csiphy: Update CPHY 3-phase registers for CSIPHY v1.2

Change-Id: I93948d5cfcf2c8dea921d34696456490abd6f1e5
Signed-off-by: Abhijit Trivedi <abhijitt@codeaurora.org>
Este cometimento está contido em:
Abhijit Trivedi
2019-11-12 12:51:16 -08:00
ascendente 524b1ab1d4 f45e3dda5c
cometimento 9b6110b579
34 ficheiros modificados com 680 adições e 503 eliminações

Ver ficheiro

@@ -30,16 +30,12 @@
#define NUM_MASTERS 2
#define NUM_QUEUES 2
#define TRUE 1
#define FALSE 0
#define ACTUATOR_DRIVER_I2C "i2c_actuator"
#define CAMX_ACTUATOR_DEV_NAME "cam-actuator-driver"
#define MSM_ACTUATOR_MAX_VREGS (10)
#define ACTUATOR_MAX_POLL_COUNT 10
enum cam_actuator_apply_state_t {
ACT_APPLY_SETTINGS_NOW,
ACT_APPLY_SETTINGS_LATER,

Ver ficheiro

@@ -49,8 +49,8 @@ static void cam_cci_flush_queue(struct cci_device *cci_dev,
} else if (rc == 0) {
CAM_ERR(CAM_CCI, "wait timeout");
/* Set reset pending flag to TRUE */
cci_dev->cci_master_info[master].reset_pending = TRUE;
/* Set reset pending flag to true */
cci_dev->cci_master_info[master].reset_pending = true;
/* Set proper mask to RESET CMD address based on MASTER */
if (master == MASTER_0)

Ver ficheiro

@@ -14,9 +14,16 @@ static struct v4l2_subdev *g_cci_subdev[MAX_CCI];
struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index)
{
struct v4l2_subdev *sub_device = NULL;
if (cci_dev_index < MAX_CCI)
return g_cci_subdev[cci_dev_index];
return NULL;
sub_device = g_cci_subdev[cci_dev_index];
else
CAM_WARN(CAM_CCI, "Index: %u is beyond max num CCI allowed: %u",
cci_dev_index,
MAX_CCI);
return sub_device;
}
static long cam_cci_subdev_ioctl(struct v4l2_subdev *sd,
@@ -69,18 +76,18 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) {
struct cam_cci_master_info *cci_master_info;
if (cci_dev->cci_master_info[MASTER_0].reset_pending == TRUE) {
if (cci_dev->cci_master_info[MASTER_0].reset_pending == true) {
cci_master_info = &cci_dev->cci_master_info[MASTER_0];
cci_dev->cci_master_info[MASTER_0].reset_pending =
FALSE;
false;
if (!cci_master_info->status)
complete(&cci_master_info->reset_complete);
cci_master_info->status = 0;
}
if (cci_dev->cci_master_info[MASTER_1].reset_pending == TRUE) {
if (cci_dev->cci_master_info[MASTER_1].reset_pending == true) {
cci_master_info = &cci_dev->cci_master_info[MASTER_1];
cci_dev->cci_master_info[MASTER_1].reset_pending =
FALSE;
false;
if (!cci_master_info->status)
complete(&cci_master_info->reset_complete);
cci_master_info->status = 0;
@@ -205,12 +212,12 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_1");
if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK) {
cci_dev->cci_master_info[MASTER_0].reset_pending = TRUE;
cci_dev->cci_master_info[MASTER_0].reset_pending = true;
cam_io_w_mb(CCI_M0_RESET_RMSK,
base + CCI_RESET_CMD_ADDR);
}
if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK) {
cci_dev->cci_master_info[MASTER_1].reset_pending = TRUE;
cci_dev->cci_master_info[MASTER_1].reset_pending = true;
cam_io_w_mb(CCI_M1_RESET_RMSK,
base + CCI_RESET_CMD_ADDR);
}
@@ -316,7 +323,7 @@ static int cam_cci_irq_routine(struct v4l2_subdev *sd, u32 status,
&cci_dev->soc_info;
ret = cam_cci_irq(soc_info->irq_line->start, cci_dev);
*handled = TRUE;
*handled = true;
return 0;
}

Ver ficheiro

@@ -42,9 +42,6 @@
#define NUM_MASTERS 2
#define NUM_QUEUES 2
#define TRUE 1
#define FALSE 0
#define CCI_PINCTRL_STATE_DEFAULT "cci_default"
#define CCI_PINCTRL_STATE_SLEEP "cci_suspend"
@@ -298,14 +295,7 @@ struct cci_write_async {
irqreturn_t cam_cci_irq(int irq_num, void *data);
#ifdef CONFIG_SPECTRA_CAMERA
extern struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index);
#else
static inline struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index)
{
return NULL;
}
#endif
struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index);
#define VIDIOC_MSM_CCI_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl *)

Ver ficheiro

@@ -52,8 +52,8 @@ int cam_cci_init(struct v4l2_subdev *sd,
for (i = 0; i < NUM_QUEUES; i++)
reinit_completion(
&cci_dev->cci_master_info[master].report_q[i]);
/* Set reset pending flag to TRUE */
cci_dev->cci_master_info[master].reset_pending = TRUE;
/* Set reset pending flag to true */
cci_dev->cci_master_info[master].reset_pending = true;
/* Set proper mask to RESET CMD address */
if (master == MASTER_0)
cam_io_w_mb(CCI_M0_RESET_RMSK,
@@ -131,7 +131,7 @@ int cam_cci_init(struct v4l2_subdev *sd,
}
}
cci_dev->cci_master_info[master].reset_pending = TRUE;
cci_dev->cci_master_info[master].reset_pending = true;
cam_io_w_mb(CCI_RESET_CMD_RMSK, base +
CCI_RESET_CMD_ADDR);
cam_io_w_mb(0x1, base + CCI_RESET_CMD_ADDR);

Ver ficheiro

@@ -14,7 +14,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = {
.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
.csiphy_common_array_size = 6,
.csiphy_reset_array_size = 5,
.csiphy_2ph_config_array_size = 21,
.csiphy_2ph_config_array_size = 20,
.csiphy_3ph_config_array_size = 34,
.csiphy_2ph_clock_lane = 0x1,
.csiphy_2ph_combo_ck_ln = 0x10,
@@ -55,118 +55,113 @@ struct
csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{
{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
};
@@ -174,118 +169,113 @@ struct csiphy_reg_t
csiphy_2ph_v1_2_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{
{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0908, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
},
{
{0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x070c, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
},
{
{0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
},
{
{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS},
},
{
{0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x060c, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
};

Ver ficheiro

@@ -334,7 +334,7 @@ csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AB0, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -369,7 +369,7 @@ csiphy_reg_t csiphy_3ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0BB0, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0BB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

Ver ficheiro

@@ -28,9 +28,6 @@
#define NUM_MASTERS 2
#define NUM_QUEUES 2
#define TRUE 1
#define FALSE 0
#undef CDBG
#ifdef CAM_SENSOR_DEBUG
#define CDBG(fmt, args...) pr_err(fmt, ##args)