samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Forkuj 0
Kod Zgłoszenia Oczekujące zmiany Actions Packages Projekty Wydania Wiki Aktywność

soc: swr-mstr: Update port params for TX master runtime

Przeglądaj źródła 
Remove static tables for master port params for soundwire TX.
As master port params are dependent on slave port config,
determine master port settings runtime and apply for
TX soundwire master ports.

Change-Id: I5e606404521abd514097ddf7500ba4e427024914
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
This commit is contained in:
Laxminath Kasam
2020-11-12 18:31:18 +05:30
rodzic 82cbe0a14f
commit 9a4b45f6bb
3 zmienionych plików z 49 dodań i 108 usunięć
Ściągnij plik aktualizacji Ściągnij plik porównania Expand all files Collapse all files

48
asoc/lahaina-port-config.h
Wyświetl plik

@@ -54,52 +54,7 @@ static struct port_params rx_frame_params_44p1KHz[SWR_MSTR_PORT_LEN] = {
{0x1FF, 0, 0, 0x8, 0x8, 0x0F, 0, 0, 0, 0x00, 0x01}, /* PCM_OUT */
};
/* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = {
{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
{7, 5, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
};
/* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
static struct port_params tx_frame_params_shima[SWR_MSTR_PORT_LEN] = {
{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */
{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
{7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
};
/* 4.8 MHz clock */
static struct port_params tx_frame_params_4p8MHz[SWR_MSTR_PORT_LEN] = {
{15, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX2 */
{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
};
/* 0.6 MHz clock */
static struct port_params tx_frame_params_0p6MHz[SWR_MSTR_PORT_LEN] = {
{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
};
/* 4.8 MHz clock */
static struct port_params tx_frame_params_shima_4p8MHz[SWR_MSTR_PORT_LEN] = {
{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0x00, 0x00}, /* TX1 */
{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
{7, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
};
/* 0.6 MHz clock */
static struct port_params tx_frame_params_shima_0p6MHz[SWR_MSTR_PORT_LEN] = {
{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX1 */
{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX2 */
{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0x00, 0x00}, /* TX3 */
};
static struct swr_mstr_port_map sm_port_map[] = {
{TX_MACRO, SWR_UC0, tx_frame_params_default},
{TX_MACRO, SWR_UC1, tx_frame_params_4p8MHz},
{TX_MACRO, SWR_UC2, tx_frame_params_0p6MHz},
{RX_MACRO, SWR_UC0, rx_frame_params_default},
{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
@@ -107,9 +62,6 @@ static struct swr_mstr_port_map sm_port_map[] = {
};
static struct swr_mstr_port_map sm_port_map_shima[] = {
{TX_MACRO, SWR_UC0, tx_frame_params_shima},
{TX_MACRO, SWR_UC1, tx_frame_params_shima_4p8MHz},
{TX_MACRO, SWR_UC2, tx_frame_params_shima_0p6MHz},
{RX_MACRO, SWR_UC0, rx_frame_params_default},
{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},