qcacmn: Confirm HP register init when enabling IPA pipes

As a part of enabling IPA pipes, the WBM2SW2 head
pointer register is written with the number of
buffers which have been allocated initially. This
register write is a critical one and failure in
writing this register can be fatal.

Confirm the written value, when initializing
the HP register for WBM2SW2 (for IPA).

Change-Id: Ib2da3a7aa6096375cf64857721619f47c50658de
CRs-Fixed: 2620750

hal/wifi3.0/hal_api.h

@@ -402,7 +402,7 @@ static inline void hal_write32_mb_confirm(struct hal_soc *hal_soc,
  */
 static inline
 void hal_write_address_32_mb(struct hal_soc *hal_soc,
-			     qdf_iomem_t addr, uint32_t value)
+			     qdf_iomem_t addr, uint32_t value, bool wr_confirm)
 {
 	uint32_t offset;
 
@@ -410,7 +410,11 @@ void hal_write_address_32_mb(struct hal_soc *hal_soc,
 		return qdf_iowrite32(addr, value);
 
 	offset = addr - hal_soc->dev_base_addr;
-	hal_write32_mb(hal_soc, offset, value);
+
+	if (qdf_unlikely(wr_confirm))
+		hal_write32_mb_confirm(hal_soc, offset, value);
+	else
+		hal_write32_mb(hal_soc, offset, value);
 }
 
 #ifdef DP_HAL_MULTIWINDOW_DIRECT_ACCESS
@@ -435,7 +439,7 @@ static inline void hal_srng_write_address_32_mb(struct hal_soc *hal_soc,
 						void __iomem *addr,
 						uint32_t value)
 {
-	hal_write_address_32_mb(hal_soc, addr, value);
+	hal_write_address_32_mb(hal_soc, addr, value, false);
 }
 #endif
 

hal/wifi3.0/hal_hw_headers.h

@@ -235,9 +235,12 @@
 #else
 #define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \
 	hal_write_address_32_mb(_srng->hal_soc,\
-		SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value))
+		SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), false)
 #endif
 
+#define SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, _dir) \
+	hal_write_address_32_mb(_srng->hal_soc,\
+		SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value), true)
 
 #define SRNG_REG_READ(_srng, _reg, _dir) \
 	hal_read_address_32_mb(_srng->hal_soc, \
@@ -249,6 +252,9 @@
 #define SRNG_DST_REG_WRITE(_srng, _reg, _value) \
 	SRNG_REG_WRITE(_srng, _reg, _value, DST)
 
+#define SRNG_DST_REG_WRITE_CONFIRM(_srng, _reg, _value) \
+	SRNG_REG_WRITE_CONFIRM(_srng, _reg, _value, DST)
+
 #define SRNG_SRC_REG_READ(_srng, _reg) \
 	SRNG_REG_READ(_srng, _reg, SRC)
 

hal/wifi3.0/hal_srng.c

@@ -393,11 +393,11 @@ static void hal_process_reg_write_q_elem(struct hal_soc *hal,
 	if (srng->ring_dir == HAL_SRNG_SRC_RING)
 		hal_write_address_32_mb(hal,
 					srng->u.src_ring.hp_addr,
-					srng->u.src_ring.hp);
+					srng->u.src_ring.hp, false);
 	else
 		hal_write_address_32_mb(hal,
 					srng->u.dst_ring.tp_addr,
-					srng->u.dst_ring.tp);
+					srng->u.dst_ring.tp, false);
 
 	SRNG_UNLOCK(&srng->lock);
 }
@@ -561,7 +561,7 @@ void hal_delayed_reg_write(struct hal_soc *hal_soc,
 	    hal_is_reg_write_tput_level_high(hal_soc)) {
 		qdf_atomic_inc(&hal_soc->stats.wstats.direct);
 		srng->wstats.direct++;
-		hal_write_address_32_mb(hal_soc, addr, value);
+		hal_write_address_32_mb(hal_soc, addr, value, false);
 	} else {
 		hal_reg_write_enqueue(hal_soc, srng, addr, value);
 	}
@@ -946,7 +946,7 @@ void hal_srng_dst_init_hp(struct hal_srng *srng,
 		return;
 
 	srng->u.dst_ring.hp_addr = vaddr;
-	SRNG_DST_REG_WRITE(srng, HP, srng->u.dst_ring.cached_hp);
+	SRNG_DST_REG_WRITE_CONFIRM(srng, HP, srng->u.dst_ring.cached_hp);
 
 	if (vaddr) {
 		*srng->u.dst_ring.hp_addr = srng->u.dst_ring.cached_hp;