Merge "disp: msm: add support for INTF WD jitter"

msm/sde/sde_hw_intf.c

@@ -69,6 +69,9 @@
 #define INTF_VSYNC_TIMESTAMP1           0x218
 #define INTF_MDP_VSYNC_TIMESTAMP0       0x21C
 #define INTF_MDP_VSYNC_TIMESTAMP1       0x220
+#define INTF_WD_TIMER_0_JITTER_CTL      0x224
+#define INTF_WD_TIMER_0_LTJ_SLOPE       0x228
+#define INTF_WD_TIMER_0_LTJ_MAX         0x22C
 #define INTF_WD_TIMER_0_CTL             0x230
 #define INTF_WD_TIMER_0_CTL2            0x234
 #define INTF_WD_TIMER_0_LOAD_VALUE      0x238
@@ -455,8 +458,39 @@ static void sde_hw_intf_setup_prg_fetch(
 	SDE_REG_WRITE(c, INTF_CONFIG, fetch_enable);
 }
 
-static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf,
-		u32 frame_rate)
+static void sde_hw_intf_configure_wd_timer_jitter(struct sde_hw_intf *intf,
+		struct intf_wd_jitter_params *wd_jitter)
+{
+	struct sde_hw_blk_reg_map *c;
+	u32 reg, jitter_ctl = 0;
+
+	c = &intf->hw;
+
+	/*
+	 * Load Jitter values with jitter feature disabled.
+	 */
+	SDE_REG_WRITE(c, INTF_WD_TIMER_0_JITTER_CTL, 0x1);
+
+	if (wd_jitter->jitter)
+		jitter_ctl |= ((wd_jitter->jitter & 0x3FF) << 16);
+
+	if (wd_jitter->ltj_max) {
+		SDE_REG_WRITE(c, INTF_WD_TIMER_0_LTJ_MAX, wd_jitter->ltj_max);
+		SDE_REG_WRITE(c, INTF_WD_TIMER_0_LTJ_SLOPE, wd_jitter->ltj_slope);
+	}
+
+	reg = SDE_REG_READ(c, INTF_WD_TIMER_0_JITTER_CTL);
+	reg |= jitter_ctl;
+	SDE_REG_WRITE(c, INTF_WD_TIMER_0_JITTER_CTL, reg);
+
+	if (wd_jitter->jitter)
+		reg |= BIT(31);
+	if (wd_jitter->ltj_max)
+		reg |= BIT(30);
+	SDE_REG_WRITE(c, INTF_WD_TIMER_0_JITTER_CTL, reg);
+}
+
+static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf, u32 frame_rate)
 {
 	struct sde_hw_blk_reg_map *c;
 	u32 reg = 0;
@@ -466,7 +500,11 @@ static void sde_hw_intf_setup_vsync_source(struct sde_hw_intf *intf,
 
 	c = &intf->hw;
 
-	SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, CALCULATE_WD_LOAD_VALUE(frame_rate));
+	reg = CALCULATE_WD_LOAD_VALUE(frame_rate);
+	if (intf->cap->features & BIT(SDE_INTF_WD_JITTER))
+		reg *= MDP_TICK_COUNT;
+
+	SDE_REG_WRITE(c, INTF_WD_TIMER_0_LOAD_VALUE, reg);
 
 	SDE_REG_WRITE(c, INTF_WD_TIMER_0_CTL, BIT(0)); /* clear timer */
 	reg |= BIT(8); /* enable heartbeat timer */
@@ -928,6 +966,9 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
 
 	if (cap & (BIT(SDE_INTF_PANEL_VSYNC_TS) | BIT(SDE_INTF_MDP_VSYNC_TS)))
 		ops->get_vsync_timestamp = sde_hw_intf_get_vsync_timestamp;
+
+	if (cap & BIT(SDE_INTF_WD_JITTER))
+		ops->configure_wd_jitter = sde_hw_intf_configure_wd_timer_jitter;
 }
 
 struct sde_hw_blk_reg_map *sde_hw_intf_init(enum sde_intf idx,