samsung-sm8650/android_kernel_samsung_sm8650-modules
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Kods Problēmas Izmaiņu pieprasījumi Darbības Pakotnes Projekti Laidieni Vikivietne Aktivitāte

msm: camera: isp: Move clock voting to common vfe top

Pārlūkot izejas kodu 
Currently, clock update function is same between different
vfe top versions. Move clock voting functions to common
top to avoid duplication.

CRs-Fixed: 2841729
Change-Id: I2504632a260ea18f8b5e38e65395db95375588bb
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Šī revīzija ir iekļauta:
Mukund Madhusudan Atre
2021-04-16 09:56:53 -07:00
revīziju iesūtīja Gerrit - the friendly Code Review server
vecāks a9c89d1f41
revīzija 98b269d0b0
5 mainīti faili ar 187 papildinājumiem un 354 dzēšanām
Lejupielādēt ielāpa failu Lejupielādēt izmaiņu failu Izvērst visus failus Savērst visus failus

107
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.c
Parādīt failu

@@ -6,6 +6,113 @@
#include "cam_vfe_top_common.h"
#include "cam_debug_util.h"
int cam_vfe_top_set_hw_clk_rate(
struct cam_vfe_top_priv_common *top_common)
{
struct cam_hw_soc_info *soc_info = NULL;
struct cam_vfe_soc_private *soc_private = NULL;
struct cam_ahb_vote ahb_vote;
int i, rc = 0, clk_lvl = -1;
unsigned long max_clk_rate = 0;
soc_info = top_common->soc_info;
soc_private = (struct cam_vfe_soc_private *)soc_info->soc_private;
for (i = 0; i < top_common->num_mux; i++) {
if (top_common->req_clk_rate[i] > max_clk_rate)
max_clk_rate = top_common->req_clk_rate[i];
}
if (max_clk_rate == top_common->hw_clk_rate) {
CAM_DBG(CAM_ISP, "VFE:%d Clock Unchanged %llu",
top_common->hw_idx, top_common->hw_clk_rate);
return 0;
}
CAM_DBG(CAM_PERF, "VFE:%d Clock name=%s idx=%d clk=%llu",
top_common->hw_idx,
soc_info->clk_name[soc_info->src_clk_idx],
soc_info->src_clk_idx, max_clk_rate);
rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate);
if (!rc) {
soc_private->ife_clk_src = max_clk_rate;
top_common->hw_clk_rate = max_clk_rate;
rc = cam_soc_util_get_clk_level(soc_info, max_clk_rate,
soc_info->src_clk_idx, &clk_lvl);
if (rc) {
CAM_WARN(CAM_ISP,
"Failed to get clk level for %s with clk_rate %llu src_idx %d rc %d",
soc_info->dev_name, max_clk_rate,
soc_info->src_clk_idx, rc);
rc = 0;
goto end;
}
ahb_vote.type = CAM_VOTE_ABSOLUTE;
ahb_vote.vote.level = clk_lvl;
cam_cpas_update_ahb_vote(soc_private->cpas_handle, &ahb_vote);
} else {
CAM_ERR(CAM_PERF, "VFE:%d Set Clock rate failed, rc=%d",
top_common->hw_idx, rc);
}
end:
return rc;
}
int cam_vfe_top_clock_update(struct cam_vfe_top_priv_common *top_common,
void *cmd_args, uint32_t arg_size)
{
struct cam_vfe_clock_update_args *clk_update = NULL;
struct cam_isp_resource_node *res = NULL;
struct cam_hw_info *hw_info = NULL;
int i, rc = 0;
clk_update =
(struct cam_vfe_clock_update_args *)cmd_args;
res = clk_update->node_res;
if (!res || !res->hw_intf->hw_priv) {
CAM_ERR(CAM_PERF, "Invalid input res %pK", res);
return -EINVAL;
}
hw_info = res->hw_intf->hw_priv;
if (res->res_type != CAM_ISP_RESOURCE_VFE_IN ||
res->res_id >= CAM_ISP_HW_VFE_IN_MAX) {
CAM_ERR(CAM_PERF, "VFE:%d Invalid res_type:%d res id%d",
res->hw_intf->hw_idx, res->res_type,
res->res_id);
return -EINVAL;
}
for (i = 0; i < top_common->num_mux; i++) {
if (top_common->mux_rsrc[i].res_id == res->res_id) {
top_common->req_clk_rate[i] = clk_update->clk_rate;
break;
}
}
if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) {
CAM_DBG(CAM_PERF,
"VFE:%d Not ready to set clocks yet :%d",
res->hw_intf->hw_idx,
hw_info->hw_state);
} else {
rc = cam_vfe_top_set_hw_clk_rate(top_common);
if (rc)
CAM_ERR(CAM_PERF,
"VFE:%d Failed in setting clock rate rc=%d",
top_common->hw_idx, rc);
}
return rc;
}
static struct cam_axi_vote *cam_vfe_top_delay_bw_reduction(
struct cam_vfe_top_priv_common *top_common,
uint64_t *to_be_applied_bw)

10
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h
Parādīt failu

@@ -29,6 +29,10 @@ struct cam_vfe_top_priv_common {
uint64_t total_bw_applied;
uint32_t hw_version;
enum cam_vfe_bw_control_action axi_vote_control[CAM_VFE_TOP_MUX_MAX];
struct cam_hw_soc_info *soc_info;
unsigned long hw_clk_rate;
unsigned long req_clk_rate[CAM_VFE_TOP_MUX_MAX];
};
struct cam_vfe_top_reg_dump_entry {
@@ -55,6 +59,12 @@ struct cam_vfe_top_dump_data {
lut_entry[CAM_VFE_TOP_MAX_LUT_DUMP_ENTRIES];
};
int cam_vfe_top_set_hw_clk_rate(
struct cam_vfe_top_priv_common *top_common);
int cam_vfe_top_clock_update(struct cam_vfe_top_priv_common *top_common,
void *cmd_args, uint32_t arg_size);
int cam_vfe_top_set_axi_bw_vote(struct cam_vfe_soc_private *soc_private,
struct cam_vfe_top_priv_common *top_common, bool start_stop);

126
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c
Parādīt failu

@@ -16,7 +16,6 @@
#define CAM_VFE_HW_RESET_HW_VAL 0x00003F87
struct cam_vfe_top_ver2_common_data {
struct cam_hw_soc_info *soc_info;
struct cam_hw_intf *hw_intf;
struct cam_vfe_top_ver2_reg_offset_common *common_reg;
struct cam_vfe_top_dump_data *dump_data;
@@ -24,9 +23,6 @@ struct cam_vfe_top_ver2_common_data {
struct cam_vfe_top_ver2_priv {
struct cam_vfe_top_ver2_common_data common_data;
unsigned long hw_clk_rate;
unsigned long req_clk_rate[
CAM_VFE_TOP_MUX_MAX];
struct cam_vfe_top_priv_common top_common;
};
@@ -44,7 +40,7 @@ static int cam_vfe_top_mux_get_base(struct cam_vfe_top_ver2_priv *top_priv,
}
if (!cdm_args || !cdm_args->res || !top_priv ||
!top_priv->common_data.soc_info) {
!top_priv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "Error! Invalid args");
return -EINVAL;
}
@@ -66,9 +62,9 @@ static int cam_vfe_top_mux_get_base(struct cam_vfe_top_ver2_priv *top_priv,
}
mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(
top_priv->common_data.soc_info, VFE_CORE_BASE_IDX);
top_priv->top_common.soc_info, VFE_CORE_BASE_IDX);
CAM_DBG(CAM_ISP, "core %d mem_base 0x%x",
top_priv->common_data.soc_info->index, mem_base);
top_priv->top_common.soc_info->index, mem_base);
cdm_util_ops->cdm_write_changebase(
cdm_args->cmd.cmd_buf_addr, mem_base);
@@ -77,39 +73,6 @@ static int cam_vfe_top_mux_get_base(struct cam_vfe_top_ver2_priv *top_priv,
return 0;
}
static int cam_vfe_top_set_hw_clk_rate(
struct cam_vfe_top_ver2_priv *top_priv)
{
struct cam_hw_soc_info *soc_info = NULL;
int i, rc = 0;
unsigned long max_clk_rate = 0;
struct cam_vfe_soc_private *soc_private = NULL;
soc_info = top_priv->common_data.soc_info;
soc_private =
(struct cam_vfe_soc_private *)soc_info->soc_private;
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->req_clk_rate[i] > max_clk_rate)
max_clk_rate = top_priv->req_clk_rate[i];
}
if (max_clk_rate == top_priv->hw_clk_rate)
return 0;
CAM_DBG(CAM_PERF, "VFE: Clock name=%s idx=%d clk=%llu",
soc_info->clk_name[soc_info->src_clk_idx],
soc_info->src_clk_idx, max_clk_rate);
soc_private->ife_clk_src = max_clk_rate;
rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate);
if (!rc)
top_priv->hw_clk_rate = max_clk_rate;
else
CAM_ERR(CAM_PERF, "Set Clock rate failed, rc=%d", rc);
return rc;
}
static int cam_vfe_top_fs_update(
struct cam_vfe_top_ver2_priv *top_priv,
void *cmd_args, uint32_t arg_size)
@@ -123,56 +86,10 @@ static int cam_vfe_top_fs_update(
return 0;
}
static int cam_vfe_top_clock_update(
struct cam_vfe_top_ver2_priv *top_priv,
void *cmd_args, uint32_t arg_size)
{
struct cam_vfe_clock_update_args *clk_update = NULL;
struct cam_isp_resource_node *res = NULL;
struct cam_hw_info *hw_info = NULL;
int i, rc = 0;
clk_update =
(struct cam_vfe_clock_update_args *)cmd_args;
res = clk_update->node_res;
if (!res || !res->hw_intf->hw_priv) {
CAM_ERR(CAM_PERF, "Invalid input res %pK", res);
return -EINVAL;
}
hw_info = res->hw_intf->hw_priv;
if (res->res_type != CAM_ISP_RESOURCE_VFE_IN ||
res->res_id >= CAM_ISP_HW_VFE_IN_MAX) {
CAM_ERR(CAM_PERF, "VFE:%d Invalid res_type:%d res id%d",
res->hw_intf->hw_idx, res->res_type,
res->res_id);
return -EINVAL;
}
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->top_common.mux_rsrc[i].res_id == res->res_id) {
top_priv->req_clk_rate[i] = clk_update->clk_rate;
break;
}
}
if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) {
CAM_DBG(CAM_PERF,
"VFE:%d Not ready to set clocks yet :%d",
res->hw_intf->hw_idx,
hw_info->hw_state);
} else
rc = cam_vfe_top_set_hw_clk_rate(top_priv);
return rc;
}
static int cam_vfe_top_dump_info(
struct cam_vfe_top_ver2_priv *top_priv, uint32_t cmd_type)
{
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
struct cam_hw_soc_info *soc_info = top_priv->top_common.soc_info;
if (!soc_info) {
CAM_ERR(CAM_ISP, "Null soc_info");
@@ -243,7 +160,7 @@ static int cam_vfe_top_wait_comp_event(struct cam_vfe_top_ver2_priv *top_priv,
}
if (!cdm_args || !cdm_args->res || !top_priv ||
!top_priv->common_data.soc_info) {
!top_priv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "Error! Invalid args");
return -EINVAL;
}
@@ -285,7 +202,7 @@ static int cam_vfe_top_add_wait_trigger(struct cam_vfe_top_ver2_priv *top_priv,
}
if (!cdm_args || !cdm_args->res || !top_priv ||
!top_priv->common_data.soc_info) {
!top_priv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "Error! Invalid args");
return -EINVAL;
}
@@ -346,13 +263,13 @@ int cam_vfe_top_get_hw_caps(void *device_priv,
vfe_cap_info = (struct cam_vfe_hw_get_hw_cap *)args;
vfe_top_prv = (struct cam_vfe_top_ver2_priv *)device_priv;
if (!vfe_top_prv->common_data.soc_info) {
if (!vfe_top_prv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "soc_info is null");
return -EFAULT;
}
vfe_soc_private = (struct cam_vfe_soc_private *)
vfe_top_prv->common_data.soc_info->soc_private;
vfe_top_prv->top_common.soc_info->soc_private;
vfe_cap_info->is_lite = (vfe_soc_private->is_ife_lite) ? true : false;
vfe_cap_info->incr =
@@ -405,7 +322,7 @@ static int cam_vfe_hw_dump(
return -ENOSPC;
}
dump_data = top_priv->common_data.dump_data;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
/*Dump registers */
for (i = 0; i < dump_data->num_reg_dump_entries; i++)
@@ -505,10 +422,10 @@ int cam_vfe_top_init_hw(void *device_priv,
struct cam_vfe_top_ver2_priv *top_priv = device_priv;
struct cam_vfe_top_ver2_common_data common_data = top_priv->common_data;
top_priv->hw_clk_rate = 0;
top_priv->top_common.hw_clk_rate = 0;
top_priv->top_common.hw_version =
cam_io_r_mb(common_data.soc_info->reg_map[0].mem_base +
cam_io_r_mb(top_priv->top_common.soc_info->reg_map[0].mem_base +
common_data.common_reg->hw_version);
return 0;
@@ -538,7 +455,7 @@ int cam_vfe_top_reset(void *device_priv,
}
CAM_DBG(CAM_ISP, "reset reg value: %x", reset_reg_val);
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
reg_common = top_priv->common_data.common_reg;
/* Mask All the IRQs except RESET */
@@ -674,7 +591,7 @@ int cam_vfe_top_start(void *device_priv,
}
top_priv = (struct cam_vfe_top_ver2_priv *)device_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if (!soc_private) {
CAM_ERR(CAM_ISP, "Error soc_private NULL");
@@ -685,7 +602,7 @@ int cam_vfe_top_start(void *device_priv,
hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv;
if (hw_info->hw_state == CAM_HW_STATE_POWER_UP) {
rc = cam_vfe_top_set_hw_clk_rate(top_priv);
rc = cam_vfe_top_set_hw_clk_rate(&top_priv->top_common);
if (rc) {
CAM_ERR(CAM_ISP,
"set_hw_clk_rate failed, rc=%d", rc);
@@ -733,7 +650,7 @@ int cam_vfe_top_stop(void *device_priv,
top_priv = (struct cam_vfe_top_ver2_priv *)device_priv;
mux_res = (struct cam_isp_resource_node *)stop_args;
hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if ((mux_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF) ||
@@ -751,8 +668,7 @@ int cam_vfe_top_stop(void *device_priv,
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->top_common.mux_rsrc[i].res_id ==
mux_res->res_id) {
top_priv->req_clk_rate[i] = 0;
top_priv->req_clk_rate[i] = 0;
top_priv->top_common.req_clk_rate[i] = 0;
top_priv->top_common.req_axi_vote[i]
.axi_path[0].camnoc_bw = 0;
top_priv->top_common.req_axi_vote[i]
@@ -794,7 +710,7 @@ int cam_vfe_top_process_cmd(void *device_priv, uint32_t cmd_type,
return -EINVAL;
}
top_priv = (struct cam_vfe_top_ver2_priv *)device_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if (!soc_private) {
CAM_ERR(CAM_ISP, "Error soc_private NULL");
@@ -814,7 +730,7 @@ int cam_vfe_top_process_cmd(void *device_priv, uint32_t cmd_type,
arg_size);
break;
case CAM_ISP_HW_CMD_CLOCK_UPDATE:
rc = cam_vfe_top_clock_update(top_priv, cmd_args,
rc = cam_vfe_top_clock_update(&top_priv->top_common, cmd_args,
arg_size);
break;
case CAM_ISP_HW_NOTIFY_OVERFLOW:
@@ -886,7 +802,7 @@ int cam_vfe_top_ver2_init(
}
vfe_top->top_priv = top_priv;
top_priv->hw_clk_rate = 0;
top_priv->top_common.hw_clk_rate = 0;
if (ver2_hw_info->num_mux > CAM_VFE_TOP_MUX_MAX) {
CAM_ERR(CAM_ISP, "Invalid number of input rsrc: %d, max: %d",
ver2_hw_info->num_mux, CAM_VFE_TOP_MUX_MAX);
@@ -902,7 +818,7 @@ int cam_vfe_top_ver2_init(
top_priv->top_common.mux_rsrc[i].hw_intf = hw_intf;
top_priv->top_common.mux_rsrc[i].res_state =
CAM_ISP_RESOURCE_STATE_AVAILABLE;
top_priv->req_clk_rate[i] = 0;
top_priv->top_common.req_clk_rate[i] = 0;
if (ver2_hw_info->mux_type[i] == CAM_VFE_CAMIF_VER_2_0) {
top_priv->top_common.mux_rsrc[i].res_id =
@@ -967,7 +883,7 @@ int cam_vfe_top_ver2_init(
vfe_top->hw_ops.process_cmd = cam_vfe_top_process_cmd;
*vfe_top_ptr = vfe_top;
top_priv->common_data.soc_info = soc_info;
top_priv->top_common.soc_info = soc_info;
top_priv->common_data.hw_intf = hw_intf;
top_priv->top_common.hw_idx = hw_intf->hw_idx;
top_priv->common_data.common_reg = ver2_hw_info->common_reg;

152
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c
Parādīt failu

@@ -20,16 +20,12 @@
struct cam_vfe_top_ver3_common_data {
struct cam_vfe_top_ver3_hw_info *hw_info;
struct cam_hw_soc_info *soc_info;
struct cam_hw_intf *hw_intf;
struct cam_vfe_top_ver3_reg_offset_common *common_reg;
};
struct cam_vfe_top_ver3_priv {
struct cam_vfe_top_ver3_common_data common_data;
unsigned long hw_clk_rate;
unsigned long req_clk_rate[
CAM_VFE_TOP_MUX_MAX];
struct cam_vfe_top_priv_common top_common;
};
@@ -63,7 +59,7 @@ static int cam_vfe_top_ver3_mux_get_base(struct cam_vfe_top_ver3_priv *top_priv,
}
if (!cdm_args || !cdm_args->res || !top_priv ||
!top_priv->common_data.soc_info) {
!top_priv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "Error, Invalid args");
return -EINVAL;
}
@@ -85,9 +81,9 @@ static int cam_vfe_top_ver3_mux_get_base(struct cam_vfe_top_ver3_priv *top_priv,
}
mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(
top_priv->common_data.soc_info, VFE_CORE_BASE_IDX);
top_priv->top_common.soc_info, VFE_CORE_BASE_IDX);
CAM_DBG(CAM_ISP, "core %d mem_base 0x%x",
top_priv->common_data.soc_info->index, mem_base);
top_priv->top_common.soc_info->index, mem_base);
cdm_util_ops->cdm_write_changebase(
cdm_args->cmd.cmd_buf_addr, mem_base);
@@ -96,58 +92,6 @@ static int cam_vfe_top_ver3_mux_get_base(struct cam_vfe_top_ver3_priv *top_priv,
return 0;
}
static int cam_vfe_top_ver3_set_hw_clk_rate(
struct cam_vfe_top_ver3_priv *top_priv)
{
struct cam_hw_soc_info *soc_info = NULL;
struct cam_vfe_soc_private *soc_private = NULL;
struct cam_ahb_vote ahb_vote;
int i, rc = 0, clk_lvl = -1;
unsigned long max_clk_rate = 0;
soc_info = top_priv->common_data.soc_info;
soc_private =
(struct cam_vfe_soc_private *)soc_info->soc_private;
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->req_clk_rate[i] > max_clk_rate)
max_clk_rate = top_priv->req_clk_rate[i];
}
if (max_clk_rate == top_priv->hw_clk_rate)
return 0;
CAM_DBG(CAM_PERF, "VFE: Clock name=%s idx=%d clk=%llu",
soc_info->clk_name[soc_info->src_clk_idx],
soc_info->src_clk_idx, max_clk_rate);
rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate);
if (!rc) {
soc_private->ife_clk_src = max_clk_rate;
top_priv->hw_clk_rate = max_clk_rate;
rc = cam_soc_util_get_clk_level(soc_info, max_clk_rate,
soc_info->src_clk_idx, &clk_lvl);
if (rc) {
CAM_WARN(CAM_ISP,
"Failed to get clk level for %s with clk_rate %llu src_idx %d rc %d",
soc_info->dev_name, max_clk_rate,
soc_info->src_clk_idx, rc);
rc = 0;
goto end;
}
ahb_vote.type = CAM_VOTE_ABSOLUTE;
ahb_vote.vote.level = clk_lvl;
cam_cpas_update_ahb_vote(soc_private->cpas_handle, &ahb_vote);
} else {
CAM_ERR(CAM_PERF, "Set Clock rate failed, rc=%d", rc);
}
end:
return rc;
}
static int cam_vfe_top_fs_update(
struct cam_vfe_top_ver3_priv *top_priv,
void *cmd_args, uint32_t arg_size)
@@ -161,56 +105,10 @@ static int cam_vfe_top_fs_update(
return 0;
}
static int cam_vfe_top_ver3_clock_update(
struct cam_vfe_top_ver3_priv *top_priv,
void *cmd_args, uint32_t arg_size)
{
struct cam_vfe_clock_update_args *clk_update = NULL;
struct cam_isp_resource_node *res = NULL;
struct cam_hw_info *hw_info = NULL;
int i, rc = 0;
clk_update =
(struct cam_vfe_clock_update_args *)cmd_args;
res = clk_update->node_res;
if (!res || !res->hw_intf->hw_priv) {
CAM_ERR(CAM_PERF, "Invalid input res %pK", res);
return -EINVAL;
}
hw_info = res->hw_intf->hw_priv;
if (res->res_type != CAM_ISP_RESOURCE_VFE_IN ||
res->res_id >= CAM_ISP_HW_VFE_IN_MAX) {
CAM_ERR(CAM_PERF, "VFE:%d Invalid res_type:%d res id%d",
res->hw_intf->hw_idx, res->res_type,
res->res_id);
return -EINVAL;
}
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->top_common.mux_rsrc[i].res_id == res->res_id) {
top_priv->req_clk_rate[i] = clk_update->clk_rate;
break;
}
}
if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) {
CAM_DBG(CAM_PERF,
"VFE:%d Not ready to set clocks yet :%d",
res->hw_intf->hw_idx,
hw_info->hw_state);
} else
rc = cam_vfe_top_ver3_set_hw_clk_rate(top_priv);
return rc;
}
static int cam_vfe_top_ver3_dump_info(
struct cam_vfe_top_ver3_priv *top_priv, uint32_t cmd_type)
{
struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info;
struct cam_hw_soc_info *soc_info = top_priv->top_common.soc_info;
if (!soc_info) {
CAM_ERR(CAM_ISP, "Null soc_info");
@@ -296,7 +194,7 @@ static int cam_vfe_top_wait_comp_event(struct cam_vfe_top_ver3_priv *top_priv,
}
if (!cdm_args || !cdm_args->res || !top_priv ||
!top_priv->common_data.soc_info) {
!top_priv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "Error, Invalid args");
return -EINVAL;
}
@@ -341,7 +239,7 @@ static int cam_vfe_top_add_wait_trigger(struct cam_vfe_top_ver3_priv *top_priv,
}
if (!cdm_args || !cdm_args->res || !top_priv ||
!top_priv->common_data.soc_info) {
!top_priv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "Error, Invalid args");
return -EINVAL;
}
@@ -408,13 +306,13 @@ int cam_vfe_top_ver3_get_hw_caps(void *device_priv,
vfe_cap_info = (struct cam_vfe_hw_get_hw_cap *)args;
vfe_top_prv = (struct cam_vfe_top_ver3_priv *)device_priv;
if (!vfe_top_prv->common_data.soc_info) {
if (!vfe_top_prv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "soc_info is null");
return -EFAULT;
}
vfe_soc_private = (struct cam_vfe_soc_private *)
vfe_top_prv->common_data.soc_info->soc_private;
vfe_top_prv->top_common.soc_info->soc_private;
vfe_cap_info->is_lite = (vfe_soc_private->is_ife_lite) ? true : false;
vfe_cap_info->incr =
@@ -433,7 +331,7 @@ int cam_vfe_top_ver3_init_hw(void *device_priv,
struct cam_vfe_top_ver3_priv *top_priv = device_priv;
struct cam_vfe_top_ver3_common_data common_data = top_priv->common_data;
top_priv->hw_clk_rate = 0;
top_priv->top_common.hw_clk_rate = 0;
/**
* Auto clock gating is enabled by default, but no harm
@@ -441,20 +339,20 @@ int cam_vfe_top_ver3_init_hw(void *device_priv,
*/
CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top");
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_0, 0x0);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_1, 0x0);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->ahb_cgc_ovd, 0x0);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->noc_cgc_ovd, 0x0);
top_priv->top_common.hw_version =
cam_io_r_mb(common_data.soc_info->reg_map[0].mem_base +
cam_io_r_mb(top_priv->top_common.soc_info->reg_map[0].mem_base +
common_data.common_reg->hw_version);
return 0;
@@ -475,7 +373,7 @@ int cam_vfe_top_ver3_reset(void *device_priv,
return -EINVAL;
}
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
reg_common = top_priv->common_data.common_reg;
soc_private = soc_info->soc_private;
@@ -636,7 +534,7 @@ int cam_vfe_top_ver3_start(void *device_priv,
}
top_priv = (struct cam_vfe_top_ver3_priv *)device_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if (!soc_private) {
CAM_ERR(CAM_ISP, "Error soc_private NULL");
@@ -647,7 +545,7 @@ int cam_vfe_top_ver3_start(void *device_priv,
hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv;
if (hw_info->hw_state == CAM_HW_STATE_POWER_UP) {
rc = cam_vfe_top_ver3_set_hw_clk_rate(top_priv);
rc = cam_vfe_top_set_hw_clk_rate(&top_priv->top_common);
if (rc) {
CAM_ERR(CAM_ISP,
"set_hw_clk_rate failed, rc=%d", rc);
@@ -695,10 +593,10 @@ int cam_vfe_top_ver3_stop(void *device_priv,
top_priv = (struct cam_vfe_top_ver3_priv *)device_priv;
mux_res = (struct cam_isp_resource_node *)stop_args;
hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if (mux_res->res_id < CAM_ISP_HW_VFE_IN_MAX) {
@@ -712,7 +610,7 @@ int cam_vfe_top_ver3_stop(void *device_priv,
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->top_common.mux_rsrc[i].res_id ==
mux_res->res_id) {
top_priv->req_clk_rate[i] = 0;
top_priv->top_common.req_clk_rate[i] = 0;
memset(&top_priv->top_common.req_axi_vote[i],
0, sizeof(struct cam_axi_vote));
top_priv->top_common.axi_vote_control[i] =
@@ -753,7 +651,7 @@ int cam_vfe_top_ver3_process_cmd(void *device_priv, uint32_t cmd_type,
}
top_priv = (struct cam_vfe_top_ver3_priv *)device_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if (!soc_private) {
CAM_ERR(CAM_ISP, "Error soc_private NULL");
@@ -774,7 +672,7 @@ int cam_vfe_top_ver3_process_cmd(void *device_priv, uint32_t cmd_type,
arg_size);
break;
case CAM_ISP_HW_CMD_CLOCK_UPDATE:
rc = cam_vfe_top_ver3_clock_update(top_priv, cmd_args,
rc = cam_vfe_top_clock_update(&top_priv->top_common, cmd_args,
arg_size);
break;
case CAM_ISP_HW_NOTIFY_OVERFLOW:
@@ -850,7 +748,7 @@ int cam_vfe_top_ver3_init(
}
vfe_top->top_priv = top_priv;
top_priv->hw_clk_rate = 0;
top_priv->top_common.hw_clk_rate = 0;
if (ver3_hw_info->num_mux > CAM_VFE_TOP_MUX_MAX) {
CAM_ERR(CAM_ISP, "Invalid number of input rsrc: %d, max: %d",
ver3_hw_info->num_mux, CAM_VFE_TOP_MUX_MAX);
@@ -868,7 +766,7 @@ int cam_vfe_top_ver3_init(
top_priv->top_common.mux_rsrc[i].hw_intf = hw_intf;
top_priv->top_common.mux_rsrc[i].res_state =
CAM_ISP_RESOURCE_STATE_AVAILABLE;
top_priv->req_clk_rate[i] = 0;
top_priv->top_common.req_clk_rate[i] = 0;
if (ver3_hw_info->mux_type[i] == CAM_VFE_CAMIF_VER_3_0) {
top_priv->top_common.mux_rsrc[i].res_id =
@@ -956,7 +854,7 @@ int cam_vfe_top_ver3_init(
vfe_top->hw_ops.process_cmd = cam_vfe_top_ver3_process_cmd;
*vfe_top_ptr = vfe_top;
top_priv->common_data.soc_info = soc_info;
top_priv->top_common.soc_info = soc_info;
top_priv->common_data.hw_intf = hw_intf;
top_priv->top_common.hw_idx = hw_intf->hw_idx;
top_priv->common_data.common_reg = ver3_hw_info->common_reg;

146
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c
Parādīt failu

@@ -22,7 +22,6 @@
#define CAM_VFE_LEN_LOG_BUF 256
struct cam_vfe_top_ver4_common_data {
struct cam_hw_soc_info *soc_info;
struct cam_hw_intf *hw_intf;
struct cam_vfe_top_ver4_reg_offset_common *common_reg;
struct cam_vfe_top_ver4_hw_info *hw_info;
@@ -30,9 +29,6 @@ struct cam_vfe_top_ver4_common_data {
struct cam_vfe_top_ver4_priv {
struct cam_vfe_top_ver4_common_data common_data;
unsigned long hw_clk_rate;
unsigned long req_clk_rate[
CAM_VFE_TOP_MUX_MAX];
struct cam_vfe_top_priv_common top_common;
atomic_t overflow_pending;
uint8_t log_buf[CAM_VFE_LEN_LOG_BUF];
@@ -701,7 +697,7 @@ static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv,
}
if (!cdm_args || !cdm_args->res || !top_priv ||
!top_priv->common_data.soc_info) {
!top_priv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "Error, Invalid args");
return -EINVAL;
}
@@ -723,13 +719,13 @@ static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv,
}
mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(
top_priv->common_data.soc_info, VFE_CORE_BASE_IDX);
top_priv->top_common.soc_info, VFE_CORE_BASE_IDX);
if (cdm_args->cdm_id == CAM_CDM_RT)
mem_base -= CAM_SOC_GET_REG_MAP_CAM_BASE(
top_priv->common_data.soc_info, RT_BASE_IDX);
top_priv->top_common.soc_info, RT_BASE_IDX);
CAM_DBG(CAM_ISP, "core %d mem_base 0x%x, cdm_id: %u",
top_priv->common_data.soc_info->index, mem_base,
top_priv->top_common.soc_info->index, mem_base,
cdm_args->cdm_id);
cdm_util_ops->cdm_write_changebase(
@@ -739,55 +735,6 @@ static int cam_vfe_top_ver4_mux_get_base(struct cam_vfe_top_ver4_priv *top_priv,
return 0;
}
static int cam_vfe_top_ver4_set_hw_clk_rate(
struct cam_vfe_top_ver4_priv *top_priv)
{
struct cam_hw_soc_info *soc_info = NULL;
struct cam_vfe_soc_private *soc_private = NULL;
struct cam_ahb_vote ahb_vote;
int i, rc = 0, clk_lvl = -1;
unsigned long max_clk_rate = 0;
soc_info = top_priv->common_data.soc_info;
soc_private =
(struct cam_vfe_soc_private *)soc_info->soc_private;
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->req_clk_rate[i] > max_clk_rate)
max_clk_rate = top_priv->req_clk_rate[i];
}
if (max_clk_rate == top_priv->hw_clk_rate)
return 0;
CAM_DBG(CAM_PERF, "VFE: Clock name=%s idx=%d clk=%llu",
soc_info->clk_name[soc_info->src_clk_idx],
soc_info->src_clk_idx, max_clk_rate);
rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate);
if (!rc) {
top_priv->hw_clk_rate = max_clk_rate;
rc = cam_soc_util_get_clk_level(soc_info, max_clk_rate,
soc_info->src_clk_idx, &clk_lvl);
if (rc) {
CAM_WARN(CAM_ISP,
"Failed to get clk level for %s with clk_rate %llu src_idx %d rc %d",
soc_info->dev_name, max_clk_rate,
soc_info->src_clk_idx, rc);
rc = 0;
goto end;
}
ahb_vote.type = CAM_VOTE_ABSOLUTE;
ahb_vote.vote.level = clk_lvl;
cam_cpas_update_ahb_vote(soc_private->cpas_handle, &ahb_vote);
} else {
CAM_ERR(CAM_PERF, "Set Clock rate failed, rc=%d", rc);
}
end:
return rc;
}
static int cam_vfe_top_fs_update(
struct cam_vfe_top_ver4_priv *top_priv,
void *cmd_args, uint32_t arg_size)
@@ -801,52 +748,6 @@ static int cam_vfe_top_fs_update(
return 0;
}
static int cam_vfe_top_ver4_clock_update(
struct cam_vfe_top_ver4_priv *top_priv,
void *cmd_args, uint32_t arg_size)
{
struct cam_vfe_clock_update_args *clk_update = NULL;
struct cam_isp_resource_node *res = NULL;
struct cam_hw_info *hw_info = NULL;
int i, rc = 0;
clk_update =
(struct cam_vfe_clock_update_args *)cmd_args;
res = clk_update->node_res;
if (!res || !res->hw_intf->hw_priv) {
CAM_ERR(CAM_PERF, "Invalid input res %pK", res);
return -EINVAL;
}
hw_info = res->hw_intf->hw_priv;
if (res->res_type != CAM_ISP_RESOURCE_VFE_IN ||
res->res_id >= CAM_ISP_HW_VFE_IN_MAX) {
CAM_ERR(CAM_PERF, "VFE:%d Invalid res_type:%d res id%d",
res->hw_intf->hw_idx, res->res_type,
res->res_id);
return -EINVAL;
}
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->top_common.mux_rsrc[i].res_id == res->res_id) {
top_priv->req_clk_rate[i] = clk_update->clk_rate;
break;
}
}
if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) {
CAM_DBG(CAM_PERF,
"VFE:%d Not ready to set clocks yet :%d",
res->hw_intf->hw_idx,
hw_info->hw_state);
} else
rc = cam_vfe_top_ver4_set_hw_clk_rate(top_priv);
return rc;
}
static void cam_vfe_top_ver4_check_module_status(
uint32_t num_reg, uint32_t *reg_val,
const struct cam_vfe_top_debug_info status_list[][8])
@@ -897,7 +798,7 @@ static void cam_vfe_top_ver4_print_debug_reg_status(
struct cam_vfe_soc_private *soc_priv;
void __iomem *base;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_priv = soc_info->soc_private;
common_reg = top_priv->common_data.common_reg;
num_reg = common_reg->num_top_debug_reg;
@@ -1006,7 +907,7 @@ static int cam_vfe_top_ver4_print_overflow_debug_info(
int res_id;
common_data = &top_priv->common_data;
soc_info = common_data->soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
status = cam_io_r(soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base +
@@ -1114,12 +1015,12 @@ int cam_vfe_top_ver4_get_hw_caps(void *device_priv, void *args, uint32_t arg_siz
vfe_cap_info = args;
vfe_top_prv = device_priv;
if (!vfe_top_prv->common_data.soc_info) {
if (!vfe_top_prv->top_common.soc_info) {
CAM_ERR(CAM_ISP, "soc info is null");
return -EFAULT;
}
soc_priv = (struct cam_vfe_soc_private *)vfe_top_prv->common_data.soc_info->soc_private;
soc_priv = (struct cam_vfe_soc_private *)vfe_top_prv->top_common.soc_info->soc_private;
vfe_cap_info->is_lite = soc_priv->is_ife_lite;
vfe_cap_info->incr = (vfe_top_prv->top_common.hw_version) & 0x00ffff;
@@ -1135,7 +1036,7 @@ int cam_vfe_top_ver4_init_hw(void *device_priv,
struct cam_vfe_top_ver4_priv *top_priv = device_priv;
struct cam_vfe_top_ver4_common_data common_data = top_priv->common_data;
top_priv->hw_clk_rate = 0;
top_priv->top_common.hw_clk_rate = 0;
/**
* Auto clock gating is enabled by default, but no harm
@@ -1143,19 +1044,20 @@ int cam_vfe_top_ver4_init_hw(void *device_priv,
*/
CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top");
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_0, 0x0);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_1, 0x0);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->ahb_cgc_ovd, 0x0);
cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->noc_cgc_ovd, 0x0);
top_priv->top_common.hw_version = cam_io_r_mb(common_data.soc_info->reg_map[0].mem_base +
top_priv->top_common.hw_version = cam_io_r_mb(
top_priv->top_common.soc_info->reg_map[0].mem_base +
common_data.common_reg->hw_version);
return 0;
}
@@ -1314,7 +1216,7 @@ static void cam_vfe_top_ver4_print_violation_info(
uint32_t val = 0;
common_data = &top_priv->common_data;
soc_info = common_data->soc_info;
soc_info = top_priv->top_common.soc_info;
base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base;
val = cam_io_r(base +
common_data->common_reg->violation_status),
@@ -1346,7 +1248,7 @@ int cam_vfe_top_ver4_start(void *device_priv,
}
top_priv = (struct cam_vfe_top_ver4_priv *)device_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if (!soc_private) {
CAM_ERR(CAM_ISP, "Error soc_private NULL");
@@ -1357,7 +1259,7 @@ int cam_vfe_top_ver4_start(void *device_priv,
hw_info = (struct cam_hw_info *)mux_res->hw_intf->hw_priv;
if (hw_info->hw_state == CAM_HW_STATE_POWER_UP) {
rc = cam_vfe_top_ver4_set_hw_clk_rate(top_priv);
rc = cam_vfe_top_set_hw_clk_rate(&top_priv->top_common);
if (rc) {
CAM_ERR(CAM_ISP,
"set_hw_clk_rate failed, rc=%d", rc);
@@ -1416,7 +1318,7 @@ int cam_vfe_top_ver4_stop(void *device_priv,
for (i = 0; i < top_priv->top_common.num_mux; i++) {
if (top_priv->top_common.mux_rsrc[i].res_id ==
mux_res->res_id) {
top_priv->req_clk_rate[i] = 0;
top_priv->top_common.req_clk_rate[i] = 0;
memset(&top_priv->top_common.req_axi_vote[i],
0, sizeof(struct cam_axi_vote));
top_priv->top_common.axi_vote_control[i] =
@@ -1456,7 +1358,7 @@ int cam_vfe_top_ver4_process_cmd(void *device_priv, uint32_t cmd_type,
}
top_priv = (struct cam_vfe_top_ver4_priv *)device_priv;
soc_info = top_priv->common_data.soc_info;
soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private;
if (!soc_private) {
CAM_ERR(CAM_ISP, "Error soc_private NULL");
@@ -1477,7 +1379,7 @@ int cam_vfe_top_ver4_process_cmd(void *device_priv, uint32_t cmd_type,
arg_size);
break;
case CAM_ISP_HW_CMD_CLOCK_UPDATE:
rc = cam_vfe_top_ver4_clock_update(top_priv, cmd_args,
rc = cam_vfe_top_clock_update(&top_priv->top_common, cmd_args,
arg_size);
break;
case CAM_ISP_HW_NOTIFY_OVERFLOW:
@@ -2212,7 +2114,7 @@ int cam_vfe_top_ver4_init(
}
vfe_top->top_priv = top_priv;
top_priv->hw_clk_rate = 0;
top_priv->top_common.hw_clk_rate = 0;
if (hw_info->num_mux > CAM_VFE_TOP_MUX_MAX) {
CAM_ERR(CAM_ISP, "Invalid number of input rsrc: %d, max: %d",
@@ -2230,7 +2132,7 @@ int cam_vfe_top_ver4_init(
top_priv->top_common.mux_rsrc[i].hw_intf = hw_intf;
top_priv->top_common.mux_rsrc[i].res_state =
CAM_ISP_RESOURCE_STATE_AVAILABLE;
top_priv->req_clk_rate[i] = 0;
top_priv->top_common.req_clk_rate[i] = 0;
if (hw_info->mux_type[i] == CAM_VFE_CAMIF_VER_4_0) {
top_priv->top_common.mux_rsrc[i].res_id =
@@ -2291,7 +2193,7 @@ int cam_vfe_top_ver4_init(
*vfe_top_ptr = vfe_top;
top_priv->common_data.hw_info = hw_info;
top_priv->common_data.soc_info = soc_info;
top_priv->top_common.soc_info = soc_info;
top_priv->common_data.hw_intf = hw_intf;
top_priv->top_common.hw_idx = hw_intf->hw_idx;
top_priv->common_data.common_reg = hw_info->common_reg;