disp: msm: dsi: Avoid re-initializing PLL registers during dyn clk switch

Currently we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL registers
to only while turning on the PLL.

Change-Id: I09eacbb37fff4e0e91d226ac08e7d5a2bfbbfe26
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>

msm/dsi/dsi_pll_5nm.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -1556,7 +1557,8 @@ int dsi_pll_5nm_configure(void *pll, bool commit)
 	if (rsc->slave)
 		dsi_pll_enable_pll_bias(rsc->slave);
 
-	dsi_pll_init_val(rsc);
+	if (commit)
+		dsi_pll_init_val(rsc);
 
 	rc = dsi_pll_5nm_set_byteclk_div(rsc, commit);