qcacmn: HAL layer changes for Moselle
Add the HAL layer APIs for supporting Moselle CRs-Fixed: 2597328 Change-Id: Idc59af4ee093e702da95aa704fd3abd76ae5834f
This commit is contained in:
Rakesh Pillai
@@ -28,7 +28,8 @@
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#include "qdf_platform.h"
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/* calculate the register address offset from bar0 of shadow register x */
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#if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490)
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#if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
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defined(QCA_WIFI_QCA6750)
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#define SHADOW_REGISTER_START_ADDRESS_OFFSET 0x000008FC
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#define SHADOW_REGISTER_END_ADDRESS_OFFSET \
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((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
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@@ -38,11 +39,11 @@
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#define SHADOW_REGISTER_END_ADDRESS_OFFSET \
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((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (MAX_SHADOW_REGISTERS)))
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#define SHADOW_REGISTER(x) ((SHADOW_REGISTER_START_ADDRESS_OFFSET) + (4 * (x)))
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#endif /* QCA_WIFI_QCA6390 || QCA_WIFI_QCA6490 */
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#endif /* QCA_WIFI_QCA6390 || QCA_WIFI_QCA6490 || QCA_WIFI_QCA6750 */
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#define MAX_UNWINDOWED_ADDRESS 0x80000
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#if defined(QCA_WIFI_QCA6390) || defined(QCA_WIFI_QCA6490) || \
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defined(QCA_WIFI_QCN9000)
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defined(QCA_WIFI_QCN9000) || defined(QCA_WIFI_QCA6750)
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#define WINDOW_ENABLE_BIT 0x40000000
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#else
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#define WINDOW_ENABLE_BIT 0x80000000
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@@ -117,7 +118,8 @@ static inline void hal_reg_write_result_check(struct hal_soc *hal_soc,
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}
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}
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#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490)
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#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) || \
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!defined(QCA_WIFI_QCA6750)
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static inline void hal_lock_reg_access(struct hal_soc *soc,
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unsigned long *flags)
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{
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@@ -232,7 +234,8 @@ static inline qdf_iomem_t hal_get_window_address(struct hal_soc *hal_soc,
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* note3: WINDOW_VALUE_MASK = big enough that trying to write past
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* that window would be a bug
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*/
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#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490)
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#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
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!defined(QCA_WIFI_QCA6750)
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static inline void hal_write32_mb(struct hal_soc *hal_soc, uint32_t offset,
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uint32_t value)
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{
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@@ -403,7 +406,8 @@ void hal_write_address_32_mb(struct hal_soc *hal_soc,
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hal_write_address_32_mb(_a, _b, _c)
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#endif
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#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490)
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#if !defined(QCA_WIFI_QCA6390) && !defined(QCA_WIFI_QCA6490) && \
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!defined(QCA_WIFI_QCA6750)
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/**
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* hal_read32_mb() - Access registers to read configuration
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* @hal_soc: hal soc handle
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@@ -771,6 +771,7 @@ hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo,
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#endif
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break;
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case TARGET_TYPE_QCA6490:
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case TARGET_TYPE_QCA6750:
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ppdu_info->rx_status.nss = 0;
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break;
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default:
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@@ -515,6 +515,7 @@ struct hal_soc {
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bool init_phase;
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};
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void hal_qca6750_attach(struct hal_soc *hal_soc);
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void hal_qca6490_attach(struct hal_soc *hal_soc);
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void hal_qca6390_attach(struct hal_soc *hal_soc);
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void hal_qca6290_attach(struct hal_soc *hal_soc);
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -39,6 +39,9 @@ void hal_qca6490_attach(struct hal_soc *hal);
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#ifdef QCA_WIFI_QCN9000
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void hal_qcn9000_attach(struct hal_soc *hal);
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#endif
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#ifdef QCA_WIFI_QCA6750
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void hal_qca6750_attach(struct hal_soc *hal);
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#endif
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#ifdef ENABLE_VERBOSE_DEBUG
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bool is_hal_verbose_debug_enabled;
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@@ -252,6 +255,12 @@ static void hal_target_based_configure(struct hal_soc *hal)
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hal_qca6490_attach(hal);
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break;
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#endif
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#ifdef QCA_WIFI_QCA6750
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case TARGET_TYPE_QCA6750:
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hal->use_register_windowing = true;
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hal_qca6750_attach(hal);
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break;
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#endif
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#if defined(QCA_WIFI_QCA8074) && defined(WIFI_TARGET_TYPE_3_0)
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case TARGET_TYPE_QCA8074:
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hal_qca8074_attach(hal);
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1835
hal/wifi3.0/qca6750/hal_6750.c
Normal file
1835
hal/wifi3.0/qca6750/hal_6750.c
Normal file
File diff suppressed because it is too large
Load Diff
356
hal/wifi3.0/qca6750/hal_6750_rx.h
Normal file
356
hal/wifi3.0/qca6750/hal_6750_rx.h
Normal file
@@ -0,0 +1,356 @@
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/*
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* Copyright (c) 2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _HAL_6750_RX_H_
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#define _HAL_6750_RX_H_
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#include "qdf_util.h"
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#include "qdf_types.h"
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#include "qdf_lock.h"
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#include "qdf_mem.h"
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#include "qdf_nbuf.h"
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#include "tcl_data_cmd.h"
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#include "mac_tcl_reg_seq_hwioreg.h"
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#include "phyrx_rssi_legacy.h"
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#include "rx_msdu_start.h"
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#include "tlv_tag_def.h"
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#include "hal_hw_headers.h"
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#include "hal_internal.h"
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#include "cdp_txrx_mon_struct.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "dp_types.h"
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#include "hal_api_mon.h"
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#include "phyrx_other_receive_info_ru_details.h"
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
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RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
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RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
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#define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \
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RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
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#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \
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RX_MSDU_END_10_DA_IS_MCBC_MASK, \
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RX_MSDU_END_10_DA_IS_MCBC_LSB))
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#define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \
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RX_MSDU_END_10_SA_IS_VALID_MASK, \
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RX_MSDU_END_10_SA_IS_VALID_LSB))
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#define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_11_SA_IDX_OFFSET)), \
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RX_MSDU_END_11_SA_IDX_MASK, \
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RX_MSDU_END_11_SA_IDX_LSB))
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#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \
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RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \
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RX_MSDU_END_10_L3_HEADER_PADDING_LSB))
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#define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
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RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \
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RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB))
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#define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_3_PN_31_0_OFFSET)), \
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RX_MPDU_INFO_3_PN_31_0_MASK, \
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RX_MPDU_INFO_3_PN_31_0_LSB))
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#define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_4_PN_63_32_OFFSET)), \
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RX_MPDU_INFO_4_PN_63_32_MASK, \
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RX_MPDU_INFO_4_PN_63_32_LSB))
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#define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_5_PN_95_64_OFFSET)), \
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RX_MPDU_INFO_5_PN_95_64_MASK, \
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RX_MPDU_INFO_5_PN_95_64_LSB))
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#define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_6_PN_127_96_OFFSET)), \
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RX_MPDU_INFO_6_PN_127_96_MASK, \
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RX_MPDU_INFO_6_PN_127_96_LSB))
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#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \
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RX_MSDU_END_10_FIRST_MSDU_MASK, \
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RX_MSDU_END_10_FIRST_MSDU_LSB))
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#define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \
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RX_MSDU_END_10_DA_IS_VALID_MASK, \
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RX_MSDU_END_10_DA_IS_VALID_LSB))
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#define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
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RX_MSDU_END_10_LAST_MSDU_OFFSET)), \
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RX_MSDU_END_10_LAST_MSDU_MASK, \
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RX_MSDU_END_10_LAST_MSDU_LSB))
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#define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
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#define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
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RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \
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RX_MPDU_INFO_10_SW_PEER_ID_MASK, \
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RX_MPDU_INFO_10_SW_PEER_ID_LSB))
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#define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_TO_DS_OFFSET)), \
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RX_MPDU_INFO_11_TO_DS_MASK, \
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RX_MPDU_INFO_11_TO_DS_LSB))
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#define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_FR_DS_OFFSET)), \
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RX_MPDU_INFO_11_FR_DS_MASK, \
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RX_MPDU_INFO_11_FR_DS_LSB))
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#define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \
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RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB))
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#define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
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RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
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RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
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#define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
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RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
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RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB))
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#define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
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RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
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RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
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#define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
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RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
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RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB))
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#define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
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RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
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RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
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#define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
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RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
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RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
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#define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \
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RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
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#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
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(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
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RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
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RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
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RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
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|
||||
#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
|
||||
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
|
||||
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
|
||||
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
|
||||
|
||||
#define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
|
||||
RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
|
||||
RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
|
||||
RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
|
||||
|
||||
#define HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(_rx_mpdu_info) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
|
||||
RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)),\
|
||||
RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, \
|
||||
RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \
|
||||
RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \
|
||||
RX_MSDU_END_14_SA_SW_PEER_ID_LSB))
|
||||
|
||||
#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
|
||||
(uint8_t *)(link_desc_va) + \
|
||||
RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
|
||||
|
||||
#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
|
||||
(uint8_t *)(msdu0) + \
|
||||
RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
|
||||
|
||||
#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
|
||||
(uint8_t *)(ent_ring_desc) + \
|
||||
RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET
|
||||
|
||||
#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
|
||||
(uint8_t *)(dst_ring_desc) + \
|
||||
REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
|
||||
|
||||
#define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID)
|
||||
|
||||
#define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS)
|
||||
|
||||
#define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID)
|
||||
|
||||
#define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY)
|
||||
|
||||
#define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID)
|
||||
|
||||
#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID)
|
||||
|
||||
#define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
|
||||
do { \
|
||||
reg_val &= \
|
||||
~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
|
||||
HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
|
||||
reg_val |= \
|
||||
HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
|
||||
AGING_LIST_ENABLE, 1) |\
|
||||
HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
|
||||
AGING_FLUSH_ENABLE, 1);\
|
||||
HAL_REG_WRITE((soc), \
|
||||
HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
|
||||
SEQ_WCSS_UMAC_REO_REG_OFFSET), \
|
||||
(reg_val)); \
|
||||
reg_val = \
|
||||
HAL_REG_READ((soc), \
|
||||
HWIO_REO_R0_MISC_CTL_ADDR( \
|
||||
SEQ_WCSS_UMAC_REO_REG_OFFSET)); \
|
||||
reg_val &= \
|
||||
~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
|
||||
reg_val |= \
|
||||
HAL_SM(HWIO_REO_R0_MISC_CTL, \
|
||||
FRAGMENT_DEST_RING, \
|
||||
(reo_params)->frag_dst_ring); \
|
||||
HAL_REG_WRITE((soc), \
|
||||
HWIO_REO_R0_MISC_CTL_ADDR( \
|
||||
SEQ_WCSS_UMAC_REO_REG_OFFSET), \
|
||||
(reg_val)); \
|
||||
} while (0)
|
||||
|
||||
#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
|
||||
((struct rx_msdu_desc_info *) \
|
||||
_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
|
||||
RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
|
||||
|
||||
#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
|
||||
((struct rx_msdu_details *) \
|
||||
_OFFSET_TO_BYTE_PTR((link_desc),\
|
||||
RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
|
||||
|
||||
#define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_12_FLOW_IDX_OFFSET)), \
|
||||
RX_MSDU_END_12_FLOW_IDX_MASK, \
|
||||
RX_MSDU_END_12_FLOW_IDX_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \
|
||||
RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \
|
||||
RX_MSDU_END_10_FLOW_IDX_INVALID_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \
|
||||
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \
|
||||
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_13_FSE_METADATA_OFFSET)), \
|
||||
RX_MSDU_END_13_FSE_METADATA_MASK, \
|
||||
RX_MSDU_END_13_FSE_METADATA_LSB))
|
||||
|
||||
#define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
|
||||
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
|
||||
RX_MSDU_END_14_CCE_METADATA_OFFSET)), \
|
||||
RX_MSDU_END_14_CCE_METADATA_MASK, \
|
||||
RX_MSDU_END_14_CCE_METADATA_LSB))
|
||||
|
||||
#define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
|
||||
(_HAL_MS( \
|
||||
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
|
||||
msdu_end_tlv.rx_msdu_end), \
|
||||
RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \
|
||||
RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \
|
||||
RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB))
|
||||
#endif
|
||||
170
hal/wifi3.0/qca6750/hal_6750_tx.h
Normal file
170
hal/wifi3.0/qca6750/hal_6750_tx.h
Normal file
@@ -0,0 +1,170 @@
|
||||
/*
|
||||
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all
|
||||
* copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
|
||||
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HAL_6750_TX_H_
|
||||
#define _HAL_6750_TX_H_
|
||||
#include "tcl_data_cmd.h"
|
||||
#include "mac_tcl_reg_seq_hwioreg.h"
|
||||
#include "phyrx_rssi_legacy.h"
|
||||
#include "hal_hw_headers.h"
|
||||
#include "hal_internal.h"
|
||||
#include "cdp_txrx_mon_struct.h"
|
||||
#include "qdf_trace.h"
|
||||
#include "hal_rx.h"
|
||||
#include "hal_tx.h"
|
||||
#include "dp_types.h"
|
||||
#include "hal_api_mon.h"
|
||||
|
||||
/**
|
||||
* hal_tx_desc_set_dscp_tid_table_id_6750() - Sets DSCP to TID conversion
|
||||
* table ID
|
||||
* @desc: Handle to Tx Descriptor
|
||||
* @id: DSCP to tid conversion table to be used for this frame
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static void hal_tx_desc_set_dscp_tid_table_id_6750(void *desc, uint8_t id)
|
||||
{
|
||||
HAL_SET_FLD(desc, TCL_DATA_CMD_5,
|
||||
DSCP_TID_TABLE_NUM) |=
|
||||
HAL_TX_SM(TCL_DATA_CMD_5,
|
||||
DSCP_TID_TABLE_NUM, id);
|
||||
}
|
||||
|
||||
#define DSCP_TID_TABLE_SIZE 24
|
||||
#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
|
||||
|
||||
/**
|
||||
* hal_tx_set_dscp_tid_map_6750() - Configure default DSCP to TID map table
|
||||
* @soc: HAL SoC context
|
||||
* @map: DSCP-TID mapping table
|
||||
* @id: mapping table ID - 0-31
|
||||
*
|
||||
* DSCP are mapped to 8 TID values using TID values programmed
|
||||
* in any of the 32 DSCP_TID_MAPS (id = 0-31).
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
static void hal_tx_set_dscp_tid_map_6750(struct hal_soc *hal_soc, uint8_t *map,
|
||||
uint8_t id)
|
||||
{
|
||||
int i;
|
||||
uint32_t addr, cmn_reg_addr;
|
||||
uint32_t value = 0, regval;
|
||||
uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
|
||||
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||
|
||||
if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX)
|
||||
return;
|
||||
|
||||
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
|
||||
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
|
||||
|
||||
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
|
||||
id * NUM_WORDS_PER_DSCP_TID_TABLE);
|
||||
|
||||
/* Enable read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval |=
|
||||
(1 <<
|
||||
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
|
||||
/* Write 8 (24 bits) DSCP-TID mappings in each interation */
|
||||
for (i = 0; i < 64; i += 8) {
|
||||
value = (map[i] |
|
||||
(map[i + 1] << 0x3) |
|
||||
(map[i + 2] << 0x6) |
|
||||
(map[i + 3] << 0x9) |
|
||||
(map[i + 4] << 0xc) |
|
||||
(map[i + 5] << 0xf) |
|
||||
(map[i + 6] << 0x12) |
|
||||
(map[i + 7] << 0x15));
|
||||
|
||||
qdf_mem_copy(&val[cnt], (void *)&value, 3);
|
||||
cnt += 3;
|
||||
}
|
||||
|
||||
for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
|
||||
regval = *(uint32_t *)(val + i);
|
||||
HAL_REG_WRITE(soc, addr,
|
||||
(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
/* Diasble read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval &=
|
||||
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_update_dscp_tid_6750() - Update the dscp tid map table as updated
|
||||
* by the user
|
||||
* @soc: HAL SoC context
|
||||
* @map: DSCP-TID mapping table
|
||||
* @id : MAP ID
|
||||
* @dscp: DSCP_TID map index
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static void hal_tx_update_dscp_tid_6750(struct hal_soc *hal_soc, uint8_t tid,
|
||||
uint8_t id, uint8_t dscp)
|
||||
{
|
||||
int index;
|
||||
uint32_t addr;
|
||||
uint32_t value;
|
||||
uint32_t regval;
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||
|
||||
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id);
|
||||
|
||||
index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
|
||||
addr += 4 * (dscp / HAL_TX_NUM_DSCP_PER_REGISTER);
|
||||
value = tid << (HAL_TX_BITS_PER_TID * index);
|
||||
|
||||
regval = HAL_REG_READ(soc, addr);
|
||||
regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
|
||||
regval |= value;
|
||||
|
||||
HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_desc_set_lmac_id_6750 - Set the lmac_id value
|
||||
* @desc: Handle to Tx Descriptor
|
||||
* @lmac_id: mac Id to ast matching
|
||||
* b00 – mac 0
|
||||
* b01 – mac 1
|
||||
* b10 – mac 2
|
||||
* b11 – all macs (legacy HK way)
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static void hal_tx_desc_set_lmac_id_6750(void *desc, uint8_t lmac_id)
|
||||
{
|
||||
HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
|
||||
HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user