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@@ -77,6 +77,8 @@ static const struct snd_kcontrol_new name##_mux = \
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#define RX_MACRO_EC_MIX_TX1_MASK 0x0f
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#define RX_MACRO_EC_MIX_TX2_MASK 0x0f
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+#define COMP_MAX_COEFF 25
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+
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struct wcd_imped_val {
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u32 imped_val;
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u8 index;
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@@ -95,6 +97,75 @@ static const struct wcd_imped_val imped_index[] = {
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{13, 9},
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};
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+struct comp_coeff_val {
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+ u8 lsb;
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+ u8 msb;
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+};
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+
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+enum {
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+ HPH_ULP,
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+ HPH_LOHIFI,
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+ HPH_MODE_MAX,
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+};
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+
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+static const struct comp_coeff_val
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+ comp_coeff_table [HPH_MODE_MAX][COMP_MAX_COEFF] = {
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+ {
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+ {0x40, 0x00},
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+ {0x4C, 0x00},
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+ {0x5A, 0x00},
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+ {0x6B, 0x00},
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+ {0x7F, 0x00},
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+ {0x97, 0x00},
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+ {0xB3, 0x00},
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+ {0xD5, 0x00},
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+ {0xFD, 0x00},
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+ {0x2D, 0x01},
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+ {0x66, 0x01},
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+ {0xA7, 0x01},
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+ {0xF8, 0x01},
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+ {0x57, 0x02},
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+ {0xC7, 0x02},
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+ {0x4B, 0x03},
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+ {0xE9, 0x03},
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+ {0xA3, 0x04},
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+ {0x7D, 0x05},
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+ {0x90, 0x06},
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+ {0xD1, 0x07},
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+ {0x49, 0x09},
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+ {0x00, 0x0B},
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+ {0x01, 0x0D},
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+ {0x59, 0x0F},
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+ },
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+ {
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+ {0x40, 0x00},
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+ {0x4C, 0x00},
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+ {0x5A, 0x00},
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+ {0x6B, 0x00},
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+ {0x80, 0x00},
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+ {0x98, 0x00},
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+ {0xB4, 0x00},
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+ {0xD5, 0x00},
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+ {0xFE, 0x00},
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+ {0x2E, 0x01},
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+ {0x66, 0x01},
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+ {0xA9, 0x01},
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+ {0xF8, 0x01},
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+ {0x56, 0x02},
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+ {0xC4, 0x02},
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+ {0x4F, 0x03},
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+ {0xF0, 0x03},
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+ {0xAE, 0x04},
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+ {0x8B, 0x05},
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+ {0x8E, 0x06},
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+ {0xBC, 0x07},
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+ {0x56, 0x09},
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+ {0x0F, 0x0B},
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+ {0x13, 0x0D},
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+ {0x6F, 0x0F},
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+ },
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+};
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+
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struct rx_macro_reg_mask_val {
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u16 reg;
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u8 mask;
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@@ -1526,6 +1597,47 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
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return 0;
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}
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+static int rx_macro_load_compander_coeff(struct snd_soc_component *component,
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+ struct rx_macro_priv *rx_priv,
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+ int interp_n, int event)
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+{
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+ int comp = 0;
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+ u16 comp_coeff_lsb_reg = 0, comp_coeff_msb_reg = 0;
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+ int i = 0;
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+ int hph_pwr_mode = HPH_LOHIFI;
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+
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+ if (!rx_priv->comp_enabled[comp])
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+ return 0;
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+
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+ if (interp_n == INTERP_HPHL) {
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+ comp_coeff_lsb_reg = BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB;
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+ comp_coeff_msb_reg = BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB;
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+ } else if (interp_n == INTERP_HPHR) {
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+ comp_coeff_lsb_reg = BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB;
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+ comp_coeff_msb_reg = BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB;
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+ } else {
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+ /* compander coefficients are loaded only for hph path */
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+ return 0;
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+ }
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+
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+ comp = interp_n;
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+ hph_pwr_mode = rx_priv->hph_pwr_mode;
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+ dev_dbg(component->dev, "%s: event %d compander %d, enabled %d\n",
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+ __func__, event, comp + 1, rx_priv->comp_enabled[comp]);
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+
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+ if (SND_SOC_DAPM_EVENT_ON(event)) {
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+ /* Load Compander Coeff */
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+ for (i = 0; i < COMP_MAX_COEFF; i++) {
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+ snd_soc_component_write(component, comp_coeff_lsb_reg,
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+ comp_coeff_table[hph_pwr_mode][i].lsb);
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+ snd_soc_component_write(component, comp_coeff_msb_reg,
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+ comp_coeff_table[hph_pwr_mode][i].msb);
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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static void rx_macro_enable_softclip_clk(struct snd_soc_component *component,
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struct rx_macro_priv *rx_priv,
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bool enable)
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@@ -2245,6 +2357,8 @@ static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
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0x20, 0x20);
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snd_soc_component_update_bits(component, rx_cfg2_reg,
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0x03, 0x03);
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+ rx_macro_load_compander_coeff(component, rx_priv,
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+ interp_idx, event);
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rx_macro_idle_detect_control(component, rx_priv,
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interp_idx, event);
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if (rx_priv->hph_hd2_mode)
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qctecmdr