fw-api: CL 7475518 - update fw common interface files

HTT/WMI: support flow override; specify multiple AST indices

Change-Id: Ic111606c3452258181f75732d9aef0fe81ee4552
CRs-Fixed: 2262693

fw/htt.h

@@ -188,9 +188,10 @@
  * 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg.
  * 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP
  * 3.69 Add htt_ul_ofdma_user_info_v0 defs
+ * 3.70 Add AST1-AST3 fields to HTT_T2H PEER_MAP_V2 msg
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 69
+#define HTT_CURRENT_VERSION_MINOR 70
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -7972,7 +7973,8 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  * to identify which peer the frame needs to be forwarded to (i.e. the
  * peer assocated with the Destination MAC Address within the packet),
  * and particularly which vdev needs to transmit the frame (for cases
- * of inter-vdev rx --> tx forwarding).
+ * of inter-vdev rx --> tx forwarding). The HW peer id here is the same
+ * meaning as AST_INDEX_0.
  * This DA-based peer ID that is provided for certain rx frames
  * (the rx frames that need to be re-transmitted as tx frames)
  * is the ID that the HW uses for referring to the peer in question,
@@ -7985,7 +7987,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  * |-----------------------------------------------------------------------|
  * |    MAC addr 3   |    MAC addr 2   |    MAC addr 1   |    MAC addr 0   |
  * |-----------------------------------------------------------------------|
- * |            HW peer ID             |    MAC addr 5   |    MAC addr 4   |
+ * |      HW peer ID / AST index 0     |    MAC addr 5   |    MAC addr 4   |
  * |-----------------------------------------------------------------------|
  *
  *
@@ -8115,26 +8117,34 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  * is the ID that the HW uses for referring to the peer in question,
  * rather than the peer ID that the SW+FW use to refer to the peer.
  *
+ * The HW peer id here is the same meaning as AST_INDEX_0.
+ * Some chips support up to 4 AST indices per peer: AST_INDEX_0, AST_INDEX_1,
+ * AST_INDEX_2, and AST_INDEX_3.  AST 0 is always valid; for AST 1 through
+ * AST 3, check the AST_VALID_MASK(3) to see if the corresponding extension
+ * AST is valid.
  *
- * |31             24|23             16|15              8|7               0|
+ * |31    28|27    24|23    20|19 17|16|15              8|7               0|
  * |-----------------------------------------------------------------------|
  * |            SW peer ID             |     VDEV ID     |     msg type    |
  * |-----------------------------------------------------------------------|
  * |    MAC addr 3   |    MAC addr 2   |    MAC addr 1   |    MAC addr 0   |
  * |-----------------------------------------------------------------------|
- * |            HW peer ID             |    MAC addr 5   |    MAC addr 4   |
+ * |      HW peer ID / AST index 0     |    MAC addr 5   |    MAC addr 4   |
  * |-----------------------------------------------------------------------|
- * |     Reserved_17_31     | Next Hop |          AST Hash Value           |
+ * |     Reserved_20_31       |ASTVM|NH|          AST Hash Value           |
  * |-----------------------------------------------------------------------|
- * |                               Reserved_0                              |
+ * | ASTFM3 | ASTFM2 | ASTFM1 | ASTFM0 |           AST index 1             |
  * |-----------------------------------------------------------------------|
- * |                               Reserved_1                              |
+ * |TID valid low pri| TID valid hi pri|           AST index 2             |
  * |-----------------------------------------------------------------------|
- * |                               Reserved_2                              |
+ * |           Reserved_1              |           AST index 3             |
  * |-----------------------------------------------------------------------|
- * |                               Reserved_3                              |
+ * |                               Reserved_2                              |
  * |-----------------------------------------------------------------------|
- *
+ * Where:
+ *    NH = Next Hop
+ *    ASTVM = AST valid mask
+ *    ASTFM = AST flow mask
  *
  * The following field definitions describe the format of the rx peer map v2
  * messages sent from the target to the host.
@@ -8158,7 +8168,7 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  *     Bits 15:0
  *     Purpose: Identifies which peer node the peer ID is for.
  *     Value: upper 2 bytes of peer node's MAC address
- *   - HW_PEER_ID
+ *   - HW_PEER_ID / AST_INDEX_0
  *     Bits 31:16
  *     Purpose: Identifies the HW peer ID corresponding to the peer MAC
  *         address, so for rx frames marked for rx --> tx forwarding, the
@@ -8173,6 +8183,36 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
  *     Bit 16
  *     Purpose: Bit indicates that a next_hop AST entry is used for WDS
  *         (Wireless Distribution System).
+ *   - AST_VALID_MASK
+ *     Bits  19:17
+ *     Purpose: Indicate if the AST 1 through AST 3 are valid
+ *   - AST_INDEX_1
+ *     Bits 15:0
+ *     Purpose: indicate the second AST index for this peer
+ *   - AST_0_FLOW_MASK
+ *     Bits 19:16
+ *     Purpose: identify the which flow the AST 0 entry corresponds to.
+ *   - AST_1_FLOW_MASK
+ *     Bits 23:20
+ *     Purpose: identify the which flow the AST 1 entry corresponds to.
+ *   - AST_2_FLOW_MASK
+ *     Bits 27:24
+ *     Purpose: identify the which flow the AST 2 entry corresponds to.
+ *   - AST_3_FLOW_MASK
+ *     Bits 31:28
+ *     Purpose: identify the which flow the AST 3 entry corresponds to.
+ *   - AST_INDEX_2
+ *     Bits 15:0
+ *     Purpose: indicate the third AST index for this peer
+ *   - TID_VALID_HI_PRI
+ *     Bits 23:16
+ *     Purpose: identify if this peer's TIDs 0-7 support HI priority flow
+ *   - TID_VALID_LOW_PRI
+ *     Bits 31:24
+ *     Purpose: identify if this peer's TIDs 0-7 support Low priority flow
+ *   - AST_INDEX_3
+ *     Bits 15:0
+ *     Purpose: indicate the fourth AST index for this peer
  */
 #define HTT_RX_PEER_MAP_V2_VDEV_ID_M        0xff00
 #define HTT_RX_PEER_MAP_V2_VDEV_ID_S        8
@@ -8188,6 +8228,29 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
 #define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S 0
 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_M       0x00010000
 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_S       16
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M     0x000e0000
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S     17
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_M        0xffff
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_S        0
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M    0x000f0000
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S    16
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M    0x00f00000
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S    20
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M    0x0f000000
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S    24
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M    0xf0000000
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S    28
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_M        0xffff
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_S        0
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M   0x00ff0000
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S   16
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M  0xff000000
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S  24
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_M        0xffff
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_S        0
 
 #define HTT_RX_PEER_MAP_V2_VDEV_ID_SET(word, value)           \
     do {                                                      \
@@ -8229,10 +8292,97 @@ PREPACK struct htt_tx_offload_deliver_ind_hdr_t
 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_GET(word) \
     (((word) & HTT_RX_PEER_MAP_V2_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V2_NEXT_HOP_S)
 
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_VALID_MASK, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_1, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_INDEX_1_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_1_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_1_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_2, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_INDEX_2_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_2_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_2_S)
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S)
+
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_SET(word, value) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_3, value); \
+        (word) |= (value)  << HTT_RX_PEER_MAP_V2_AST_INDEX_3_S; \
+    } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_GET(word) \
+    (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_3_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_3_S)
+
+
 #define HTT_RX_PEER_MAP_V2_MAC_ADDR_OFFSET       4  /* bytes */
 #define HTT_RX_PEER_MAP_V2_HW_PEER_ID_OFFSET     8  /* bytes */
 #define HTT_RX_PEER_MAP_V2_AST_HASH_INDEX_OFFSET 12 /* bytes */
 #define HTT_RX_PEER_MAP_V2_NEXT_HOP_OFFSET       12 /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_OFFSET     12  /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_OFFSET        16  /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_X_FLOW_MASK_OFFSET    16  /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_OFFSET        20  /* bytes */
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LO_PRI_OFFSET   20  /* bytes */
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_OFFSET   20  /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_OFFSET        24  /* bytes */
 
 #define HTT_RX_PEER_MAP_V2_BYTES 32
 

fw/wmi_services.h

@@ -398,6 +398,7 @@ typedef  enum  {
     WMI_SERVICE_PER_PEER_HTT_STATS_RESET = 213, /* FW supports HTT per peer stats reset facility */
     WMI_SERVICE_DELETE_ALL_PEER_SUPPORT = 214, /* target supports cmd to delete all peers within a vdev */
     WMI_SERVICE_DYNAMIC_HW_MODE_SWITCH_SUPPORT = 215, /* target supports Dynamic HW mode switch */
+    WMI_SERVICE_MSDU_FLOW_OVERRIDE_BY_HOST = 216, /* target supports flow override feature */
 
     /******* ADD NEW SERVICES HERE *******/
 

fw/wmi_unified.h

@@ -3229,8 +3229,76 @@ typedef struct {
      *        other - reserved.
      */
     A_UINT32 ul_resp_config;
+
+    /* msdu_flow_override_config0 - contains AST enable bitmask
+     * AST0 is unconditionally enabled, unless the MSDU flow override feature
+     * is entirely disabled.
+     * AST1 through AST3 are conditionally enabled, based on bits 0-2 in
+     * msdu_flow_override_config0.
+     * If all three bits are 0, no msdu flow override feature at all in FW.
+     *
+     * The WMI_MSDU_FLOW_AST_ENABLE_GET and WMI_MSDU_FLOW_AST_ENABLE_SET
+     * macros are used to read and write these bitfields.
+     */
+    A_UINT32 msdu_flow_override_config0;
+
+     /* msdu_flow_override_config1:
+      * Bits 3:0   - AST0_FLOW_MASK(4)
+      * Bits 7:4   - AST1_FLOW_MASK(4)
+      * Bits 11:8  - AST2_FLOW_MASK(4)
+      * Bits 15:12 - AST3_FLOW_MASK(4)
+      * Bits 23:16 - TID_VALID_HI_PRI (8)
+      * Bits 31:24 - TID_VALID_LOW_PRI (8)
+      *
+      * The macros
+      * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_GET
+      * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_SET
+      * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_GET
+      * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_SET
+      * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_GET
+      * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_SET
+      * are used to read and write these bitfields.
+      */
+    A_UINT32 msdu_flow_override_config1;
 } wmi_resource_config;
 
+#define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \
+    (((ast_x) == 0) ? 1 : ((msdu_flow_config0) & (1 << ((ast_x) - 1))))
+#define WMI_MSDU_FLOW_AST_ENABLE_SET(msdu_flow_config0, ast_x, enable) \
+    do { \
+        if ((ast_x) == 0) break;  \
+        if ((enable)) { \
+            (msdu_flow_config0) |= (1 << ((ast_x) - 1)); \
+        } else { \
+            (msdu_flow_config0) &= ~(1 << ((ast_x) - 1)); \
+        } \
+    } while(0)
+
+#define WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_GET(msdu_flow_config1, ast_x) \
+    (((msdu_flow_config1) & (0x0f << ((ast_x) * 4))) >> ((ast_x) * 4))
+#define WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_SET( \
+    msdu_flow_config1, ast_x, mask) \
+    do { \
+        (msdu_flow_config1) &= ~(0xF << ((ast_x) * 4)); \
+        (msdu_flow_config1) |= ((mask) << ((ast_x) * 4)); \
+    } while(0)
+
+#define WMI_MSDU_FLOW_TID_VALID_HI_MASKS_GET(msdu_flow_config1) \
+    (((msdu_flow_config1) & 0xff0000) >> 16)
+#define WMI_MSDU_FLOW_TID_VALID_HI_MASKS_SET(msdu_flow_config1, mask) \
+    do { \
+        (msdu_flow_config1) &= ~0xff0000; \
+        (msdu_flow_config1) |= ((mask) << 16); \
+    } while(0)
+
+#define WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_GET(msdu_flow_config1) \
+    ((msdu_flow_config1 & 0xff000000) >> 24)
+#define WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_SET(msdu_flow_config1, mask) \
+    do { \
+        (msdu_flow_config1) &= ~0xff000000; \
+        (msdu_flow_config1) |= ((mask) << 24); \
+    } while(0)
+
 #define WMI_RSRC_CFG_FLAG_SET(word32, flag, value) \
     do { \
         (word32) &= ~WMI_RSRC_CFG_FLAG_ ## flag ## _M; \
@@ -9862,6 +9930,24 @@ typedef enum {
      */
     WMI_VDEV_PARAM_MCAST_RC_STALE_PERIOD,       /* 0x94 */
 
+    /*
+     * Bits 3:0   - AST0_FLOW_MASK(4)
+     * Bits 7:4   - AST1_FLOW_MASK(4)
+     * Bits 11:8  - AST2_FLOW_MASK(4)
+     * Bits 15:12 - AST3_FLOW_MASK(4)
+     * Bits 23:16 - TID_VALID_HI_PRI(8)
+     * Bits 31:24 - TID_VALID_LOW_PRI(8)
+     *
+     * The below macros can be used to set/get the relevent fields.
+     * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_GET(msdu_flow_config1, ast_x)
+     * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_SET(msdu_flow_config1, ast_x, mask)
+     * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_GET(msdu_flow_config1)
+     * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_SET(msdu_flow_config1, mask)
+     * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_GET(msdu_flow_config1)
+     * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_SET(msdu_flow_config1, mask)
+     */
+    WMI_VDEV_PARAM_MSDU_FLOW_OVERRIDE_CONFIG,  /* 0x95 */
+
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are

fw/wmi_version.h

@@ -36,7 +36,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 685
+#define __WMI_REVISION_ 686
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work