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msm: camera: cpas: Enable camnoc interrupts

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Enable camnoc interrupts to get notifications
for UBWC encoder and decoder errors.

Change-Id: Ie7d89dcaf4c81e9ce5af9f28e9a5e0a9cf3eeaa8
Signed-off-by: Suresh Vankadara <svankada@codeaurora.org>
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
This commit is contained in:
Jigarkumar Zala
2019-07-29 11:57:38 -07:00
parent 2f6c89b46f
commit 93e8362a07
2 changed files with 13 additions and 7 deletions
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4
drivers/cam_cpas/cpas_top/cam_cpastop_hw.c
View File

@@ -334,6 +334,9 @@ static int cam_cpastop_reset_irq(struct cam_hw_info *cpas_hw)
{ {
int i; int i;
if (camnoc_info->irq_sbm->sbm_enable.enable == false)
return 0;
cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
&camnoc_info->irq_sbm->sbm_clear); &camnoc_info->irq_sbm->sbm_clear);
for (i = 0; i < camnoc_info->irq_err_size; i++) { for (i = 0; i < camnoc_info->irq_err_size; i++) {
@@ -508,6 +511,7 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
{ {
int i; int i;
cam_cpastop_reset_irq(cpas_hw);
for (i = 0; i < camnoc_info->specific_size; i++) { for (i = 0; i < camnoc_info->specific_size; i++) {
if (camnoc_info->specific[i].enable) { if (camnoc_info->specific[i].enable) {
cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC, cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,

16
drivers/cam_cpas/cpas_top/cpastop_v175_130.h
View File

@@ -67,18 +67,19 @@ static struct cam_camnoc_irq_err
.err_enable = { .err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE, .access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true, .enable = true,
.offset = 0x3BA0, /* SPECIFIC_IFE02_ENCERREN_LOW */ .offset = 0x3BA0, /* SPECIFIC_IFE0_MAIN_ENCERREN_LOW */
.value = 1, .value = 1,
}, },
.err_status = { .err_status = {
.access_type = CAM_REG_TYPE_READ, .access_type = CAM_REG_TYPE_READ,
.enable = true, .enable = true,
.offset = 0x3B90, /* SPECIFIC_IFE02_ENCERRSTATUS_LOW */ /* SPECIFIC_IFE0_MAIN_ENCERRSTATUS_LOW */
.offset = 0x3B90,
}, },
.err_clear = { .err_clear = {
.access_type = CAM_REG_TYPE_WRITE, .access_type = CAM_REG_TYPE_WRITE,
.enable = true, .enable = true,
.offset = 0x3B98, /* SPECIFIC_IFE02_ENCERRCLR_LOW */ .offset = 0x3B98, /* SPECIFIC_IFE0_MAIN_ENCERRCLR_LOW */
.value = 1, .value = 1,
}, },
}, },
@@ -89,18 +90,19 @@ static struct cam_camnoc_irq_err
.err_enable = { .err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE, .access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true, .enable = true,
.offset = 0x55a0, /* SPECIFIC_IFE13_ENCERREN_LOW */ .offset = 0x55A0, /* SPECIFIC_IFE1_WR_ENCERREN_LOW */
.value = 1, .value = 1,
}, },
.err_status = { .err_status = {
.access_type = CAM_REG_TYPE_READ, .access_type = CAM_REG_TYPE_READ,
.enable = true, .enable = true,
.offset = 0x5590, /* SPECIFIC_IFE13_ENCERRSTATUS_LOW */ /* SPECIFIC_IFE1_WR_ENCERRSTATUS_LOW */
.offset = 0x5590,
}, },
.err_clear = { .err_clear = {
.access_type = CAM_REG_TYPE_WRITE, .access_type = CAM_REG_TYPE_WRITE,
.enable = true, .enable = true,
.offset = 0x5598, /* SPECIFIC_IFE13_ENCERRCLR_LOW */ .offset = 0x5598, /* SPECIFIC_IFE1_WR_ENCERRCLR_LOW */
.value = 1, .value = 1,
}, },
}, },
@@ -133,7 +135,7 @@ static struct cam_camnoc_irq_err
.err_enable = { .err_enable = {
.access_type = CAM_REG_TYPE_READ_WRITE, .access_type = CAM_REG_TYPE_READ_WRITE,
.enable = true, .enable = true,
.offset = 0x2Ba0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */ .offset = 0x2BA0, /* SPECIFIC_IBL_WR_ENCERREN_LOW */
.value = 1, .value = 1,
}, },
.err_status = { .err_status = {