Merge "msm: camera: isp: Remove reprogramming of CSID registers" into camera-kernel.lnx.5.0
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@@ -2196,6 +2196,23 @@ static int cam_convert_rdi_out_res_id_to_src(int res_id)
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return CAM_ISP_HW_VFE_IN_MAX;
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}
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static int cam_convert_csid_res_to_path(int res_id)
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{
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if (res_id == CAM_IFE_PIX_PATH_RES_IPP)
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return CAM_ISP_PXL_PATH;
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else if (res_id == CAM_IFE_PIX_PATH_RES_PPP)
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return CAM_ISP_PPP_PATH;
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else if (res_id == CAM_IFE_PIX_PATH_RES_RDI_0)
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return CAM_ISP_RDI0_PATH;
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else if (res_id == CAM_IFE_PIX_PATH_RES_RDI_1)
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return CAM_ISP_RDI1_PATH;
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else if (res_id == CAM_IFE_PIX_PATH_RES_RDI_2)
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return CAM_ISP_RDI2_PATH;
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else if (res_id == CAM_IFE_PIX_PATH_RES_RDI_3)
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return CAM_ISP_RDI3_PATH;
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return 0;
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}
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static int cam_convert_res_id_to_hw_path(int res_id)
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{
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if (res_id == CAM_ISP_HW_VFE_IN_LCR)
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@@ -3273,7 +3290,8 @@ static enum cam_ife_pix_path_res_id
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static int cam_ife_hw_mgr_acquire_res_ife_csid_rdi(
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struct cam_ife_hw_mgr_ctx *ife_ctx,
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struct cam_isp_in_port_generic_info *in_port)
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struct cam_isp_in_port_generic_info *in_port,
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uint32_t *acquired_hw_path)
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{
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int rc = -EINVAL;
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int i;
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@@ -3362,6 +3380,9 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_rdi(
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ife_ctx->left_hw_idx =
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csid_res->hw_res[0]->hw_intf->hw_idx;
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}
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if (ife_ctx->flags.is_sfe_shdr)
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*acquired_hw_path |= cam_convert_csid_res_to_path(
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csid_res->res_id);
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cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_csid, &csid_res);
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}
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@@ -4161,7 +4182,8 @@ skip_csid_pxl:
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if (in_port->rdi_count) {
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/* get ife csid RDI resource */
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rc = cam_ife_hw_mgr_acquire_res_ife_csid_rdi(ife_ctx, in_port);
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rc = cam_ife_hw_mgr_acquire_res_ife_csid_rdi(ife_ctx, in_port,
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acquired_hw_path);
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if (rc) {
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CAM_ERR(CAM_ISP,
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"Acquire IFE CSID RDI resource Failed");
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@@ -422,8 +422,6 @@ static struct cam_ife_csid_ver2_pxl_reg_info
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.bin_pd_detect_x_end_shift_val = 16,
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.bin_pd_detect_y_offset_shift_val = 0,
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.bin_pd_detect_y_end_shift_val = 16,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.lut_bank_0_sel_val = 0,
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.lut_bank_1_sel_val = 1,
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.fatal_err_mask = 0x186004,
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@@ -617,8 +615,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186004,
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.non_fatal_err_mask = 0x10000000,
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@@ -713,8 +709,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186004,
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.non_fatal_err_mask = 0x10000000,
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@@ -809,8 +803,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186004,
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.non_fatal_err_mask = 0x10000000,
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@@ -905,8 +897,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186004,
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.non_fatal_err_mask = 0x10000000,
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@@ -1001,8 +991,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.format_measure_en_shift_val = 3,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186004,
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.non_fatal_err_mask = 0x10000000,
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@@ -450,8 +450,6 @@ static struct cam_ife_csid_ver2_pxl_reg_info
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.bin_pd_detect_x_end_shift_val = 16,
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.bin_pd_detect_y_offset_shift_val = 0,
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.bin_pd_detect_y_end_shift_val = 16,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.lut_bank_0_sel_val = 0,
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.lut_bank_1_sel_val = 1,
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.fatal_err_mask = 0x186007,
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@@ -642,8 +640,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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@@ -738,8 +734,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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@@ -834,8 +828,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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@@ -930,8 +922,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.timestamp_en_shift_val = 4,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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@@ -1026,8 +1016,6 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.format_measure_en_shift_val = 3,
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.debug_byte_cntr_rst_shift_val = 2,
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.offline_mode_en_shift_val = 2,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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@@ -1885,7 +1885,6 @@ static int cam_ife_csid_hw_ver2_config_path_data(
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path_cfg->vertical_bin = reserve->in_port->vertical_bin;
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path_cfg->qcfa_bin = reserve->in_port->qcfa_bin;
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path_cfg->num_bytes_out = reserve->in_port->num_bytes_out;
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path_cfg->pix_pattern = reserve->in_port->test_pattern;
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if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) {
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path_cfg->start_pixel = reserve->in_port->left_start;
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path_cfg->end_pixel = reserve->in_port->left_stop;
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@@ -2033,12 +2032,9 @@ static int cam_ife_csid_ver_config_camif(
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path_cfg->camif_data.epoch0 = epoch0;
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path_cfg->camif_data.pix_pattern = reserve->in_port->test_pattern;
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end:
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CAM_DBG(CAM_ISP, "CSID[%d] pix_pattern: %d epoch0: 0x%x",
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csid_hw->hw_intf->hw_idx,
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path_cfg->camif_data.pix_pattern, epoch0);
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CAM_DBG(CAM_ISP, "CSID[%d] epoch0: 0x%x",
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csid_hw->hw_intf->hw_idx, epoch0);
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return rc;
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}
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@@ -2467,9 +2463,6 @@ static int cam_ife_csid_ver2_init_config_rdi_path(
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/* set frame drop pattern to 0 and period to 1 */
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cam_io_w_mb(1, mem_base + path_reg->frm_drop_period_addr);
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cam_io_w_mb(0, mem_base + path_reg->frm_drop_pattern_addr);
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/* set irq sub sample pattern to 1 and period to 0 */
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cam_io_w_mb(0, mem_base + path_reg->irq_subsample_period_addr);
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cam_io_w_mb(1, mem_base + path_reg->irq_subsample_pattern_addr);
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/*TODO Need to check for any hw errata like 480 and 580*/
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/* set pxl drop pattern to 0 and period to 1 */
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@@ -2647,9 +2640,6 @@ static int cam_ife_csid_ver2_init_config_pxl_path(
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/* set frame drop pattern to 0 and period to 1 */
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cam_io_w_mb(1, mem_base + path_reg->frm_drop_period_addr);
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cam_io_w_mb(0, mem_base + path_reg->frm_drop_pattern_addr);
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/* set irq sub sample pattern to 1 and period to 1 */
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cam_io_w_mb(0, mem_base + path_reg->irq_subsample_period_addr);
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cam_io_w_mb(1, mem_base + path_reg->irq_subsample_pattern_addr);
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/* set pxl drop pattern to 0 and period to 1 */
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cam_io_w_mb(0, mem_base + path_reg->pix_drop_pattern_addr);
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cam_io_w_mb(1, mem_base + path_reg->pix_drop_period_addr);
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@@ -2760,12 +2750,6 @@ static int cam_ife_csid_ver2_program_rdi_path(
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csid_hw->hw_intf->hw_idx, res->res_id);
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/*Program the camif part */
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val = (path_cfg->camif_data.pix_pattern <<
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path_reg->pix_pattern_shift_val) |
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(path_cfg->camif_data.stripe_loc <<
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path_reg->stripe_loc_shift_val);
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cam_io_w_mb(val, mem_base + path_reg->camif_frame_cfg_addr);
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cam_io_w_mb(path_cfg->camif_data.epoch0 <<
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path_reg->epoch0_shift_val,
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mem_base + path_reg->epoch_irq_cfg_addr);
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@@ -2898,12 +2882,6 @@ static int cam_ife_csid_ver2_program_ipp_path(
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mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
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path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
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val = (path_cfg->camif_data.pix_pattern <<
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path_reg->pix_pattern_shift_val) |
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(path_cfg->camif_data.stripe_loc <<
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path_reg->stripe_loc_shift_val);
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cam_io_w_mb(val, mem_base + path_reg->camif_frame_cfg_addr);
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cam_io_w_mb(path_cfg->camif_data.epoch0 << path_reg->epoch0_shift_val,
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mem_base + path_reg->epoch_irq_cfg_addr);
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@@ -3114,12 +3092,6 @@ static int cam_ife_csid_ver2_program_ppp_path(
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path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
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val = (path_cfg->camif_data.pix_pattern <<
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path_reg->pix_pattern_shift_val) |
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(path_cfg->camif_data.stripe_loc <<
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path_reg->stripe_loc_shift_val);
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cam_io_w_mb(val, mem_base + path_reg->camif_frame_cfg_addr);
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cam_io_w_mb(path_cfg->camif_data.epoch0 << path_reg->epoch0_shift_val,
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mem_base + path_reg->epoch_irq_cfg_addr);
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@@ -115,16 +115,12 @@ struct cam_ife_csid_ver2_evt_payload {
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};
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/*
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* struct cam_ife_csid_ver2_path_cfg: place holder for path parameters
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* struct cam_ife_csid_ver2_camif_data: place holder for camif parameters
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*
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* @pix_pattern: Pix pattern for incoming data
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* @stripe_loc: Stripe location
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* @epoch0_cfg: Epoch 0 configuration value
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* @epoch1_cfg: Epoch 1 configuration value
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*/
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struct cam_ife_csid_ver2_camif_data {
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uint32_t pix_pattern;
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uint32_t stripe_loc;
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uint32_t epoch0;
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uint32_t epoch1;
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};
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@@ -149,7 +145,6 @@ struct cam_ife_csid_ver2_camif_data {
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* @qcfa_bin : qcfa binning enable/disable on path
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* @hor_ver_bin : horizontal vertical binning enable/disable on path
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* @num_bytes_out: Number of bytes out
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* @pix_pattern: Pixel Pattern
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* @irq_handle: IRQ handle
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* @err_irq_handle: Error IRQ handle
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* @discard_irq_handle: IRQ handle for SOF when discarding initial frames
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@@ -183,7 +178,6 @@ struct cam_ife_csid_ver2_path_cfg {
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uint32_t qcfa_bin;
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uint32_t hor_ver_bin;
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uint32_t num_bytes_out;
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uint32_t pix_pattern;
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uint32_t irq_handle;
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uint32_t err_irq_handle;
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uint32_t discard_irq_handle;
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@@ -295,14 +289,11 @@ struct cam_ife_csid_ver2_rdi_reg_info {
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uint32_t byte_cntr_en_shift_val;
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uint32_t offline_mode_en_shift_val;
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uint32_t debug_byte_cntr_rst_shift_val;
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uint32_t stripe_loc_shift_val;
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uint32_t pix_pattern_shift_val;
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uint32_t ccif_violation_en;
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uint32_t overflow_ctrl_mode_val;
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uint32_t overflow_ctrl_en;
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uint32_t fatal_err_mask;
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uint32_t non_fatal_err_mask;
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uint32_t pix_pattern_shift;
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uint32_t camif_irq_mask;
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uint32_t rup_aup_mask;
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uint32_t top_irq_mask;
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@@ -410,8 +401,6 @@ struct cam_ife_csid_ver2_pxl_reg_info {
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uint32_t bin_pd_detect_x_end_shift_val;
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uint32_t bin_pd_detect_y_offset_shift_val;
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uint32_t bin_pd_detect_y_end_shift_val;
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uint32_t stripe_loc_shift_val;
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uint32_t pix_pattern_shift_val;
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uint32_t epoch0_cfg_val;
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uint32_t epoch1_cfg_val;
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uint32_t epoch0_shift_val;
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@@ -473,8 +462,6 @@ struct cam_ife_csid_ver2_common_reg_info {
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uint32_t num_padding_rows_shift_val;
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uint32_t num_vbi_lines_shift_val;
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uint32_t num_hbi_cycles_shift_val;
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uint32_t camif_stripe_loc_shift_val;
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uint32_t camif_pix_pattern_shift_val;
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uint32_t epoch0_line_shift_val;
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uint32_t epoch1_line_shift_val;
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uint32_t camif_width_shift_val;
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