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Merge "disp: pll: limit clock rate of shadow VCO clock"

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qctecmdr
2019-07-26 06:42:29 -07:00
committed by Gerrit - the friendly Code Review server
parent abb4577e29 80d06ebb7c
commit 91edc96425
1 changed files with 4 additions and 0 deletions
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4
pll/dsi_pll_7nm.c
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@@ -2404,6 +2404,8 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev,
if (dsi_pll_7nm_is_hw_revision_v4_1(pll_res)) { if (dsi_pll_7nm_is_hw_revision_v4_1(pll_res)) {
dsi0pll_vco_clk.min_rate = 600000000; dsi0pll_vco_clk.min_rate = 600000000;
dsi0pll_vco_clk.max_rate = 5000000000; dsi0pll_vco_clk.max_rate = 5000000000;
dsi0pll_shadow_vco_clk.min_rate = 600000000;
dsi0pll_shadow_vco_clk.max_rate = 5000000000;
} }
for (i = VCO_CLK_0; i <= SHADOW_PCLK_SRC_0_CLK; i++) { for (i = VCO_CLK_0; i <= SHADOW_PCLK_SRC_0_CLK; i++) {
@@ -2456,6 +2458,8 @@ int dsi_pll_clock_register_7nm(struct platform_device *pdev,
if (dsi_pll_7nm_is_hw_revision_v4_1(pll_res)) { if (dsi_pll_7nm_is_hw_revision_v4_1(pll_res)) {
dsi1pll_vco_clk.min_rate = 600000000; dsi1pll_vco_clk.min_rate = 600000000;
dsi1pll_vco_clk.max_rate = 5000000000; dsi1pll_vco_clk.max_rate = 5000000000;
dsi1pll_shadow_vco_clk.min_rate = 600000000;
dsi1pll_shadow_vco_clk.max_rate = 5000000000;
} }
for (i = VCO_CLK_1; i <= SHADOW_PCLK_SRC_1_CLK; i++) { for (i = VCO_CLK_1; i <= SHADOW_PCLK_SRC_1_CLK; i++) {