Add 'qcom/opensource/audio-kernel/' from commit '0ee387dfadf349618494d6f82ec8cec796ebef70'

git-subtree-dir: qcom/opensource/audio-kernel
git-subtree-mainline: 99ab089c55
git-subtree-split: 0ee387dfad
Change-Id:
repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/audio-kernel-ar
tag: AUDIO.LA.9.0.r1-07400-lanai.0

qcom/opensource/audio-kernel/Android.bp

@@ -0,0 +1,43 @@
+headers_src = [
+    "include/uapi/audio/*/**/*.h",
+]
+
+audio_headers_out = [
+    "linux/msm_audio.h",
+    "sound/audio_effects.h",
+    "sound/audio_slimslave.h",
+    "sound/devdep_params.h",
+    "sound/lsm_params.h",
+    "sound/msmcal-hwdep.h",
+    "sound/voice_params.h",
+    "sound/wcd-dsp-glink.h",
+    "linux/msm_audio_calibration.h",
+]
+
+audio_kernel_headers_verbose = "--verbose "
+genrule {
+    name: "qti_generate_audio_kernel_headers",
+    tools: ["headers_install.sh",
+            "unifdef"
+    ],
+    tool_files: [
+         "audio_kernel_headers.py",
+    ],
+    srcs: headers_src,
+    cmd: "python3 -u $(location audio_kernel_headers.py) " +
+        audio_kernel_headers_verbose +
+        "--header_arch arm64 " +
+        "--gen_dir $(genDir) " +
+        "--audio_include_uapi $(locations include/uapi/audio/*/**/*.h) " +
+        "--unifdef $(location unifdef) " +
+        "--headers_install $(location headers_install.sh)",
+    out: audio_headers_out,
+}
+
+cc_library_headers {
+    name: "qti_audio_kernel_uapi",
+    generated_headers: ["qti_generate_audio_kernel_headers"],
+    export_generated_headers: ["qti_generate_audio_kernel_headers"],
+    vendor: true,
+    recovery_available: true
+}

qcom/opensource/audio-kernel/Android.mk

@@ -0,0 +1,575 @@
+# Android makefile for audio kernel modules
+
+LOCAL_PATH := $(call my-dir)
+
+ifeq ($(call is-board-platform-in-list,taro),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_WAIPIO=m
+endif
+
+ifeq ($(call is-board-platform-in-list,kalama),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_KALAMA=m
+endif
+
+ifeq ($(call is-board-platform-in-list,bengal),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_BENGAL=m
+endif
+
+ifeq ($(call is-board-platform-in-list,holi blair),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_HOLI=m
+endif
+
+ifeq ($(call is-board-platform-in-list,pineapple cliffs volcano),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_PINEAPPLE=m
+endif
+
+ifeq ($(call is-board-platform-in-list,volcano),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_VOLCANO=m
+endif
+
+ifeq ($(call is-board-platform-in-list,pitti),true)
+AUDIO_SELECT  := CONFIG_SND_SOC_PITTI=m
+endif
+
+ifeq ($(ENABLE_AUDIO_LEGACY_TECHPACK),true)
+include $(call all-subdir-makefiles)
+LOCAL_PATH := vendor/qcom/opensource/audio-kernel
+endif
+
+# Build/Package only in case of supported target
+ifeq ($(call is-board-platform-in-list,taro kalama bengal pineapple cliffs pitti holi blair gen4 msmnile niobe volcano), true)
+
+# This makefile is only for DLKM
+ifneq ($(findstring vendor,$(LOCAL_PATH)),)
+
+ifneq ($(findstring opensource,$(LOCAL_PATH)),)
+	AUDIO_BLD_DIR := $(abspath .)/vendor/qcom/opensource/audio-kernel
+endif # opensource
+
+include $(AUDIO_BLD_DIR)/EnableBazel.mk
+DLKM_DIR := $(TOP)/device/qcom/common/dlkm
+
+
+###########################################################
+# This is set once per LOCAL_PATH, not per (kernel) module
+KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
+
+# We are actually building audio.ko here, as per the
+# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
+# This means we need to rename the module to <chipset>_audio.ko
+# after audio.ko is built.
+KBUILD_OPTIONS += MODNAME=audio_dlkm
+KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
+KBUILD_OPTIONS += $(AUDIO_SELECT)
+
+ifneq ($(call is-board-platform-in-list, bengal holi blair msmnile gen4),true)
+KBUILD_OPTIONS += KBUILD_EXTRA_SYMBOLS=$(PWD)/$(call intermediates-dir-for,DLKM,msm-ext-disp-module-symvers)/Module.symvers
+endif
+
+ifeq ($(call is-board-platform-in-list, gen4 msmnile),true)
+KBUILD_OPTIONS += CONFIG_SND_SOC_AUTO=y
+ifneq (,$(filter $(TARGET_BOARD_PLATFORM)$(TARGET_BOARD_SUFFIX), gen4_gvm msmnile_gvmq))
+KBUILD_OPTIONS +=CONFIG_SND_SOC_GVM=y
+endif
+endif
+
+AUDIO_SRC_FILES := \
+	$(wildcard $(LOCAL_PATH)/*) \
+	$(wildcard $(LOCAL_PATH)/*/*) \
+	$(wildcard $(LOCAL_PATH)/*/*/*) \
+	$(wildcard $(LOCAL_PATH)/*/*/*/*)
+
+ifneq (,$(filter $(TARGET_BOARD_PLATFORM)$(TARGET_BOARD_SUFFIX), gen4_gvm msmnile_gvmq))
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := stub_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/stub_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### ASOC MACHINE ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := machine_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/spf_machine_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### LPASS-CDC CODEC  ###########################
+else
+########################### dsp ################################
+
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := q6_notifier_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := dsp/q6_notifier_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := spf_core_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := dsp/spf_core_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := audpkt_ion_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := dsp/audpkt_ion_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := gpr_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := ipc/gpr_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := audio_pkt_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := ipc/audio_pkt_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := q6_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := dsp/q6_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := adsp_loader_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := dsp/adsp_loader_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+
+########################### ipc  ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := audio_prm_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := dsp/audio_prm_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := q6_pdr_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := dsp/q6_pdr_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+
+############################ soc ###############################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := pinctrl_lpi_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := soc/pinctrl_lpi_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := swr_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := soc/swr_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := swr_ctrl_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := soc/swr_ctrl_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := snd_event_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := soc/snd_event_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################  ASOC CODEC ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd_core_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd_core_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := mbhc_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/mbhc_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+ifneq ($(call is-board-platform-in-list, bengal holi blair pitti),true)
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := swr_dmic_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/swr_dmic_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+endif
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd9xxx_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd9xxx_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+ifneq ($(call is-board-platform-in-list, bengal holi blair),true)
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := swr_haptics_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/swr_haptics_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+endif
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := stub_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/stub_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### ASOC MACHINE ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := machine_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/machine_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### LPASS-CDC CODEC  ###########################
+ifneq ($(call is-board-platform-in-list, bengal holi blair),true)
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := lpass_cdc_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := lpass_cdc_wsa2_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := lpass_cdc_wsa_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := lpass_cdc_va_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := lpass_cdc_tx_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := lpass_cdc_rx_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+
+ifneq ($(call is-board-platform-in-list, pitti),true)
+########################### WSA884x CODEC  ###########################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wsa884x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wsa884x/wsa884x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+
+########################### WSA883x CODEC  ###########################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wsa883x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wsa883x/wsa883x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+
+########################### WCD937x CODEC  ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd937x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd937x/wcd937x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd937x_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd937x/wcd937x_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### WCD938x CODEC  ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd938x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd938x/wcd938x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd938x_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### WCD939x CODEC  ################################
+endif
+
+ifneq ($(call is-board-platform-in-list, niobe pitti),true)
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd939x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd939x/wcd939x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd939x_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd939x/wcd939x_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd9378_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd9378/wcd9378_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd9378_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+endif
+ifeq ($(call is-board-platform-in-list, pitti),true)
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wsa881x_analog_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wsa881x_analog_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd9378_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd9378/wcd9378_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd9378_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+endif
+###########################################################
+ifeq ($(AUDIO_DLKM_ENABLE), true)
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := hdmi_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/hdmi_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+LOCAL_REQUIRED_MODULES    := msm-ext-disp-module-symvers
+LOCAL_ADDITIONAL_DEPENDENCIES := $(call intermediates-dir-for,DLKM,msm-ext-disp-module-symvers)/Module.symvers
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+endif
+endif
+
+ifeq ($(call is-board-platform-in-list, bengal holi blair),true)
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := bolero_cdc_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/bolero/bolero_cdc_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := va_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/bolero/va_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := tx_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/bolero/tx_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := rx_macro_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/bolero/rx_macro_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wsa881x_analog_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wsa881x_analog_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+########################### WCD937x CODEC  ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd937x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd937x/wcd937x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd937x_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd937x/wcd937x_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+endif
+
+ifeq ($(call is-board-platform-in-list,holi blair),true)
+########################### WCD938x CODEC  ################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd938x_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd938x/wcd938x_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+###########################################################
+include $(CLEAR_VARS)
+LOCAL_SRC_FILES           := $(AUDIO_SRC_FILES)
+LOCAL_MODULE              := wcd938x_slave_dlkm.ko
+LOCAL_MODULE_KBUILD_NAME  := asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
+LOCAL_MODULE_TAGS         := optional
+LOCAL_MODULE_DEBUG_ENABLE := true
+LOCAL_MODULE_PATH         := $(KERNEL_MODULES_OUT)
+include $(DLKM_DIR)/Build_external_kernelmodule.mk
+endif
+##########################################################
+endif # DLKM check
+endif # supported target check
+endif

qcom/opensource/audio-kernel/BUILD.bazel

@@ -0,0 +1,50 @@
+package(
+    default_visibility = [
+        "//visibility:public",
+    ],
+)
+
+load("//build/kernel/kleaf:kernel.bzl", "ddk_headers")
+
+ddk_headers(
+    name = "audio_common_headers",
+    hdrs = glob([
+        "include/asoc/*.h",
+        "include/bindings/*.h",
+        "include/dsp/*.h",
+        "include/ipc/*.h",
+        "include/soc/*.h"
+    ]),
+    includes = ["include"]
+)
+ddk_headers(
+    name = "audio_uapi_headers",
+    hdrs = glob([
+        "include/uapi/audio/**/*.h"
+    ]),
+    includes = ["include/uapi/audio"]
+)
+ddk_headers(
+    name = "audio_src_headers",
+    hdrs = glob([
+        "asoc/**/*.h",
+        "dsp/**/*.h",
+        "ipc/**/*.h",
+        "soc/**/*.h"
+    ])
+)
+ddk_headers(
+    name = "audio_configs",
+    hdrs = glob([
+        "config/*.h"
+    ]),
+    includes = ["config"]
+)
+ddk_headers(
+    name = "audio_headers",
+    hdrs = [":audio_common_headers",  ":audio_uapi_headers", ":audio_src_headers", ":audio_configs"]
+)
+
+load(":build/audio_target.bzl", "define_audio_target")
+
+define_audio_target()

qcom/opensource/audio-kernel/EnableBazel.mk

@@ -0,0 +1,153 @@
+ifeq ($(call is-board-platform-in-list,pineapple cliffs volcano),true)
+LOCAL_MODULE_DDK_BUILD := true
+
+LOCAL_MODULE_DDK_SUBTARGET_REGEX := "$(TARGET_BOARD_PLATFORM)_audio.*"
+
+LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_dmic_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_haptics_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa884x/wsa884x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa883x/wsa883x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd939x/wcd939x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd939x/wcd939x_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
+endif
+
+ifeq ($(call is-board-platform-in-list,pitti),true)
+LOCAL_MODULE_DDK_BUILD := true
+
+LOCAL_MODULE_DDK_SUBTARGET_REGEX := "audio.*"
+
+LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_haptics_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa881x_analog_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9378/wcd9378_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
+endif
+
+ifeq ($(call is-board-platform-in-list,blair),true)
+LOCAL_MODULE_DDK_BUILD := true
+
+LOCAL_MODULE_DDK_SUBTARGET_REGEX := "audio.*"
+
+LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/bolero/bolero_cdc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/bolero/va_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/bolero/tx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/bolero/rx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa881x_analog_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
+endif
+
+ifeq ($(call is-board-platform-in-list, niobe),true)
+LOCAL_MODULE_DDK_BUILD := true
+
+LOCAL_MODULE_DDK_SUBTARGET_REGEX := "audio.*"
+
+LOCAL_MODULE_KO_DIRS := dsp/q6_notifier_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/spf_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audpkt_ion_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/gpr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += ipc/audio_pkt_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/adsp_loader_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/audio_prm_dlkm.ko
+LOCAL_MODULE_KO_DIRS += dsp/q6_pdr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/pinctrl_lpi_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/swr_ctrl_dlkm.ko
+LOCAL_MODULE_KO_DIRS += soc/snd_event_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd_core_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/mbhc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_dmic_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd9xxx_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/swr_haptics_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/stub_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/machine_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa2_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_wsa_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_va_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_tx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/lpass-cdc/lpass_cdc_rx_macro_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa884x/wsa884x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wsa883x/wsa883x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd937x/wcd937x_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/wcd938x/wcd938x_slave_dlkm.ko
+LOCAL_MODULE_KO_DIRS += asoc/codecs/hdmi_dlkm.ko
+endif

qcom/opensource/audio-kernel/Kbuild

@@ -0,0 +1 @@
+obj-y := dsp/ ipc/ soc/ asoc/ asoc/codecs/ asoc/codecs/lpass-cdc/ asoc/codecs/bolero/ asoc/codecs/wcd939x/ asoc/codecs/wsa884x/ asoc/codecs/wcd938x/ asoc/codecs/wsa883x/ asoc/codecs/wcd937x/ asoc/codecs/wcd9378/

qcom/opensource/audio-kernel/Makefile

@@ -0,0 +1,25 @@
+ifeq ($(TARGET_SUPPORT), monaco)
+KBUILD_OPTIONS := CONFIG_SND_SOC_AUTO=y
+KBUILD_OPTIONS += CONFIG_SND_SOC_SA7255=m
+KBUILD_OPTIONS += MODNAME=audio_dlkm
+endif
+
+ifeq ($(AUTO_GVM), yes)
+KBUILD_OPTIONS += CONFIG_SND_SOC_AUTO=y
+KBUILD_OPTIONS += CONFIG_SND_SOC_GVM=y
+KBUILD_OPTIONS += MODNAME=audio_dlkm
+endif
+
+M=$(PWD)
+AUDIO_ROOT=$(KERNEL_SRC)/$(M)
+
+KBUILD_OPTIONS+=  AUDIO_ROOT=$(AUDIO_ROOT)
+
+all: modules
+
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
+
+%:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
+

qcom/opensource/audio-kernel/Makefile.am

@@ -0,0 +1,96 @@
+AUDIO_ROOT=$(PWD)
+UAPI_OUT=$(PWD)
+HEADER_INSTALL_DIR=$(KERNEL_SRC)/scripts
+KERNEL_BINARY_DIR=$(KERNEL_SRC)/../kernel-build-artifacts
+
+KBUILD_OPTIONS := AUDIO_ROOT=$(PWD)
+KBUILD_OPTIONS += MODNAME=audio
+KBUILD_OPTIONS += UAPI_OUT=$(PWD)
+
+AUDIO_KERNEL_HEADERS_PATH1 =  $(shell ls ./include/uapi/audio/linux/*.h)
+AUDIO_KERNEL_HEADERS_PATH2 =  $(shell ls ./include/uapi/audio/linux/mfd/wcd9xxx/*.h)
+AUDIO_KERNEL_HEADERS_PATH3 =  $(shell ls ./include/uapi/audio/sound/*.h)
+
+ifeq ($(TARGET_SUPPORT),qcs40x)
+KBUILD_OPTIONS += CONFIG_ARCH_QCS405=y
+endif
+ifeq ($(TARGET_SUPPORT), sdmsteppe)
+KBUILD_OPTIONS += CONFIG_ARCH_SM6150=y
+endif
+ifeq ($(TARGET_SUPPORT), sdxlemur))
+KBUILD_OPTIONS += CONFIG_ARCH_SDXLEMUR=y
+endif
+
+subdir-ccflags-y += -I$(AUDIO_ROOT)/include/uapi/
+
+subdir-ccflags-y += -I$(AUDIO_ROOT)/include/uapi/
+
+obj-m := ipc/
+obj-m += dsp/
+obj-m += soc/
+obj-m += asoc/
+obj-m += asoc/codecs/
+ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sdmsteppe sdxlemur))
+obj-m += asoc/codecs/wcd934x/
+endif
+ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qcs40x))
+obj-m += asoc/codecs/bolero/
+obj-m += asoc/codecs/csra66x0/
+obj-m += asoc/codecs/ep92/
+endif
+ifeq ($(TARGET_SUPPORT), sdmsteppe)
+obj-m += asoc/codecs/bolero/
+obj-m += asoc/codecs/wcd937x/
+endif
+
+ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sa8155 sa8155ivi sa6155 sa8195 qtiquingvm))
+KBUILD_OPTIONS += CONFIG_SND_SOC_AUTO=y
+obj-m := ipc/
+obj-m += dsp/
+obj-m += asoc/
+obj-m += asoc/codecs/
+obj-m += soc/
+ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sa8155 sa8155ivi sa8195 qtiquingvm))
+KBUILD_OPTIONS += CONFIG_SND_SOC_SA8155=m
+endif
+ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sa6155))
+KBUILD_OPTIONS += CONFIG_SND_SOC_SA6155=m
+endif
+endif
+
+define PROCESS_HEADERS
+	$(foreach name,$(1),$(shell cd $(KERNEL_BINARY_DIR) && $(KERNEL_SRC)/scripts/headers_install.sh $(2)$(name) $(3)$(name)))
+endef
+
+all:
+	$(shell rm -fr $(shell pwd)/soc/core.h)
+	$(shell ln -s $(KERNEL_SRC)/drivers/pinctrl/core.h $(shell pwd)/soc/core.h)
+	$(shell rm -fr $(shell pwd)/include/soc/internal.h)
+	$(shell ln -s $(KERNEL_SRC)/drivers/base/regmap/internal.h $(shell pwd)/include/soc/internal.h)
+	$(shell rm -fr $(shell pwd)/soc/pinctrl-utils.h)
+	$(shell ln -s $(KERNEL_SRC)/drivers/pinctrl/pinctrl-utils.h $(shell pwd)/soc/pinctrl-utils.h)
+	$(shell rm -fr $(shell pwd)/include/soc/qcom/secure_buffer.h)
+	$(shell ln -s $(KERNEL_SRC)/include/soc/qcom/secure_buffer.h $(shell pwd)/include/soc/qcom/secure_buffer.h)
+	$(shell mkdir $(shell pwd)/linux)
+	$(shell mkdir $(shell pwd)/sound)
+	$(shell mkdir $(shell pwd)/linux/mfd)
+	$(shell mkdir $(shell pwd)/linux/mfd/wcd9xxx)
+	$(call PROCESS_HEADERS, $(notdir $(shell ls $(AUDIO_ROOT)/include/uapi/audio/linux/*.h)), $(AUDIO_ROOT)/include/uapi/audio/linux/, $(UAPI_OUT)/linux/)
+	$(call PROCESS_HEADERS, $(notdir $(shell ls $(AUDIO_ROOT)/include/uapi/audio/linux/mfd/wcd9xxx/*.h)), $(AUDIO_ROOT)/include/uapi/audio/linux/mfd/wcd9xxx/, $(UAPI_OUT)/linux/mfd/wcd9xxx/)
+	$(call PROCESS_HEADERS, $(notdir $(shell ls $(AUDIO_ROOT)/include/uapi/audio/sound/*.h)), $(AUDIO_ROOT)/include/uapi/audio/sound/, $(UAPI_OUT)/sound/)
+	$(shell mkdir $(KERNEL_BINARY_DIR)/usr/include/audio)
+	$(shell mkdir $(KERNEL_BINARY_DIR)/usr/include/audio/sound)
+	$(shell mkdir $(KERNEL_BINARY_DIR)/usr/include/audio/linux)
+	$(shell mkdir $(KERNEL_BINARY_DIR)/usr/include/audio/linux/mfd)
+	$(shell mkdir $(KERNEL_BINARY_DIR)/usr/include/audio/linux/mfd/wcd9xxx)
+	$(call PROCESS_HEADERS, $(notdir $(shell ls $(AUDIO_ROOT)/include/uapi/audio/linux/*.h)), $(AUDIO_ROOT)/include/uapi/audio/linux/, $(KERNEL_BINARY_DIR)/usr/include/audio/linux/)
+	$(call PROCESS_HEADERS, $(notdir $(shell ls $(AUDIO_ROOT)/include/uapi/audio/linux/mfd/wcd9xxx/*.h)), $(AUDIO_ROOT)/include/uapi/audio/linux/mfd/wcd9xxx/, $(KERNEL_BINARY_DIR)/usr/include/audio/linux/mfd/wcd9xxx/)
+	$(call PROCESS_HEADERS, $(notdir $(shell ls $(AUDIO_ROOT)/include/uapi/audio/sound/*.h)), $(AUDIO_ROOT)/include/uapi/audio/sound/, $(KERNEL_BINARY_DIR)/usr/include/audio/sound/)
+	$(MAKE) -C $(KERNEL_SRC) M=$(shell pwd) modules $(KBUILD_OPTIONS)
+
+modules_install:
+	$(MAKE) INSTALL_MOD_STRIP=1 -C $(KERNEL_SRC) M=$(shell pwd) modules_install
+
+clean:
+	rm -f *.o *.ko *.mod.c *.mod.o *~ .*.cmd Module.symvers
+	rm -rf .tmp_versions

qcom/opensource/audio-kernel/NOTICE

@@ -0,0 +1,24 @@
+Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License version 2 and
+only version 2 as published by the Free Software Foundation.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+________________________________________
+
+Copyright (C) 2008 Google, Inc.
+Copyright (C) 2008 HTC Corporation
+Copyright (c) 2010-2017, The Linux Foundation. All rights reserved.
+
+This software is licensed under the terms of the GNU General Public
+License version 2, as published by the Free Software Foundation, and
+may be copied, distributed, and modified under those terms.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.

qcom/opensource/audio-kernel/asoc/Kbuild

@@ -0,0 +1,347 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(CONFIG_SND_SOC_AUTO), y)
+	ifdef CONFIG_SND_SOC_SA8155
+		include $(AUDIO_ROOT)/config/sa8155auto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/sa8155autoconf.h
+	endif
+	ifdef CONFIG_SND_SOC_SA6155
+		include $(AUDIO_ROOT)/config/sa6155auto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/sa6155autoconf.h
+	endif
+	ifdef CONFIG_SND_SOC_GVM
+	    include $(AUDIO_ROOT)/config/gvmauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/gvmautoconf.h
+	endif
+	ifdef CONFIG_SND_SOC_SA7255
+		include $(AUDIO_ROOT)/config/sa7255auto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/sa7255autoconf.h
+	endif
+
+else
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_SM8150), y)
+		ifdef CONFIG_SND_SOC_SA8155
+			include $(AUDIO_ROOT)/config/sa8155auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sa8155autoconf.h
+		else
+			include $(AUDIO_ROOT)/config/sm8150auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sm8150autoconf.h
+		endif
+	endif
+	ifeq ($(CONFIG_ARCH_SM6150), y)
+		ifdef CONFIG_SND_SOC_SA6155
+			include $(AUDIO_ROOT)/config/sa6155auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sa6155autoconf.h
+		else
+			include $(AUDIO_ROOT)/config/sm6150auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+		endif
+	endif
+	ifeq ($(CONFIG_ARCH_TRINKET), y)
+		include $(AUDIO_ROOT)/config/sm6150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KONA), y)
+		include $(AUDIO_ROOT)/config/konaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/konaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_WAIPIO), y)
+		include $(AUDIO_ROOT)/config/waipioauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/waipioautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KALAMA), y)
+		include $(AUDIO_ROOT)/config/kalamaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/kalamaautoconf.h
+	endif
+	ifeq ($(BOARD_PLATFORM), pineapple)
+		include $(AUDIO_ROOT)/config/pineappleauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
+	endif
+	ifeq ($(BOARD_PLATFORM), cliffs)
+		include $(AUDIO_ROOT)/config/pineappleauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
+	endif
+	ifeq ($(BOARD_PLATFORM), volcano)
+		include $(AUDIO_ROOT)/config/volcanoauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/volcanoautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PITTI), y)
+		include $(AUDIO_ROOT)/config/pittiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pittiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_LITO), y)
+		include $(AUDIO_ROOT)/config/litoauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/litoautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KHAJE), y)
+		include $(AUDIO_ROOT)/config/bengalauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/bengalautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_HOLI), y)
+		include $(AUDIO_ROOT)/config/holiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/holiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_BLAIR), y)
+		include $(AUDIO_ROOT)/config/holiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/holiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
+		ifdef CONFIG_SND_SOC_SA8155
+			include $(AUDIO_ROOT)/config/sa8155auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sa8155autoconf.h
+		else
+			include $(AUDIO_ROOT)/config/sm8150auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sm8150autoconf.h
+		endif
+	endif
+	ifeq ($(CONFIG_ARCH_QCS405), y)
+		include $(AUDIO_ROOT)/config/qcs405auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/qcs405autoconf.h
+	endif
+	ifeq ($(CONFIG_QTI_QUIN_GVM), y)
+		include $(AUDIO_ROOT)/config/gvmauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/gvmautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_SDXLEMUR), y)
+		include $(AUDIO_ROOT)/config/sdxlemurauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sdxlemurautoconf.h
+	endif
+endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ ASoC Drivers ############
+
+MACHINE_OBJS += msm_common.o
+
+# for SM8150 sound card driver
+ifdef CONFIG_SND_SOC_SM8150
+	MACHINE_OBJS += sm8150.o
+	MACHINE_OBJS += machine_815x_init.o
+endif
+
+# for SM6150 sound card driver
+ifdef CONFIG_SND_SOC_SM6150
+	MACHINE_OBJS += sm6150.o
+	MACHINE_OBJS += machine_615x_init.o
+endif
+
+# For sa6155 sound card driver
+ifdef CONFIG_SND_SOC_SA6155
+	MACHINE_OBJS += sa6155.o
+endif
+
+# for qcs405 sound card driver
+ifdef CONFIG_SND_SOC_QCS405
+	MACHINE_OBJS += qcs405.o
+endif
+
+# for KONA sound card driver
+ifdef CONFIG_SND_SOC_KONA
+	MACHINE_OBJS += kona.o
+endif
+
+# for LAHAINA sound card driver
+ifdef CONFIG_SND_SOC_LAHAINA
+	MACHINE_OBJS += lahaina.o
+endif
+
+# for WAIPIO sound card driver
+ifdef CONFIG_SND_SOC_WAIPIO
+	MACHINE_OBJS += waipio.o
+endif
+
+# for KALAMA sound card driver
+ifdef CONFIG_SND_SOC_KALAMA
+	MACHINE_OBJS += kalama.o
+endif
+
+# for PINEAPPLE sound card driver
+ifdef CONFIG_SND_SOC_PINEAPPLE
+	MACHINE_OBJS += pineapple.o
+endif
+
+# for VOLCANO sound card driver
+ifdef CONFIG_SND_SOC_VOLCANO
+	MACHINE_OBJS += pineapple.o
+endif
+
+# for PITTI sound card driver
+ifdef CONFIG_SND_SOC_PITTI
+	MACHINE_OBJS += pineapple.o
+endif
+
+# for HOLI sound card driver
+ifdef CONFIG_SND_SOC_HOLI
+	MACHINE_OBJS += holi.o
+endif
+
+ifdef CONFIG_SND_SOC_LITO
+	MACHINE_OBJS += kona.o
+endif
+
+# for BENGAL sound card driver
+ifdef CONFIG_SND_SOC_BENGAL
+	MACHINE_OBJS += bengal.o
+endif
+
+# for sa8155 sound card driver
+ifdef CONFIG_SND_SOC_SA8155
+	MACHINE_OBJS += sa8155.o
+endif
+
+# for sa7255 sound card driver
+ifdef CONFIG_SND_SOC_SA7255_AUTO_SPF
+    SPF_MACHINE_OBJS += msm_common.o
+    SPF_MACHINE_OBJS += auto_spf_dummy.o
+endif
+
+ifdef CONFIG_SND_SOC_QDSP6V2
+	PLATFORM_OBJS += platform_init.o
+endif
+
+ifdef CONFIG_SND_SOC_SDX
+	MACHINE_OBJS += sdx-target.o
+endif
+
+ifdef CONFIG_SND_SOC_GVM_AUTO_SPF
+    SPF_MACHINE_OBJS += gvm_auto_spf_dummy.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+EXTRA_CFLAGS += $(INCS)
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 1)
+	obj-y += codecs/
+endif
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_QDSP6V2) += platform_dlkm.o
+platform_dlkm-y := $(PLATFORM_OBJS)
+
+obj-$(CONFIG_SND_SOC_SM8150) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_SM6150) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_SA6155) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_QCS405) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_KONA) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_LAHAINA) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_WAIPIO) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_KALAMA) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_PINEAPPLE) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_VOLCANO) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_PITTI) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_HOLI) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_LITO) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_BENGAL) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_SA8155) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_SDX) += machine_dlkm.o
+machine_dlkm-y := $(MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_GVM_AUTO_SPF) += spf_machine_dlkm.o
+spf_machine_dlkm-y := $(SPF_MACHINE_OBJS)
+
+obj-$(CONFIG_SND_SOC_SA7255_AUTO_SPF) += spf_machine_dlkm.o
+spf_machine_dlkm-y := $(SPF_MACHINE_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/Makefile

@@ -0,0 +1,6 @@
+modules:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

qcom/opensource/audio-kernel/asoc/bengal-port-config.h

@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _BENGAL_PORT_CONFIG
+#define _BENGAL_PORT_CONFIG
+
+#include <soc/swr-common.h>
+
+/*
+ * Add port configuration in the format
+ *{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl}
+ */
+
+static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
+	{3,  0,  0,  0xFF, 0xFF, 1,    0xFF, 0xFF, 1},
+	{31, 0,  0,  3,    6,    7,    0,    0xFF, 0},
+	{31, 11, 11, 0xFF, 0xFF, 4,    1,    0xFF, 0},
+	{7,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0},
+	{0,  0,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0,    0},
+};
+
+static struct port_params rx_frame_params_rouleur[SWR_MSTR_PORT_LEN] = {
+	{3,  0,  0,  0xFF, 0xFF, 1,    0xFF, 0xFF, 1},
+	{31, 0,  0,  3,    6,    7,    0,    0xFF, 0},
+	{31, 1,  0,  0xFF, 0xFF, 4,    1,    0xFF, 0},
+	{7,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0},
+	{0,  0,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0,    0},
+};
+
+
+static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
+	{3,  0,  0,  0xFF, 0xFF, 1,    0xFF, 0xFF, 1},
+	{31, 0,  0,  3,    6,    7,    0,    0xFF, 0},
+	{31, 11, 11, 0xFF, 0xFF, 4,    1,    0xFF, 0},
+	{7,  9,  0,  0xFF, 0xFF, 0xFF, 0xFF, 1,    0},
+	{3,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 3,    0},
+};
+
+/* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
+static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = {
+	{3,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0},  /* TX1 */
+	{3,  2,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0},  /* TX2 */
+	{3,  1,  0,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0},  /* TX3 */
+};
+
+static struct swr_mstr_port_map sm_port_map[] = {
+	{VA_MACRO, SWR_UC0, tx_frame_params_default},
+	{RX_MACRO, SWR_UC0, rx_frame_params_default},
+	{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
+};
+
+static struct swr_mstr_port_map sm_port_map_rouleur[] = {
+	{VA_MACRO, SWR_UC0, tx_frame_params_default},
+	{RX_MACRO, SWR_UC0, rx_frame_params_rouleur},
+	{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
+};
+#endif /* _BENGAL_PORT_CONFIG */

qcom/opensource/audio-kernel/asoc/codecs/Kbuild

@@ -0,0 +1,330 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(CONFIG_SND_SOC_AUTO), y)
+	ifdef CONFIG_SND_SOC_SA8155
+		include $(AUDIO_ROOT)/config/sa8155auto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/sa8155autoconf.h
+	endif
+	ifdef CONFIG_SND_SOC_SA6155
+		include $(AUDIO_ROOT)/config/sa6155auto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/sa6155autoconf.h
+	endif
+	ifdef CONFIG_SND_SOC_GVM
+		include $(AUDIO_ROOT)/config/gvmauto.conf
+        INCS    +=  -include $(AUDIO_ROOT)/config/gvmautoconf.h
+	endif
+	ifdef CONFIG_SND_SOC_SA7255
+		include $(AUDIO_ROOT)/config/sa7255auto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/sa7255autoconf.h
+	endif
+else
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_SM8150), y)
+		ifdef CONFIG_SND_SOC_SA8155
+			include $(AUDIO_ROOT)/config/sa8155auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sa8155autoconf.h
+		else
+			include $(AUDIO_ROOT)/config/sm8150auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sm8150autoconf.h
+		endif
+	endif
+	ifeq ($(CONFIG_ARCH_SM6150), y)
+		ifdef CONFIG_SND_SOC_SA6155
+			include $(AUDIO_ROOT)/config/sa6155auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sa6155autoconf.h
+		else
+			include $(AUDIO_ROOT)/config/sm6150auto.conf
+			INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+		endif
+	endif
+	ifeq ($(CONFIG_ARCH_TRINKET), y)
+		include $(AUDIO_ROOT)/config/sm6150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KONA), y)
+		include $(AUDIO_ROOT)/config/konaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/konaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_WAIPIO), y)
+		include $(AUDIO_ROOT)/config/waipioauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/waipioautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KALAMA), y)
+		include $(AUDIO_ROOT)/config/kalamaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/kalamaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
+		include $(AUDIO_ROOT)/config/pineappleauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PITTI), y)
+		include $(AUDIO_ROOT)/config/pittiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pittiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_LITO), y)
+		include $(AUDIO_ROOT)/config/litoauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/litoautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KHAJE), y)
+		include $(AUDIO_ROOT)/config/bengalauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/bengalautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_HOLI), y)
+		include $(AUDIO_ROOT)/config/holiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/holiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_BLAIR), y)
+		include $(AUDIO_ROOT)/config/holiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/holiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
+		include $(AUDIO_ROOT)/config/sm8150auto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm8150autoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_QCS405), y)
+		include $(AUDIO_ROOT)/config/qcs405auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/qcs405autoconf.h
+	endif
+	ifeq ($(CONFIG_QTI_QUIN_GVM), y)
+		include $(AUDIO_ROOT)/config/gvmauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/gvmautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_SDXLEMUR), y)
+		include $(AUDIO_ROOT)/config/sdxlemurauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sdxlemurautoconf.h
+	endif
+endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ ASoC Codecs ############
+ifdef CONFIG_WCD9XXX_CODEC_CORE
+	CORE_OBJS += wcd9xxx-rst.o
+	CORE_OBJS += wcd9xxx-core-init.o
+	CORE_OBJS += wcd9xxx-core.o
+	CORE_OBJS += wcd9xxx-irq.o
+	CORE_OBJS += wcd9xxx-slimslave.o
+	CORE_OBJS += wcd9xxx-utils.o
+	CORE_OBJS += wcd9335-regmap.o
+	CORE_OBJS += wcd9335-tables.o
+	CORE_OBJS += msm-cdc-pinctrl.o
+	CORE_OBJS += msm-cdc-supply.o
+	CORE_OBJS += wcd934x/wcd934x-regmap.o
+	CORE_OBJS += wcd934x/wcd934x-tables.o
+endif
+
+ifdef CONFIG_WCD9XXX_CODEC_CORE_V2
+	CORE_OBJS += wcd9xxx-core-init.o
+	CORE_OBJS += msm-cdc-pinctrl.o
+	CORE_OBJS += msm-cdc-supply.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD9XXX_V2
+ifdef CONFIG_WCD9XXX_CODEC_CORE
+	WCD9XXX_OBJS += wcd9xxx-common-v2.o
+	WCD9XXX_OBJS += wcd9xxx-resmgr-v2.o
+	WCD9XXX_OBJS += wcd-dsp-utils.o
+	WCD9XXX_OBJS += wcd-dsp-mgr.o
+else
+	WCD9XXX_OBJS += wcd-clsh.o
+endif
+	WCD9XXX_OBJS += wcdcal-hwdep.o
+	WCD9XXX_OBJS += wcd9xxx-soc-init.o
+	WCD9XXX_OBJS += audio-ext-clk-up.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD9335
+	WCD9335_OBJS += wcd9335.o
+endif
+
+ifdef CONFIG_SND_SOC_WSA881X
+	WSA881X_OBJS += wsa881x.o
+	WSA881X_OBJS += wsa881x-tables.o
+	WSA881X_OBJS += wsa881x-regmap.o
+	WSA881X_OBJS += wsa881x-temp-sensor.o
+endif
+
+ifdef CONFIG_SND_SOC_SWR_DMIC
+       SWR_DMIC_OBJS += swr-dmic.o
+endif
+
+ifdef CONFIG_SND_SOC_WSA881X_ANALOG
+	INCS += -include $(KERNEL_SRC)/drivers/base/regmap/internal.h
+	WSA881X_ANALOG_OBJS += wsa881x-analog.o
+	WSA881X_ANALOG_OBJS += wsa881x-tables-analog.o
+	WSA881X_ANALOG_OBJS += wsa881x-regmap-analog.o
+ifndef CONFIG_WSA881X_TEMP_SENSOR_DISABLE
+	WSA881X_ANALOG_OBJS += wsa881x-temp-sensor.o
+endif
+endif
+ifdef CONFIG_SND_SOC_MSM_STUB
+	STUB_OBJS += msm_stub.o
+endif
+ifdef CONFIG_SND_SOC_WCD_SPI
+	SPI_OBJS += wcd-spi.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD_CPE
+	WCD_CPE_OBJS += wcd_cpe_core.o
+	WCD_CPE_OBJS += wcd_cpe_services.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD_MBHC
+	MBHC_OBJS += wcd-mbhc-v2.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD_MBHC_ADC
+	MBHC_OBJS += wcd-mbhc-adc.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD_MBHC_LEGACY
+	MBHC_OBJS += wcd-mbhc-legacy.o
+endif
+
+ifdef CONFIG_SND_SOC_MSM_HDMI_CODEC_RX
+	HDMICODEC_OBJS += msm_hdmi_codec_rx.o
+endif
+
+ifdef CONFIG_SND_SOC_WCD_IRQ
+	CORE_OBJS += wcd-irq.o
+endif
+
+ifdef CONFIG_SND_SWR_HAPTICS
+	SWR_HAP_OBJS += swr-haptics.o
+endif
+
+ifdef CONFIG_LPASS_BT_SWR
+	LPASS_BT_SWR_OBJS += lpass-bt-swr.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+
+EXTRA_CFLAGS += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 1)
+	obj-y	+= wcd934x/
+	obj-y	+= wcd937x/
+	obj-y	+= wcd938x/
+	obj-y	+= wcd939x/
+	obj-y	+= wcd9378/
+	obj-y	+= bolero/
+	obj-y	+= lpass-cdc/
+	obj-y	+= wsa884x/
+	obj-y	+= wsa883x/
+	obj-y	+= rouleur/
+	obj-y	+= ./
+endif
+# Module information used by KBuild framework
+obj-$(CONFIG_WCD9XXX_CODEC_CORE) += wcd_core_dlkm.o
+obj-$(CONFIG_WCD9XXX_CODEC_CORE_V2) += wcd_core_dlkm.o
+wcd_core_dlkm-y := $(CORE_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD9XXX_V2) += wcd9xxx_dlkm.o
+wcd9xxx_dlkm-y := $(WCD9XXX_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD9335) += wcd9335_dlkm.o
+wcd9335_dlkm-y := $(WCD9335_OBJS)
+
+obj-$(CONFIG_SND_SOC_WSA881X) += wsa881x_dlkm.o
+wsa881x_dlkm-y := $(WSA881X_OBJS)
+
+obj-$(CONFIG_SND_SOC_SWR_DMIC) += swr_dmic_dlkm.o
+swr_dmic_dlkm-y := $(SWR_DMIC_OBJS)
+
+obj-$(CONFIG_SND_SOC_WSA881X_ANALOG) += wsa881x_analog_dlkm.o
+wsa881x_analog_dlkm-y := $(WSA881X_ANALOG_OBJS)
+
+obj-$(CONFIG_SND_SOC_MSM_STUB) += stub_dlkm.o
+stub_dlkm-y := $(STUB_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD_CPE) += wcd_cpe_dlkm.o
+wcd_cpe_dlkm-y := $(WCD_CPE_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD_SPI) += wcd_spi_dlkm.o
+wcd_spi_dlkm-y := $(SPI_OBJS)
+
+obj-$(CONFIG_SND_SOC_WCD_MBHC) += mbhc_dlkm.o
+mbhc_dlkm-y := $(MBHC_OBJS)
+
+obj-$(CONFIG_SND_SOC_MSM_HDMI_CODEC_RX) += hdmi_dlkm.o
+hdmi_dlkm-y := $(HDMICODEC_OBJS)
+
+obj-$(CONFIG_SND_SWR_HAPTICS) += swr_haptics_dlkm.o
+swr_haptics_dlkm-y := $(SWR_HAP_OBJS)
+
+obj-$(CONFIG_LPASS_BT_SWR) += lpass_bt_swr_dlkm.o
+lpass_bt_swr_dlkm-y := $(LPASS_BT_SWR_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/codecs/Makefile

@@ -0,0 +1,6 @@
+modules:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/Kbuild

@@ -0,0 +1,120 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+
+	ifeq ($(CONFIG_ARCH_SDM670), y)
+		include $(AUDIO_ROOT)/config/sdm670auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sdm670autoconf.h
+	endif
+
+	ifeq ($(CONFIG_ARCH_SM8150), y)
+		include $(AUDIO_ROOT)/config/sm8150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm8150autoconf.h
+	endif
+
+	ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
+		include $(AUDIO_ROOT)/config/sm8150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm8150autoconf.h
+	endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+# for AQT1000 Codec
+ifeq ($(CONFIG_SND_SOC_AQT1000), m)
+	AQT1000_CDC_OBJS += aqt1000-regmap.o
+	AQT1000_CDC_OBJS += aqt1000-utils.o
+	AQT1000_CDC_OBJS += aqt1000-core.o
+	AQT1000_CDC_OBJS += aqt1000-irq.o
+	AQT1000_CDC_OBJS += aqt1000-clsh.o
+	AQT1000_CDC_OBJS += aqt1000.o
+	AQT1000_CDC_OBJS += aqt1000-mbhc.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=	$(COMMON_INC) \
+	$(UAPI_INC)
+
+EXTRA_CFLAGS += $(INCS)
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/aqt1000/Module.symvers
+endif
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_AQT1000) += aqt1000_cdc_dlkm.o
+aqt1000_cdc_dlkm-y := $(AQT1000_CDC_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-api.h

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef AQT1000_API_H
+#define AQT1000_API_H
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <sound/soc.h>
+
+extern int aqt_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
+					int volt, int micb_num);
+extern int aqt_cdc_mclk_enable(struct snd_soc_component *component,
+			       bool enable);
+extern int aqt_get_micb_vout_ctl_val(u32 micb_mv);
+extern int aqt_micbias_control(struct snd_soc_component *component,
+			       int micb_num, int req, bool is_dapm);
+
+#endif /* AQT1000_API_H */

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-clsh.c

@@ -0,0 +1,833 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <sound/soc.h>
+#include "aqt1000-registers.h"
+#include "aqt1000-clsh.h"
+
+#define AQT_USLEEP_RANGE 50
+#define MAX_IMPED_PARAMS 6
+
+enum aqt_vref_dac_sel {
+	VREF_N1P9V = 0,
+	VREF_N1P86V,
+	VREF_N181V,
+	VREF_N1P74V,
+	VREF_N1P7V,
+	VREF_N0P9V,
+	VREF_N1P576V,
+	VREF_N1P827V,
+};
+
+enum aqt_vref_ctl {
+	CONTROLLER = 0,
+	I2C,
+};
+
+enum aqt_hd2_res_div_ctl {
+	DISCONNECT = 0,
+	P5_0P35,
+	P75_0P68,
+	P82_0P77,
+	P9_0P87,
+};
+
+enum aqt_curr_bias_err_amp {
+	I_0P25UA = 0,
+	I_0P5UA,
+	I_0P75UA,
+	I_1UA,
+	I_1P25UA,
+	I_1P5UA,
+	I_1P75UA,
+	I_2UA,
+};
+
+static const struct aqt_reg_mask_val imped_table_aqt[][MAX_IMPED_PARAMS] = {
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf2},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf2},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf2},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf2},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf4},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf4},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf4},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf4},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf7},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf7},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x01},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf7},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf7},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x01},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xf9},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xf9},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xf9},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xf9},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfa},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfa},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfa},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfa},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfb},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfb},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfb},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfb},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfc},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfc},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfc},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfc},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x00},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x00},
+	},
+	{
+		{AQT1000_CDC_RX1_RX_VOL_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX1_RX_VOL_MIX_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX1_RX_PATH_SEC1, 0x01, 0x01},
+		{AQT1000_CDC_RX2_RX_VOL_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX2_RX_VOL_MIX_CTL, 0xff, 0xfd},
+		{AQT1000_CDC_RX2_RX_PATH_SEC1, 0x01, 0x01},
+	},
+};
+
+static const struct aqt_imped_val imped_index[] = {
+	{4, 0},
+	{5, 1},
+	{6, 2},
+	{7, 3},
+	{8, 4},
+	{9, 5},
+	{10, 6},
+	{11, 7},
+	{12, 8},
+	{13, 9},
+};
+
+static void (*clsh_state_fp[NUM_CLSH_STATES])(struct snd_soc_component *,
+					      struct aqt_clsh_cdc_data *,
+					      u8 req_state, bool en, int mode);
+
+static int get_impedance_index(int imped)
+{
+	int i = 0;
+
+	if (imped < imped_index[i].imped_val) {
+		pr_debug("%s, detected impedance is less than 4 Ohm\n",
+				__func__);
+		i = 0;
+		goto ret;
+	}
+	if (imped >= imped_index[ARRAY_SIZE(imped_index) - 1].imped_val) {
+		pr_debug("%s, detected impedance is greater than 12 Ohm\n",
+				__func__);
+		i = ARRAY_SIZE(imped_index) - 1;
+		goto ret;
+	}
+	for (i = 0; i < ARRAY_SIZE(imped_index) - 1; i++) {
+		if (imped >= imped_index[i].imped_val &&
+			imped < imped_index[i + 1].imped_val)
+			break;
+	}
+ret:
+	pr_debug("%s: selected impedance index = %d\n",
+			__func__, imped_index[i].index);
+	return imped_index[i].index;
+}
+
+/*
+ * Function: aqt_clsh_imped_config
+ * Params: component, imped, reset
+ * Description:
+ * This function updates HPHL and HPHR gain settings
+ * according to the impedance value.
+ */
+void aqt_clsh_imped_config(struct snd_soc_component *component,
+			   int imped, bool reset)
+{
+	int i;
+	int index = 0;
+	int table_size;
+
+	static const struct aqt_reg_mask_val
+				(*imped_table_ptr)[MAX_IMPED_PARAMS];
+
+	table_size = ARRAY_SIZE(imped_table_aqt);
+	imped_table_ptr = imped_table_aqt;
+
+	/* reset = 1, which means request is to reset the register values */
+	if (reset) {
+		for (i = 0; i < MAX_IMPED_PARAMS; i++)
+			snd_soc_component_update_bits(component,
+				imped_table_ptr[index][i].reg,
+				imped_table_ptr[index][i].mask, 0);
+		return;
+	}
+	index = get_impedance_index(imped);
+	if (index >= (ARRAY_SIZE(imped_index) - 1)) {
+		pr_debug("%s, impedance not in range = %d\n", __func__, imped);
+		return;
+	}
+	if (index >= table_size) {
+		pr_debug("%s, impedance index not in range = %d\n", __func__,
+			index);
+		return;
+	}
+	for (i = 0; i < MAX_IMPED_PARAMS; i++)
+		snd_soc_component_update_bits(component,
+				imped_table_ptr[index][i].reg,
+				imped_table_ptr[index][i].mask,
+				imped_table_ptr[index][i].val);
+}
+EXPORT_SYMBOL(aqt_clsh_imped_config);
+
+static const char *mode_to_str(int mode)
+{
+	switch (mode) {
+	case CLS_H_NORMAL:
+		return "CLS_H_NORMAL";
+	case CLS_H_HIFI:
+		return "CLS_H_HIFI";
+	case CLS_H_LOHIFI:
+		return "CLS_H_LOHIFI";
+	case CLS_H_LP:
+		return "CLS_H_LP";
+	case CLS_H_ULP:
+		return "CLS_H_ULP";
+	case CLS_AB:
+		return "CLS_AB";
+	case CLS_AB_HIFI:
+		return "CLS_AB_HIFI";
+	default:
+		return "CLS_H_INVALID";
+	};
+}
+
+static const char *const state_to_str[] = {
+	[AQT_CLSH_STATE_IDLE] = "STATE_IDLE",
+	[AQT_CLSH_STATE_HPHL] = "STATE_HPH_L",
+	[AQT_CLSH_STATE_HPHR] = "STATE_HPH_R",
+	[AQT_CLSH_STATE_HPH_ST] = "STATE_HPH_ST",
+};
+
+static inline void
+aqt_enable_clsh_block(struct snd_soc_component *component,
+		      struct aqt_clsh_cdc_data *clsh_d, bool enable)
+{
+	if ((enable && ++clsh_d->clsh_users == 1) ||
+	    (!enable && --clsh_d->clsh_users == 0))
+		snd_soc_component_update_bits(component, AQT1000_CDC_CLSH_CRC,
+				0x01, (u8) enable);
+	if (clsh_d->clsh_users < 0)
+		clsh_d->clsh_users = 0;
+	dev_dbg(component->dev, "%s: clsh_users %d, enable %d", __func__,
+		clsh_d->clsh_users, enable);
+}
+
+static inline bool aqt_clsh_enable_status(struct snd_soc_component *component)
+{
+	return snd_soc_component_read32(
+			component, AQT1000_CDC_CLSH_CRC) & 0x01;
+}
+
+static inline int aqt_clsh_get_int_mode(struct aqt_clsh_cdc_data *clsh_d,
+					int clsh_state)
+{
+	int mode;
+
+	if ((clsh_state != AQT_CLSH_STATE_HPHL) &&
+	    (clsh_state != AQT_CLSH_STATE_HPHR))
+		mode = CLS_NONE;
+	else
+		mode = clsh_d->interpolator_modes[ffs(clsh_state)];
+
+	return mode;
+}
+
+static inline void aqt_clsh_set_int_mode(struct aqt_clsh_cdc_data *clsh_d,
+					int clsh_state, int mode)
+{
+	if ((clsh_state != AQT_CLSH_STATE_HPHL) &&
+	    (clsh_state != AQT_CLSH_STATE_HPHR))
+		return;
+
+	clsh_d->interpolator_modes[ffs(clsh_state)] = mode;
+}
+
+static inline void aqt_clsh_set_buck_mode(struct snd_soc_component *component,
+					  int mode)
+{
+	if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
+	    mode == CLS_AB_HIFI || mode == CLS_AB)
+		snd_soc_component_update_bits(component,
+				AQT1000_ANA_RX_SUPPLIES,
+				0x08, 0x08); /* set to HIFI */
+	else
+		snd_soc_component_update_bits(component,
+				AQT1000_ANA_RX_SUPPLIES,
+				0x08, 0x00); /* set to default */
+}
+
+static inline void aqt_clsh_set_flyback_mode(
+			struct snd_soc_component *component, int mode)
+{
+	if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
+	    mode == CLS_AB_HIFI || mode == CLS_AB)
+		snd_soc_component_update_bits(component,
+				AQT1000_ANA_RX_SUPPLIES,
+				0x04, 0x04); /* set to HIFI */
+	else
+		snd_soc_component_update_bits(component,
+				AQT1000_ANA_RX_SUPPLIES,
+				0x04, 0x00); /* set to Default */
+}
+
+static inline void aqt_clsh_gm3_boost_disable(
+			struct snd_soc_component *component, int mode)
+{
+	if (mode == CLS_H_HIFI || mode == CLS_H_LOHIFI ||
+	    mode == CLS_AB_HIFI || mode == CLS_AB) {
+		snd_soc_component_update_bits(component,
+				AQT1000_HPH_CNP_WG_CTL,
+				0x80, 0x0); /* disable GM3 Boost */
+		snd_soc_component_update_bits(component,
+				AQT1000_FLYBACK_VNEG_CTRL_4,
+				0xF0, 0x80);
+	} else {
+		snd_soc_component_update_bits(component,
+				AQT1000_HPH_CNP_WG_CTL,
+				0x80, 0x80); /* set to Default */
+		snd_soc_component_update_bits(component,
+				AQT1000_FLYBACK_VNEG_CTRL_4,
+				0xF0, 0x70);
+	}
+}
+
+static inline void aqt_clsh_flyback_dac_ctl(
+			struct snd_soc_component *component, int vref)
+{
+	snd_soc_component_update_bits(component,
+			AQT1000_FLYBACK_VNEGDAC_CTRL_2,
+			0xE0, (vref << 5));
+}
+
+static inline void aqt_clsh_mode_vref_ctl(struct snd_soc_component *component,
+					  int vref_ctl)
+{
+	if (vref_ctl == I2C) {
+		snd_soc_component_update_bits(component, AQT1000_CLASSH_MODE_3,
+					      0x02, 0x02);
+		snd_soc_component_update_bits(component, AQT1000_CLASSH_MODE_2,
+					      0xFF, 0x1C);
+	} else {
+		snd_soc_component_update_bits(component, AQT1000_CLASSH_MODE_2,
+					      0xFF, 0x3A);
+		snd_soc_component_update_bits(component, AQT1000_CLASSH_MODE_3,
+					      0x02, 0x00);
+	}
+}
+
+static inline void aqt_clsh_buck_current_bias_ctl(
+			struct snd_soc_component *component, bool enable)
+{
+	if (enable) {
+		snd_soc_component_update_bits(component,
+				AQT1000_BUCK_5V_IBIAS_CTL_4,
+				0x70, (I_2UA << 4));
+		snd_soc_component_update_bits(component,
+				AQT1000_BUCK_5V_IBIAS_CTL_4,
+				0x07, I_0P25UA);
+		snd_soc_component_update_bits(component,
+				AQT1000_BUCK_5V_CTRL_CCL_2,
+				0x3F, 0x3F);
+	} else {
+		snd_soc_component_update_bits(component,
+				AQT1000_BUCK_5V_IBIAS_CTL_4,
+				0x70, (I_1UA << 4));
+		snd_soc_component_update_bits(component,
+				AQT1000_BUCK_5V_IBIAS_CTL_4,
+				0x07, I_1UA);
+		snd_soc_component_update_bits(component,
+				AQT1000_BUCK_5V_CTRL_CCL_2,
+				0x3F, 0x20);
+	}
+}
+
+static inline void aqt_clsh_rdac_hd2_ctl(struct snd_soc_component *component,
+					 u8 hd2_div_ctl, u8 state)
+{
+	u16 reg = 0;
+
+	if (state == AQT_CLSH_STATE_HPHL)
+		reg = AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_L;
+	else if (state == AQT_CLSH_STATE_HPHR)
+		reg = AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_R;
+	else
+		dev_err(component->dev, "%s: Invalid state: %d\n",
+			__func__, state);
+	if (!reg)
+		snd_soc_component_update_bits(component, reg,
+					      0x0F, hd2_div_ctl);
+}
+
+static inline void aqt_clsh_force_iq_ctl(struct snd_soc_component *component,
+					 int mode)
+{
+	if (mode == CLS_H_LOHIFI || mode == CLS_AB) {
+		snd_soc_component_update_bits(component,
+				AQT1000_HPH_NEW_INT_PA_MISC2,
+				0x20, 0x20);
+		snd_soc_component_update_bits(component,
+				AQT1000_RX_BIAS_HPH_LOWPOWER,
+				0xF0, 0xC0);
+		snd_soc_component_update_bits(component,
+				AQT1000_HPH_PA_CTL1,
+				0x0E, 0x02);
+	} else {
+
+		snd_soc_component_update_bits(component,
+				AQT1000_HPH_NEW_INT_PA_MISC2,
+				0x20, 0x0);
+		snd_soc_component_update_bits(component,
+				AQT1000_RX_BIAS_HPH_LOWPOWER,
+				0xF0, 0x80);
+		snd_soc_component_update_bits(component,
+				AQT1000_HPH_PA_CTL1,
+				0x0E, 0x06);
+	}
+}
+
+static void aqt_clsh_buck_ctrl(struct snd_soc_component *component,
+			       struct aqt_clsh_cdc_data *clsh_d,
+			       int mode,
+			       bool enable)
+{
+	/* enable/disable buck */
+	if ((enable && (++clsh_d->buck_users == 1)) ||
+	   (!enable && (--clsh_d->buck_users == 0)))
+		snd_soc_component_update_bits(component,
+				AQT1000_ANA_RX_SUPPLIES,
+				(1 << 7), (enable << 7));
+	dev_dbg(component->dev, "%s: buck_users %d, enable %d, mode: %s",
+		__func__, clsh_d->buck_users, enable, mode_to_str(mode));
+	/*
+	 * 500us sleep is required after buck enable/disable
+	 * as per HW requirement
+	 */
+	usleep_range(500, 500 + AQT_USLEEP_RANGE);
+}
+
+static void aqt_clsh_flyback_ctrl(struct snd_soc_component *component,
+				  struct aqt_clsh_cdc_data *clsh_d,
+				  int mode,
+				  bool enable)
+{
+	/* enable/disable flyback */
+	if ((enable && (++clsh_d->flyback_users == 1)) ||
+	   (!enable && (--clsh_d->flyback_users == 0))) {
+		snd_soc_component_update_bits(component,
+				AQT1000_ANA_RX_SUPPLIES,
+				(1 << 6), (enable << 6));
+		/* 100usec delay is needed as per HW requirement */
+		usleep_range(100, 110);
+	}
+	dev_dbg(component->dev, "%s: flyback_users %d, enable %d, mode: %s",
+		__func__, clsh_d->flyback_users, enable, mode_to_str(mode));
+	/*
+	 * 500us sleep is required after flyback enable/disable
+	 * as per HW requirement
+	 */
+	usleep_range(500, 500 + AQT_USLEEP_RANGE);
+}
+
+static void aqt_clsh_set_hph_mode(struct snd_soc_component *component,
+				  int mode)
+{
+	u8 val = 0;
+	u8 gain = 0;
+	u8 res_val = VREF_FILT_R_0OHM;
+	u8 ipeak = DELTA_I_50MA;
+
+	switch (mode) {
+	case CLS_H_NORMAL:
+		res_val = VREF_FILT_R_50KOHM;
+		val = 0x00;
+		gain = DAC_GAIN_0DB;
+		ipeak = DELTA_I_50MA;
+		break;
+	case CLS_AB:
+		val = 0x00;
+		gain = DAC_GAIN_0DB;
+		ipeak = DELTA_I_50MA;
+		break;
+	case CLS_AB_HIFI:
+		val = 0x08;
+		break;
+	case CLS_H_HIFI:
+		val = 0x08;
+		gain = DAC_GAIN_M0P2DB;
+		ipeak = DELTA_I_50MA;
+		break;
+	case CLS_H_LOHIFI:
+		val = 0x00;
+		break;
+	case CLS_H_ULP:
+		val = 0x0C;
+		break;
+	case CLS_H_LP:
+		val = 0x04;
+		ipeak = DELTA_I_30MA;
+		break;
+	default:
+		return;
+	};
+
+	if (mode == CLS_H_LOHIFI || mode == CLS_AB)
+		val = 0x04;
+
+	snd_soc_component_update_bits(component, AQT1000_ANA_HPH, 0x0C, val);
+}
+
+static void aqt_clsh_set_buck_regulator_mode(
+			struct snd_soc_component *component, int mode)
+{
+	snd_soc_component_update_bits(component, AQT1000_ANA_RX_SUPPLIES,
+			    0x02, 0x00);
+}
+
+static void aqt_clsh_state_hph_st(struct snd_soc_component *component,
+				  struct aqt_clsh_cdc_data *clsh_d,
+				  u8 req_state, bool is_enable, int mode)
+{
+	dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
+		mode_to_str(mode),
+		is_enable ? "enable" : "disable");
+
+	if (mode == CLS_AB || mode == CLS_AB_HIFI)
+		return;
+
+	if (is_enable) {
+		if (req_state == AQT_CLSH_STATE_HPHL)
+			snd_soc_component_update_bits(component,
+					    AQT1000_CDC_RX1_RX_PATH_CFG0,
+					    0x40, 0x40);
+		if (req_state == AQT_CLSH_STATE_HPHR)
+			snd_soc_component_update_bits(component,
+					    AQT1000_CDC_RX2_RX_PATH_CFG0,
+					    0x40, 0x40);
+	} else {
+		if (req_state == AQT_CLSH_STATE_HPHL)
+			snd_soc_component_update_bits(component,
+					    AQT1000_CDC_RX1_RX_PATH_CFG0,
+					    0x40, 0x00);
+		if (req_state == AQT_CLSH_STATE_HPHR)
+			snd_soc_component_update_bits(component,
+					    AQT1000_CDC_RX2_RX_PATH_CFG0,
+					    0x40, 0x00);
+	}
+}
+
+static void aqt_clsh_state_hph_r(struct snd_soc_component *component,
+				 struct aqt_clsh_cdc_data *clsh_d,
+				 u8 req_state, bool is_enable, int mode)
+{
+	dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
+		mode_to_str(mode),
+		is_enable ? "enable" : "disable");
+
+	if (mode == CLS_H_NORMAL) {
+		dev_err(component->dev, "%s: Normal mode not applicable for hph_r\n",
+			__func__);
+		return;
+	}
+
+	if (is_enable) {
+		if (mode != CLS_AB && mode != CLS_AB_HIFI) {
+			aqt_enable_clsh_block(component, clsh_d, true);
+			/*
+			 * These K1 values depend on the Headphone Impedance
+			 * For now it is assumed to be 16 ohm
+			 */
+			snd_soc_component_update_bits(component,
+					AQT1000_CDC_CLSH_K1_MSB,
+					0x0F, 0x00);
+			snd_soc_component_update_bits(component,
+					AQT1000_CDC_CLSH_K1_LSB,
+					0xFF, 0xC0);
+			snd_soc_component_update_bits(component,
+					    AQT1000_CDC_RX2_RX_PATH_CFG0,
+					    0x40, 0x40);
+		}
+		aqt_clsh_set_buck_regulator_mode(component, mode);
+		aqt_clsh_set_flyback_mode(component, mode);
+		aqt_clsh_gm3_boost_disable(component, mode);
+		aqt_clsh_flyback_dac_ctl(component, VREF_N0P9V);
+		aqt_clsh_mode_vref_ctl(component, I2C);
+		aqt_clsh_force_iq_ctl(component, mode);
+		aqt_clsh_rdac_hd2_ctl(component, P82_0P77, req_state);
+		aqt_clsh_flyback_ctrl(component, clsh_d, mode, true);
+		aqt_clsh_flyback_dac_ctl(component, VREF_N1P827V);
+		aqt_clsh_set_buck_mode(component, mode);
+		aqt_clsh_buck_ctrl(component, clsh_d, mode, true);
+		aqt_clsh_mode_vref_ctl(component, CONTROLLER);
+		aqt_clsh_buck_current_bias_ctl(component, true);
+		aqt_clsh_set_hph_mode(component, mode);
+	} else {
+		aqt_clsh_set_hph_mode(component, CLS_H_NORMAL);
+		aqt_clsh_buck_current_bias_ctl(component, false);
+
+		if (mode != CLS_AB && mode != CLS_AB_HIFI) {
+			snd_soc_component_update_bits(component,
+					    AQT1000_CDC_RX2_RX_PATH_CFG0,
+					    0x40, 0x00);
+			aqt_enable_clsh_block(component, clsh_d, false);
+		}
+		/* buck and flyback set to default mode and disable */
+		aqt_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
+		aqt_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
+		aqt_clsh_rdac_hd2_ctl(component, P5_0P35, req_state);
+		aqt_clsh_force_iq_ctl(component, CLS_H_NORMAL);
+		aqt_clsh_gm3_boost_disable(component, CLS_H_NORMAL);
+		aqt_clsh_set_flyback_mode(component, CLS_H_NORMAL);
+		aqt_clsh_set_buck_mode(component, CLS_H_NORMAL);
+		aqt_clsh_set_buck_regulator_mode(component, CLS_H_NORMAL);
+	}
+}
+
+static void aqt_clsh_state_hph_l(struct snd_soc_component *component,
+				 struct aqt_clsh_cdc_data *clsh_d,
+				 u8 req_state, bool is_enable, int mode)
+{
+	dev_dbg(component->dev, "%s: mode: %s, %s\n", __func__,
+		mode_to_str(mode), is_enable ? "enable" : "disable");
+
+	if (mode == CLS_H_NORMAL) {
+		dev_err(component->dev, "%s: Normal mode not applicable for hph_l\n",
+			__func__);
+		return;
+	}
+
+	if (is_enable) {
+		if (mode != CLS_AB && mode != CLS_AB_HIFI) {
+			aqt_enable_clsh_block(component, clsh_d, true);
+			/*
+			 * These K1 values depend on the Headphone Impedance
+			 * For now it is assumed to be 16 ohm
+			 */
+			snd_soc_component_update_bits(component,
+					AQT1000_CDC_CLSH_K1_MSB,
+					0x0F, 0x00);
+			snd_soc_component_update_bits(component,
+					AQT1000_CDC_CLSH_K1_LSB,
+					0xFF, 0xC0);
+			snd_soc_component_update_bits(component,
+					AQT1000_CDC_RX1_RX_PATH_CFG0,
+					0x40, 0x40);
+		}
+		aqt_clsh_set_buck_regulator_mode(component, mode);
+		aqt_clsh_set_flyback_mode(component, mode);
+		aqt_clsh_gm3_boost_disable(component, mode);
+		aqt_clsh_flyback_dac_ctl(component, VREF_N0P9V);
+		aqt_clsh_mode_vref_ctl(component, I2C);
+		aqt_clsh_force_iq_ctl(component, mode);
+		aqt_clsh_rdac_hd2_ctl(component, P82_0P77, req_state);
+		aqt_clsh_flyback_ctrl(component, clsh_d, mode, true);
+		aqt_clsh_flyback_dac_ctl(component, VREF_N1P827V);
+		aqt_clsh_set_buck_mode(component, mode);
+		aqt_clsh_buck_ctrl(component, clsh_d, mode, true);
+		aqt_clsh_mode_vref_ctl(component, CONTROLLER);
+		aqt_clsh_buck_current_bias_ctl(component, true);
+		aqt_clsh_set_hph_mode(component, mode);
+	} else {
+		aqt_clsh_set_hph_mode(component, CLS_H_NORMAL);
+		aqt_clsh_buck_current_bias_ctl(component, false);
+
+		if (mode != CLS_AB && mode != CLS_AB_HIFI) {
+			snd_soc_component_update_bits(component,
+					    AQT1000_CDC_RX1_RX_PATH_CFG0,
+					    0x40, 0x00);
+			aqt_enable_clsh_block(component, clsh_d, false);
+		}
+		/* set buck and flyback to Default Mode */
+		aqt_clsh_buck_ctrl(component, clsh_d, CLS_H_NORMAL, false);
+		aqt_clsh_flyback_ctrl(component, clsh_d, CLS_H_NORMAL, false);
+		aqt_clsh_rdac_hd2_ctl(component, P5_0P35, req_state);
+		aqt_clsh_force_iq_ctl(component, CLS_H_NORMAL);
+		aqt_clsh_gm3_boost_disable(component, CLS_H_NORMAL);
+		aqt_clsh_set_flyback_mode(component, CLS_H_NORMAL);
+		aqt_clsh_set_buck_mode(component, CLS_H_NORMAL);
+		aqt_clsh_set_buck_regulator_mode(component, CLS_H_NORMAL);
+	}
+}
+
+static void aqt_clsh_state_err(struct snd_soc_component *component,
+		struct aqt_clsh_cdc_data *clsh_d,
+		u8 req_state, bool is_enable, int mode)
+{
+	dev_err(component->dev,
+		"%s Wrong request for class H state machine requested to %s %s",
+		__func__, is_enable ? "enable" : "disable",
+		state_to_str[req_state]);
+}
+
+/*
+ * Function: aqt_clsh_is_state_valid
+ * Params: state
+ * Description:
+ * Provides information on valid states of Class H configuration
+ */
+static bool aqt_clsh_is_state_valid(u8 state)
+{
+	switch (state) {
+	case AQT_CLSH_STATE_IDLE:
+	case AQT_CLSH_STATE_HPHL:
+	case AQT_CLSH_STATE_HPHR:
+	case AQT_CLSH_STATE_HPH_ST:
+		return true;
+	default:
+		return false;
+	};
+}
+
+/*
+ * Function: aqt_clsh_fsm
+ * Params: component, cdc_clsh_d, req_state, req_type, clsh_event
+ * Description:
+ * This function handles PRE DAC and POST DAC conditions of different devices
+ * and updates class H configuration of different combination of devices
+ * based on validity of their states. cdc_clsh_d will contain current
+ * class h state information
+ */
+void aqt_clsh_fsm(struct snd_soc_component *component,
+		struct aqt_clsh_cdc_data *cdc_clsh_d,
+		u8 clsh_event, u8 req_state,
+		int int_mode)
+{
+	u8 old_state, new_state;
+
+	switch (clsh_event) {
+	case AQT_CLSH_EVENT_PRE_DAC:
+		old_state = cdc_clsh_d->state;
+		new_state = old_state | req_state;
+
+		if (!aqt_clsh_is_state_valid(new_state)) {
+			dev_err(component->dev,
+				"%s: Class-H not a valid new state: %s\n",
+				__func__, state_to_str[new_state]);
+			return;
+		}
+		if (new_state == old_state) {
+			dev_err(component->dev,
+				"%s: Class-H already in requested state: %s\n",
+				__func__, state_to_str[new_state]);
+			return;
+		}
+		cdc_clsh_d->state = new_state;
+		aqt_clsh_set_int_mode(cdc_clsh_d, req_state, int_mode);
+		(*clsh_state_fp[new_state]) (component, cdc_clsh_d, req_state,
+					     CLSH_REQ_ENABLE, int_mode);
+		dev_dbg(component->dev,
+			"%s: ClassH state transition from %s to %s\n",
+			__func__, state_to_str[old_state],
+			state_to_str[cdc_clsh_d->state]);
+		break;
+	case AQT_CLSH_EVENT_POST_PA:
+		old_state = cdc_clsh_d->state;
+		new_state = old_state & (~req_state);
+		if (new_state < NUM_CLSH_STATES) {
+			if (!aqt_clsh_is_state_valid(old_state)) {
+				dev_err(component->dev,
+					"%s:Invalid old state:%s\n",
+					__func__, state_to_str[old_state]);
+				return;
+			}
+			if (new_state == old_state) {
+				dev_err(component->dev,
+					"%s: Class-H already in requested state: %s\n",
+					__func__,state_to_str[new_state]);
+				return;
+			}
+			(*clsh_state_fp[old_state]) (component, cdc_clsh_d,
+					req_state, CLSH_REQ_DISABLE,
+					int_mode);
+			cdc_clsh_d->state = new_state;
+			aqt_clsh_set_int_mode(cdc_clsh_d, req_state, CLS_NONE);
+			dev_dbg(component->dev, "%s: ClassH state transition from %s to %s\n",
+				__func__, state_to_str[old_state],
+				state_to_str[cdc_clsh_d->state]);
+		}
+		break;
+	};
+}
+EXPORT_SYMBOL(aqt_clsh_fsm);
+
+/*
+ * Function: aqt_clsh_get_clsh_state
+ * Params: clsh
+ * Description:
+ * This function returns the state of the class H controller
+ */
+int aqt_clsh_get_clsh_state(struct aqt_clsh_cdc_data *clsh)
+{
+	return clsh->state;
+}
+EXPORT_SYMBOL(aqt_clsh_get_clsh_state);
+
+/*
+ * Function: aqt_clsh_init
+ * Params: clsh
+ * Description:
+ * This function initializes the class H controller
+ */
+void aqt_clsh_init(struct aqt_clsh_cdc_data *clsh)
+{
+	int i;
+
+	clsh->state = AQT_CLSH_STATE_IDLE;
+
+	for (i = 0; i < NUM_CLSH_STATES; i++)
+		clsh_state_fp[i] = aqt_clsh_state_err;
+
+	clsh_state_fp[AQT_CLSH_STATE_HPHL] = aqt_clsh_state_hph_l;
+	clsh_state_fp[AQT_CLSH_STATE_HPHR] = aqt_clsh_state_hph_r;
+	clsh_state_fp[AQT_CLSH_STATE_HPH_ST] = aqt_clsh_state_hph_st;
+	/* Set interpolator modes to NONE */
+	aqt_clsh_set_int_mode(clsh, AQT_CLSH_STATE_HPHL, CLS_NONE);
+	aqt_clsh_set_int_mode(clsh, AQT_CLSH_STATE_HPHR, CLS_NONE);
+	clsh->flyback_users = 0;
+	clsh->buck_users = 0;
+	clsh->clsh_users = 0;
+}
+EXPORT_SYMBOL(aqt_clsh_init);

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-clsh.h

@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _AQT1000_CLSH_H
+#define _AQT1000_CLSH_H
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <sound/soc.h>
+#include <linux/kernel.h>
+
+#define CLSH_REQ_ENABLE true
+#define CLSH_REQ_DISABLE false
+
+#define AQT_CLSH_EVENT_PRE_DAC 0x01
+#define AQT_CLSH_EVENT_POST_PA 0x02
+/*
+ * Basic states for Class H state machine.
+ * represented as a bit mask within a u8 data type
+ * bit 0: HPH Left mode
+ * bit 1: HPH Right mode
+ */
+#define	AQT_CLSH_STATE_IDLE 0x00
+#define	AQT_CLSH_STATE_HPHL (0x01 << 0)
+#define	AQT_CLSH_STATE_HPHR (0x01 << 1)
+
+/*
+ * Though number of CLSH states are 2, max state shoulbe be 3
+ * because state array index starts from 1.
+ */
+#define AQT_CLSH_STATE_MAX 3
+#define NUM_CLSH_STATES (0x01 << AQT_CLSH_STATE_MAX)
+
+
+/* Derived State: Bits 1 and 2 should be set for Headphone stereo */
+#define AQT_CLSH_STATE_HPH_ST (AQT_CLSH_STATE_HPHL | \
+			       AQT_CLSH_STATE_HPHR)
+
+enum {
+	CLS_H_NORMAL = 0, /* Class-H Default */
+	CLS_H_HIFI, /* Class-H HiFi */
+	CLS_H_LP, /* Class-H Low Power */
+	CLS_AB, /* Class-AB Low HIFI*/
+	CLS_H_LOHIFI, /* LoHIFI */
+	CLS_H_ULP, /* Ultra Low power */
+	CLS_AB_HIFI, /* Class-AB */
+	CLS_NONE, /* None of the above modes */
+};
+
+enum {
+	DAC_GAIN_0DB = 0,
+	DAC_GAIN_0P2DB,
+	DAC_GAIN_0P4DB,
+	DAC_GAIN_0P6DB,
+	DAC_GAIN_0P8DB,
+	DAC_GAIN_M0P2DB,
+	DAC_GAIN_M0P4DB,
+	DAC_GAIN_M0P6DB,
+};
+
+enum {
+	VREF_FILT_R_0OHM = 0,
+	VREF_FILT_R_25KOHM,
+	VREF_FILT_R_50KOHM,
+	VREF_FILT_R_100KOHM,
+};
+
+enum {
+	DELTA_I_0MA,
+	DELTA_I_10MA,
+	DELTA_I_20MA,
+	DELTA_I_30MA,
+	DELTA_I_40MA,
+	DELTA_I_50MA,
+};
+
+struct aqt_imped_val {
+	u32 imped_val;
+	u8 index;
+};
+
+struct aqt_clsh_cdc_data {
+	u8 state;
+	int flyback_users;
+	int buck_users;
+	int clsh_users;
+	int interpolator_modes[AQT_CLSH_STATE_MAX];
+};
+
+struct aqt_reg_mask_val {
+	u16 reg;
+	u8 mask;
+	u8 val;
+};
+
+extern void aqt_clsh_fsm(struct snd_soc_component *component,
+		struct aqt_clsh_cdc_data *cdc_clsh_d,
+		u8 clsh_event, u8 req_state,
+		int int_mode);
+
+extern void aqt_clsh_init(struct aqt_clsh_cdc_data *clsh);
+extern int aqt_clsh_get_clsh_state(struct aqt_clsh_cdc_data *clsh);
+extern void aqt_clsh_imped_config(struct snd_soc_component *component,
+		int imped, bool reset);
+
+#endif /* _AQT1000_CLSH_H */

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-core.c

@@ -0,0 +1,638 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2011-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/ratelimit.h>
+#include <linux/mfd/core.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/debugfs.h>
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/pm_runtime.h>
+#include <sound/soc.h>
+#include <asoc/msm-cdc-pinctrl.h>
+#include <asoc/msm-cdc-supply.h>
+#include "aqt1000-registers.h"
+#include "aqt1000-internal.h"
+#include "aqt1000.h"
+#include "aqt1000-utils.h"
+#include "aqt1000-irq.h"
+
+static int aqt1000_bringup(struct aqt1000 *aqt)
+{
+	struct aqt1000_pdata *pdata;
+	u8 clk_div = 0, mclk = 1;
+
+	if (!aqt->regmap) {
+		dev_err(aqt->dev, "%s: aqt regmap is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Bringup register write sequence */
+	regmap_update_bits(aqt->regmap, AQT1000_BUCK_5V_CTRL_CCL_1, 0xF0, 0xF0);
+	regmap_update_bits(aqt->regmap, AQT1000_BIAS_CCOMP_FINE_ADJ,
+			   0xF0, 0x90);
+	regmap_update_bits(aqt->regmap, AQT1000_ANA_BIAS, 0x80, 0x80);
+	regmap_update_bits(aqt->regmap, AQT1000_ANA_BIAS, 0x40, 0x40);
+
+	/* Added 1msec sleep as per HW requirement */
+	usleep_range(1000, 1010);
+
+	regmap_update_bits(aqt->regmap, AQT1000_ANA_BIAS, 0x40, 0x00);
+
+	clk_div = 0x04; /* Assumption is CLK DIV 2 */
+	pdata = dev_get_platdata(aqt->dev);
+	if (pdata) {
+		if (pdata->mclk_rate == AQT1000_CLK_12P288MHZ)
+			mclk = 0;
+		clk_div = (((pdata->ext_clk_rate / pdata->mclk_rate) >> 1)
+				<< 2);
+	}
+	regmap_update_bits(aqt->regmap, AQT1000_CHIP_CFG0_CLK_CFG_MCLK,
+			   0x03, mclk);
+
+	regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK1_PRG,
+			   0x0C, clk_div);
+
+	/* Source clock enable */
+	regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK1_PRG, 0x02, 0x02);
+
+	/* Ungate the source clock */
+	regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK1_PRG, 0x10, 0x10);
+
+	/* Set the I2S_HS_CLK reference to CLK DIV 2 */
+	regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK2_I2S_HS_CLK_PRG,
+			   0x60, 0x20);
+
+	/* Set the PLL preset to CLK9P6M_IN_12P288M_OUT */
+	regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_PLL_PRESET, 0x0F, 0x02);
+
+	/* Enable clock PLL */
+	regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_PLL_ENABLES,
+			   0x01, 0x01);
+
+	/* Add 100usec delay as per HW requirement */
+	usleep_range(100, 110);
+
+	/* Set AQT to I2S Master */
+	regmap_update_bits(aqt->regmap, AQT1000_I2S_I2S_0_CTL, 0x02, 0x02);
+
+	/* Enable I2S HS clock */
+	regmap_update_bits(aqt->regmap, AQT1000_CLK_SYS_MCLK2_I2S_HS_CLK_PRG,
+			   0x01, 0x01);
+
+	regmap_update_bits(aqt->regmap, AQT1000_CHIP_CFG0_CLK_CFG_MCLK,
+			   0x04, 0x00);
+
+	/* Add 100usec delay as per HW requirement */
+	usleep_range(100, 110);
+	regmap_update_bits(aqt->regmap, AQT1000_CDC_CLK_RST_CTRL_MCLK_CONTROL,
+			   0x01, 0x01);
+	regmap_update_bits(aqt->regmap, AQT1000_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
+			   0x01, 0x01);
+	regmap_update_bits(aqt->regmap, AQT1000_CHIP_CFG0_CLK_CTL_CDC_DIG,
+			   0x01, 0x01);
+
+	/* Codec digital reset */
+	regmap_update_bits(aqt->regmap, AQT1000_CHIP_CFG0_RST_CTL, 0x01, 0x01);
+	/* Add 100usec delay as per HW requirement */
+	usleep_range(100, 110);
+
+	return 0;
+}
+
+static int aqt1000_device_init(struct aqt1000 *aqt)
+{
+	int ret = 0;
+
+	mutex_init(&aqt->io_lock);
+	mutex_init(&aqt->xfer_lock);
+	mutex_init(&aqt->cdc_bg_clk_lock);
+	mutex_init(&aqt->master_bias_lock);
+
+	ret = aqt1000_bringup(aqt);
+	if (ret) {
+		ret = -EPROBE_DEFER;
+		goto done;
+	}
+
+	ret = aqt_irq_init(aqt);
+	if (ret)
+		goto done;
+
+	return ret;
+done:
+	mutex_destroy(&aqt->io_lock);
+	mutex_destroy(&aqt->xfer_lock);
+	mutex_destroy(&aqt->cdc_bg_clk_lock);
+	mutex_destroy(&aqt->master_bias_lock);
+	return ret;
+}
+
+static int aqt1000_i2c_write(struct aqt1000 *aqt1000, unsigned short reg,
+			     void *val, int bytes)
+{
+	struct i2c_msg *msg;
+	int ret = 0;
+	u8 reg_addr = 0;
+	u8 data[bytes + 1];
+	struct aqt1000_i2c *aqt1000_i2c;
+	u8 *value = (u8 *)val;
+
+	aqt1000_i2c = &aqt1000->i2c_dev;
+	if (aqt1000_i2c == NULL || aqt1000_i2c->client == NULL) {
+		pr_err("%s: Failed to get device info\n", __func__);
+		return -ENODEV;
+	}
+	reg_addr = (u8)reg;
+	msg = &aqt1000_i2c->xfer_msg[0];
+	msg->addr = aqt1000_i2c->client->addr;
+	msg->len = bytes + 1;
+	msg->flags = 0;
+	data[0] = reg;
+	data[1] = *value;
+	msg->buf = data;
+	ret = i2c_transfer(aqt1000_i2c->client->adapter,
+			   aqt1000_i2c->xfer_msg, 1);
+	/* Try again if the write fails */
+	if (ret != 1) {
+		ret = i2c_transfer(aqt1000_i2c->client->adapter,
+						aqt1000_i2c->xfer_msg, 1);
+		if (ret != 1) {
+			dev_err(aqt1000->dev,
+				"%s: I2C write failed, reg: 0x%x ret: %d\n",
+				__func__, reg, ret);
+			return ret;
+		}
+	}
+	dev_dbg(aqt1000->dev, "%s: write success register = %x val = %x\n",
+		__func__, reg, data[1]);
+	return 0;
+}
+
+static int aqt1000_i2c_read(struct aqt1000 *aqt1000, unsigned short reg,
+				  void *dst, int bytes)
+{
+	struct i2c_msg *msg;
+	int ret = 0;
+	u8 reg_addr = 0;
+	struct aqt1000_i2c *aqt1000_i2c;
+	u8 i = 0;
+	unsigned char *dest = (unsigned char *)dst;
+
+	aqt1000_i2c = &aqt1000->i2c_dev;
+	if (aqt1000_i2c == NULL || aqt1000_i2c->client == NULL) {
+		pr_err("%s: Failed to get device info\n", __func__);
+		return -ENODEV;
+	}
+	for (i = 0; i < bytes; i++) {
+		reg_addr = (u8)reg++;
+		msg = &aqt1000_i2c->xfer_msg[0];
+		msg->addr = aqt1000_i2c->client->addr;
+		msg->len = 1;
+		msg->flags = 0;
+		msg->buf = &reg_addr;
+
+		msg = &aqt1000_i2c->xfer_msg[1];
+		msg->addr = aqt1000_i2c->client->addr;
+		msg->len = 1;
+		msg->flags = I2C_M_RD;
+		msg->buf = dest++;
+		ret = i2c_transfer(aqt1000_i2c->client->adapter,
+				aqt1000_i2c->xfer_msg, 2);
+
+		/* Try again if read fails first time */
+		if (ret != 2) {
+			ret = i2c_transfer(aqt1000_i2c->client->adapter,
+					   aqt1000_i2c->xfer_msg, 2);
+			if (ret != 2) {
+				dev_err(aqt1000->dev,
+					"%s: I2C read failed, reg: 0x%x\n",
+					__func__, reg);
+				return ret;
+			}
+		}
+	}
+	return 0;
+}
+
+static int aqt1000_reset(struct device *dev)
+{
+	struct aqt1000 *aqt1000;
+	int rc = 0;
+
+	if (!dev)
+		return -ENODEV;
+
+	aqt1000 = dev_get_drvdata(dev);
+	if (!aqt1000)
+		return -EINVAL;
+
+	if (!aqt1000->aqt_rst_np) {
+		dev_err(dev, "%s: reset gpio device node not specified\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	if (!msm_cdc_pinctrl_get_state(aqt1000->aqt_rst_np)) {
+		rc = msm_cdc_pinctrl_select_sleep_state(aqt1000->aqt_rst_np);
+		if (rc) {
+			dev_err(dev, "%s: aqt sleep state request fail!\n",
+				__func__);
+			return rc;
+		}
+
+		/* 20ms sleep required after pulling the reset gpio to LOW */
+		msleep(20);
+
+		rc = msm_cdc_pinctrl_select_active_state(aqt1000->aqt_rst_np);
+		if (rc) {
+			dev_err(dev,
+				"%s: aqt active state request fail, ret: %d\n",
+				__func__, rc);
+			return rc;
+		}
+		/* 20ms sleep required after pulling the reset gpio to HIGH */
+		msleep(20);
+	}
+
+	return rc;
+}
+
+static int aqt1000_read_of_property_u32(struct device *dev, const char *name,
+					u32 *val)
+{
+	int rc = 0;
+
+	rc = of_property_read_u32(dev->of_node, name, val);
+	if (rc)
+		dev_err(dev, "%s: Looking up %s property in node %s failed",
+			__func__, name, dev->of_node->full_name);
+
+	return rc;
+}
+
+static void aqt1000_dt_parse_micbias_info(struct device *dev,
+					  struct aqt1000_micbias_setting *mb)
+{
+	u32 prop_val;
+	int rc;
+
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias-ldoh-v", NULL)) {
+		rc = aqt1000_read_of_property_u32(dev,
+						  "qcom,cdc-micbias-ldoh-v",
+						  &prop_val);
+		if (!rc)
+			mb->ldoh_v  =  (u8)prop_val;
+	}
+
+	/* MB1 */
+	if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt1-mv",
+			     NULL)) {
+		rc = aqt1000_read_of_property_u32(dev,
+						  "qcom,cdc-micbias-cfilt1-mv",
+						   &prop_val);
+		if (!rc)
+			mb->cfilt1_mv = prop_val;
+
+		rc = aqt1000_read_of_property_u32(dev,
+						"qcom,cdc-micbias1-cfilt-sel",
+						&prop_val);
+		if (!rc)
+			mb->bias1_cfilt_sel = (u8)prop_val;
+
+	} else if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
+				    NULL)) {
+		rc = aqt1000_read_of_property_u32(dev,
+						  "qcom,cdc-micbias1-mv",
+						  &prop_val);
+		if (!rc)
+			mb->micb1_mv = prop_val;
+	} else {
+		dev_info(dev, "%s: Micbias1 DT property not found\n",
+			__func__);
+	}
+
+	/* Print micbias info */
+	dev_dbg(dev, "%s: ldoh_v %u cfilt1_mv %u micb1_mv %u \n", __func__,
+		(u32)mb->ldoh_v, (u32)mb->cfilt1_mv, (u32)mb->micb1_mv);
+}
+
+static struct aqt1000_pdata *aqt1000_populate_dt_data(struct device *dev)
+{
+	struct aqt1000_pdata *pdata;
+	u32 prop_val;
+
+	if (!dev || !dev->of_node)
+		return NULL;
+
+	pdata = devm_kzalloc(dev, sizeof(struct aqt1000_pdata),
+			     GFP_KERNEL);
+	if (!pdata)
+		return NULL;
+
+	/* Parse power supplies */
+	msm_cdc_get_power_supplies(dev, &pdata->regulator,
+				   &pdata->num_supplies);
+	if (!pdata->regulator || (pdata->num_supplies <= 0)) {
+		dev_err(dev, "%s: no power supplies defined for codec\n",
+			__func__);
+		goto err_power_sup;
+	}
+
+	/* Parse micbias info */
+	aqt1000_dt_parse_micbias_info(dev, &pdata->micbias);
+
+	pdata->aqt_rst_np = of_parse_phandle(dev->of_node,
+					     "qcom,aqt-rst-gpio-node", 0);
+	if (!pdata->aqt_rst_np) {
+		dev_err(dev, "%s: Looking up %s property in node %s failed\n",
+			__func__, "qcom,aqt-rst-gpio-node",
+			dev->of_node->full_name);
+		goto err_parse_dt_prop;
+	}
+
+	if (!(aqt1000_read_of_property_u32(dev, "qcom,cdc-ext-clk-rate",
+					   &prop_val)))
+		pdata->ext_clk_rate = prop_val;
+	if (pdata->ext_clk_rate != AQT1000_CLK_24P576MHZ &&
+	    pdata->ext_clk_rate != AQT1000_CLK_19P2MHZ &&
+	    pdata->ext_clk_rate != AQT1000_CLK_12P288MHZ) {
+		/* Use the default ext_clk_rate if the DT value is wrong */
+		pdata->ext_clk_rate = AQT1000_CLK_9P6MHZ;
+	}
+
+	prop_val = 0;
+	if (!(aqt1000_read_of_property_u32(dev, "qcom,cdc-mclk-clk-rate",
+					   &prop_val)))
+		pdata->mclk_rate = prop_val;
+
+	if (pdata->mclk_rate != AQT1000_CLK_9P6MHZ &&
+	    pdata->mclk_rate != AQT1000_CLK_12P288MHZ) {
+		dev_err(dev, "%s: Invalid mclk_rate = %u\n", __func__,
+			pdata->mclk_rate);
+		goto err_parse_dt_prop;
+	}
+	if (pdata->ext_clk_rate % pdata->mclk_rate) {
+		dev_err(dev,
+			"%s: Invalid clock group, ext_clk = %d mclk = %d\n",
+			__func__, pdata->ext_clk_rate, pdata->mclk_rate);
+		goto err_parse_dt_prop;
+	}
+
+	pdata->irq_gpio = of_get_named_gpio(dev->of_node,
+					    "qcom,gpio-connect", 0);
+	if (!gpio_is_valid(pdata->irq_gpio)) {
+		dev_err(dev, "%s: TLMM connect gpio not found\n", __func__);
+		goto err_parse_dt_prop;
+	}
+
+	return pdata;
+
+err_parse_dt_prop:
+	devm_kfree(dev, pdata->regulator);
+	pdata->regulator = NULL;
+	pdata->num_supplies = 0;
+err_power_sup:
+	devm_kfree(dev, pdata);
+	return NULL;
+}
+
+static int aqt1000_bringdown(struct device *dev)
+{
+	/* No sequence for teardown */
+
+	return 0;
+}
+
+static void aqt1000_device_exit(struct aqt1000 *aqt)
+{
+	aqt_irq_exit(aqt);
+	aqt1000_bringdown(aqt->dev);
+	mutex_destroy(&aqt->io_lock);
+	mutex_destroy(&aqt->xfer_lock);
+	mutex_destroy(&aqt->cdc_bg_clk_lock);
+	mutex_destroy(&aqt->master_bias_lock);
+}
+
+static int aqt1000_i2c_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	struct aqt1000 *aqt1000 = NULL;
+	struct aqt1000_pdata *pdata = NULL;
+	int ret = 0;
+
+	pdata = aqt1000_populate_dt_data(&client->dev);
+	if (!pdata) {
+		dev_err(&client->dev,
+			"%s: Fail to obtain pdata from device tree\n",
+			__func__);
+		ret = -EINVAL;
+		goto fail;
+	}
+	client->dev.platform_data = pdata;
+
+	aqt1000 = devm_kzalloc(&client->dev, sizeof(struct aqt1000),
+			       GFP_KERNEL);
+	if (!aqt1000) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	aqt1000->regmap = aqt1000_regmap_init(&client->dev,
+			&aqt1000_regmap_config);
+	if (IS_ERR(aqt1000->regmap)) {
+		ret = PTR_ERR(aqt1000->regmap);
+		dev_err(&client->dev,
+			"%s: Failed to init register map: %d\n",
+			__func__, ret);
+		goto fail;
+	}
+	aqt1000->aqt_rst_np = pdata->aqt_rst_np;
+	if (!aqt1000->aqt_rst_np) {
+		dev_err(&client->dev, "%s: pinctrl not used for rst_n\n",
+			__func__);
+		ret = -EINVAL;
+		goto fail;
+	}
+
+	if (i2c_check_functionality(client->adapter,
+				    I2C_FUNC_I2C) == 0) {
+		dev_dbg(&client->dev, "%s: can't talk I2C?\n", __func__);
+		ret = -EIO;
+		goto fail;
+	}
+	dev_set_drvdata(&client->dev, aqt1000);
+	aqt1000->dev = &client->dev;
+	aqt1000->dev_up = true;
+	aqt1000->mclk_rate = pdata->mclk_rate;
+	aqt1000->irq = client->irq;
+
+	aqt1000->num_of_supplies = pdata->num_supplies;
+	ret = msm_cdc_init_supplies(aqt1000->dev, &aqt1000->supplies,
+				    pdata->regulator,
+				    pdata->num_supplies);
+	if (!aqt1000->supplies) {
+		dev_err(aqt1000->dev, "%s: Cannot init aqt supplies\n",
+			__func__);
+		goto err_codec;
+	}
+	ret = msm_cdc_enable_static_supplies(aqt1000->dev,
+					     aqt1000->supplies,
+					     pdata->regulator,
+					     pdata->num_supplies);
+	if (ret) {
+		dev_err(aqt1000->dev, "%s: aqt static supply enable failed!\n",
+			__func__);
+		goto err_codec;
+	}
+	/* 5 usec sleep is needed as per HW requirement */
+	usleep_range(5, 10);
+
+	ret = aqt1000_reset(aqt1000->dev);
+	if (ret) {
+		dev_err(aqt1000->dev, "%s: Codec reset failed\n", __func__);
+		goto err_supplies;
+	}
+
+	aqt1000->i2c_dev.client = client;
+	aqt1000->read_dev = aqt1000_i2c_read;
+	aqt1000->write_dev = aqt1000_i2c_write;
+
+	ret = aqt1000_device_init(aqt1000);
+	if (ret) {
+		pr_err("%s: error, initializing device failed (%d)\n",
+		       __func__, ret);
+		goto err_supplies;
+	}
+
+	pm_runtime_set_active(aqt1000->dev);
+	pm_runtime_enable(aqt1000->dev);
+
+	ret = aqt_register_codec(&client->dev);
+	if (ret) {
+		dev_err(aqt1000->dev, "%s: Codec registration failed\n",
+			 __func__);
+		goto err_cdc_register;
+	}
+
+	return ret;
+
+err_cdc_register:
+	pm_runtime_disable(aqt1000->dev);
+	aqt1000_device_exit(aqt1000);
+err_supplies:
+	msm_cdc_release_supplies(aqt1000->dev, aqt1000->supplies,
+				 pdata->regulator,
+				 pdata->num_supplies);
+	pdata->regulator = NULL;
+	pdata->num_supplies = 0;
+err_codec:
+	devm_kfree(&client->dev, aqt1000);
+	dev_set_drvdata(&client->dev, NULL);
+fail:
+	return ret;
+}
+
+static int aqt1000_i2c_remove(struct i2c_client *client)
+{
+	struct aqt1000 *aqt;
+	struct aqt1000_pdata *pdata = client->dev.platform_data;
+
+	aqt = dev_get_drvdata(&client->dev);
+
+	pm_runtime_disable(aqt->dev);
+	msm_cdc_release_supplies(aqt->dev, aqt->supplies,
+				 pdata->regulator,
+				 pdata->num_supplies);
+	aqt1000_device_exit(aqt);
+	dev_set_drvdata(&client->dev, NULL);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int aqt1000_runtime_resume(struct device *dev)
+{
+	dev_dbg(dev, "%s system resume\n", __func__);
+
+	return 0;
+}
+
+static int aqt1000_runtime_suspend(struct device *dev)
+{
+	dev_dbg(dev, "%s system suspend\n", __func__);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+static int aqt1000_i2c_resume(struct device *dev)
+{
+	pr_debug("%s system resume\n", __func__);
+	return 0;
+}
+
+static int aqt1000_i2c_suspend(struct device *dev)
+{
+	pr_debug("%s system suspend\n", __func__);
+	return 0;
+}
+#endif
+
+static struct i2c_device_id aqt1000_id_table[] = {
+	{"aqt1000-i2c", 0},
+	{}
+};
+MODULE_DEVICE_TABLE(i2c, aqt1000_id_table);
+
+static const struct dev_pm_ops aqt1000_i2c_pm_ops = {
+	SET_RUNTIME_PM_OPS(aqt1000_runtime_suspend,
+			   aqt1000_runtime_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(aqt1000_i2c_suspend,
+				aqt1000_i2c_resume)
+};
+
+static const struct of_device_id aqt_match_table[] = {
+	{.compatible = "qcom,aqt1000-i2c-codec"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, aqt_match_table);
+
+static struct i2c_driver aqt1000_i2c_driver = {
+	.driver                 = {
+		.owner          =       THIS_MODULE,
+		.name           =       "aqt1000-i2c-codec",
+#ifdef CONFIG_PM_SLEEP
+		.pm             =       &aqt1000_i2c_pm_ops,
+#endif
+		.of_match_table =       aqt_match_table,
+	},
+	.id_table               =       aqt1000_id_table,
+	.probe                  =       aqt1000_i2c_probe,
+	.remove                 =       aqt1000_i2c_remove,
+};
+
+static int __init aqt1000_init(void)
+{
+	return i2c_add_driver(&aqt1000_i2c_driver);
+}
+module_init(aqt1000_init);
+
+static void __exit aqt1000_exit(void)
+{
+	i2c_del_driver(&aqt1000_i2c_driver);
+}
+module_exit(aqt1000_exit);
+
+MODULE_DESCRIPTION("AQT1000 Codec driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-internal.h

@@ -0,0 +1,162 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _AQT1000_INTERNAL_H
+#define _AQT1000_INTERNAL_H
+
+#include <linux/types.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+
+#define AQT1000_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
+			    SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
+			    SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
+			    SNDRV_PCM_RATE_384000)
+/* Fractional Rates */
+#define AQT1000_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
+				 SNDRV_PCM_RATE_176400)
+
+#define AQT1000_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
+				    SNDRV_PCM_FMTBIT_S24_LE)
+
+#define AQT1000_FORMATS_S16_S24_S32_LE (SNDRV_PCM_FMTBIT_S16_LE | \
+					SNDRV_PCM_FMTBIT_S24_LE | \
+					SNDRV_PCM_FMTBIT_S32_LE)
+
+#define AQT1000_FORMATS_S16_LE (SNDRV_PCM_FMTBIT_S16_LE)
+
+/* Macros for packing register writes into a U32 */
+#define AQT1000_PACKED_REG_SIZE sizeof(u32)
+#define AQT1000_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
+	do { \
+		((reg) = ((packed >> 16) & (0xffff))); \
+		((mask) = ((packed >> 8) & (0xff))); \
+		((val) = ((packed) & (0xff))); \
+	} while (0)
+
+#define STRING(name) #name
+#define AQT_DAPM_ENUM(name, reg, offset, text) \
+static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
+static const struct snd_kcontrol_new name##_mux = \
+		SOC_DAPM_ENUM(STRING(name), name##_enum)
+
+#define AQT_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \
+static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \
+static const struct snd_kcontrol_new name##_mux = \
+		SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname)
+
+#define AQT_DAPM_MUX(name, shift, kctl) \
+		SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux)
+
+
+#define AQT1000_INTERP_MUX_NUM_INPUTS 3
+#define AQT1000_RX_PATH_CTL_OFFSET 20
+
+#define BYTE_BIT_MASK(nr) (1 << ((nr) % BITS_PER_BYTE))
+
+#define AQT1000_REG_BITS 8
+#define AQT1000_MAX_VALID_ADC_MUX  3
+
+#define AQT1000_AMIC_PWR_LEVEL_LP 0
+#define AQT1000_AMIC_PWR_LEVEL_DEFAULT 1
+#define AQT1000_AMIC_PWR_LEVEL_HP 2
+#define AQT1000_AMIC_PWR_LVL_MASK 0x60
+#define AQT1000_AMIC_PWR_LVL_SHIFT 0x5
+
+#define AQT1000_DEC_PWR_LVL_MASK 0x06
+#define AQT1000_DEC_PWR_LVL_DF 0x00
+#define AQT1000_DEC_PWR_LVL_LP 0x02
+#define AQT1000_DEC_PWR_LVL_HP 0x04
+#define AQT1000_STRING_LEN 100
+
+#define AQT1000_CDC_SIDETONE_IIR_COEFF_MAX 5
+
+#define AQT1000_MAX_MICBIAS 1
+#define DAPM_MICBIAS1_STANDALONE "MIC BIAS1 Standalone"
+
+#define  TX_HPF_CUT_OFF_FREQ_MASK    0x60
+#define  CF_MIN_3DB_4HZ              0x0
+#define  CF_MIN_3DB_75HZ             0x1
+#define  CF_MIN_3DB_150HZ            0x2
+
+enum {
+	AUDIO_NOMINAL,
+	HPH_PA_DELAY,
+	CLSH_Z_CONFIG,
+	ANC_MIC_AMIC1,
+	ANC_MIC_AMIC2,
+	ANC_MIC_AMIC3,
+};
+
+enum {
+	INTn_1_INP_SEL_ZERO = 0,
+	INTn_1_INP_SEL_DEC0,
+	INTn_1_INP_SEL_DEC1,
+	INTn_1_INP_SEL_IIR0,
+	INTn_1_INP_SEL_IIR1,
+	INTn_1_INP_SEL_RX0,
+	INTn_1_INP_SEL_RX1,
+};
+
+enum {
+	INTn_2_INP_SEL_ZERO = 0,
+	INTn_2_INP_SEL_RX0,
+	INTn_2_INP_SEL_RX1,
+	INTn_2_INP_SEL_PROXIMITY,
+};
+
+/* Codec supports 2 IIR filters */
+enum {
+	IIR0 = 0,
+	IIR1,
+	IIR_MAX,
+};
+
+enum {
+	ASRC_IN_HPHL,
+	ASRC_IN_HPHR,
+	ASRC_INVALID,
+};
+
+enum {
+	CONV_88P2K_TO_384K,
+	CONV_96K_TO_352P8K,
+	CONV_352P8K_TO_384K,
+	CONV_384K_TO_352P8K,
+	CONV_384K_TO_384K,
+	CONV_96K_TO_384K,
+};
+
+enum aqt_notify_event {
+	AQT_EVENT_INVALID,
+	/* events for micbias ON and OFF */
+	AQT_EVENT_PRE_MICBIAS_1_OFF,
+	AQT_EVENT_POST_MICBIAS_1_OFF,
+	AQT_EVENT_PRE_MICBIAS_1_ON,
+	AQT_EVENT_POST_MICBIAS_1_ON,
+	AQT_EVENT_PRE_DAPM_MICBIAS_1_OFF,
+	AQT_EVENT_POST_DAPM_MICBIAS_1_OFF,
+	AQT_EVENT_PRE_DAPM_MICBIAS_1_ON,
+	AQT_EVENT_POST_DAPM_MICBIAS_1_ON,
+	/* events for PA ON and OFF */
+	AQT_EVENT_PRE_HPHL_PA_ON,
+	AQT_EVENT_POST_HPHL_PA_OFF,
+	AQT_EVENT_PRE_HPHR_PA_ON,
+	AQT_EVENT_POST_HPHR_PA_OFF,
+	AQT_EVENT_PRE_HPHL_PA_OFF,
+	AQT_EVENT_PRE_HPHR_PA_OFF,
+	AQT_EVENT_OCP_OFF,
+	AQT_EVENT_OCP_ON,
+	AQT_EVENT_LAST,
+};
+
+struct interp_sample_rate {
+	int sample_rate;
+	int rate_val;
+};
+
+extern struct regmap_config aqt1000_regmap_config;
+extern int aqt_register_codec(struct device *dev);
+
+#endif /* _AQT1000_INTERNAL_H */

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-irq.c

@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/ratelimit.h>
+#include <linux/irqdomain.h>
+#include <linux/regmap.h>
+#include <linux/pm_runtime.h>
+
+#include "pdata.h"
+#include "aqt1000.h"
+
+#include "aqt1000-registers.h"
+#include "aqt1000-irq.h"
+
+static const struct regmap_irq aqt1000_irqs[AQT1000_NUM_IRQS] = {
+	REGMAP_IRQ_REG(AQT1000_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x01),
+	REGMAP_IRQ_REG(AQT1000_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x02),
+	REGMAP_IRQ_REG(AQT1000_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
+	REGMAP_IRQ_REG(AQT1000_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
+	REGMAP_IRQ_REG(AQT1000_IRQ_MBHC_SW_DET, 0, 0x10),
+	REGMAP_IRQ_REG(AQT1000_IRQ_HPH_PA_OCPL_FAULT, 0, 0x20),
+	REGMAP_IRQ_REG(AQT1000_IRQ_HPH_PA_OCPR_FAULT, 0, 0x40),
+	REGMAP_IRQ_REG(AQT1000_IRQ_HPH_PA_CNPL_COMPLETE, 0, 0x80),
+	REGMAP_IRQ_REG(AQT1000_IRQ_HPH_PA_CNPR_COMPLETE, 1, 0x01),
+	REGMAP_IRQ_REG(AQT1000_CDC_HPHL_SURGE, 1, 0x02),
+	REGMAP_IRQ_REG(AQT1000_CDC_HPHR_SURGE, 1, 0x04),
+};
+
+static const struct regmap_irq_chip aqt_regmap_irq_chip = {
+	.name = "AQT1000",
+	.irqs = aqt1000_irqs,
+	.num_irqs = ARRAY_SIZE(aqt1000_irqs),
+	.num_regs = 2,
+	.status_base = AQT1000_INTR_CTRL_INT_STATUS_2,
+	.mask_base = AQT1000_INTR_CTRL_INT_MASK_2,
+	.unmask_base = AQT1000_INTR_CTRL_INT_CLEAR_2,
+	.ack_base = AQT1000_INTR_CTRL_INT_STATUS_2,
+	.runtime_pm = true,
+};
+
+static int aqt_map_irq(struct aqt1000 *aqt, int irq)
+{
+	return regmap_irq_get_virq(aqt->irq_chip, irq);
+}
+
+/**
+ * aqt_request_irq: Request a thread handler for the given IRQ
+ * @aqt: pointer to aqt1000 structure
+ * @irq: irq number
+ * @name: name for the IRQ thread
+ * @handler: irq handler
+ * @data: data pointer
+ *
+ * Returns 0 on success or error on failure
+ */
+int aqt_request_irq(struct aqt1000 *aqt, int irq, const char *name,
+			irq_handler_t handler, void *data)
+{
+	irq = aqt_map_irq(aqt, irq);
+	if (irq < 0)
+		return irq;
+
+	return request_threaded_irq(irq, NULL, handler,
+				    IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+				    name, data);
+}
+EXPORT_SYMBOL(aqt_request_irq);
+
+/**
+ * aqt_free_irq: Free the IRQ resources allocated during request_irq
+ * @aqt: pointer to aqt1000 structure
+ * @irq: irq number
+ * @data: data pointer
+ */
+void aqt_free_irq(struct aqt1000 *aqt, int irq, void *data)
+{
+	irq = aqt_map_irq(aqt, irq);
+	if (irq < 0)
+		return;
+
+	free_irq(irq, data);
+}
+EXPORT_SYMBOL(aqt_free_irq);
+
+/**
+ * aqt_enable_irq: Enable the given IRQ
+ * @aqt: pointer to aqt1000 structure
+ * @irq: irq number
+ */
+void aqt_enable_irq(struct aqt1000 *aqt, int irq)
+{
+	if (aqt)
+		enable_irq(aqt_map_irq(aqt, irq));
+}
+EXPORT_SYMBOL(aqt_enable_irq);
+
+/**
+ * aqt_disable_irq: Disable the given IRQ
+ * @aqt: pointer to aqt1000 structure
+ * @irq: irq number
+ */
+void aqt_disable_irq(struct aqt1000 *aqt, int irq)
+{
+	if (aqt)
+		disable_irq(aqt_map_irq(aqt, irq));
+}
+EXPORT_SYMBOL(aqt_disable_irq);
+
+static irqreturn_t aqt_irq_thread(int irq, void *data)
+{
+	int ret = 0;
+	u8 sts[2];
+	struct aqt1000 *aqt = data;
+	int num_irq_regs = aqt->num_irq_regs;
+	struct aqt1000_pdata *pdata;
+
+	pdata = dev_get_platdata(aqt->dev);
+
+	memset(sts, 0, sizeof(sts));
+	ret = regmap_bulk_read(aqt->regmap, AQT1000_INTR_CTRL_INT_STATUS_2,
+				sts, num_irq_regs);
+	if (ret < 0) {
+		dev_err(aqt->dev, "%s: Failed to read intr status: %d\n",
+			__func__, ret);
+	} else if (ret == 0) {
+		while (gpio_get_value_cansleep(pdata->irq_gpio))
+			handle_nested_irq(irq_find_mapping(aqt->virq, 0));
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void aqt_irq_disable(struct irq_data *data)
+{
+}
+
+static void aqt_irq_enable(struct irq_data *data)
+{
+}
+
+static struct irq_chip aqt_irq_chip = {
+	.name = "AQT",
+	.irq_disable = aqt_irq_disable,
+	.irq_enable = aqt_irq_enable,
+};
+
+static struct lock_class_key aqt_irq_lock_class;
+static struct lock_class_key aqt_irq_lock_requested_class;
+
+static int aqt_irq_map(struct irq_domain *irqd, unsigned int virq,
+			irq_hw_number_t hw)
+{
+	struct aqt1000 *data = irqd->host_data;
+
+	irq_set_chip_data(virq, data);
+	irq_set_chip_and_handler(virq, &aqt_irq_chip, handle_simple_irq);
+	irq_set_lockdep_class(virq, &aqt_irq_lock_class,
+			      &aqt_irq_lock_requested_class);
+	irq_set_nested_thread(virq, 1);
+	irq_set_noprobe(virq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops aqt_domain_ops = {
+	.map = aqt_irq_map,
+	.xlate = irq_domain_xlate_twocell,
+};
+
+/**
+ * aqt_irq_init: Initializes IRQ module
+ * @aqt: pointer to aqt1000 structure
+ *
+ * Returns 0 on success or error on failure
+ */
+int aqt_irq_init(struct aqt1000 *aqt)
+{
+	int i, ret;
+	unsigned int flags = IRQF_ONESHOT;
+	struct irq_data *irq_data;
+	struct aqt1000_pdata *pdata;
+
+	if (!aqt) {
+		pr_err("%s: Null pointer handle\n", __func__);
+		return -EINVAL;
+	}
+
+	pdata = dev_get_platdata(aqt->dev);
+	if (!pdata) {
+		dev_err(aqt->dev, "%s: Invalid platform data\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Select default if not defined in DT */
+	flags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
+	if (pdata->irq_flags)
+		flags = pdata->irq_flags;
+
+	if (pdata->irq_gpio) {
+		aqt->irq = gpio_to_irq(pdata->irq_gpio);
+		ret = devm_gpio_request_one(aqt->dev, pdata->irq_gpio,
+					    GPIOF_IN, "AQT IRQ");
+		if (ret) {
+			dev_err(aqt->dev, "%s: Failed to request gpio %d\n",
+				__func__, ret);
+			pdata->irq_gpio = 0;
+			return ret;
+		}
+	}
+
+	irq_data = irq_get_irq_data(aqt->irq);
+	if (!irq_data) {
+		dev_err(aqt->dev, "%s: Invalid IRQ: %d\n",
+			__func__, aqt->irq);
+		return -EINVAL;
+	}
+
+	aqt->num_irq_regs = aqt_regmap_irq_chip.num_regs;
+	for (i = 0; i < aqt->num_irq_regs; i++) {
+		regmap_write(aqt->regmap,
+			     (AQT1000_INTR_CTRL_INT_TYPE_2 + i), 0);
+	}
+
+	aqt->virq = irq_domain_add_linear(NULL, 1, &aqt_domain_ops, aqt);
+	if (!aqt->virq) {
+		dev_err(aqt->dev, "%s: Failed to add IRQ domain\n", __func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	ret = regmap_add_irq_chip(aqt->regmap,
+				  irq_create_mapping(aqt->virq, 0),
+				  IRQF_ONESHOT, 0, &aqt_regmap_irq_chip,
+				  &aqt->irq_chip);
+	if (ret) {
+		dev_err(aqt->dev, "%s: Failed to add IRQs: %d\n",
+			__func__, ret);
+		goto err;
+	}
+
+	ret = request_threaded_irq(aqt->irq, NULL, aqt_irq_thread, flags,
+				   "aqt", aqt);
+	if (ret) {
+		dev_err(aqt->dev, "%s: failed to register irq: %d\n",
+			__func__, ret);
+		goto err_irq;
+	}
+
+	return 0;
+
+err_irq:
+	regmap_del_irq_chip(irq_create_mapping(aqt->virq, 1), aqt->irq_chip);
+err:
+	return ret;
+}
+EXPORT_SYMBOL(aqt_irq_init);
+
+/**
+ * aqt_irq_exit: Uninitialize regmap IRQ and free IRQ resources
+ * @aqt: pointer to aqt1000 structure
+ *
+ * Returns 0 on success or error on failure
+ */
+int aqt_irq_exit(struct aqt1000 *aqt)
+{
+	if (!aqt) {
+		pr_err("%s: Null pointer handle\n", __func__);
+		return -EINVAL;
+	}
+	regmap_del_irq_chip(irq_create_mapping(aqt->virq, 1), aqt->irq_chip);
+	free_irq(aqt->irq, aqt);
+
+	return 0;
+}
+EXPORT_SYMBOL(aqt_irq_exit);

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-irq.h

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __AQT1000_IRQ_H_
+#define __AQT1000_IRQ_H_
+
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/regmap.h>
+
+enum {
+	/* INTR_CTRL_INT_MASK_2 */
+	AQT1000_IRQ_MBHC_BUTTON_RELEASE_DET = 0,
+	AQT1000_IRQ_MBHC_BUTTON_PRESS_DET,
+	AQT1000_IRQ_MBHC_ELECT_INS_REM_DET,
+	AQT1000_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
+	AQT1000_IRQ_MBHC_SW_DET,
+	AQT1000_IRQ_HPH_PA_OCPL_FAULT,
+	AQT1000_IRQ_HPH_PA_OCPR_FAULT,
+	AQT1000_IRQ_HPH_PA_CNPL_COMPLETE,
+
+	/* INTR_CTRL_INT_MASK_3 */
+	AQT1000_IRQ_HPH_PA_CNPR_COMPLETE,
+	AQT1000_CDC_HPHL_SURGE,
+	AQT1000_CDC_HPHR_SURGE,
+	AQT1000_NUM_IRQS,
+};
+
+int aqt_request_irq(struct aqt1000 *aqt, int irq, const char *name,
+			irq_handler_t handler, void *data);
+void aqt_free_irq(struct aqt1000 *aqt, int irq, void *data);
+int aqt_irq_init(struct aqt1000 *aqt);
+int aqt_irq_exit(struct aqt1000 *aqt);
+void aqt_enable_irq(struct aqt1000 *aqt, int irq);
+void aqt_disable_irq(struct aqt1000 *aqt, int irq);
+
+#endif /* __AQT1000_IRQ_H_ */

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-mbhc.h

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ */
+#ifndef __AQT1000_MBHC_H__
+#define __AQT1000_MBHC_H__
+#include <asoc/wcd-mbhc-v2.h>
+
+struct aqt1000_mbhc {
+	struct wcd_mbhc wcd_mbhc;
+	struct blocking_notifier_head notifier;
+	struct aqt1000 *aqt;
+	struct fw_info *fw_data;
+	bool mbhc_started;
+};
+
+#if IS_ENABLED(CONFIG_SND_SOC_AQT1000)
+extern int aqt_mbhc_init(struct aqt1000_mbhc **mbhc,
+			   struct snd_soc_component *component,
+			   struct fw_info *fw_data);
+extern void aqt_mbhc_hs_detect_exit(struct snd_soc_component *component);
+extern int aqt_mbhc_hs_detect(struct snd_soc_component *component,
+				struct wcd_mbhc_config *mbhc_cfg);
+extern void aqt_mbhc_deinit(struct snd_soc_component *component);
+extern int aqt_mbhc_post_ssr_init(struct aqt1000_mbhc *mbhc,
+				    struct snd_soc_component *component);
+extern int aqt_mbhc_get_impedance(struct aqt1000_mbhc *aqt_mbhc,
+				    uint32_t *zl, uint32_t *zr);
+#else
+static inline int aqt_mbhc_init(struct aqt1000_mbhc **mbhc,
+				  struct snd_soc_component *component,
+				  struct fw_info *fw_data)
+{
+	return 0;
+}
+static inline void aqt_mbhc_hs_detect_exit(struct snd_soc_component *component)
+{
+}
+static inline int aqt_mbhc_hs_detect(struct snd_soc_component *component,
+				       struct wcd_mbhc_config *mbhc_cfg)
+{
+		return 0;
+}
+static inline void aqt_mbhc_deinit(struct snd_soc_component *component)
+{
+}
+static inline int aqt_mbhc_post_ssr_init(struct aqt1000_mbhc *mbhc,
+					   struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static inline int aqt_mbhc_get_impedance(struct aqt1000_mbhc *aqt_mbhc,
+					   uint32_t *zl, uint32_t *zr)
+{
+	if (zl)
+		*zl = 0;
+	if (zr)
+		*zr = 0;
+	return -EINVAL;
+}
+#endif
+
+#endif /* __AQT1000_MBHC_H__ */

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-registers.h

@@ -0,0 +1,873 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _AQT1000_REGISTERS_H
+#define _AQT1000_REGISTERS_H
+
+#define AQT1000_PAGE0_BASE                  (0x00000000)
+#define AQT1000_PAGE0_PAGE_REGISTER                       (0x00000000)
+#define AQT1000_CHIP_CFG0_BASE              (0x00000001)
+#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE0                   (0x00000001)
+#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE1                   (0x00000002)
+#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE2                   (0x00000003)
+#define AQT1000_CHIP_CFG0_CHIP_ID_BYTE3                   (0x00000004)
+#define AQT1000_CHIP_CFG0_EFUSE_CTL                       (0x00000005)
+#define AQT1000_CHIP_CFG0_EFUSE_TEST0                     (0x00000006)
+#define AQT1000_CHIP_CFG0_EFUSE_TEST1                     (0x00000007)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT0                  (0x00000009)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT1                  (0x0000000A)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT2                  (0x0000000B)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT3                  (0x0000000C)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT4                  (0x0000000D)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT5                  (0x0000000E)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT6                  (0x0000000F)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT7                  (0x00000010)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT8                  (0x00000011)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT9                  (0x00000012)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT10                 (0x00000013)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT11                 (0x00000014)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT12                 (0x00000015)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT13                 (0x00000016)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT14                 (0x00000017)
+#define AQT1000_CHIP_CFG0_EFUSE_VAL_OUT15                 (0x00000018)
+#define AQT1000_CHIP_CFG0_EFUSE_STATUS                    (0x00000019)
+#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_NONNEGO            (0x0000001A)
+#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_1                  (0x0000001B)
+#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_2                  (0x0000001C)
+#define AQT1000_CHIP_CFG0_I2C_SLAVE_ID_3                  (0x0000001D)
+#define AQT1000_CHIP_CFG0_I2C_ACTIVE                      (0x00000020)
+#define AQT1000_CHIP_CFG0_CLK_CFG_MCLK                    (0x00000021)
+#define AQT1000_CHIP_CFG0_CLK_CFG_MCLK2                   (0x00000022)
+#define AQT1000_CHIP_CFG0_CLK_CTL_CDC_DIG                 (0x00000023)
+#define AQT1000_CHIP_CFG0_RST_CTL                         (0x00000032)
+#define AQT1000_CHIP_CFG0_EFUSE2_CTL                      (0x0000003D)
+#define AQT1000_CHIP_CFG0_EFUSE2_TEST0                    (0x0000003E)
+#define AQT1000_CHIP_CFG0_EFUSE2_TEST1                    (0x0000003F)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT0                 (0x00000040)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT1                 (0x00000041)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT2                 (0x00000042)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT3                 (0x00000043)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT4                 (0x00000044)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT5                 (0x00000045)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT6                 (0x00000046)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT7                 (0x00000047)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT8                 (0x00000048)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT9                 (0x00000049)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT10                (0x0000004A)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT11                (0x0000004B)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT12                (0x0000004C)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT13                (0x0000004D)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT14                (0x0000004E)
+#define AQT1000_CHIP_CFG0_EFUSE2_VAL_OUT15                (0x0000004F)
+#define AQT1000_CHIP_CFG0_EFUSE2_STATUS                   (0x00000050)
+#define AQT1000_CHIP_CFG1_BASE              (0x00000051)
+#define AQT1000_CHIP_CFG1_PWR_CTL                         (0x00000051)
+#define AQT1000_CHIP_CFG1_BUS_MTRX_CFG                    (0x00000052)
+#define AQT1000_CHIP_CFG1_DMA_BUS_VOTE                    (0x00000053)
+#define AQT1000_CHIP_CFG1_USB_BUS_VOTE                    (0x00000054)
+#define AQT1000_CHIP_CFG1_BLSP_BUS_VOTE                   (0x00000055)
+#define AQT1000_CHIP_CFG1_PWR_MEM_SD                      (0x00000059)
+#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_SD_RAM              (0x0000005C)
+#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_SD_ROM              (0x0000005D)
+#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_FORCE_DS_RAM        (0x0000005E)
+#define AQT1000_CHIP_CFG1_PWR_SYS_MEM_FORCE_DS_ROM        (0x0000005F)
+#define AQT1000_CHIP_CFG1_CLK_CFG_FLL                     (0x00000061)
+#define AQT1000_CHIP_CFG1_CLK_CFG_SPI_M                   (0x00000062)
+#define AQT1000_CHIP_CFG1_CLK_CFG_I2C_M                   (0x00000063)
+#define AQT1000_CHIP_CFG1_CLK_CFG_UART                    (0x00000064)
+#define AQT1000_CHIP_CFG1_RST_USB_SS                      (0x00000071)
+#define AQT1000_CHIP_CFG1_RST_BLSP                        (0x00000072)
+#define AQT1000_CHIP_CFG1_RST_BUS_MTRX                    (0x00000073)
+#define AQT1000_CHIP_CFG1_RST_MISC                        (0x00000074)
+#define AQT1000_CHIP_CFG1_ANA_WAIT_STATE_CTL              (0x00000081)
+#define AQT1000_PAGE1_BASE                  (0x00000100)
+#define AQT1000_PAGE1_PAGE_REGISTER                       (0x00000100)
+#define AQT1000_FLL_BASE                    (0x00000101)
+#define AQT1000_FLL_USER_CTL_0                            (0x00000101)
+#define AQT1000_FLL_USER_CTL_1                            (0x00000102)
+#define AQT1000_FLL_USER_CTL_2                            (0x00000103)
+#define AQT1000_FLL_USER_CTL_3                            (0x00000104)
+#define AQT1000_FLL_USER_CTL_4                            (0x00000105)
+#define AQT1000_FLL_USER_CTL_5                            (0x00000106)
+#define AQT1000_FLL_USER_CTL_6                            (0x00000107)
+#define AQT1000_FLL_USER_CTL_7                            (0x00000108)
+#define AQT1000_FLL_USER_CTL_8                            (0x00000109)
+#define AQT1000_FLL_USER_CTL_9                            (0x0000010A)
+#define AQT1000_FLL_L_VAL_CTL_0                           (0x0000010B)
+#define AQT1000_FLL_L_VAL_CTL_1                           (0x0000010C)
+#define AQT1000_FLL_DSM_FRAC_CTL_0                        (0x0000010D)
+#define AQT1000_FLL_DSM_FRAC_CTL_1                        (0x0000010E)
+#define AQT1000_FLL_CONFIG_CTL_0                          (0x0000010F)
+#define AQT1000_FLL_CONFIG_CTL_1                          (0x00000110)
+#define AQT1000_FLL_CONFIG_CTL_2                          (0x00000111)
+#define AQT1000_FLL_CONFIG_CTL_3                          (0x00000112)
+#define AQT1000_FLL_CONFIG_CTL_4                          (0x00000113)
+#define AQT1000_FLL_TEST_CTL_0                            (0x00000114)
+#define AQT1000_FLL_TEST_CTL_1                            (0x00000115)
+#define AQT1000_FLL_TEST_CTL_2                            (0x00000116)
+#define AQT1000_FLL_TEST_CTL_3                            (0x00000117)
+#define AQT1000_FLL_TEST_CTL_4                            (0x00000118)
+#define AQT1000_FLL_TEST_CTL_5                            (0x00000119)
+#define AQT1000_FLL_TEST_CTL_6                            (0x0000011A)
+#define AQT1000_FLL_TEST_CTL_7                            (0x0000011B)
+#define AQT1000_FLL_FREQ_CTL_0                            (0x0000011C)
+#define AQT1000_FLL_FREQ_CTL_1                            (0x0000011D)
+#define AQT1000_FLL_FREQ_CTL_2                            (0x0000011E)
+#define AQT1000_FLL_FREQ_CTL_3                            (0x0000011F)
+#define AQT1000_FLL_SSC_CTL_0                             (0x00000120)
+#define AQT1000_FLL_SSC_CTL_1                             (0x00000121)
+#define AQT1000_FLL_SSC_CTL_2                             (0x00000122)
+#define AQT1000_FLL_SSC_CTL_3                             (0x00000123)
+#define AQT1000_FLL_FLL_MODE                              (0x00000124)
+#define AQT1000_FLL_STATUS_0                              (0x00000125)
+#define AQT1000_FLL_STATUS_1                              (0x00000126)
+#define AQT1000_FLL_STATUS_2                              (0x00000127)
+#define AQT1000_FLL_STATUS_3                              (0x00000128)
+#define AQT1000_PAGE2_BASE                  (0x00000200)
+#define AQT1000_PAGE2_PAGE_REGISTER                       (0x00000200)
+#define AQT1000_I2S_BASE                    (0x00000201)
+#define AQT1000_I2S_I2S_0_TX_CFG                          (0x00000201)
+#define AQT1000_I2S_I2S_0_RX_CFG                          (0x00000202)
+#define AQT1000_I2S_I2S_0_CTL                             (0x00000203)
+#define AQT1000_I2S_I2S_CLKSRC_CTL                        (0x00000204)
+#define AQT1000_I2S_I2S_HS_CLK_CTL                        (0x00000205)
+#define AQT1000_I2S_I2S_0_RST                             (0x00000206)
+#define AQT1000_I2S_SHADOW_I2S_0_CTL                      (0x00000207)
+#define AQT1000_I2S_SHADOW_I2S_0_RX_CFG                   (0x00000208)
+#define AQT1000_PAGE5_BASE                  (0x00000500)
+#define AQT1000_PAGE5_PAGE_REGISTER                       (0x00000500)
+#define AQT1000_INTR_CTRL_INTR_CTRL_BASE    (0x00000501)
+#define AQT1000_INTR_CTRL_MCU_INT_POLARITY                (0x00000501)
+#define AQT1000_INTR_CTRL_INT_MASK_0                      (0x00000502)
+#define AQT1000_INTR_CTRL_INT_MASK_1                      (0x00000503)
+#define AQT1000_INTR_CTRL_INT_MASK_2                      (0x00000504)
+#define AQT1000_INTR_CTRL_INT_MASK_3                      (0x00000505)
+#define AQT1000_INTR_CTRL_INT_MASK_4                      (0x00000506)
+#define AQT1000_INTR_CTRL_INT_MASK_5                      (0x00000507)
+#define AQT1000_INTR_CTRL_INT_MASK_6                      (0x00000508)
+#define AQT1000_INTR_CTRL_INT_STATUS_0                    (0x00000509)
+#define AQT1000_INTR_CTRL_INT_STATUS_1                    (0x0000050A)
+#define AQT1000_INTR_CTRL_INT_STATUS_2                    (0x0000050B)
+#define AQT1000_INTR_CTRL_INT_STATUS_3                    (0x0000050C)
+#define AQT1000_INTR_CTRL_INT_STATUS_4                    (0x0000050D)
+#define AQT1000_INTR_CTRL_INT_STATUS_5                    (0x0000050E)
+#define AQT1000_INTR_CTRL_INT_STATUS_6                    (0x0000050F)
+#define AQT1000_INTR_CTRL_INT_CLEAR_0                     (0x00000510)
+#define AQT1000_INTR_CTRL_INT_CLEAR_1                     (0x00000511)
+#define AQT1000_INTR_CTRL_INT_CLEAR_2                     (0x00000512)
+#define AQT1000_INTR_CTRL_INT_CLEAR_3                     (0x00000513)
+#define AQT1000_INTR_CTRL_INT_CLEAR_4                     (0x00000514)
+#define AQT1000_INTR_CTRL_INT_CLEAR_5                     (0x00000515)
+#define AQT1000_INTR_CTRL_INT_CLEAR_6                     (0x00000516)
+#define AQT1000_INTR_CTRL_INT_TYPE_0                      (0x00000517)
+#define AQT1000_INTR_CTRL_INT_TYPE_1                      (0x00000518)
+#define AQT1000_INTR_CTRL_INT_TYPE_2                      (0x00000519)
+#define AQT1000_INTR_CTRL_INT_TYPE_3                      (0x0000051A)
+#define AQT1000_INTR_CTRL_INT_TYPE_4                      (0x0000051B)
+#define AQT1000_INTR_CTRL_INT_TYPE_5                      (0x0000051C)
+#define AQT1000_INTR_CTRL_INT_TYPE_6                      (0x0000051D)
+#define AQT1000_INTR_CTRL_INT_TEST_EN_0                   (0x0000051E)
+#define AQT1000_INTR_CTRL_INT_TEST_EN_1                   (0x0000051F)
+#define AQT1000_INTR_CTRL_INT_TEST_EN_2                   (0x00000520)
+#define AQT1000_INTR_CTRL_INT_TEST_EN_3                   (0x00000521)
+#define AQT1000_INTR_CTRL_INT_TEST_EN_4                   (0x00000522)
+#define AQT1000_INTR_CTRL_INT_TEST_EN_5                   (0x00000523)
+#define AQT1000_INTR_CTRL_INT_TEST_EN_6                   (0x00000524)
+#define AQT1000_INTR_CTRL_INT_TEST_VAL_0                  (0x00000525)
+#define AQT1000_INTR_CTRL_INT_TEST_VAL_1                  (0x00000526)
+#define AQT1000_INTR_CTRL_INT_TEST_VAL_2                  (0x00000527)
+#define AQT1000_INTR_CTRL_INT_TEST_VAL_3                  (0x00000528)
+#define AQT1000_INTR_CTRL_INT_TEST_VAL_4                  (0x00000529)
+#define AQT1000_INTR_CTRL_INT_TEST_VAL_5                  (0x0000052A)
+#define AQT1000_INTR_CTRL_INT_TEST_VAL_6                  (0x0000052B)
+#define AQT1000_INTR_CTRL_INT_DEST_0                      (0x0000052C)
+#define AQT1000_INTR_CTRL_INT_DEST_1                      (0x0000052D)
+#define AQT1000_INTR_CTRL_INT_DEST_2                      (0x0000052E)
+#define AQT1000_INTR_CTRL_INT_DEST_3                      (0x0000052F)
+#define AQT1000_INTR_CTRL_INT_DEST_4                      (0x00000530)
+#define AQT1000_INTR_CTRL_INT_DEST_5                      (0x00000531)
+#define AQT1000_INTR_CTRL_INT_DEST_6                      (0x00000532)
+#define AQT1000_INTR_CTRL_INT_DEST_7                      (0x00000533)
+#define AQT1000_INTR_CTRL_INT_DEST_8                      (0x00000534)
+#define AQT1000_INTR_CTRL_INT_DEST_9                      (0x00000535)
+#define AQT1000_INTR_CTRL_INT_DEST_10                     (0x00000536)
+#define AQT1000_INTR_CTRL_INT_DEST_11                     (0x00000537)
+#define AQT1000_INTR_CTRL_INT_DEST_12                     (0x00000538)
+#define AQT1000_INTR_CTRL_INT_DEST_13                     (0x00000539)
+#define AQT1000_INTR_CTRL_CLR_COMMIT                      (0x000005E1)
+#define AQT1000_ANA_BASE                    (0x00000600)
+#define AQT1000_ANA_PAGE_REGISTER                         (0x00000600)
+#define AQT1000_ANA_BIAS                                  (0x00000601)
+#define AQT1000_ANA_RX_SUPPLIES                           (0x00000608)
+#define AQT1000_ANA_HPH                                   (0x00000609)
+#define AQT1000_ANA_AMIC1                                 (0x0000060E)
+#define AQT1000_ANA_AMIC2                                 (0x0000060F)
+#define AQT1000_ANA_AMIC3                                 (0x00000610)
+#define AQT1000_ANA_AMIC3_HPF                             (0x00000611)
+#define AQT1000_ANA_MBHC_MECH                             (0x00000614)
+#define AQT1000_ANA_MBHC_ELECT                            (0x00000615)
+#define AQT1000_ANA_MBHC_ZDET                             (0x00000616)
+#define AQT1000_ANA_MBHC_RESULT_1                         (0x00000617)
+#define AQT1000_ANA_MBHC_RESULT_2                         (0x00000618)
+#define AQT1000_ANA_MBHC_RESULT_3                         (0x00000619)
+#define AQT1000_ANA_MBHC_BTN0                             (0x0000061A)
+#define AQT1000_ANA_MBHC_BTN1                             (0x0000061B)
+#define AQT1000_ANA_MBHC_BTN2                             (0x0000061C)
+#define AQT1000_ANA_MBHC_BTN3                             (0x0000061D)
+#define AQT1000_ANA_MBHC_BTN4                             (0x0000061E)
+#define AQT1000_ANA_MBHC_BTN5                             (0x0000061F)
+#define AQT1000_ANA_MBHC_BTN6                             (0x00000620)
+#define AQT1000_ANA_MBHC_BTN7                             (0x00000621)
+#define AQT1000_ANA_MICB1                                 (0x00000622)
+#define AQT1000_ANA_MICB1_RAMP                            (0x00000624)
+#define AQT1000_BIAS_BASE                   (0x00000628)
+#define AQT1000_BIAS_CTL                                  (0x00000628)
+#define AQT1000_BIAS_CCOMP_FINE_ADJ                       (0x00000629)
+#define AQT1000_LED_BASE                    (0x0000062E)
+#define AQT1000_LED_LED_MODE_SEL_R                        (0x0000062E)
+#define AQT1000_LED_LED_MISC_R                            (0x0000062F)
+#define AQT1000_LED_LED_MODE_SEL_G                        (0x00000630)
+#define AQT1000_LED_LED_MISC_G                            (0x00000631)
+#define AQT1000_LED_LED_MODE_SEL_B                        (0x00000632)
+#define AQT1000_LED_LED_MISC_B                            (0x00000633)
+#define AQT1000_LDOH_BASE                   (0x0000063A)
+#define AQT1000_LDOH_MODE                                 (0x0000063A)
+#define AQT1000_LDOH_BIAS                                 (0x0000063B)
+#define AQT1000_LDOH_STB_LOADS                            (0x0000063C)
+#define AQT1000_LDOH_MISC1                                (0x0000063D)
+#define AQT1000_LDOL_BASE                   (0x00000640)
+#define AQT1000_LDOL_VDDCX_ADJUST                         (0x00000640)
+#define AQT1000_LDOL_DISABLE_LDOL                         (0x00000641)
+#define AQT1000_BUCK_5V_BASE                (0x00000644)
+#define AQT1000_BUCK_5V_EN_CTL                            (0x00000644)
+#define AQT1000_BUCK_5V_VOUT_SEL                          (0x00000645)
+#define AQT1000_BUCK_5V_CTRL_VCL_1                        (0x00000646)
+#define AQT1000_BUCK_5V_CTRL_VCL_2                        (0x00000647)
+#define AQT1000_BUCK_5V_CTRL_CCL_2                        (0x00000648)
+#define AQT1000_BUCK_5V_CTRL_CCL_1                        (0x00000649)
+#define AQT1000_BUCK_5V_CTRL_CCL_3                        (0x0000064A)
+#define AQT1000_BUCK_5V_CTRL_CCL_4                        (0x0000064B)
+#define AQT1000_BUCK_5V_CTRL_CCL_5                        (0x0000064C)
+#define AQT1000_BUCK_5V_IBIAS_CTL_1                       (0x0000064D)
+#define AQT1000_BUCK_5V_IBIAS_CTL_2                       (0x0000064E)
+#define AQT1000_BUCK_5V_IBIAS_CTL_3                       (0x0000064F)
+#define AQT1000_BUCK_5V_IBIAS_CTL_4                       (0x00000650)
+#define AQT1000_BUCK_5V_IBIAS_CTL_5                       (0x00000651)
+#define AQT1000_BUCK_5V_ATEST_DTEST_CTL                   (0x00000652)
+#define AQT1000_PON_BASE                    (0x00000653)
+#define AQT1000_PON_BG_CTRL                               (0x00000653)
+#define AQT1000_PON_TEST_CTRL                             (0x00000654)
+#define AQT1000_MBHC_BASE                   (0x00000656)
+#define AQT1000_MBHC_CTL_CLK                              (0x00000656)
+#define AQT1000_MBHC_CTL_ANA                              (0x00000657)
+#define AQT1000_MBHC_CTL_SPARE_1                          (0x00000658)
+#define AQT1000_MBHC_CTL_SPARE_2                          (0x00000659)
+#define AQT1000_MBHC_CTL_BCS                              (0x0000065A)
+#define AQT1000_MBHC_MOISTURE_DET_FSM_STATUS              (0x0000065B)
+#define AQT1000_MBHC_TEST_CTL                             (0x0000065C)
+#define AQT1000_MICB1_BASE                  (0x0000066B)
+#define AQT1000_MICB1_TEST_CTL_1                          (0x0000066B)
+#define AQT1000_MICB1_TEST_CTL_2                          (0x0000066C)
+#define AQT1000_MICB1_TEST_CTL_3                          (0x0000066D)
+#define AQT1000_MICB1_MISC_BASE             (0x0000066E)
+#define AQT1000_MICB1_MISC_MICB1_INM_RES_BIAS             (0x0000066E)
+#define AQT1000_MICB1_MISC_MICB_MISC1                     (0x0000066F)
+#define AQT1000_MICB1_MISC_MICB_MISC2                     (0x00000670)
+#define AQT1000_TX_COM_BASE                 (0x00000677)
+#define AQT1000_TX_COM_ADC_VCM                            (0x00000677)
+#define AQT1000_TX_COM_BIAS_ATEST                         (0x00000678)
+#define AQT1000_TX_COM_ADC_INT1_IB                        (0x00000679)
+#define AQT1000_TX_COM_ADC_INT2_IB                        (0x0000067A)
+#define AQT1000_TX_COM_TXFE_DIV_CTL                       (0x0000067B)
+#define AQT1000_TX_COM_TXFE_DIV_START                     (0x0000067C)
+#define AQT1000_TX_COM_TXFE_DIV_STOP_9P6M                 (0x0000067D)
+#define AQT1000_TX_COM_TXFE_DIV_STOP_12P288M              (0x0000067E)
+#define AQT1000_TX_1_2_BASE                 (0x0000067F)
+#define AQT1000_TX_1_2_TEST_EN                            (0x0000067F)
+#define AQT1000_TX_1_2_ADC_IB                             (0x00000680)
+#define AQT1000_TX_1_2_ATEST_REFCTL                       (0x00000681)
+#define AQT1000_TX_1_2_TEST_CTL                           (0x00000682)
+#define AQT1000_TX_1_2_TEST_BLK_EN                        (0x00000683)
+#define AQT1000_TX_1_2_TXFE_CLKDIV                        (0x00000684)
+#define AQT1000_TX_1_2_SAR1_ERR                           (0x00000685)
+#define AQT1000_TX_1_2_SAR2_ERR                           (0x00000686)
+#define AQT1000_TX_3_BASE                   (0x00000687)
+#define AQT1000_TX_3_TEST_EN                              (0x00000687)
+#define AQT1000_TX_3_ADC_IB                               (0x00000688)
+#define AQT1000_TX_3_ATEST_REFCTL                         (0x00000689)
+#define AQT1000_TX_3_TEST_CTL                             (0x0000068A)
+#define AQT1000_TX_3_TEST_BLK_EN                          (0x0000068B)
+#define AQT1000_TX_3_TXFE_CLKDIV                          (0x0000068C)
+#define AQT1000_TX_3_SAR1_ERR                             (0x0000068D)
+#define AQT1000_TX_3_SAR2_ERR                             (0x0000068E)
+#define AQT1000_TX_BASE                     (0x0000068F)
+#define AQT1000_TX_ATEST1_2_SEL                           (0x0000068F)
+#define AQT1000_CLASSH_BASE                 (0x00000697)
+#define AQT1000_CLASSH_MODE_1                             (0x00000697)
+#define AQT1000_CLASSH_MODE_2                             (0x00000698)
+#define AQT1000_CLASSH_MODE_3                             (0x00000699)
+#define AQT1000_CLASSH_CTRL_VCL_1                         (0x0000069A)
+#define AQT1000_CLASSH_CTRL_VCL_2                         (0x0000069B)
+#define AQT1000_CLASSH_CTRL_CCL_1                         (0x0000069C)
+#define AQT1000_CLASSH_CTRL_CCL_2                         (0x0000069D)
+#define AQT1000_CLASSH_CTRL_CCL_3                         (0x0000069E)
+#define AQT1000_CLASSH_CTRL_CCL_4                         (0x0000069F)
+#define AQT1000_CLASSH_CTRL_CCL_5                         (0x000006A0)
+#define AQT1000_CLASSH_BUCK_TMUX_A_D                      (0x000006A1)
+#define AQT1000_CLASSH_BUCK_SW_DRV_CNTL                   (0x000006A2)
+#define AQT1000_CLASSH_SPARE                              (0x000006A3)
+#define AQT1000_FLYBACK_BASE                (0x000006A4)
+#define AQT1000_FLYBACK_EN                                (0x000006A4)
+#define AQT1000_FLYBACK_VNEG_CTRL_1                       (0x000006A5)
+#define AQT1000_FLYBACK_VNEG_CTRL_2                       (0x000006A6)
+#define AQT1000_FLYBACK_VNEG_CTRL_3                       (0x000006A7)
+#define AQT1000_FLYBACK_VNEG_CTRL_4                       (0x000006A8)
+#define AQT1000_FLYBACK_VNEG_CTRL_5                       (0x000006A9)
+#define AQT1000_FLYBACK_VNEG_CTRL_6                       (0x000006AA)
+#define AQT1000_FLYBACK_VNEG_CTRL_7                       (0x000006AB)
+#define AQT1000_FLYBACK_VNEG_CTRL_8                       (0x000006AC)
+#define AQT1000_FLYBACK_VNEG_CTRL_9                       (0x000006AD)
+#define AQT1000_FLYBACK_VNEGDAC_CTRL_1                    (0x000006AE)
+#define AQT1000_FLYBACK_VNEGDAC_CTRL_2                    (0x000006AF)
+#define AQT1000_FLYBACK_VNEGDAC_CTRL_3                    (0x000006B0)
+#define AQT1000_FLYBACK_CTRL_1                            (0x000006B1)
+#define AQT1000_FLYBACK_TEST_CTL                          (0x000006B2)
+#define AQT1000_RX_BASE                     (0x000006B3)
+#define AQT1000_RX_AUX_SW_CTL                             (0x000006B3)
+#define AQT1000_RX_PA_AUX_IN_CONN                         (0x000006B4)
+#define AQT1000_RX_TIMER_DIV                              (0x000006B5)
+#define AQT1000_RX_OCP_CTL                                (0x000006B6)
+#define AQT1000_RX_OCP_COUNT                              (0x000006B7)
+#define AQT1000_RX_BIAS_ATEST                             (0x000006B8)
+#define AQT1000_RX_BIAS_MISC1                             (0x000006B9)
+#define AQT1000_RX_BIAS_HPH_LDO                           (0x000006BA)
+#define AQT1000_RX_BIAS_HPH_PA                            (0x000006BB)
+#define AQT1000_RX_BIAS_HPH_RDACBUFF_CNP2                 (0x000006BC)
+#define AQT1000_RX_BIAS_HPH_RDAC_LDO                      (0x000006BD)
+#define AQT1000_RX_BIAS_HPH_CNP1                          (0x000006BE)
+#define AQT1000_RX_BIAS_HPH_LOWPOWER                      (0x000006BF)
+#define AQT1000_RX_BIAS_MISC2                             (0x000006C0)
+#define AQT1000_RX_BIAS_MISC3                             (0x000006C1)
+#define AQT1000_RX_BIAS_MISC4                             (0x000006C2)
+#define AQT1000_RX_BIAS_MISC5                             (0x000006C3)
+#define AQT1000_RX_BIAS_BUCK_RST                          (0x000006C4)
+#define AQT1000_RX_BIAS_BUCK_VREF_ERRAMP                  (0x000006C5)
+#define AQT1000_RX_BIAS_FLYB_ERRAMP                       (0x000006C6)
+#define AQT1000_RX_BIAS_FLYB_BUFF                         (0x000006C7)
+#define AQT1000_RX_BIAS_FLYB_MID_RST                      (0x000006C8)
+#define AQT1000_HPH_BASE                    (0x000006C9)
+#define AQT1000_HPH_L_STATUS                              (0x000006C9)
+#define AQT1000_HPH_R_STATUS                              (0x000006CA)
+#define AQT1000_HPH_CNP_EN                                (0x000006CB)
+#define AQT1000_HPH_CNP_WG_CTL                            (0x000006CC)
+#define AQT1000_HPH_CNP_WG_TIME                           (0x000006CD)
+#define AQT1000_HPH_OCP_CTL                               (0x000006CE)
+#define AQT1000_HPH_AUTO_CHOP                             (0x000006CF)
+#define AQT1000_HPH_CHOP_CTL                              (0x000006D0)
+#define AQT1000_HPH_PA_CTL1                               (0x000006D1)
+#define AQT1000_HPH_PA_CTL2                               (0x000006D2)
+#define AQT1000_HPH_L_EN                                  (0x000006D3)
+#define AQT1000_HPH_L_TEST                                (0x000006D4)
+#define AQT1000_HPH_L_ATEST                               (0x000006D5)
+#define AQT1000_HPH_R_EN                                  (0x000006D6)
+#define AQT1000_HPH_R_TEST                                (0x000006D7)
+#define AQT1000_HPH_R_ATEST                               (0x000006D8)
+#define AQT1000_HPH_RDAC_CLK_CTL1                         (0x000006D9)
+#define AQT1000_HPH_RDAC_CLK_CTL2                         (0x000006DA)
+#define AQT1000_HPH_RDAC_LDO_CTL                          (0x000006DB)
+#define AQT1000_HPH_RDAC_CHOP_CLK_LP_CTL                  (0x000006DC)
+#define AQT1000_HPH_REFBUFF_UHQA_CTL                      (0x000006DD)
+#define AQT1000_HPH_REFBUFF_LP_CTL                        (0x000006DE)
+#define AQT1000_HPH_L_DAC_CTL                             (0x000006DF)
+#define AQT1000_HPH_R_DAC_CTL                             (0x000006E0)
+#define AQT1000_HPHLR_BASE                  (0x000006E1)
+#define AQT1000_HPHLR_SURGE_COMP_SEL                      (0x000006E1)
+#define AQT1000_HPHLR_SURGE_EN                            (0x000006E2)
+#define AQT1000_HPHLR_SURGE_MISC1                         (0x000006E3)
+#define AQT1000_HPHLR_SURGE_STATUS                        (0x000006E4)
+#define AQT1000_ANA_NEW_BASE                (0x00000700)
+#define AQT1000_ANA_NEW_PAGE_REGISTER                     (0x00000700)
+#define AQT1000_HPH_NEW_BASE                (0x00000701)
+#define AQT1000_HPH_NEW_ANA_HPH2                          (0x00000701)
+#define AQT1000_HPH_NEW_ANA_HPH3                          (0x00000702)
+#define AQT1000_CLK_SYS_BASE                (0x0000070E)
+#define AQT1000_CLK_SYS_MCLK1_PRG                         (0x0000070E)
+#define AQT1000_CLK_SYS_MCLK2_I2S_HS_CLK_PRG              (0x0000070F)
+#define AQT1000_CLK_SYS_XO_CAP_XTP                        (0x00000710)
+#define AQT1000_CLK_SYS_XO_CAP_XTM                        (0x00000711)
+#define AQT1000_CLK_SYS_PLL_ENABLES                       (0x00000712)
+#define AQT1000_CLK_SYS_PLL_PRESET                        (0x00000713)
+#define AQT1000_CLK_SYS_PLL_STATUS                        (0x00000714)
+#define AQT1000_MBHC_NEW_BASE               (0x0000071F)
+#define AQT1000_MBHC_NEW_ELECT_REM_CLAMP_CTL              (0x0000071F)
+#define AQT1000_MBHC_NEW_CTL_1                            (0x00000720)
+#define AQT1000_MBHC_NEW_CTL_2                            (0x00000721)
+#define AQT1000_MBHC_NEW_PLUG_DETECT_CTL                  (0x00000722)
+#define AQT1000_MBHC_NEW_ZDET_ANA_CTL                     (0x00000723)
+#define AQT1000_MBHC_NEW_ZDET_RAMP_CTL                    (0x00000724)
+#define AQT1000_MBHC_NEW_FSM_STATUS                       (0x00000725)
+#define AQT1000_MBHC_NEW_ADC_RESULT                       (0x00000726)
+#define AQT1000_HPH_NEW_INT_BASE            (0x00000732)
+#define AQT1000_HPH_NEW_INT_RDAC_GAIN_CTL                 (0x00000732)
+#define AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_L                (0x00000733)
+#define AQT1000_HPH_NEW_INT_RDAC_VREF_CTL                 (0x00000734)
+#define AQT1000_HPH_NEW_INT_RDAC_OVERRIDE_CTL             (0x00000735)
+#define AQT1000_HPH_NEW_INT_RDAC_HD2_CTL_R                (0x00000736)
+#define AQT1000_HPH_NEW_INT_PA_MISC1                      (0x00000737)
+#define AQT1000_HPH_NEW_INT_PA_MISC2                      (0x00000738)
+#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC                  (0x00000739)
+#define AQT1000_HPH_NEW_INT_HPH_TIMER1                    (0x0000073A)
+#define AQT1000_HPH_NEW_INT_HPH_TIMER2                    (0x0000073B)
+#define AQT1000_HPH_NEW_INT_HPH_TIMER3                    (0x0000073C)
+#define AQT1000_HPH_NEW_INT_HPH_TIMER4                    (0x0000073D)
+#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC2                 (0x0000073E)
+#define AQT1000_HPH_NEW_INT_PA_RDAC_MISC3                 (0x0000073F)
+#define AQT1000_RX_NEW_INT_BASE             (0x00000745)
+#define AQT1000_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI           (0x00000745)
+#define AQT1000_RX_NEW_INT_HPH_RDAC_BIAS_ULP              (0x00000746)
+#define AQT1000_RX_NEW_INT_HPH_RDAC_LDO_LP                (0x00000747)
+#define AQT1000_CLK_SYS_INT_BASE            (0x0000076C)
+#define AQT1000_CLK_SYS_INT_CLK_TEST1                     (0x0000076C)
+#define AQT1000_CLK_SYS_INT_XO_TEST1                      (0x0000076D)
+#define AQT1000_CLK_SYS_INT_XO_TEST2                      (0x0000076E)
+#define AQT1000_CLK_SYS_INT_POST_DIV_REG0                 (0x0000076F)
+#define AQT1000_CLK_SYS_INT_POST_DIV_REG1                 (0x00000770)
+#define AQT1000_CLK_SYS_INT_REF_DIV_REG0                  (0x00000771)
+#define AQT1000_CLK_SYS_INT_REF_DIV_REG1                  (0x00000772)
+#define AQT1000_CLK_SYS_INT_FILTER_REG0                   (0x00000773)
+#define AQT1000_CLK_SYS_INT_FILTER_REG1                   (0x00000774)
+#define AQT1000_CLK_SYS_INT_PLL_L_VAL                     (0x00000775)
+#define AQT1000_CLK_SYS_INT_PLL_M_VAL                     (0x00000776)
+#define AQT1000_CLK_SYS_INT_PLL_N_VAL                     (0x00000777)
+#define AQT1000_CLK_SYS_INT_TEST_REG0                     (0x00000778)
+#define AQT1000_CLK_SYS_INT_PFD_CP_DSM_PROG               (0x00000779)
+#define AQT1000_CLK_SYS_INT_VCO_PROG                      (0x0000077A)
+#define AQT1000_CLK_SYS_INT_TEST_REG1                     (0x0000077B)
+#define AQT1000_CLK_SYS_INT_LDO_LOCK_CFG                  (0x0000077C)
+#define AQT1000_CLK_SYS_INT_DIG_LOCK_DET_CFG              (0x0000077D)
+#define AQT1000_MBHC_NEW_INT_BASE           (0x000007AF)
+#define AQT1000_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL         (0x000007AF)
+#define AQT1000_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL    (0x000007B0)
+#define AQT1000_MBHC_NEW_INT_MECH_DET_CURRENT             (0x000007B1)
+#define AQT1000_MBHC_NEW_INT_SPARE_2                      (0x000007B2)
+#define AQT1000_PAGE10_BASE                 (0x00000A00)
+#define AQT1000_PAGE10_PAGE_REGISTER                      (0x00000A00)
+#define AQT1000_CDC_ANC0_BASE               (0x00000A01)
+#define AQT1000_CDC_ANC0_CLK_RESET_CTL                    (0x00000A01)
+#define AQT1000_CDC_ANC0_MODE_1_CTL                       (0x00000A02)
+#define AQT1000_CDC_ANC0_MODE_2_CTL                       (0x00000A03)
+#define AQT1000_CDC_ANC0_FF_SHIFT                         (0x00000A04)
+#define AQT1000_CDC_ANC0_FB_SHIFT                         (0x00000A05)
+#define AQT1000_CDC_ANC0_LPF_FF_A_CTL                     (0x00000A06)
+#define AQT1000_CDC_ANC0_LPF_FF_B_CTL                     (0x00000A07)
+#define AQT1000_CDC_ANC0_LPF_FB_CTL                       (0x00000A08)
+#define AQT1000_CDC_ANC0_SMLPF_CTL                        (0x00000A09)
+#define AQT1000_CDC_ANC0_DCFLT_SHIFT_CTL                  (0x00000A0A)
+#define AQT1000_CDC_ANC0_IIR_ADAPT_CTL                    (0x00000A0B)
+#define AQT1000_CDC_ANC0_IIR_COEFF_1_CTL                  (0x00000A0C)
+#define AQT1000_CDC_ANC0_IIR_COEFF_2_CTL                  (0x00000A0D)
+#define AQT1000_CDC_ANC0_FF_A_GAIN_CTL                    (0x00000A0E)
+#define AQT1000_CDC_ANC0_FF_B_GAIN_CTL                    (0x00000A0F)
+#define AQT1000_CDC_ANC0_FB_GAIN_CTL                      (0x00000A10)
+#define AQT1000_CDC_ANC0_RC_COMMON_CTL                    (0x00000A11)
+#define AQT1000_CDC_ANC0_FIFO_COMMON_CTL                  (0x00000A13)
+#define AQT1000_CDC_ANC0_RC0_STATUS_FMIN_CNTR             (0x00000A14)
+#define AQT1000_CDC_ANC0_RC1_STATUS_FMIN_CNTR             (0x00000A15)
+#define AQT1000_CDC_ANC0_RC0_STATUS_FMAX_CNTR             (0x00000A16)
+#define AQT1000_CDC_ANC0_RC1_STATUS_FMAX_CNTR             (0x00000A17)
+#define AQT1000_CDC_ANC0_STATUS_FIFO                      (0x00000A18)
+#define AQT1000_CDC_ANC1_BASE               (0x00000A19)
+#define AQT1000_CDC_ANC1_CLK_RESET_CTL                    (0x00000A19)
+#define AQT1000_CDC_ANC1_MODE_1_CTL                       (0x00000A1A)
+#define AQT1000_CDC_ANC1_MODE_2_CTL                       (0x00000A1B)
+#define AQT1000_CDC_ANC1_FF_SHIFT                         (0x00000A1C)
+#define AQT1000_CDC_ANC1_FB_SHIFT                         (0x00000A1D)
+#define AQT1000_CDC_ANC1_LPF_FF_A_CTL                     (0x00000A1E)
+#define AQT1000_CDC_ANC1_LPF_FF_B_CTL                     (0x00000A1F)
+#define AQT1000_CDC_ANC1_LPF_FB_CTL                       (0x00000A20)
+#define AQT1000_CDC_ANC1_SMLPF_CTL                        (0x00000A21)
+#define AQT1000_CDC_ANC1_DCFLT_SHIFT_CTL                  (0x00000A22)
+#define AQT1000_CDC_ANC1_IIR_ADAPT_CTL                    (0x00000A23)
+#define AQT1000_CDC_ANC1_IIR_COEFF_1_CTL                  (0x00000A24)
+#define AQT1000_CDC_ANC1_IIR_COEFF_2_CTL                  (0x00000A25)
+#define AQT1000_CDC_ANC1_FF_A_GAIN_CTL                    (0x00000A26)
+#define AQT1000_CDC_ANC1_FF_B_GAIN_CTL                    (0x00000A27)
+#define AQT1000_CDC_ANC1_FB_GAIN_CTL                      (0x00000A28)
+#define AQT1000_CDC_ANC1_RC_COMMON_CTL                    (0x00000A29)
+#define AQT1000_CDC_ANC1_FIFO_COMMON_CTL                  (0x00000A2B)
+#define AQT1000_CDC_ANC1_RC0_STATUS_FMIN_CNTR             (0x00000A2C)
+#define AQT1000_CDC_ANC1_RC1_STATUS_FMIN_CNTR             (0x00000A2D)
+#define AQT1000_CDC_ANC1_RC0_STATUS_FMAX_CNTR             (0x00000A2E)
+#define AQT1000_CDC_ANC1_RC1_STATUS_FMAX_CNTR             (0x00000A2F)
+#define AQT1000_CDC_ANC1_STATUS_FIFO                      (0x00000A30)
+#define AQT1000_CDC_TX0_BASE                (0x00000A31)
+#define AQT1000_CDC_TX0_TX_PATH_CTL                       (0x00000A31)
+#define AQT1000_CDC_TX0_TX_PATH_CFG0                      (0x00000A32)
+#define AQT1000_CDC_TX0_TX_PATH_CFG1                      (0x00000A33)
+#define AQT1000_CDC_TX0_TX_VOL_CTL                        (0x00000A34)
+#define AQT1000_CDC_TX0_TX_PATH_SEC0                      (0x00000A37)
+#define AQT1000_CDC_TX0_TX_PATH_SEC1                      (0x00000A38)
+#define AQT1000_CDC_TX0_TX_PATH_SEC2                      (0x00000A39)
+#define AQT1000_CDC_TX0_TX_PATH_SEC3                      (0x00000A3A)
+#define AQT1000_CDC_TX0_TX_PATH_SEC4                      (0x00000A3B)
+#define AQT1000_CDC_TX0_TX_PATH_SEC5                      (0x00000A3C)
+#define AQT1000_CDC_TX0_TX_PATH_SEC6                      (0x00000A3D)
+#define AQT1000_CDC_TX1_BASE                (0x00000A41)
+#define AQT1000_CDC_TX1_TX_PATH_CTL                       (0x00000A41)
+#define AQT1000_CDC_TX1_TX_PATH_CFG0                      (0x00000A42)
+#define AQT1000_CDC_TX1_TX_PATH_CFG1                      (0x00000A43)
+#define AQT1000_CDC_TX1_TX_VOL_CTL                        (0x00000A44)
+#define AQT1000_CDC_TX1_TX_PATH_SEC0                      (0x00000A47)
+#define AQT1000_CDC_TX1_TX_PATH_SEC1                      (0x00000A48)
+#define AQT1000_CDC_TX1_TX_PATH_SEC2                      (0x00000A49)
+#define AQT1000_CDC_TX1_TX_PATH_SEC3                      (0x00000A4A)
+#define AQT1000_CDC_TX1_TX_PATH_SEC4                      (0x00000A4B)
+#define AQT1000_CDC_TX1_TX_PATH_SEC5                      (0x00000A4C)
+#define AQT1000_CDC_TX1_TX_PATH_SEC6                      (0x00000A4D)
+#define AQT1000_CDC_TX2_BASE                (0x00000A51)
+#define AQT1000_CDC_TX2_TX_PATH_CTL                       (0x00000A51)
+#define AQT1000_CDC_TX2_TX_PATH_CFG0                      (0x00000A52)
+#define AQT1000_CDC_TX2_TX_PATH_CFG1                      (0x00000A53)
+#define AQT1000_CDC_TX2_TX_VOL_CTL                        (0x00000A54)
+#define AQT1000_CDC_TX2_TX_PATH_SEC0                      (0x00000A57)
+#define AQT1000_CDC_TX2_TX_PATH_SEC1                      (0x00000A58)
+#define AQT1000_CDC_TX2_TX_PATH_SEC2                      (0x00000A59)
+#define AQT1000_CDC_TX2_TX_PATH_SEC3                      (0x00000A5A)
+#define AQT1000_CDC_TX2_TX_PATH_SEC4                      (0x00000A5B)
+#define AQT1000_CDC_TX2_TX_PATH_SEC5                      (0x00000A5C)
+#define AQT1000_CDC_TX2_TX_PATH_SEC6                      (0x00000A5D)
+#define AQT1000_CDC_TX2_TX_PATH_SEC7                      (0x00000A5E)
+#define AQT1000_PAGE11_BASE                 (0x00000B00)
+#define AQT1000_PAGE11_PAGE_REGISTER                      (0x00000B00)
+#define AQT1000_CDC_COMPANDER1_BASE         (0x00000B01)
+#define AQT1000_CDC_COMPANDER1_CTL0                       (0x00000B01)
+#define AQT1000_CDC_COMPANDER1_CTL1                       (0x00000B02)
+#define AQT1000_CDC_COMPANDER1_CTL2                       (0x00000B03)
+#define AQT1000_CDC_COMPANDER1_CTL3                       (0x00000B04)
+#define AQT1000_CDC_COMPANDER1_CTL4                       (0x00000B05)
+#define AQT1000_CDC_COMPANDER1_CTL5                       (0x00000B06)
+#define AQT1000_CDC_COMPANDER1_CTL6                       (0x00000B07)
+#define AQT1000_CDC_COMPANDER1_CTL7                       (0x00000B08)
+#define AQT1000_CDC_COMPANDER2_BASE         (0x00000B09)
+#define AQT1000_CDC_COMPANDER2_CTL0                       (0x00000B09)
+#define AQT1000_CDC_COMPANDER2_CTL1                       (0x00000B0A)
+#define AQT1000_CDC_COMPANDER2_CTL2                       (0x00000B0B)
+#define AQT1000_CDC_COMPANDER2_CTL3                       (0x00000B0C)
+#define AQT1000_CDC_COMPANDER2_CTL4                       (0x00000B0D)
+#define AQT1000_CDC_COMPANDER2_CTL5                       (0x00000B0E)
+#define AQT1000_CDC_COMPANDER2_CTL6                       (0x00000B0F)
+#define AQT1000_CDC_COMPANDER2_CTL7                       (0x00000B10)
+#define AQT1000_CDC_RX1_BASE                (0x00000B55)
+#define AQT1000_CDC_RX1_RX_PATH_CTL                       (0x00000B55)
+#define AQT1000_CDC_RX1_RX_PATH_CFG0                      (0x00000B56)
+#define AQT1000_CDC_RX1_RX_PATH_CFG1                      (0x00000B57)
+#define AQT1000_CDC_RX1_RX_PATH_CFG2                      (0x00000B58)
+#define AQT1000_CDC_RX1_RX_VOL_CTL                        (0x00000B59)
+#define AQT1000_CDC_RX1_RX_PATH_MIX_CTL                   (0x00000B5A)
+#define AQT1000_CDC_RX1_RX_PATH_MIX_CFG                   (0x00000B5B)
+#define AQT1000_CDC_RX1_RX_VOL_MIX_CTL                    (0x00000B5C)
+#define AQT1000_CDC_RX1_RX_PATH_SEC0                      (0x00000B5D)
+#define AQT1000_CDC_RX1_RX_PATH_SEC1                      (0x00000B5E)
+#define AQT1000_CDC_RX1_RX_PATH_SEC2                      (0x00000B5F)
+#define AQT1000_CDC_RX1_RX_PATH_SEC3                      (0x00000B60)
+#define AQT1000_CDC_RX1_RX_PATH_SEC4                      (0x00000B61)
+#define AQT1000_CDC_RX1_RX_PATH_SEC5                      (0x00000B62)
+#define AQT1000_CDC_RX1_RX_PATH_SEC6                      (0x00000B63)
+#define AQT1000_CDC_RX1_RX_PATH_SEC7                      (0x00000B64)
+#define AQT1000_CDC_RX1_RX_PATH_MIX_SEC0                  (0x00000B65)
+#define AQT1000_CDC_RX1_RX_PATH_MIX_SEC1                  (0x00000B66)
+#define AQT1000_CDC_RX1_RX_PATH_DSMDEM_CTL                (0x00000B67)
+#define AQT1000_CDC_RX2_BASE                (0x00000B69)
+#define AQT1000_CDC_RX2_RX_PATH_CTL                       (0x00000B69)
+#define AQT1000_CDC_RX2_RX_PATH_CFG0                      (0x00000B6A)
+#define AQT1000_CDC_RX2_RX_PATH_CFG1                      (0x00000B6B)
+#define AQT1000_CDC_RX2_RX_PATH_CFG2                      (0x00000B6C)
+#define AQT1000_CDC_RX2_RX_VOL_CTL                        (0x00000B6D)
+#define AQT1000_CDC_RX2_RX_PATH_MIX_CTL                   (0x00000B6E)
+#define AQT1000_CDC_RX2_RX_PATH_MIX_CFG                   (0x00000B6F)
+#define AQT1000_CDC_RX2_RX_VOL_MIX_CTL                    (0x00000B70)
+#define AQT1000_CDC_RX2_RX_PATH_SEC0                      (0x00000B71)
+#define AQT1000_CDC_RX2_RX_PATH_SEC1                      (0x00000B72)
+#define AQT1000_CDC_RX2_RX_PATH_SEC2                      (0x00000B73)
+#define AQT1000_CDC_RX2_RX_PATH_SEC3                      (0x00000B74)
+#define AQT1000_CDC_RX2_RX_PATH_SEC4                      (0x00000B75)
+#define AQT1000_CDC_RX2_RX_PATH_SEC5                      (0x00000B76)
+#define AQT1000_CDC_RX2_RX_PATH_SEC6                      (0x00000B77)
+#define AQT1000_CDC_RX2_RX_PATH_SEC7                      (0x00000B78)
+#define AQT1000_CDC_RX2_RX_PATH_MIX_SEC0                  (0x00000B79)
+#define AQT1000_CDC_RX2_RX_PATH_MIX_SEC1                  (0x00000B7A)
+#define AQT1000_CDC_RX2_RX_PATH_DSMDEM_CTL                (0x00000B7B)
+#define AQT1000_CDC_EQ_IIR0_BASE            (0x00000BD1)
+#define AQT1000_CDC_EQ_IIR0_PATH_CTL                      (0x00000BD1)
+#define AQT1000_CDC_EQ_IIR0_PATH_CFG0                     (0x00000BD2)
+#define AQT1000_CDC_EQ_IIR0_PATH_CFG1                     (0x00000BD3)
+#define AQT1000_CDC_EQ_IIR0_PATH_CFG2                     (0x00000BD4)
+#define AQT1000_CDC_EQ_IIR0_PATH_CFG3                     (0x00000BD5)
+#define AQT1000_CDC_EQ_IIR0_COEF_CFG0                     (0x00000BD6)
+#define AQT1000_CDC_EQ_IIR0_COEF_CFG1                     (0x00000BD7)
+#define AQT1000_CDC_EQ_IIR1_BASE            (0x00000BE1)
+#define AQT1000_CDC_EQ_IIR1_PATH_CTL                      (0x00000BE1)
+#define AQT1000_CDC_EQ_IIR1_PATH_CFG0                     (0x00000BE2)
+#define AQT1000_CDC_EQ_IIR1_PATH_CFG1                     (0x00000BE3)
+#define AQT1000_CDC_EQ_IIR1_PATH_CFG2                     (0x00000BE4)
+#define AQT1000_CDC_EQ_IIR1_PATH_CFG3                     (0x00000BE5)
+#define AQT1000_CDC_EQ_IIR1_COEF_CFG0                     (0x00000BE6)
+#define AQT1000_CDC_EQ_IIR1_COEF_CFG1                     (0x00000BE7)
+#define AQT1000_PAGE12_BASE                 (0x00000C00)
+#define AQT1000_PAGE12_PAGE_REGISTER                      (0x00000C00)
+#define AQT1000_CDC_CLSH_CDC_CLSH_BASE      (0x00000C01)
+#define AQT1000_CDC_CLSH_CRC                              (0x00000C01)
+#define AQT1000_CDC_CLSH_DLY_CTRL                         (0x00000C02)
+#define AQT1000_CDC_CLSH_DECAY_CTRL                       (0x00000C03)
+#define AQT1000_CDC_CLSH_HPH_V_PA                         (0x00000C04)
+#define AQT1000_CDC_CLSH_EAR_V_PA                         (0x00000C05)
+#define AQT1000_CDC_CLSH_HPH_V_HD                         (0x00000C06)
+#define AQT1000_CDC_CLSH_EAR_V_HD                         (0x00000C07)
+#define AQT1000_CDC_CLSH_K1_MSB                           (0x00000C08)
+#define AQT1000_CDC_CLSH_K1_LSB                           (0x00000C09)
+#define AQT1000_CDC_CLSH_K2_MSB                           (0x00000C0A)
+#define AQT1000_CDC_CLSH_K2_LSB                           (0x00000C0B)
+#define AQT1000_CDC_CLSH_IDLE_CTRL                        (0x00000C0C)
+#define AQT1000_CDC_CLSH_IDLE_HPH                         (0x00000C0D)
+#define AQT1000_CDC_CLSH_IDLE_EAR                         (0x00000C0E)
+#define AQT1000_CDC_CLSH_TEST0                            (0x00000C0F)
+#define AQT1000_CDC_CLSH_TEST1                            (0x00000C10)
+#define AQT1000_CDC_CLSH_OVR_VREF                         (0x00000C11)
+#define AQT1000_MIXING_ASRC0_BASE           (0x00000C55)
+#define AQT1000_MIXING_ASRC0_CLK_RST_CTL                  (0x00000C55)
+#define AQT1000_MIXING_ASRC0_CTL0                         (0x00000C56)
+#define AQT1000_MIXING_ASRC0_CTL1                         (0x00000C57)
+#define AQT1000_MIXING_ASRC0_FIFO_CTL                     (0x00000C58)
+#define AQT1000_MIXING_ASRC0_STATUS_FMIN_CNTR_LSB         (0x00000C59)
+#define AQT1000_MIXING_ASRC0_STATUS_FMIN_CNTR_MSB         (0x00000C5A)
+#define AQT1000_MIXING_ASRC0_STATUS_FMAX_CNTR_LSB         (0x00000C5B)
+#define AQT1000_MIXING_ASRC0_STATUS_FMAX_CNTR_MSB         (0x00000C5C)
+#define AQT1000_MIXING_ASRC0_STATUS_FIFO                  (0x00000C5D)
+#define AQT1000_MIXING_ASRC1_BASE           (0x00000C61)
+#define AQT1000_MIXING_ASRC1_CLK_RST_CTL                  (0x00000C61)
+#define AQT1000_MIXING_ASRC1_CTL0                         (0x00000C62)
+#define AQT1000_MIXING_ASRC1_CTL1                         (0x00000C63)
+#define AQT1000_MIXING_ASRC1_FIFO_CTL                     (0x00000C64)
+#define AQT1000_MIXING_ASRC1_STATUS_FMIN_CNTR_LSB         (0x00000C65)
+#define AQT1000_MIXING_ASRC1_STATUS_FMIN_CNTR_MSB         (0x00000C66)
+#define AQT1000_MIXING_ASRC1_STATUS_FMAX_CNTR_LSB         (0x00000C67)
+#define AQT1000_MIXING_ASRC1_STATUS_FMAX_CNTR_MSB         (0x00000C68)
+#define AQT1000_MIXING_ASRC1_STATUS_FIFO                  (0x00000C69)
+#define AQT1000_CDC_SIDETONE_SRC0_BASE      (0x00000CB5)
+#define AQT1000_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL         (0x00000CB5)
+#define AQT1000_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1        (0x00000CB6)
+#define AQT1000_SIDETONE_ASRC0_BASE         (0x00000CBD)
+#define AQT1000_SIDETONE_ASRC0_CLK_RST_CTL                (0x00000CBD)
+#define AQT1000_SIDETONE_ASRC0_CTL0                       (0x00000CBE)
+#define AQT1000_SIDETONE_ASRC0_CTL1                       (0x00000CBF)
+#define AQT1000_SIDETONE_ASRC0_FIFO_CTL                   (0x00000CC0)
+#define AQT1000_SIDETONE_ASRC0_STATUS_FMIN_CNTR_LSB       (0x00000CC1)
+#define AQT1000_SIDETONE_ASRC0_STATUS_FMIN_CNTR_MSB       (0x00000CC2)
+#define AQT1000_SIDETONE_ASRC0_STATUS_FMAX_CNTR_LSB       (0x00000CC3)
+#define AQT1000_SIDETONE_ASRC0_STATUS_FMAX_CNTR_MSB       (0x00000CC4)
+#define AQT1000_SIDETONE_ASRC0_STATUS_FIFO                (0x00000CC5)
+#define AQT1000_EC_REF_HQ0_BASE             (0x00000CD5)
+#define AQT1000_EC_REF_HQ0_EC_REF_HQ_PATH_CTL             (0x00000CD5)
+#define AQT1000_EC_REF_HQ0_EC_REF_HQ_CFG0                 (0x00000CD6)
+#define AQT1000_EC_REF_HQ1_BASE             (0x00000CDD)
+#define AQT1000_EC_REF_HQ1_EC_REF_HQ_PATH_CTL             (0x00000CDD)
+#define AQT1000_EC_REF_HQ1_EC_REF_HQ_CFG0                 (0x00000CDE)
+#define AQT1000_EC_ASRC0_BASE               (0x00000CE5)
+#define AQT1000_EC_ASRC0_CLK_RST_CTL                      (0x00000CE5)
+#define AQT1000_EC_ASRC0_CTL0                             (0x00000CE6)
+#define AQT1000_EC_ASRC0_CTL1                             (0x00000CE7)
+#define AQT1000_EC_ASRC0_FIFO_CTL                         (0x00000CE8)
+#define AQT1000_EC_ASRC0_STATUS_FMIN_CNTR_LSB             (0x00000CE9)
+#define AQT1000_EC_ASRC0_STATUS_FMIN_CNTR_MSB             (0x00000CEA)
+#define AQT1000_EC_ASRC0_STATUS_FMAX_CNTR_LSB             (0x00000CEB)
+#define AQT1000_EC_ASRC0_STATUS_FMAX_CNTR_MSB             (0x00000CEC)
+#define AQT1000_EC_ASRC0_STATUS_FIFO                      (0x00000CED)
+#define AQT1000_EC_ASRC1_BASE               (0x00000CF1)
+#define AQT1000_EC_ASRC1_CLK_RST_CTL                      (0x00000CF1)
+#define AQT1000_EC_ASRC1_CTL0                             (0x00000CF2)
+#define AQT1000_EC_ASRC1_CTL1                             (0x00000CF3)
+#define AQT1000_EC_ASRC1_FIFO_CTL                         (0x00000CF4)
+#define AQT1000_EC_ASRC1_STATUS_FMIN_CNTR_LSB             (0x00000CF5)
+#define AQT1000_EC_ASRC1_STATUS_FMIN_CNTR_MSB             (0x00000CF6)
+#define AQT1000_EC_ASRC1_STATUS_FMAX_CNTR_LSB             (0x00000CF7)
+#define AQT1000_EC_ASRC1_STATUS_FMAX_CNTR_MSB             (0x00000CF8)
+#define AQT1000_EC_ASRC1_STATUS_FIFO                      (0x00000CF9)
+#define AQT1000_PAGE13_BASE                 (0x00000D00)
+#define AQT1000_PAGE13_PAGE_REGISTER                      (0x00000D00)
+#define AQT1000_CDC_RX_INP_MUX_CDC_RX_INP_MUX_BASE (0x00000D01)
+#define AQT1000_CDC_RX_INP_MUX_RX_INT1_CFG0               (0x00000D03)
+#define AQT1000_CDC_RX_INP_MUX_RX_INT1_CFG1               (0x00000D04)
+#define AQT1000_CDC_RX_INP_MUX_RX_INT2_CFG0               (0x00000D05)
+#define AQT1000_CDC_RX_INP_MUX_RX_INT2_CFG1               (0x00000D06)
+#define AQT1000_CDC_RX_INP_MUX_EQ_IIR_CFG0                (0x00000D11)
+#define AQT1000_CDC_RX_INP_MUX_DSD_CFG0                   (0x00000D12)
+#define AQT1000_CDC_RX_INP_MUX_RX_MIX_CFG0                (0x00000D13)
+#define AQT1000_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0          (0x00000D18)
+#define AQT1000_CDC_RX_INP_MUX_ANC_CFG0                   (0x00000D1A)
+#define AQT1000_CDC_RX_INP_MUX_SPLINE_ASRC_CFG0           (0x00000D1B)
+#define AQT1000_CDC_RX_INP_MUX_EC_REF_HQ_CFG0             (0x00000D1C)
+#define AQT1000_CDC_TX_INP_MUX_CDC_TX_INP_MUX_BASE (0x00000D1D)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX0_CFG0              (0x00000D1D)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX0_CFG1              (0x00000D1E)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX1_CFG0              (0x00000D1F)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX1_CFG1              (0x00000D20)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX2_CFG0              (0x00000D21)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX2_CFG1              (0x00000D22)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX10_CFG0             (0x00000D29)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX10_CFG1             (0x00000D2A)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX11_CFG0             (0x00000D2B)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX11_CFG1             (0x00000D2C)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX12_CFG0             (0x00000D2D)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX12_CFG1             (0x00000D2E)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX13_CFG0             (0x00000D2F)
+#define AQT1000_CDC_TX_INP_MUX_ADC_MUX13_CFG1             (0x00000D30)
+#define AQT1000_CDC_SIDETONE_IIR_INP_MUX_CDC_SIDETONE_IIR_INP_MUX_BASE (0xD31)
+#define AQT1000_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0    (0x00000D31)
+#define AQT1000_CDC_IF_ROUTER_CDC_IF_ROUTER_BASE (0x00000D3D)
+#define AQT1000_CDC_IF_ROUTER_TX_MUX_CFG0                 (0x00000D3D)
+#define AQT1000_CDC_CLK_RST_CTRL_CDC_CLK_RST_CTRL_BASE (0x00000D41)
+#define AQT1000_CDC_CLK_RST_CTRL_MCLK_CONTROL             (0x00000D41)
+#define AQT1000_CDC_CLK_RST_CTRL_FS_CNT_CONTROL           (0x00000D42)
+#define AQT1000_CDC_CLK_RST_CTRL_DSD_CONTROL              (0x00000D44)
+#define AQT1000_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL       (0x00000D45)
+#define AQT1000_CDC_CLK_RST_CTRL_GFM_CONTROL              (0x00000D46)
+#define AQT1000_CDC_CLK_RST_CTRL_I2S_CONTROL              (0x00000D47)
+#define AQT1000_CDC_SIDETONE_IIR0_BASE      (0x00000D55)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_PATH_CTL            (0x00000D55)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL         (0x00000D56)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL         (0x00000D57)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL         (0x00000D58)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL         (0x00000D59)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL         (0x00000D5A)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL         (0x00000D5B)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL         (0x00000D5C)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL         (0x00000D5D)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_CTL                 (0x00000D5E)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL      (0x00000D5F)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL         (0x00000D60)
+#define AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL         (0x00000D61)
+#define AQT1000_CDC_TOP_CDC_TOP_BASE        (0x00000D81)
+#define AQT1000_CDC_TOP_TOP_CFG0                          (0x00000D81)
+#define AQT1000_CDC_TOP_HPHL_COMP_WR_LSB                  (0x00000D89)
+#define AQT1000_CDC_TOP_HPHL_COMP_WR_MSB                  (0x00000D8A)
+#define AQT1000_CDC_TOP_HPHL_COMP_LUT                     (0x00000D8B)
+#define AQT1000_CDC_TOP_HPHL_COMP_RD_LSB                  (0x00000D8C)
+#define AQT1000_CDC_TOP_HPHL_COMP_RD_MSB                  (0x00000D8D)
+#define AQT1000_CDC_TOP_HPHR_COMP_WR_LSB                  (0x00000D8E)
+#define AQT1000_CDC_TOP_HPHR_COMP_WR_MSB                  (0x00000D8F)
+#define AQT1000_CDC_TOP_HPHR_COMP_LUT                     (0x00000D90)
+#define AQT1000_CDC_TOP_HPHR_COMP_RD_LSB                  (0x00000D91)
+#define AQT1000_CDC_TOP_HPHR_COMP_RD_MSB                  (0x00000D92)
+#define AQT1000_CDC_DSD0_BASE               (0x00000DB1)
+#define AQT1000_CDC_DSD0_PATH_CTL                         (0x00000DB1)
+#define AQT1000_CDC_DSD0_CFG0                             (0x00000DB2)
+#define AQT1000_CDC_DSD0_CFG1                             (0x00000DB3)
+#define AQT1000_CDC_DSD0_CFG2                             (0x00000DB4)
+#define AQT1000_CDC_DSD0_CFG3                             (0x00000DB5)
+#define AQT1000_CDC_DSD0_CFG4                             (0x00000DB6)
+#define AQT1000_CDC_DSD0_CFG5                             (0x00000DB7)
+#define AQT1000_CDC_DSD1_BASE               (0x00000DC1)
+#define AQT1000_CDC_DSD1_PATH_CTL                         (0x00000DC1)
+#define AQT1000_CDC_DSD1_CFG0                             (0x00000DC2)
+#define AQT1000_CDC_DSD1_CFG1                             (0x00000DC3)
+#define AQT1000_CDC_DSD1_CFG2                             (0x00000DC4)
+#define AQT1000_CDC_DSD1_CFG3                             (0x00000DC5)
+#define AQT1000_CDC_DSD1_CFG4                             (0x00000DC6)
+#define AQT1000_CDC_DSD1_CFG5                             (0x00000DC7)
+#define AQT1000_CDC_RX_IDLE_DET_CDC_RX_IDLE_DET_BASE (0x00000DD1)
+#define AQT1000_CDC_RX_IDLE_DET_PATH_CTL                  (0x00000DD1)
+#define AQT1000_CDC_RX_IDLE_DET_CFG0                      (0x00000DD2)
+#define AQT1000_CDC_RX_IDLE_DET_CFG1                      (0x00000DD3)
+#define AQT1000_CDC_RX_IDLE_DET_CFG2                      (0x00000DD4)
+#define AQT1000_CDC_RX_IDLE_DET_CFG3                      (0x00000DD5)
+#define AQT1000_CDC_DOP_DET_CDC_DOP_DET_BASE (0x00000DD9)
+#define AQT1000_CDC_DOP_DET_CTL                           (0x00000DD9)
+#define AQT1000_CDC_DOP_DET_CFG0                          (0x00000DDA)
+#define AQT1000_CDC_DOP_DET_CFG1                          (0x00000DDB)
+#define AQT1000_CDC_DOP_DET_CFG2                          (0x00000DDC)
+#define AQT1000_CDC_DOP_DET_CFG3                          (0x00000DDD)
+#define AQT1000_CDC_DOP_DET_CFG4                          (0x00000DDE)
+#define AQT1000_CDC_DOP_DET_STATUS0                       (0x00000DE1)
+#define AQT1000_PAGE15_BASE                 (0x00000F00)
+#define AQT1000_PAGE15_PAGE_REGISTER                      (0x00000F00)
+#define AQT1000_CDC_DEBUG_CDC_DEBUG_BASE    (0x00000FA1)
+#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG0                 (0x00000FA1)
+#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG1                 (0x00000FA2)
+#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG2                 (0x00000FA3)
+#define AQT1000_CDC_DEBUG_DSD0_DEBUG_CFG3                 (0x00000FA4)
+#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG0                 (0x00000FA5)
+#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG1                 (0x00000FA6)
+#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG2                 (0x00000FA7)
+#define AQT1000_CDC_DEBUG_DSD1_DEBUG_CFG3                 (0x00000FA8)
+#define AQT1000_CDC_DEBUG_RC_RE_ASRC_DEBUG_CFG0           (0x00000FAB)
+#define AQT1000_CDC_DEBUG_ANC0_RC0_FIFO_CTL               (0x00000FAC)
+#define AQT1000_CDC_DEBUG_ANC0_RC1_FIFO_CTL               (0x00000FAD)
+#define AQT1000_CDC_DEBUG_ANC1_RC0_FIFO_CTL               (0x00000FAE)
+#define AQT1000_CDC_DEBUG_ANC1_RC1_FIFO_CTL               (0x00000FAF)
+#define AQT1000_CDC_DEBUG_ANC_RC_RST_DBG_CNTR             (0x00000FB0)
+#define AQT1000_PAGE128_BASE                (0x00008000)
+#define AQT1000_PAGE128_PAGE_REGISTER                     (0x00008000)
+#define AQT1000_TLMM_TLMM_BASE              (0x00008001)
+#define AQT1000_TLMM_SPI_CLK_PINCFG                       (0x00008001)
+#define AQT1000_TLMM_SPI_MOSI_PINCFG                      (0x00008002)
+#define AQT1000_TLMM_SPI_MISO_PINCFG                      (0x00008003)
+#define AQT1000_TLMM_SPI_CS_N_PINCFG                      (0x00008004)
+#define AQT1000_TLMM_GPIO1_PINCFG                         (0x00008005)
+#define AQT1000_TLMM_GPIO2_PINCFG                         (0x00008006)
+#define AQT1000_TLMM_GPIO3_PINCFG                         (0x00008007)
+#define AQT1000_TLMM_GPIO4_PINCFG                         (0x00008008)
+#define AQT1000_TLMM_GPIO5_PINCFG                         (0x00008009)
+#define AQT1000_TLMM_GPIO6_PINCFG                         (0x0000800A)
+#define AQT1000_TLMM_GPIO7_PINCFG                         (0x0000800B)
+#define AQT1000_TLMM_GPIO8_PINCFG                         (0x0000800C)
+#define AQT1000_TLMM_GPIO9_PINCFG                         (0x0000800D)
+#define AQT1000_TLMM_GPIO10_PINCFG                        (0x0000800E)
+#define AQT1000_PAD_CTRL_PAD_CTRL_BASE      (0x00008031)
+#define AQT1000_PAD_CTRL_PAD_PDN_CTRL_0                   (0x00008031)
+#define AQT1000_PAD_CTRL_PAD_PDN_CTRL_1                   (0x00008032)
+#define AQT1000_PAD_CTRL_PAD_PU_CTRL_0                    (0x00008033)
+#define AQT1000_PAD_CTRL_PAD_PU_CTRL_1                    (0x00008034)
+#define AQT1000_PAD_CTRL_GPIO_CTL_0_OE                    (0x00008036)
+#define AQT1000_PAD_CTRL_GPIO_CTL_1_OE                    (0x00008037)
+#define AQT1000_PAD_CTRL_GPIO_CTL_0_DATA                  (0x00008038)
+#define AQT1000_PAD_CTRL_GPIO_CTL_1_DATA                  (0x00008039)
+#define AQT1000_PAD_CTRL_PAD_DRVCTL                       (0x0000803A)
+#define AQT1000_PAD_CTRL_PIN_STATUS                       (0x0000803B)
+#define AQT1000_PAD_CTRL_MEM_CTRL                         (0x0000803C)
+#define AQT1000_PAD_CTRL_PAD_INP_DISABLE_0                (0x0000803E)
+#define AQT1000_PAD_CTRL_PAD_INP_DISABLE_1                (0x0000803F)
+#define AQT1000_PAD_CTRL_PIN_CTL_OE_0                     (0x00008040)
+#define AQT1000_PAD_CTRL_PIN_CTL_OE_1                     (0x00008041)
+#define AQT1000_PAD_CTRL_PIN_CTL_DATA_0                   (0x00008042)
+#define AQT1000_PAD_CTRL_PIN_CTL_DATA_1                   (0x00008043)
+#define AQT1000_PAD_CTRL_USB_PHY_CLK_DIV                  (0x00008044)
+#define AQT1000_PAD_CTRL_DEBUG_BUS_CDC                    (0x00008045)
+#define AQT1000_PAD_CTRL_DEBUG_BUS_SEL                    (0x00008046)
+#define AQT1000_PAD_CTRL_DEBUG_EN_1                       (0x00008047)
+#define AQT1000_PAD_CTRL_DEBUG_EN_2                       (0x00008048)
+#define AQT1000_PAD_CTRL_DEBUG_EN_3                       (0x00008049)
+#define AQT1000_PAD_CTRL_DEBUG_EN_4                       (0x0000804A)
+#define AQT1000_PAD_CTRL_DEBUG_EN_5                       (0x0000804B)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_0                  (0x0000804C)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_1                  (0x0000804D)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_2                  (0x0000804E)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_3                  (0x0000804F)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_4                  (0x00008050)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_5                  (0x00008051)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_6                  (0x00008052)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_7                  (0x00008053)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_8                  (0x00008054)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_9                  (0x00008055)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_10                 (0x00008056)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_11                 (0x00008057)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_12                 (0x00008058)
+#define AQT1000_PAD_CTRL_DEBUG_MUX_BIT_13                 (0x00008059)
+#define AQT1000_PAD_CTRL_DEBUG_READ_0                     (0x0000805A)
+#define AQT1000_PAD_CTRL_DEBUG_READ_1                     (0x0000805B)
+#define AQT1000_PAD_CTRL_DEBUG_READ_2                     (0x0000805C)
+#define AQT1000_PAD_CTRL_DEBUG_READ_3                     (0x0000805D)
+#define AQT1000_PAD_CTRL_FPGA_CTL                         (0x00008061)
+#define AQT1000_MAX_REGISTER                              (0x000080FF)
+
+#endif /*_AQT_REGISTERS_H*/

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-regmap.c

@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "aqt1000-registers.h"
+#include "aqt1000-reg-defaults.h"
+#include "aqt1000-internal.h"
+
+static bool aqt1000_is_readable_register(struct device *dev, unsigned int reg)
+{
+	u8 pg_num, reg_offset;
+	const u8 *reg_tbl = NULL;
+
+	/*
+	 * Get the page number from MSB of codec register. If its 0x80, assign
+	 * the corresponding page index PAGE_0x80.
+	 */
+	pg_num = reg >> 0x8;
+	if (pg_num == 0x80)
+		pg_num = AQT1000_PAGE_128;
+	else if (pg_num > 15)
+		return false;
+
+	reg_tbl = aqt1000_reg[pg_num];
+	reg_offset = reg & 0xFF;
+
+	if (reg_tbl && reg_tbl[reg_offset])
+		return true;
+	else
+		return false;
+}
+
+static bool aqt1000_is_volatile_register(struct device *dev, unsigned int reg)
+{
+	u8 pg_num, reg_offset;
+	const u8 *reg_tbl = NULL;
+
+	pg_num = reg >> 0x8;
+	if (pg_num == 0x80)
+		pg_num = AQT1000_PAGE_128;
+	else if (pg_num > 15)
+		return false;
+
+	reg_tbl = aqt1000_reg[pg_num];
+	reg_offset = reg & 0xFF;
+
+	if (reg_tbl && reg_tbl[reg_offset] == AQT1000_RO)
+		return true;
+
+	/* IIR Coeff registers are not cacheable */
+	if ((reg >= AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL) &&
+	    (reg <= AQT1000_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL))
+		return true;
+
+	if ((reg >= AQT1000_CDC_ANC0_IIR_COEFF_1_CTL) &&
+	    (reg <= AQT1000_CDC_ANC0_FB_GAIN_CTL))
+		return true;
+
+	if ((reg >= AQT1000_CDC_ANC1_IIR_COEFF_1_CTL) &&
+	    (reg <= AQT1000_CDC_ANC1_FB_GAIN_CTL))
+		return true;
+
+	/*
+	 * Need to mark volatile for registers that are writable but
+	 * only few bits are read-only
+	 */
+	switch (reg) {
+	case AQT1000_BUCK_5V_CTRL_CCL_1:
+	case AQT1000_BIAS_CCOMP_FINE_ADJ:
+	case AQT1000_ANA_BIAS:
+	case AQT1000_BUCK_5V_IBIAS_CTL_4:
+	case AQT1000_BUCK_5V_CTRL_CCL_2:
+	case AQT1000_CHIP_CFG0_RST_CTL:
+	case AQT1000_CHIP_CFG0_CLK_CTL_CDC_DIG:
+	case AQT1000_CHIP_CFG0_CLK_CFG_MCLK:
+	case AQT1000_CHIP_CFG0_EFUSE_CTL:
+	case AQT1000_CDC_CLK_RST_CTRL_FS_CNT_CONTROL:
+	case AQT1000_CDC_CLK_RST_CTRL_MCLK_CONTROL:
+	case AQT1000_ANA_RX_SUPPLIES:
+	case AQT1000_ANA_MBHC_MECH:
+	case AQT1000_ANA_MBHC_ELECT:
+	case AQT1000_ANA_MBHC_ZDET:
+	case AQT1000_ANA_MICB1:
+	case AQT1000_BUCK_5V_EN_CTL:
+		return true;
+	}
+
+	return false;
+}
+
+struct regmap_config aqt1000_regmap_config = {
+	.reg_bits = 16,
+	.val_bits = 8,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_defaults = aqt1000_defaults,
+	.num_reg_defaults = ARRAY_SIZE(aqt1000_defaults),
+	.max_register = AQT1000_MAX_REGISTER,
+	.volatile_reg = aqt1000_is_volatile_register,
+	.readable_reg = aqt1000_is_readable_register,
+};

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-routing.h

@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+#ifndef AQT1000_ROUTING_H
+#define AQT1000_ROUTING_H
+
+#include <sound/soc-dapm.h>
+
+const struct snd_soc_dapm_route aqt_audio_map[] = {
+
+	/* CDC Tx interface */
+
+	{"AQT AIF1 CAP", NULL, "AQT AIF1 CAP Mixer"},
+	{"AQT AIF1 CAP Mixer", "TX0", "AQT TX0_MUX"},
+	{"AQT AIF1 CAP Mixer", "TX1", "AQT TX1_MUX"},
+
+	{"AQT TX0_MUX", "DEC_L", "AQT ADC0 MUX"},
+	{"AQT TX0_MUX", "DEC_R", "AQT ADC1 MUX"},
+	{"AQT TX0_MUX", "DEC_V", "AQT ADC2 MUX"},
+
+	{"AQT TX1_MUX", "DEC_L", "AQT ADC0 MUX"},
+	{"AQT TX1_MUX", "DEC_R", "AQT ADC1 MUX"},
+	{"AQT TX1_MUX", "DEC_V", "AQT ADC2 MUX"},
+
+	{"AQT ADC0 MUX", "AMIC", "AQT AMIC0_MUX"},
+	{"AQT ADC0 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
+	{"AQT ADC0 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
+
+	{"AQT ADC1 MUX", "AMIC", "AQT AMIC1_MUX"},
+	{"AQT ADC1 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
+	{"AQT ADC1 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
+
+	{"AQT ADC2 MUX", "AMIC", "AQT AMIC2_MUX"},
+	{"AQT ADC2 MUX", "ANC_FB0", "AQT ANC_FB_TUNE0"},
+	{"AQT ADC2 MUX", "ANC_FB1", "AQT ANC_FB_TUNE1"},
+
+	{"AQT AMIC0_MUX", "ADC_L", "AQT ADC_L"},
+	{"AQT AMIC0_MUX", "ADC_R", "AQT ADC_R"},
+	{"AQT AMIC0_MUX", "ADC_V", "AQT ADC_V"},
+
+	{"AQT AMIC1_MUX", "ADC_L", "AQT ADC_L"},
+	{"AQT AMIC1_MUX", "ADC_R", "AQT ADC_R"},
+	{"AQT AMIC1_MUX", "ADC_V", "AQT ADC_V"},
+
+	{"AQT AMIC2_MUX", "ADC_L", "AQT ADC_L"},
+	{"AQT AMIC2_MUX", "ADC_R", "AQT ADC_R"},
+	{"AQT AMIC2_MUX", "ADC_V", "AQT ADC_V"},
+
+	{"AQT ADC_L", NULL, "AQT AMIC1"},
+	{"AQT ADC_R", NULL, "AQT AMIC2"},
+	{"AQT ADC_V", NULL, "AQT AMIC3"},
+
+	{"AQT AMIC10_MUX", "ADC_L", "AQT ADC_L"},
+	{"AQT AMIC10_MUX", "ADC_R", "AQT ADC_R"},
+	{"AQT AMIC10_MUX", "ADC_V", "AQT ADC_V"},
+
+	{"AQT AMIC11_MUX", "ADC_L", "AQT ADC_L"},
+	{"AQT AMIC11_MUX", "ADC_R", "AQT ADC_R"},
+	{"AQT AMIC11_MUX", "ADC_V", "AQT ADC_V"},
+
+	{"AQT AMIC12_MUX", "ADC_L", "AQT ADC_L"},
+	{"AQT AMIC12_MUX", "ADC_R", "AQT ADC_R"},
+	{"AQT AMIC12_MUX", "ADC_V", "AQT ADC_V"},
+
+	{"AQT AMIC13_MUX", "ADC_L", "AQT ADC_L"},
+	{"AQT AMIC13_MUX", "ADC_R", "AQT ADC_R"},
+	{"AQT AMIC13_MUX", "ADC_V", "AQT ADC_V"},
+
+	{"AQT ANC OUT HPHL Enable", "Switch", "AQT AMIC10_MUX"},
+	{"AQT ANC OUT HPHL Enable", "Switch", "AQT AMIC11_MUX"},
+	{"AQT ANC OUT HPHR Enable", "Switch", "AQT AMIC12_MUX"},
+	{"AQT ANC OUT HPHR Enable", "Switch", "AQT AMIC13_MUX"},
+
+	{"AQT RX INT1 MIX2", NULL, "AQT ANC OUT HPHL Enable"},
+	{"AQT RX INT2 MIX2", NULL, "AQT ANC OUT HPHR Enable"},
+
+	{"AQT ANC0 FB MUX", "ANC_IN_HPHL", "AQT RX INT1 MIX2"},
+	{"AQT ANC1 FB MUX", "ANC_IN_HPHR", "AQT RX INT2 MIX2"},
+
+	{"AQT I2S_L RX", NULL, "AQT AIF1 PB"},
+	{"AQT I2S_R RX", NULL, "AQT AIF1 PB"},
+
+	{"AQT RX INT1_1 MUX", "I2S0_L", "AQT I2S_L RX"},
+	{"AQT RX INT1_1 MUX", "I2S0_R", "AQT I2S_R RX"},
+	{"AQT RX INT1_1 MUX", "DEC_L", "AQT ADC0 MUX"},
+	{"AQT RX INT1_1 MUX", "DEC_R", "AQT ADC1 MUX"},
+	{"AQT RX INT1_1 MUX", "DEC_V", "AQT ADC2 MUX"},
+
+	{"AQT RX INT2_1 MUX", "I2S0_L", "AQT I2S_L RX"},
+	{"AQT RX INT2_1 MUX", "I2S0_R", "AQT I2S_R RX"},
+	{"AQT RX INT2_1 MUX", "DEC_L", "AQT ADC0 MUX"},
+	{"AQT RX INT2_1 MUX", "DEC_R", "AQT ADC1 MUX"},
+	{"AQT RX INT2_1 MUX", "DEC_V", "AQT ADC2 MUX"},
+
+	{"AQT RX INT1_2 MUX", "I2S0_L", "AQT I2S_L RX"},
+	{"AQT RX INT1_2 MUX", "I2S0_R", "AQT I2S_R RX"},
+	{"AQT RX INT1_2 MUX", "DEC_L", "AQT ADC0 MUX"},
+	{"AQT RX INT1_2 MUX", "DEC_R", "AQT ADC1 MUX"},
+	{"AQT RX INT1_2 MUX", "DEC_V", "AQT ADC2 MUX"},
+	{"AQT RX INT1_2 MUX", "IIR0", "AQT IIR0"},
+
+	{"AQT RX INT2_2 MUX", "I2S0_L", "AQT I2S_L RX"},
+	{"AQT RX INT2_2 MUX", "I2S0_R", "AQT I2S_R RX"},
+	{"AQT RX INT2_2 MUX", "DEC_L", "AQT ADC0 MUX"},
+	{"AQT RX INT2_2 MUX", "DEC_R", "AQT ADC1 MUX"},
+	{"AQT RX INT2_2 MUX", "DEC_V", "AQT ADC2 MUX"},
+	{"AQT RX INT2_2 MUX", "IIR0", "AQT IIR0"},
+
+	{"AQT RX INT1_1 INTERP", NULL, "AQT RX INT1_1 MUX"},
+	{"AQT RX INT1 MIX1", NULL, "AQT RX INT1_1 INTERP"},
+	{"AQT RX INT1 MIX2", NULL, "AQT RX INT1 MIX1"},
+
+	{"AQT RX INT1_2 INTERP", NULL, "AQT RX INT1_2 MUX"},
+	{"AQT RX INT1 MIX1", NULL, "AQT RX INT1_2 INTERP"},
+
+	{"AQT ASRC0 MUX", "ASRC_IN_HPHL", "AQT RX INT1_2 INTERP"},
+	{"AQT RX INT1 MIX1", "HPHL Switch", "AQT ASRC0 MUX"},
+
+	{"AQT RX INT2_1 INTERP", NULL, "AQT RX INT2_1 MUX"},
+	{"AQT RX INT2 MIX1", NULL, "AQT RX INT2_1 INTERP"},
+	{"AQT RX INT2 MIX2", NULL, "AQT RX INT2 MIX1"},
+
+	{"AQT RX INT2_2 INTERP", NULL, "AQT RX INT2_2 MUX"},
+	{"AQT RX INT2 MIX1", NULL, "AQT RX INT2_2 INTERP"},
+
+	{"AQT ASRC1 MUX", "ASRC_IN_HPHR", "AQT RX INT2_2 INTERP"},
+	{"AQT RX INT2 MIX1", "HPHR Switch", "AQT ASRC1 MUX"},
+
+	{"AQT RX INT1 DEM MUX", "CLSH_DSM_OUT", "AQT RX INT1 MIX2"},
+	{"AQT RX INT1 DAC", NULL, "AQT RX INT1 DEM MUX"},
+	{"AQT RX INT1 DAC", NULL, "AQT RX_BIAS"},
+	{"AQT RX_BIAS", NULL, "AQT MCLK"},
+	{"AQT MIC BIAS1", NULL, "AQT MCLK"},
+	{"AQT HPHL PA", NULL, "AQT RX INT1 DAC"},
+	{"AQT HPHL", NULL, "AQT HPHL PA"},
+
+	{"AQT RX INT2 DEM MUX", "CLSH_DSM_OUT", "AQT RX INT2 MIX2"},
+	{"AQT RX INT2 DAC", NULL, "AQT RX INT2 DEM MUX"},
+	{"AQT RX INT2 DAC", NULL, "AQT RX_BIAS"},
+	{"AQT HPHR PA", NULL, "AQT RX INT2 DAC"},
+	{"AQT HPHR", NULL, "AQT HPHR PA"},
+
+	{"AQT ANC HPHL PA", NULL, "AQT RX INT1 DAC"},
+	{"AQT ANC HPHL", NULL, "AQT ANC HPHL PA"},
+
+	{"AQT ANC HPHR PA", NULL, "AQT RX INT2 DAC"},
+	{"AQT ANC HPHR", NULL, "AQT ANC HPHR PA"},
+
+	{"AQT IIR0", NULL, "AQT ADC2 MUX"},
+	{"AQT SRC0", NULL, "AQT IIR0"},
+	{"AQT RX ST MUX", "SRC0", "AQT SRC0"},
+
+	{"AQT RX INT1 MIX2", NULL, "AQT RX ST MUX"},
+	{"AQT RX INT2 MIX2", NULL, "AQT RX ST MUX"},
+
+	/* Native clk main path routing */
+	{"AQT RX INT1_1 NATIVE MUX", "ON", "AQT RX INT1_1 MUX"},
+	{"AQT RX INT1_1 INTERP", NULL, "AQT RX INT1_1 NATIVE MUX"},
+	{"AQT RX INT1_1 NATIVE MUX", NULL, "AQT RX INT1 NATIVE SUPPLY"},
+
+	{"AQT RX INT2_1 NATIVE MUX", "ON", "AQT RX INT2_1 MUX"},
+	{"AQT RX INT2_1 INTERP", NULL, "AQT RX INT2_1 NATIVE MUX"},
+	{"AQT RX INT2_1 NATIVE MUX", NULL, "AQT RX INT2 NATIVE SUPPLY"},
+};
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-utils.c

@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include "aqt1000.h"
+#include "aqt1000-utils.h"
+
+#define REG_BYTES 2
+#define VAL_BYTES 1
+/*
+ * Page Register Address that APP Proc uses to
+ * access codec registers is identified as 0x00
+ */
+#define PAGE_REG_ADDR 0x00
+
+static int aqt_page_write(struct aqt1000 *aqt, unsigned short *reg)
+{
+	int ret = 0;
+	unsigned short c_reg, reg_addr;
+	u8 pg_num, prev_pg_num;
+
+	c_reg = *reg;
+	pg_num = c_reg >> 8;
+	reg_addr = c_reg & 0xff;
+	if (aqt->prev_pg_valid) {
+		prev_pg_num = aqt->prev_pg;
+		if (prev_pg_num != pg_num) {
+			ret = aqt->write_dev(
+					aqt, PAGE_REG_ADDR,
+					(void *) &pg_num, 1);
+			if (ret < 0)
+				dev_err(aqt->dev,
+					"%s: page write error, pg_num: 0x%x\n",
+					__func__, pg_num);
+			else {
+				aqt->prev_pg = pg_num;
+				dev_dbg(aqt->dev, "%s: Page 0x%x Write to 0x00\n",
+					__func__, pg_num);
+			}
+		}
+	} else {
+		ret = aqt->write_dev(
+				aqt, PAGE_REG_ADDR, (void *) &pg_num, 1);
+		if (ret < 0)
+			dev_err(aqt->dev,
+				"%s: page write error, pg_num: 0x%x\n",
+				__func__, pg_num);
+		else {
+			aqt->prev_pg = pg_num;
+			aqt->prev_pg_valid = true;
+			dev_dbg(aqt->dev, "%s: Page 0x%x Write to 0x00\n",
+				__func__, pg_num);
+		}
+	}
+	*reg = reg_addr;
+	return ret;
+}
+
+static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
+			   void *val, size_t val_size)
+{
+	struct device *dev = context;
+	struct aqt1000 *aqt = dev_get_drvdata(dev);
+	unsigned short c_reg, rreg;
+	int ret, i;
+
+	if (!aqt) {
+		dev_err(dev, "%s: aqt is NULL\n", __func__);
+		return -EINVAL;
+	}
+	if (!reg || !val) {
+		dev_err(dev, "%s: reg or val is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (reg_size != REG_BYTES) {
+		dev_err(dev, "%s: register size %zd bytes, not supported\n",
+			__func__, reg_size);
+		return -EINVAL;
+	}
+
+	mutex_lock(&aqt->io_lock);
+	c_reg = *(u16 *)reg;
+	rreg = c_reg;
+
+	ret = aqt_page_write(aqt, &c_reg);
+	if (ret)
+		goto err;
+	ret = aqt->read_dev(aqt, c_reg, val, val_size);
+	if (ret < 0)
+		dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
+			__func__, ret, rreg, val_size);
+	else {
+		for (i = 0; i < val_size; i++)
+			dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n",
+				__func__, ((u8 *)val)[i], rreg + i);
+	}
+err:
+	mutex_unlock(&aqt->io_lock);
+	return ret;
+}
+
+static int regmap_bus_gather_write(void *context,
+				   const void *reg, size_t reg_size,
+				   const void *val, size_t val_size)
+{
+	struct device *dev = context;
+	struct aqt1000 *aqt = dev_get_drvdata(dev);
+	unsigned short c_reg, rreg;
+	int ret, i;
+
+	if (!aqt) {
+		dev_err(dev, "%s: aqt is NULL\n", __func__);
+		return -EINVAL;
+	}
+	if (!reg || !val) {
+		dev_err(dev, "%s: reg or val is NULL\n", __func__);
+		return -EINVAL;
+	}
+	if (reg_size != REG_BYTES) {
+		dev_err(dev, "%s: register size %zd bytes, not supported\n",
+			__func__, reg_size);
+		return -EINVAL;
+	}
+	mutex_lock(&aqt->io_lock);
+	c_reg = *(u16 *)reg;
+	rreg = c_reg;
+
+	ret = aqt_page_write(aqt, &c_reg);
+	if (ret)
+		goto err;
+
+	for (i = 0; i < val_size; i++)
+		dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i],
+			rreg + i);
+
+	ret = aqt->write_dev(aqt, c_reg, (void *) val, val_size);
+	if (ret < 0)
+		dev_err(dev, "%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
+			__func__, ret, rreg, val_size);
+
+err:
+	mutex_unlock(&aqt->io_lock);
+	return ret;
+}
+
+static int regmap_bus_write(void *context, const void *data, size_t count)
+{
+	struct device *dev = context;
+	struct aqt1000 *aqt = dev_get_drvdata(dev);
+
+	if (!aqt)
+		return -EINVAL;
+
+	WARN_ON(count < REG_BYTES);
+
+	return regmap_bus_gather_write(context, data, REG_BYTES,
+					       data + REG_BYTES,
+					       count - REG_BYTES);
+}
+
+static struct regmap_bus regmap_bus_config = {
+	.write = regmap_bus_write,
+	.gather_write = regmap_bus_gather_write,
+	.read = regmap_bus_read,
+	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+/*
+ * aqt1000_regmap_init:
+ *	Initialize aqt1000 register map
+ *
+ * @dev: pointer to wcd device
+ * @config: pointer to register map config
+ *
+ * Returns pointer to regmap structure for success
+ * or NULL in case of failure.
+ */
+struct regmap *aqt1000_regmap_init(struct device *dev,
+				   const struct regmap_config *config)
+{
+	return devm_regmap_init(dev, &regmap_bus_config, dev, config);
+}
+EXPORT_SYMBOL(aqt1000_regmap_init);

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000-utils.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __WCD9XXX_UTILS_H__
+#define __WCD9XXX_UTILS_H__
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+struct regmap *aqt1000_regmap_init(struct device *dev,
+				   const struct regmap_config *config);
+#endif

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/aqt1000.h

@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef AQT1000_H
+#define AQT1000_H
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/i2c.h>
+#include "pdata.h"
+#include "aqt1000-clsh.h"
+
+#define AQT1000_MAX_MICBIAS 1
+#define AQT1000_NUM_INTERPOLATORS 2
+#define AQT1000_NUM_DECIMATORS 3
+#define  AQT1000_VOUT_CTL_TO_MICB(v)  (1000 + v * 50)
+#define AQT1000_RX_PATH_CTL_OFFSET 20
+
+#define AQT1000_CLK_24P576MHZ 24576000
+#define AQT1000_CLK_19P2MHZ 19200000
+#define AQT1000_CLK_12P288MHZ 12288000
+#define AQT1000_CLK_9P6MHZ 9600000
+
+#define AQT1000_ST_IIR_COEFF_MAX 5
+
+enum {
+	AQT1000_RX0 = 0,
+	AQT1000_RX1,
+	AQT1000_RX_MAX,
+};
+
+enum {
+	AQT_NONE,
+	AQT_MCLK,
+	AQT_RCO,
+};
+
+enum {
+	AQT_TX0 = 0,
+	AQT_TX1,
+};
+
+enum {
+	ASRC0,
+	ASRC1,
+	ASRC_MAX,
+};
+
+/* Each IIR has 5 Filter Stages */
+enum {
+	BAND1 = 0,
+	BAND2,
+	BAND3,
+	BAND4,
+	BAND5,
+	BAND_MAX,
+};
+
+enum {
+	AQT1000_TX0 = 0,
+	AQT1000_TX1,
+	AQT1000_TX2,
+	AQT1000_TX_MAX,
+};
+
+enum {
+	INTERP_HPHL,
+	INTERP_HPHR,
+	INTERP_MAX,
+};
+
+enum {
+	INTERP_MAIN_PATH,
+	INTERP_MIX_PATH,
+};
+
+enum {
+	COMPANDER_1, /* HPH_L */
+	COMPANDER_2, /* HPH_R */
+	COMPANDER_MAX,
+};
+
+enum {
+	AIF1_PB = 0,
+	AIF1_CAP,
+	NUM_CODEC_DAIS,
+};
+
+struct aqt_codec_dai_data {
+	u32 rate;
+	u32 *ch_num;
+	u32 ch_act;
+	u32 ch_tot;
+};
+
+struct aqt_idle_detect_config {
+	u8 hph_idle_thr;
+	u8 hph_idle_detect_en;
+};
+
+struct aqt1000_i2c {
+	struct i2c_client *client;
+	struct i2c_msg xfer_msg[2];
+	struct mutex xfer_lock;
+	int mod_id;
+};
+
+struct aqt1000_cdc_dai_data {
+	u32 rate;		/* sample rate */
+	u32 bit_width;		/* sit width 16,24,32 */
+	struct list_head ch_list;
+	wait_queue_head_t dai_wait;
+};
+
+struct tx_mute_work {
+	struct aqt1000 *aqt;
+	u8 decimator;
+	struct delayed_work dwork;
+};
+
+struct hpf_work {
+	struct aqt1000 *aqt;
+	u8 decimator;
+	u8 hpf_cut_off_freq;
+	struct delayed_work dwork;
+};
+
+struct aqt1000 {
+	struct device *dev;
+	struct mutex io_lock;
+	struct mutex xfer_lock;
+	struct mutex reset_lock;
+
+	struct device_node *aqt_rst_np;
+
+	int (*read_dev)(struct aqt1000 *aqt, unsigned short reg,
+			void *dest, int bytes);
+	int (*write_dev)(struct aqt1000 *aqt, unsigned short reg,
+			 void *src, int bytes);
+
+	u32 num_of_supplies;
+	struct regulator_bulk_data *supplies;
+
+	u32 mclk_rate;
+	struct regmap *regmap;
+	struct snd_soc_component *component;
+	bool dev_up;
+	bool prev_pg_valid;
+	u8 prev_pg;
+
+	struct aqt1000_i2c i2c_dev;
+
+	/* Codec params */
+
+	/* ANC related */
+	u32 anc_slot;
+	bool anc_func;
+
+	/* compander */
+	int comp_enabled[COMPANDER_MAX];
+
+	/* class h specific data */
+	struct aqt_clsh_cdc_data clsh_d;
+
+	/* Interpolator Mode Select for HPH_L and HPH_R */
+	u32 hph_mode;
+
+	unsigned long status_mask;
+
+	struct aqt1000_cdc_dai_data dai[NUM_CODEC_DAIS];
+
+	struct mutex micb_lock;
+
+	struct clk *ext_clk;
+
+	/* mbhc module */
+	struct aqt1000_mbhc *mbhc;
+
+	struct mutex codec_mutex;
+
+	/* cal info for codec */
+	struct fw_info *fw_data;
+
+	int native_clk_users;
+	/* ASRC users count */
+	int asrc_users[ASRC_MAX];
+	int asrc_output_mode[ASRC_MAX];
+	/* Main path clock users count */
+	int main_clk_users[AQT1000_NUM_INTERPOLATORS];
+
+	struct aqt_idle_detect_config idle_det_cfg;
+	u32 rx_bias_count;
+
+	s32 micb_ref;
+	s32 pullup_ref;
+	int master_bias_users;
+	int mclk_users;
+	int i2s_users;
+
+	struct hpf_work tx_hpf_work[AQT1000_NUM_DECIMATORS];
+	struct tx_mute_work tx_mute_dwork[AQT1000_NUM_DECIMATORS];
+
+	struct mutex master_bias_lock;
+	struct mutex cdc_bg_clk_lock;
+	struct mutex i2s_lock;
+
+	/* Interrupt */
+	struct regmap_irq_chip_data *irq_chip;
+	int num_irq_regs;
+	struct irq_domain *virq;
+	int irq;
+	int irq_base;
+
+	/* Entry for version info */
+	struct snd_info_entry *entry;
+	struct snd_info_entry *version_entry;
+};
+
+#endif /* AQT1000_H */

qcom/opensource/audio-kernel/asoc/codecs/aqt1000/pdata.h

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _AQT1000_PDATA_H_
+#define _AQT1000_PDATA_H_
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <asoc/msm-cdc-supply.h>
+
+struct aqt1000_micbias_setting {
+	u8 ldoh_v;
+	u32 cfilt1_mv;
+	u32 micb1_mv;
+	u8 bias1_cfilt_sel;
+};
+
+struct aqt1000_pdata {
+	unsigned int irq_gpio;
+	unsigned int irq_flags;
+	struct cdc_regulator *regulator;
+	int num_supplies;
+	struct aqt1000_micbias_setting micbias;
+	struct device_node *aqt_rst_np;
+	u32 mclk_rate;
+	u32 ext_clk_rate;
+	u32 ext_1p8v_supply;
+};
+
+#endif /* _AQT1000_PDATA_H_ */

qcom/opensource/audio-kernel/asoc/codecs/audio-ext-clk-up.c

@@ -0,0 +1,773 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <bindings/qcom,audio-ext-clk.h>
+#include <linux/ratelimit.h>
+#ifdef CONFIG_AUDIO_PRM
+#include <dsp/audio_prm.h>
+#else
+#include "audio-ext-clk-up.h"
+#endif
+enum {
+	AUDIO_EXT_CLK_PMI,
+	AUDIO_EXT_CLK_LNBB2,
+	AUDIO_EXT_CLK_LPASS,
+	AUDIO_EXT_CLK_LPASS2,
+	AUDIO_EXT_CLK_LPASS3,
+	AUDIO_EXT_CLK_LPASS4,
+	AUDIO_EXT_CLK_LPASS5,
+	AUDIO_EXT_CLK_LPASS6,
+	AUDIO_EXT_CLK_LPASS7,
+	AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE,
+	AUDIO_EXT_CLK_LPASS8,
+	AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE,
+	AUDIO_EXT_CLK_LPASS9,
+	AUDIO_EXT_CLK_LPASS10,
+	AUDIO_EXT_CLK_LPASS11,
+	AUDIO_EXT_CLK_LPASS12,
+	AUDIO_EXT_CLK_LPASS13,
+	AUDIO_EXT_CLK_LPASS14,
+	AUDIO_EXT_CLK_LPASS15,
+	AUDIO_EXT_CLK_LPASS16,
+	AUDIO_EXT_CLK_LPASS_MAX,
+	AUDIO_EXT_CLK_EXTERNAL_PLL = AUDIO_EXT_CLK_LPASS_MAX,
+	AUDIO_EXT_CLK_MAX,
+};
+
+struct pinctrl_info {
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *sleep;
+	struct pinctrl_state *active;
+	char __iomem *base;
+};
+
+struct audio_ext_clk {
+	struct pinctrl_info pnctrl_info;
+	struct clk_fixed_factor fact;
+};
+
+struct audio_ext_clk_priv {
+	struct device *dev;
+	int clk_src;
+	uint32_t enable;
+#ifdef CONFIG_AUDIO_PRM
+	struct clk_cfg prm_clk_cfg;
+#endif
+	struct audio_ext_clk audio_clk;
+	const char *clk_name;
+	uint32_t lpass_core_hwvote_client_handle;
+	uint32_t lpass_audio_hwvote_client_handle;
+};
+
+static inline struct audio_ext_clk_priv *to_audio_clk(struct clk_hw *hw)
+{
+	return container_of(hw, struct audio_ext_clk_priv, audio_clk.fact.hw);
+}
+
+static int audio_ext_clk_prepare(struct clk_hw *hw)
+{
+	struct audio_ext_clk_priv *clk_priv = to_audio_clk(hw);
+	struct pinctrl_info *pnctrl_info = &clk_priv->audio_clk.pnctrl_info;
+	int ret;
+	static DEFINE_RATELIMIT_STATE(rtl, 1 * HZ, 1);
+
+	if ((clk_priv->clk_src >= AUDIO_EXT_CLK_LPASS) &&
+		(clk_priv->clk_src < AUDIO_EXT_CLK_LPASS_MAX) && !clk_priv->enable)  {
+#ifdef CONFIG_AUDIO_PRM
+	    pr_debug("%s: clk_id %x ", __func__, clk_priv->prm_clk_cfg.clk_id);
+		ret = audio_prm_set_lpass_clk_cfg(&clk_priv->prm_clk_cfg,1);
+#else
+		pr_debug("%s: audio prm not enabled", __func__);
+		ret = -EPERM;
+#endif
+		if (ret < 0) {
+			if (__ratelimit(&rtl))
+				pr_err_ratelimited("%s prm set lpass clk failed\n",
+				__func__);
+			return ret;
+		}
+		clk_priv->enable = 1;
+	}
+
+	if (pnctrl_info->pinctrl) {
+		ret = pinctrl_select_state(pnctrl_info->pinctrl,
+				pnctrl_info->active);
+		if (ret) {
+			pr_err("%s: active state select failed with %d\n",
+				__func__, ret);
+			return -EIO;
+		}
+	}
+
+	if (pnctrl_info->base)
+		iowrite32(1, pnctrl_info->base);
+	return 0;
+}
+
+static void audio_ext_clk_unprepare(struct clk_hw *hw)
+{
+	struct audio_ext_clk_priv *clk_priv = to_audio_clk(hw);
+	struct pinctrl_info *pnctrl_info = &clk_priv->audio_clk.pnctrl_info;
+	int ret;
+	static DEFINE_RATELIMIT_STATE(rtl, 1 * HZ, 1);
+
+	if (pnctrl_info->pinctrl) {
+		ret = pinctrl_select_state(pnctrl_info->pinctrl,
+					   pnctrl_info->sleep);
+		if (ret) {
+			pr_err("%s: active state select failed with %d\n",
+				__func__, ret);
+			return;
+		}
+	}
+
+	if ((clk_priv->clk_src >= AUDIO_EXT_CLK_LPASS) &&
+		(clk_priv->clk_src < AUDIO_EXT_CLK_LPASS_MAX))  {
+		clk_priv->enable = 0;
+#ifdef CONFIG_AUDIO_PRM
+		pr_debug("%s: clk_id %x", __func__,
+				clk_priv->prm_clk_cfg.clk_id);
+		ret = audio_prm_set_lpass_clk_cfg(&clk_priv->prm_clk_cfg, 0);
+#else
+		pr_debug("%s: audio prm not enabled", __func__);
+		ret = -EPERM;
+#endif
+		if (ret < 0) {
+			if (__ratelimit(&rtl))
+				pr_err_ratelimited("%s: unset lpass clk cfg failed, ret = %d\n",
+				__func__, ret);
+		}
+	}
+
+	if (pnctrl_info->base)
+		iowrite32(0, pnctrl_info->base);
+}
+
+static u8 audio_ext_clk_get_parent(struct clk_hw *hw)
+{
+	struct audio_ext_clk_priv *clk_priv = to_audio_clk(hw);
+	int num_parents = clk_hw_get_num_parents(hw);
+	const char * const *parent_names = hw->init->parent_names;
+	u8 i = 0, ret = hw->init->num_parents + 1;
+
+	if ((clk_priv->clk_src == AUDIO_EXT_CLK_PMI) && clk_priv->clk_name) {
+		for (i = 0; i < num_parents; i++) {
+			if (!strcmp(parent_names[i], clk_priv->clk_name))
+				ret = i;
+		}
+		pr_debug("%s: parent index = %u\n", __func__, ret);
+		return ret;
+	} else
+		return 0;
+}
+
+static int lpass_hw_vote_prepare(struct clk_hw *hw)
+{
+	struct audio_ext_clk_priv *clk_priv = to_audio_clk(hw);
+	int ret;
+	static DEFINE_RATELIMIT_STATE(rtl, 1 * HZ, 1);
+
+	if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE)  {
+#ifdef CONFIG_AUDIO_PRM
+		pr_debug("%s: core vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
+		ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
+			HW_CORE_ID_LPASS, 1);
+#else
+		pr_debug("%s: audio prm not enabled", __func__);
+		ret = -EPERM;
+#endif
+		if (ret < 0) {
+			if (__ratelimit(&rtl))
+				pr_err("%s lpass core hw vote failed %d\n",
+					__func__, ret);
+			return ret;
+		}
+	}
+
+	if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE)  {
+#ifdef CONFIG_AUDIO_PRM
+		pr_debug("%s: audio vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
+		ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
+			HW_CORE_ID_DCODEC, 1);
+#else
+		pr_debug("%s: audio prm not enabled", __func__);
+		ret = -EPERM;
+#endif
+		if (ret < 0) {
+			if (__ratelimit(&rtl))
+				pr_err("%s lpass audio hw vote failed %d\n",
+				__func__, ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static void lpass_hw_vote_unprepare(struct clk_hw *hw)
+{
+	struct audio_ext_clk_priv *clk_priv = to_audio_clk(hw);
+	int ret = 0;
+
+	if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE) {
+#ifdef CONFIG_AUDIO_PRM
+		pr_debug("%s: core vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
+		ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
+				HW_CORE_ID_LPASS, 0);
+#else
+		pr_debug("%s: audio prm not enabled", __func__);
+		ret = -EPERM;
+#endif
+		if (ret < 0) {
+			pr_err("%s lpass core hw vote failed %d\n",
+				__func__, ret);
+		}
+	}
+
+	if (clk_priv->clk_src == AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE) {
+
+#ifdef CONFIG_AUDIO_PRM
+		pr_debug("%s: audio vote clk_id %x \n", __func__, clk_priv->prm_clk_cfg.clk_id);
+		ret = audio_prm_set_lpass_hw_core_req(&clk_priv->prm_clk_cfg,
+				HW_CORE_ID_DCODEC, 0);
+#else
+		pr_debug("%s: audio prm not enabled", __func__);
+		ret = -EPERM;
+#endif
+		if (ret < 0) {
+			pr_err("%s lpass audio hw unvote failed %d\n",
+				__func__, ret);
+		}
+	}
+}
+
+static const struct clk_ops audio_ext_clk_ops = {
+	.prepare = audio_ext_clk_prepare,
+	.unprepare = audio_ext_clk_unprepare,
+	.get_parent = audio_ext_clk_get_parent,
+};
+
+static const struct clk_ops lpass_hw_vote_ops = {
+	.prepare = lpass_hw_vote_prepare,
+	.unprepare = lpass_hw_vote_unprepare,
+};
+
+static const char * const audio_ext_pmi_div_clk[] = {
+	"qpnp_clkdiv_1",
+	"pms405_div_clk1",
+	"pm6150_div_clk1",
+	"pm6125_div_clk1",
+};
+
+static int audio_ext_clk_dummy_prepare(struct clk_hw *hw)
+{
+	return 0;
+}
+
+static void audio_ext_clk_dummy_unprepare(struct clk_hw *hw)
+{
+
+}
+
+static const struct clk_ops audio_ext_clk_dummy_ops = {
+	.prepare = audio_ext_clk_dummy_prepare,
+	.unprepare = audio_ext_clk_dummy_unprepare,
+};
+
+static struct audio_ext_clk audio_clk_array[] = {
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_ext_pmi_clk",
+				.parent_names = audio_ext_pmi_div_clk,
+				.num_parents =
+					 ARRAY_SIZE(audio_ext_pmi_div_clk),
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_ext_pmi_lnbb_clk",
+				.parent_names = (const char *[])
+							{ "ln_bb_clk2" },
+				.num_parents = 1,
+				.ops = &audio_ext_clk_dummy_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk2",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk3",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk4",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk5",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk6",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk7",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.hw.init = &(struct clk_init_data){
+				.name = "lpass_hw_vote_clk",
+				.ops = &lpass_hw_vote_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk8",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.hw.init = &(struct clk_init_data){
+				.name = "lpass_audio_hw_vote_clk",
+				.ops = &lpass_hw_vote_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk9",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk10",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk11",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk12",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk13",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk14",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk15",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk16",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_external_pll_clk",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+};
+
+static int audio_get_pinctrl(struct platform_device *pdev)
+{
+	struct device *dev =  &pdev->dev;
+	struct audio_ext_clk_priv *clk_priv = platform_get_drvdata(pdev);
+	struct pinctrl_info *pnctrl_info;
+	struct pinctrl *pinctrl;
+	int ret;
+	u32 reg;
+
+	pnctrl_info = &clk_priv->audio_clk.pnctrl_info;
+	if (pnctrl_info->pinctrl) {
+		dev_err(dev, "%s: already requested before\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	pinctrl = devm_pinctrl_get(dev);
+	if (IS_ERR_OR_NULL(pinctrl)) {
+		dev_err(dev, "%s: Unable to get pinctrl handle\n",
+			__func__);
+		return -EINVAL;
+	}
+	pnctrl_info->pinctrl = pinctrl;
+	/* get all state handles from Device Tree */
+	pnctrl_info->sleep = pinctrl_lookup_state(pinctrl, "sleep");
+	if (IS_ERR(pnctrl_info->sleep)) {
+		dev_err(dev, "%s: could not get sleep pinstate\n",
+			__func__);
+		goto err;
+	}
+	pnctrl_info->active = pinctrl_lookup_state(pinctrl, "active");
+	if (IS_ERR(pnctrl_info->active)) {
+		dev_err(dev, "%s: could not get active pinstate\n",
+			__func__);
+		goto err;
+	}
+	/* Reset the TLMM pins to a default state */
+	ret = pinctrl_select_state(pnctrl_info->pinctrl,
+				   pnctrl_info->sleep);
+	if (ret) {
+		dev_err(dev, "%s: Disable TLMM pins failed with %d\n",
+			__func__, ret);
+		goto err;
+	}
+
+	ret = of_property_read_u32(dev->of_node, "qcom,mclk-clk-reg", &reg);
+	if (ret < 0) {
+		dev_dbg(dev, "%s: miss mclk reg\n", __func__);
+	} else {
+		pnctrl_info->base = ioremap(reg, sizeof(u32));
+		if (pnctrl_info->base ==  NULL) {
+			dev_err(dev, "%s ioremap failed\n", __func__);
+			goto err;
+		}
+	}
+
+	return 0;
+
+err:
+	devm_pinctrl_put(pnctrl_info->pinctrl);
+	return -EINVAL;
+}
+
+static int audio_put_pinctrl(struct platform_device *pdev)
+{
+	struct audio_ext_clk_priv *clk_priv = platform_get_drvdata(pdev);
+	struct pinctrl_info *pnctrl_info = NULL;
+
+	pnctrl_info = &clk_priv->audio_clk.pnctrl_info;
+	if (pnctrl_info && pnctrl_info->pinctrl) {
+		devm_pinctrl_put(pnctrl_info->pinctrl);
+		pnctrl_info->pinctrl = NULL;
+	}
+
+	return 0;
+}
+
+static int audio_get_clk_data(struct platform_device *pdev)
+{
+	int ret;
+	struct clk *audio_clk;
+	struct clk_hw *clkhw;
+	struct clk_onecell_data *clk_data;
+	struct audio_ext_clk_priv *clk_priv = platform_get_drvdata(pdev);
+
+	clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	clk_data->clk_num = 1;
+	clk_data->clks = devm_kzalloc(&pdev->dev,
+				sizeof(struct clk *),
+				GFP_KERNEL);
+	if (!clk_data->clks)
+		return -ENOMEM;
+
+	clkhw = &clk_priv->audio_clk.fact.hw;
+	audio_clk = devm_clk_register(&pdev->dev, clkhw);
+	if (IS_ERR(audio_clk)) {
+		dev_err(&pdev->dev,
+			"%s: clock register failed for clk_src = %d\\n",
+			__func__, clk_priv->clk_src);
+		ret = PTR_ERR(audio_clk);
+		return ret;
+	}
+	clk_data->clks[0] = audio_clk;
+
+	ret = of_clk_add_provider(pdev->dev.of_node,
+			 of_clk_src_onecell_get, clk_data);
+	if (ret)
+		dev_err(&pdev->dev, "%s: clock add failed for clk_src = %d\n",
+			__func__, clk_priv->clk_src);
+
+	return ret;
+}
+
+static int audio_ref_clk_probe(struct platform_device *pdev)
+{
+	int ret;
+	struct audio_ext_clk_priv *clk_priv;
+	u32 clk_freq = 0, clk_id = 0, clk_src = 0, use_pinctrl = 0;
+
+	clk_priv = devm_kzalloc(&pdev->dev, sizeof(*clk_priv), GFP_KERNEL);
+	if (!clk_priv)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(pdev->dev.of_node,
+			"qcom,codec-ext-clk-src",
+			&clk_src);
+	if (ret) {
+		dev_err(&pdev->dev, "%s: could not get clk source, ret = %d\n",
+				__func__, ret);
+		return ret;
+	}
+
+	if (clk_src >= AUDIO_EXT_CLK_MAX) {
+		dev_err(&pdev->dev, "%s: Invalid clk source = %d\n",
+				__func__, clk_src);
+		return -EINVAL;
+	}
+	clk_priv->clk_name = NULL;
+	clk_priv->clk_src = clk_src;
+	memcpy(&clk_priv->audio_clk, &audio_clk_array[clk_src],
+		   sizeof(struct audio_ext_clk));
+
+#ifdef CONFIG_AUDIO_PRM
+	/* Init prm clk cfg default values */
+	clk_priv->prm_clk_cfg.clk_id = CLOCK_ID_QUI_MI2S_OSR;
+	clk_priv->prm_clk_cfg.clk_freq_in_hz = OSR_CLOCK_9_P600_MHZ;
+	clk_priv->prm_clk_cfg.clk_attri = CLOCK_ATTRIBUTE_COUPLE_NO;
+	clk_priv->prm_clk_cfg.clk_root = 0;
+#endif
+
+	ret = of_property_read_u32(pdev->dev.of_node,
+			"qcom,codec-lpass-ext-clk-freq",
+			&clk_freq);
+	if (!ret) {
+#ifdef CONFIG_AUDIO_PRM
+		clk_priv->prm_clk_cfg.clk_freq_in_hz = clk_freq;
+#endif
+	}
+
+	ret = of_property_read_u32(pdev->dev.of_node,
+			"qcom,codec-lpass-clk-id",
+			&clk_id);
+	if (!ret) {
+#ifdef CONFIG_AUDIO_PRM
+		clk_priv->prm_clk_cfg.clk_id = clk_id;
+		dev_dbg(&pdev->dev, "%s: PRM ext-clk freq: %d, lpass clk_id: %d, clk_src: %d\n",
+			__func__, clk_priv->prm_clk_cfg.clk_freq_in_hz,
+			clk_priv->prm_clk_cfg.clk_id, clk_priv->clk_src);
+#endif
+	}
+
+        dev_dbg(&pdev->dev, "%s: PRM2 ext-clk freq: %d, lpass clk_id: %d, clk_src: %d\n",
+                        __func__, clk_priv->prm_clk_cfg.clk_freq_in_hz,
+                        clk_priv->prm_clk_cfg.clk_id, clk_priv->clk_src);
+
+	platform_set_drvdata(pdev, clk_priv);
+
+	ret = of_property_read_string(pdev->dev.of_node, "pmic-clock-names",
+				      &clk_priv->clk_name);
+	if (ret)
+		dev_dbg(&pdev->dev, "%s: could not find pmic clock names\n",
+			__func__);
+	/*
+	 * property qcom,use-pinctrl to be defined in DTSI to val 1
+	 * for clock nodes using pinctrl
+	 */
+	of_property_read_u32(pdev->dev.of_node, "qcom,use-pinctrl",
+			     &use_pinctrl);
+	dev_dbg(&pdev->dev, "%s: use-pinctrl : %d\n",
+		__func__, use_pinctrl);
+
+	if (use_pinctrl) {
+		ret = audio_get_pinctrl(pdev);
+		if (ret) {
+			dev_err(&pdev->dev, "%s: Parsing PMI pinctrl failed\n",
+				__func__);
+			return ret;
+		}
+	}
+
+	ret = audio_get_clk_data(pdev);
+	if (ret) {
+		dev_err(&pdev->dev, "%s: clk_init is failed\n",
+			__func__);
+		audio_put_pinctrl(pdev);
+		return ret;
+	}
+	return 0;
+}
+
+static int audio_ref_clk_remove(struct platform_device *pdev)
+{
+	audio_put_pinctrl(pdev);
+
+	return 0;
+}
+
+static const struct of_device_id audio_ref_clk_match[] = {
+	{.compatible = "qcom,audio-ref-clk"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, audio_ref_clk_match);
+
+static struct platform_driver audio_ref_clk_driver = {
+	.driver = {
+		.name = "audio-ref-clk",
+		.owner = THIS_MODULE,
+		.of_match_table = audio_ref_clk_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = audio_ref_clk_probe,
+	.remove = audio_ref_clk_remove,
+};
+
+int audio_ref_clk_platform_init(void)
+{
+	return platform_driver_register(&audio_ref_clk_driver);
+}
+
+void audio_ref_clk_platform_exit(void)
+{
+	platform_driver_unregister(&audio_ref_clk_driver);
+}
+
+MODULE_DESCRIPTION("Audio Ref Up Clock module platform driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/audio-ext-clk-up.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __AUDIO_EXT_CLK_UP_H_
+#define __AUDIO_EXT_CLK_UP_H_
+
+int audio_ref_clk_platform_init(void);
+void audio_ref_clk_platform_exit(void);
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/audio-ext-clk.c

@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2015-2017, 2019 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/clk/msm-clk-provider.h>
+#include <linux/clk/msm-clk.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <dt-bindings/clock/audio-ext-clk.h>
+#include <sound/q6afe-v2.h>
+#include "audio-ext-clk-up.h"
+
+struct pinctrl_info {
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *sleep;
+	struct pinctrl_state *active;
+};
+
+struct audio_ext_ap_clk {
+	bool enabled;
+	int gpio;
+	struct clk c;
+};
+
+struct audio_ext_pmi_clk {
+	int gpio;
+	struct clk c;
+};
+
+struct audio_ext_ap_clk2 {
+	bool enabled;
+	struct pinctrl_info pnctrl_info;
+	struct clk c;
+};
+
+static struct afe_clk_set clk2_config = {
+	Q6AFE_LPASS_CLK_CONFIG_API_VERSION,
+	Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR,
+	Q6AFE_LPASS_IBIT_CLK_11_P2896_MHZ,
+	Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
+	Q6AFE_LPASS_CLK_ROOT_DEFAULT,
+	0,
+};
+
+static inline struct audio_ext_ap_clk *to_audio_ap_clk(struct clk *clk)
+{
+	return container_of(clk, struct audio_ext_ap_clk, c);
+}
+
+static int audio_ext_clk_prepare(struct clk *clk)
+{
+	struct audio_ext_ap_clk *audio_clk = to_audio_ap_clk(clk);
+
+	pr_debug("%s: gpio: %d\n", __func__, audio_clk->gpio);
+	if (gpio_is_valid(audio_clk->gpio))
+		return gpio_direction_output(audio_clk->gpio, 1);
+	return 0;
+}
+
+static void audio_ext_clk_unprepare(struct clk *clk)
+{
+	struct audio_ext_ap_clk *audio_clk = to_audio_ap_clk(clk);
+
+	pr_debug("%s: gpio: %d\n", __func__, audio_clk->gpio);
+	if (gpio_is_valid(audio_clk->gpio))
+		gpio_direction_output(audio_clk->gpio, 0);
+}
+
+static inline struct audio_ext_ap_clk2 *to_audio_ap_clk2(struct clk *clk)
+{
+	return container_of(clk, struct audio_ext_ap_clk2, c);
+}
+
+static int audio_ext_clk2_prepare(struct clk *clk)
+{
+	struct audio_ext_ap_clk2 *audio_clk2 = to_audio_ap_clk2(clk);
+	struct pinctrl_info *pnctrl_info = &audio_clk2->pnctrl_info;
+	int ret;
+
+
+	if (!pnctrl_info->pinctrl || !pnctrl_info->active)
+		return 0;
+
+	ret = pinctrl_select_state(pnctrl_info->pinctrl,
+				   pnctrl_info->active);
+	if (ret) {
+		pr_err("%s: active state select failed with %d\n",
+			__func__, ret);
+		return -EIO;
+	}
+
+	clk2_config.enable = 1;
+	ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk2_config);
+	if (ret < 0) {
+		pr_err("%s: failed to set clock, ret = %d\n", __func__, ret);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void audio_ext_clk2_unprepare(struct clk *clk)
+{
+	struct audio_ext_ap_clk2 *audio_clk2 = to_audio_ap_clk2(clk);
+	struct pinctrl_info *pnctrl_info = &audio_clk2->pnctrl_info;
+	int ret;
+
+	if (!pnctrl_info->pinctrl || !pnctrl_info->sleep)
+		return;
+
+	ret = pinctrl_select_state(pnctrl_info->pinctrl,
+				   pnctrl_info->sleep);
+	if (ret)
+		pr_err("%s: sleep state select failed with %d\n",
+			__func__, ret);
+
+	clk2_config.enable = 0;
+	ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk2_config);
+	if (ret < 0)
+		pr_err("%s: failed to reset clock, ret = %d\n", __func__, ret);
+}
+
+static const struct clk_ops audio_ext_ap_clk_ops = {
+	.prepare = audio_ext_clk_prepare,
+	.unprepare = audio_ext_clk_unprepare,
+};
+
+static const struct clk_ops audio_ext_ap_clk2_ops = {
+	.prepare = audio_ext_clk2_prepare,
+	.unprepare = audio_ext_clk2_unprepare,
+};
+
+static struct audio_ext_pmi_clk audio_pmi_clk = {
+	.gpio = -EINVAL,
+	.c = {
+		.dbg_name = "audio_ext_pmi_clk",
+		.ops = &clk_ops_dummy,
+		CLK_INIT(audio_pmi_clk.c),
+	},
+};
+
+static struct audio_ext_pmi_clk audio_pmi_lnbb_clk = {
+	.gpio = -EINVAL,
+	.c = {
+		.dbg_name = "audio_ext_pmi_lnbb_clk",
+		.ops = &clk_ops_dummy,
+		CLK_INIT(audio_pmi_lnbb_clk.c),
+	},
+};
+
+static struct audio_ext_ap_clk audio_ap_clk = {
+	.gpio = -EINVAL,
+	.c = {
+		.dbg_name = "audio_ext_ap_clk",
+		.ops = &audio_ext_ap_clk_ops,
+		CLK_INIT(audio_ap_clk.c),
+	},
+};
+
+static struct audio_ext_ap_clk2 audio_ap_clk2 = {
+	.c = {
+		.dbg_name = "audio_ext_ap_clk2",
+		.ops = &audio_ext_ap_clk2_ops,
+		CLK_INIT(audio_ap_clk2.c),
+	},
+};
+
+static struct clk_lookup audio_ref_clock[] = {
+	CLK_LIST(audio_ap_clk),
+	CLK_LIST(audio_pmi_clk),
+	CLK_LIST(audio_pmi_lnbb_clk),
+	CLK_LIST(audio_ap_clk2),
+};
+
+static int audio_get_pinctrl(struct platform_device *pdev)
+{
+	struct pinctrl_info *pnctrl_info;
+	struct pinctrl *pinctrl;
+	int ret;
+
+	pnctrl_info = &audio_ap_clk2.pnctrl_info;
+
+	if (pnctrl_info->pinctrl) {
+		dev_dbg(&pdev->dev, "%s: already requested before\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (IS_ERR_OR_NULL(pinctrl)) {
+		dev_dbg(&pdev->dev, "%s: Unable to get pinctrl handle\n",
+			__func__);
+		return -EINVAL;
+	}
+	pnctrl_info->pinctrl = pinctrl;
+	/* get all state handles from Device Tree */
+	pnctrl_info->sleep = pinctrl_lookup_state(pinctrl, "sleep");
+	if (IS_ERR(pnctrl_info->sleep)) {
+		dev_err(&pdev->dev, "%s: could not get sleep pinstate\n",
+			__func__);
+		goto err;
+	}
+	pnctrl_info->active = pinctrl_lookup_state(pinctrl, "active");
+	if (IS_ERR(pnctrl_info->active)) {
+		dev_err(&pdev->dev, "%s: could not get active pinstate\n",
+			__func__);
+		goto err;
+	}
+	/* Reset the TLMM pins to a default state */
+	ret = pinctrl_select_state(pnctrl_info->pinctrl,
+				   pnctrl_info->sleep);
+	if (ret) {
+		dev_err(&pdev->dev, "%s: Disable TLMM pins failed with %d\n",
+			__func__, ret);
+		goto err;
+	}
+	return 0;
+
+err:
+	devm_pinctrl_put(pnctrl_info->pinctrl);
+	return -EINVAL;
+}
+
+static int audio_ref_clk_probe(struct platform_device *pdev)
+{
+	int clk_gpio;
+	int ret;
+	struct clk *audio_clk;
+
+	clk_gpio = of_get_named_gpio(pdev->dev.of_node,
+				     "qcom,audio-ref-clk-gpio", 0);
+	if (clk_gpio > 0) {
+		ret = gpio_request(clk_gpio, "EXT_CLK");
+		if (ret) {
+			dev_err(&pdev->dev,
+				"Request ext clk gpio failed %d, err:%d\n",
+				clk_gpio, ret);
+			goto err;
+		}
+		if (of_property_read_bool(pdev->dev.of_node,
+					"qcom,node_has_rpm_clock")) {
+			audio_clk = clk_get(&pdev->dev, NULL);
+			if (IS_ERR(audio_clk)) {
+				dev_err(&pdev->dev, "Failed to get RPM div clk\n");
+				ret = PTR_ERR(audio_clk);
+				goto err_gpio;
+			}
+			audio_pmi_clk.c.parent = audio_clk;
+			audio_pmi_clk.gpio = clk_gpio;
+		} else
+			audio_ap_clk.gpio = clk_gpio;
+
+	} else {
+		if (of_property_read_bool(pdev->dev.of_node,
+					"qcom,node_has_rpm_clock")) {
+			audio_clk = clk_get(&pdev->dev, NULL);
+			if (IS_ERR(audio_clk)) {
+				dev_err(&pdev->dev, "Failed to get lnbbclk2\n");
+				ret = PTR_ERR(audio_clk);
+				goto err;
+			}
+			audio_pmi_lnbb_clk.c.parent = audio_clk;
+			audio_pmi_lnbb_clk.gpio = -EINVAL;
+		}
+	}
+
+	ret = audio_get_pinctrl(pdev);
+	if (ret)
+		dev_dbg(&pdev->dev, "%s: Parsing pinctrl failed\n",
+			__func__);
+
+	ret = of_msm_clock_register(pdev->dev.of_node, audio_ref_clock,
+			      ARRAY_SIZE(audio_ref_clock));
+	if (ret) {
+		dev_err(&pdev->dev, "%s: audio ref clock register failed\n",
+			__func__);
+		goto err_gpio;
+	}
+
+	return 0;
+
+err_gpio:
+	gpio_free(clk_gpio);
+
+err:
+	return ret;
+}
+
+static int audio_ref_clk_remove(struct platform_device *pdev)
+{
+	struct pinctrl_info *pnctrl_info = &audio_ap_clk2.pnctrl_info;
+
+	if (audio_pmi_clk.gpio > 0)
+		gpio_free(audio_pmi_clk.gpio);
+	else if (audio_ap_clk.gpio > 0)
+		gpio_free(audio_ap_clk.gpio);
+
+	if (pnctrl_info->pinctrl) {
+		devm_pinctrl_put(pnctrl_info->pinctrl);
+		pnctrl_info->pinctrl = NULL;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id audio_ref_clk_match[] = {
+	{.compatible = "qcom,audio-ref-clk"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, audio_ref_clk_match);
+
+static struct platform_driver audio_ref_clk_driver = {
+	.driver = {
+		.name = "audio-ref-clk",
+		.owner = THIS_MODULE,
+		.of_match_table = audio_ref_clk_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = audio_ref_clk_probe,
+	.remove = audio_ref_clk_remove,
+};
+
+int audio_ref_clk_platform_init(void)
+{
+	return platform_driver_register(&audio_ref_clk_driver);
+}
+
+void audio_ref_clk_platform_exit(void)
+{
+	platform_driver_unregister(&audio_ref_clk_driver);
+}
+
+MODULE_DESCRIPTION("Audio Ref Clock module platform driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/bolero/Kbuild

@@ -0,0 +1,163 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_SM6150), y)
+		include $(AUDIO_ROOT)/config/sm6150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_TRINKET), y)
+		include $(AUDIO_ROOT)/config/sm6150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KONA), y)
+		include $(AUDIO_ROOT)/config/konaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/konaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_WAIPIO), y)
+		include $(AUDIO_ROOT)/config/waipioauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/waipioautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_HOLI), y)
+		include $(AUDIO_ROOT)/config/holiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/holiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_BLAIR), y)
+		include $(AUDIO_ROOT)/config/holiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/holiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_LITO), y)
+		include $(AUDIO_ROOT)/config/litoauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/litoautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KHAJE), y)
+		include $(AUDIO_ROOT)/config/bengalauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/bengalautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_QCS405), y)
+		include $(AUDIO_ROOT)/config/qcs405auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/qcs405autoconf.h
+	endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ BOLERO ############
+
+# for BOLERO Codec
+ifdef CONFIG_SND_SOC_BOLERO
+	BOLERO_OBJS += bolero-cdc.o
+	BOLERO_OBJS += bolero-cdc-utils.o
+	BOLERO_OBJS += bolero-cdc-regmap.o
+	BOLERO_OBJS += bolero-cdc-tables.o
+	BOLERO_OBJS += bolero-clk-rsc.o
+endif
+
+ifdef CONFIG_WSA_MACRO
+	WSA_OBJS += wsa-macro.o
+endif
+
+ifdef CONFIG_VA_MACRO
+	VA_OBJS += va-macro.o
+endif
+
+ifdef CONFIG_TX_MACRO
+	TX_OBJS += tx-macro.o
+endif
+
+ifdef CONFIG_RX_MACRO
+	RX_OBJS += rx-macro.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+EXTRA_CFLAGS += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_BOLERO) += bolero_cdc_dlkm.o
+bolero_cdc_dlkm-y := $(BOLERO_OBJS)
+
+obj-$(CONFIG_WSA_MACRO) += wsa_macro_dlkm.o
+wsa_macro_dlkm-y := $(WSA_OBJS)
+
+obj-$(CONFIG_VA_MACRO) += va_macro_dlkm.o
+va_macro_dlkm-y := $(VA_OBJS)
+
+obj-$(CONFIG_TX_MACRO) += tx_macro_dlkm.o
+tx_macro_dlkm-y := $(TX_OBJS)
+
+obj-$(CONFIG_RX_MACRO) += rx_macro_dlkm.o
+rx_macro_dlkm-y := $(RX_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/codecs/bolero/Makefile

@@ -0,0 +1,6 @@
+modules:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

qcom/opensource/audio-kernel/asoc/codecs/bolero/bolero-cdc-registers.h

@@ -0,0 +1,844 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _BOLERO_CDC_REGISTERS_H
+#define _BOLERO_CDC_REGISTERS_H
+
+#define TX_START_OFFSET 0x0000
+
+#define BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (TX_START_OFFSET + 0x0000)
+#define BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (TX_START_OFFSET + 0x0004)
+#define BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL	(TX_START_OFFSET + 0x0008)
+#define BOLERO_CDC_TX_TOP_CSR_TOP_CFG0		(TX_START_OFFSET + 0x0080)
+#define BOLERO_CDC_TX_TOP_CSR_ANC_CFG		(TX_START_OFFSET + 0x0084)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_CTRL		(TX_START_OFFSET + 0x0088)
+#define BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK		(TX_START_OFFSET + 0x0090)
+#define BOLERO_CDC_TX_TOP_CSR_DEBUG_BUS		(TX_START_OFFSET + 0x0094)
+#define BOLERO_CDC_TX_TOP_CSR_DEBUG_EN		(TX_START_OFFSET + 0x0098)
+#define BOLERO_CDC_TX_TOP_CSR_TX_I2S_CTL	(TX_START_OFFSET + 0x00A4)
+#define BOLERO_CDC_TX_TOP_CSR_I2S_CLK		(TX_START_OFFSET + 0x00A8)
+#define BOLERO_CDC_TX_TOP_CSR_I2S_RESET		(TX_START_OFFSET + 0x00AC)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL	(TX_START_OFFSET + 0x00C0)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC1_CTL	(TX_START_OFFSET + 0x00C4)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC2_CTL	(TX_START_OFFSET + 0x00C8)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC3_CTL	(TX_START_OFFSET + 0x00CC)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_AMIC0_CTL	(TX_START_OFFSET + 0x00D0)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_AMIC1_CTL	(TX_START_OFFSET + 0x00D4)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_MIC2_CTL	(TX_START_OFFSET + 0x00C0)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_MIC3_CTL	(TX_START_OFFSET + 0x00C4)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_MIC4_CTL	(TX_START_OFFSET + 0x00C8)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_MIC5_CTL	(TX_START_OFFSET + 0x00CC)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_MIC0_CTL	(TX_START_OFFSET + 0x00D0)
+#define BOLERO_CDC_TX_TOP_CSR_SWR_MIC1_CTL	(TX_START_OFFSET + 0x00D4)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0	(TX_START_OFFSET + 0x0100)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1	(TX_START_OFFSET + 0x0104)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0	(TX_START_OFFSET + 0x0108)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1	(TX_START_OFFSET + 0x010C)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0	(TX_START_OFFSET + 0x0110)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1	(TX_START_OFFSET + 0x0114)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0	(TX_START_OFFSET + 0x0118)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1	(TX_START_OFFSET + 0x011C)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0	(TX_START_OFFSET + 0x0120)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1	(TX_START_OFFSET + 0x0124)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0	(TX_START_OFFSET + 0x0128)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1	(TX_START_OFFSET + 0x012C)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0	(TX_START_OFFSET + 0x0130)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1	(TX_START_OFFSET + 0x0134)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0	(TX_START_OFFSET + 0x0138)
+#define BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1	(TX_START_OFFSET + 0x013C)
+#define BOLERO_CDC_TX_ANC0_CLK_RESET_CTL	(TX_START_OFFSET + 0x0200)
+#define BOLERO_CDC_TX_ANC0_MODE_1_CTL		(TX_START_OFFSET + 0x0204)
+#define BOLERO_CDC_TX_ANC0_MODE_2_CTL		(TX_START_OFFSET + 0x0208)
+#define BOLERO_CDC_TX_ANC0_FF_SHIFT		(TX_START_OFFSET + 0x020C)
+#define BOLERO_CDC_TX_ANC0_FB_SHIFT		(TX_START_OFFSET + 0x0210)
+#define BOLERO_CDC_TX_ANC0_LPF_FF_A_CTL	(TX_START_OFFSET + 0x0214)
+#define BOLERO_CDC_TX_ANC0_LPF_FF_B_CTL	(TX_START_OFFSET + 0x0218)
+#define BOLERO_CDC_TX_ANC0_LPF_FB_CTL	(TX_START_OFFSET + 0x021C)
+#define BOLERO_CDC_TX_ANC0_SMLPF_CTL	(TX_START_OFFSET + 0x0220)
+#define BOLERO_CDC_TX_ANC0_DCFLT_SHIFT_CTL	(TX_START_OFFSET + 0x0224)
+#define BOLERO_CDC_TX_ANC0_IIR_ADAPT_CTL	(TX_START_OFFSET + 0x0228)
+#define BOLERO_CDC_TX_ANC0_IIR_COEFF_1_CTL	(TX_START_OFFSET + 0x022C)
+#define BOLERO_CDC_TX_ANC0_IIR_COEFF_2_CTL	(TX_START_OFFSET + 0x0230)
+#define BOLERO_CDC_TX_ANC0_FF_A_GAIN_CTL	(TX_START_OFFSET + 0x0234)
+#define BOLERO_CDC_TX_ANC0_FF_B_GAIN_CTL	(TX_START_OFFSET + 0x0238)
+#define BOLERO_CDC_TX_ANC0_FB_GAIN_CTL	(TX_START_OFFSET + 0x023C)
+#define BOLERO_CDC_TX0_TX_PATH_CTL	(TX_START_OFFSET + 0x0400)
+#define BOLERO_CDC_TX0_TX_PATH_CFG0	(TX_START_OFFSET + 0x0404)
+#define BOLERO_CDC_TX0_TX_PATH_CFG1	(TX_START_OFFSET + 0x0408)
+#define BOLERO_CDC_TX0_TX_VOL_CTL	(TX_START_OFFSET + 0x040C)
+#define BOLERO_CDC_TX0_TX_PATH_SEC0	(TX_START_OFFSET + 0x0410)
+#define BOLERO_CDC_TX0_TX_PATH_SEC1	(TX_START_OFFSET + 0x0414)
+#define BOLERO_CDC_TX0_TX_PATH_SEC2	(TX_START_OFFSET + 0x0418)
+#define BOLERO_CDC_TX0_TX_PATH_SEC3	(TX_START_OFFSET + 0x041C)
+#define BOLERO_CDC_TX0_TX_PATH_SEC4	(TX_START_OFFSET + 0x0420)
+#define BOLERO_CDC_TX0_TX_PATH_SEC5	(TX_START_OFFSET + 0x0424)
+#define BOLERO_CDC_TX0_TX_PATH_SEC6	(TX_START_OFFSET + 0x0428)
+#define BOLERO_CDC_TX0_TX_PATH_SEC7	(TX_START_OFFSET + 0x042C)
+#define BOLERO_CDC_TX1_TX_PATH_CTL	(TX_START_OFFSET + 0x0480)
+#define BOLERO_CDC_TX1_TX_PATH_CFG0	(TX_START_OFFSET + 0x0484)
+#define BOLERO_CDC_TX1_TX_PATH_CFG1	(TX_START_OFFSET + 0x0488)
+#define BOLERO_CDC_TX1_TX_VOL_CTL	(TX_START_OFFSET + 0x048C)
+#define BOLERO_CDC_TX1_TX_PATH_SEC0	(TX_START_OFFSET + 0x0490)
+#define BOLERO_CDC_TX1_TX_PATH_SEC1	(TX_START_OFFSET + 0x0494)
+#define BOLERO_CDC_TX1_TX_PATH_SEC2	(TX_START_OFFSET + 0x0498)
+#define BOLERO_CDC_TX1_TX_PATH_SEC3	(TX_START_OFFSET + 0x049C)
+#define BOLERO_CDC_TX1_TX_PATH_SEC4	(TX_START_OFFSET + 0x04A0)
+#define BOLERO_CDC_TX1_TX_PATH_SEC5	(TX_START_OFFSET + 0x04A4)
+#define BOLERO_CDC_TX1_TX_PATH_SEC6	(TX_START_OFFSET + 0x04A8)
+#define BOLERO_CDC_TX2_TX_PATH_CTL	(TX_START_OFFSET + 0x0500)
+#define BOLERO_CDC_TX2_TX_PATH_CFG0	(TX_START_OFFSET + 0x0504)
+#define BOLERO_CDC_TX2_TX_PATH_CFG1	(TX_START_OFFSET + 0x0508)
+#define BOLERO_CDC_TX2_TX_VOL_CTL	(TX_START_OFFSET + 0x050C)
+#define BOLERO_CDC_TX2_TX_PATH_SEC0	(TX_START_OFFSET + 0x0510)
+#define BOLERO_CDC_TX2_TX_PATH_SEC1	(TX_START_OFFSET + 0x0514)
+#define BOLERO_CDC_TX2_TX_PATH_SEC2	(TX_START_OFFSET + 0x0518)
+#define BOLERO_CDC_TX2_TX_PATH_SEC3	(TX_START_OFFSET + 0x051C)
+#define BOLERO_CDC_TX2_TX_PATH_SEC4	(TX_START_OFFSET + 0x0520)
+#define BOLERO_CDC_TX2_TX_PATH_SEC5	(TX_START_OFFSET + 0x0524)
+#define BOLERO_CDC_TX2_TX_PATH_SEC6	(TX_START_OFFSET + 0x0528)
+#define BOLERO_CDC_TX3_TX_PATH_CTL	(TX_START_OFFSET + 0x0580)
+#define BOLERO_CDC_TX3_TX_PATH_CFG0	(TX_START_OFFSET + 0x0584)
+#define BOLERO_CDC_TX3_TX_PATH_CFG1	(TX_START_OFFSET + 0x0588)
+#define BOLERO_CDC_TX3_TX_VOL_CTL	(TX_START_OFFSET + 0x058C)
+#define BOLERO_CDC_TX3_TX_PATH_SEC0	(TX_START_OFFSET + 0x0590)
+#define BOLERO_CDC_TX3_TX_PATH_SEC1	(TX_START_OFFSET + 0x0594)
+#define BOLERO_CDC_TX3_TX_PATH_SEC2	(TX_START_OFFSET + 0x0598)
+#define BOLERO_CDC_TX3_TX_PATH_SEC3	(TX_START_OFFSET + 0x059C)
+#define BOLERO_CDC_TX3_TX_PATH_SEC4	(TX_START_OFFSET + 0x05A0)
+#define BOLERO_CDC_TX3_TX_PATH_SEC5	(TX_START_OFFSET + 0x05A4)
+#define BOLERO_CDC_TX3_TX_PATH_SEC6	(TX_START_OFFSET + 0x05A8)
+#define BOLERO_CDC_TX4_TX_PATH_CTL	(TX_START_OFFSET + 0x0600)
+#define BOLERO_CDC_TX4_TX_PATH_CFG0	(TX_START_OFFSET + 0x0604)
+#define BOLERO_CDC_TX4_TX_PATH_CFG1	(TX_START_OFFSET + 0x0608)
+#define BOLERO_CDC_TX4_TX_VOL_CTL	(TX_START_OFFSET + 0x060C)
+#define BOLERO_CDC_TX4_TX_PATH_SEC0	(TX_START_OFFSET + 0x0610)
+#define BOLERO_CDC_TX4_TX_PATH_SEC1	(TX_START_OFFSET + 0x0614)
+#define BOLERO_CDC_TX4_TX_PATH_SEC2	(TX_START_OFFSET + 0x0618)
+#define BOLERO_CDC_TX4_TX_PATH_SEC3	(TX_START_OFFSET + 0x061C)
+#define BOLERO_CDC_TX4_TX_PATH_SEC4	(TX_START_OFFSET + 0x0620)
+#define BOLERO_CDC_TX4_TX_PATH_SEC5	(TX_START_OFFSET + 0x0624)
+#define BOLERO_CDC_TX4_TX_PATH_SEC6	(TX_START_OFFSET + 0x0628)
+#define BOLERO_CDC_TX5_TX_PATH_CTL	(TX_START_OFFSET + 0x0680)
+#define BOLERO_CDC_TX5_TX_PATH_CFG0	(TX_START_OFFSET + 0x0684)
+#define BOLERO_CDC_TX5_TX_PATH_CFG1	(TX_START_OFFSET + 0x0688)
+#define BOLERO_CDC_TX5_TX_VOL_CTL	(TX_START_OFFSET + 0x068C)
+#define BOLERO_CDC_TX5_TX_PATH_SEC0	(TX_START_OFFSET + 0x0690)
+#define BOLERO_CDC_TX5_TX_PATH_SEC1	(TX_START_OFFSET + 0x0694)
+#define BOLERO_CDC_TX5_TX_PATH_SEC2	(TX_START_OFFSET + 0x0698)
+#define BOLERO_CDC_TX5_TX_PATH_SEC3	(TX_START_OFFSET + 0x069C)
+#define BOLERO_CDC_TX5_TX_PATH_SEC4	(TX_START_OFFSET + 0x06A0)
+#define BOLERO_CDC_TX5_TX_PATH_SEC5	(TX_START_OFFSET + 0x06A4)
+#define BOLERO_CDC_TX5_TX_PATH_SEC6	(TX_START_OFFSET + 0x06A8)
+#define BOLERO_CDC_TX6_TX_PATH_CTL	(TX_START_OFFSET + 0x0700)
+#define BOLERO_CDC_TX6_TX_PATH_CFG0	(TX_START_OFFSET + 0x0704)
+#define BOLERO_CDC_TX6_TX_PATH_CFG1	(TX_START_OFFSET + 0x0708)
+#define BOLERO_CDC_TX6_TX_VOL_CTL	(TX_START_OFFSET + 0x070C)
+#define BOLERO_CDC_TX6_TX_PATH_SEC0	(TX_START_OFFSET + 0x0710)
+#define BOLERO_CDC_TX6_TX_PATH_SEC1	(TX_START_OFFSET + 0x0714)
+#define BOLERO_CDC_TX6_TX_PATH_SEC2	(TX_START_OFFSET + 0x0718)
+#define BOLERO_CDC_TX6_TX_PATH_SEC3	(TX_START_OFFSET + 0x071C)
+#define BOLERO_CDC_TX6_TX_PATH_SEC4	(TX_START_OFFSET + 0x0720)
+#define BOLERO_CDC_TX6_TX_PATH_SEC5	(TX_START_OFFSET + 0x0724)
+#define BOLERO_CDC_TX6_TX_PATH_SEC6	(TX_START_OFFSET + 0x0728)
+#define BOLERO_CDC_TX7_TX_PATH_CTL	(TX_START_OFFSET + 0x0780)
+#define BOLERO_CDC_TX7_TX_PATH_CFG0	(TX_START_OFFSET + 0x0784)
+#define BOLERO_CDC_TX7_TX_PATH_CFG1	(TX_START_OFFSET + 0x0788)
+#define BOLERO_CDC_TX7_TX_VOL_CTL	(TX_START_OFFSET + 0x078C)
+#define BOLERO_CDC_TX7_TX_PATH_SEC0	(TX_START_OFFSET + 0x0790)
+#define BOLERO_CDC_TX7_TX_PATH_SEC1	(TX_START_OFFSET + 0x0794)
+#define BOLERO_CDC_TX7_TX_PATH_SEC2	(TX_START_OFFSET + 0x0798)
+#define BOLERO_CDC_TX7_TX_PATH_SEC3	(TX_START_OFFSET + 0x079C)
+#define BOLERO_CDC_TX7_TX_PATH_SEC4	(TX_START_OFFSET + 0x07A0)
+#define BOLERO_CDC_TX7_TX_PATH_SEC5	(TX_START_OFFSET + 0x07A4)
+#define BOLERO_CDC_TX7_TX_PATH_SEC6	(TX_START_OFFSET + 0x07A8)
+#define TX_MAX_OFFSET			(TX_START_OFFSET + 0x07A8)
+
+#define BOLERO_CDC_TX_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 */
+
+#define RX_START_OFFSET				0x1000
+#define BOLERO_CDC_RX_TOP_TOP_CFG0		(RX_START_OFFSET + 0x0000)
+#define BOLERO_CDC_RX_TOP_SWR_CTRL		(RX_START_OFFSET + 0x0008)
+#define BOLERO_CDC_RX_TOP_DEBUG			(RX_START_OFFSET + 0x000C)
+#define BOLERO_CDC_RX_TOP_DEBUG_BUS		(RX_START_OFFSET + 0x0010)
+#define BOLERO_CDC_RX_TOP_DEBUG_EN0		(RX_START_OFFSET + 0x0014)
+#define BOLERO_CDC_RX_TOP_DEBUG_EN1		(RX_START_OFFSET + 0x0018)
+#define BOLERO_CDC_RX_TOP_DEBUG_EN2		(RX_START_OFFSET + 0x001C)
+#define BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB	(RX_START_OFFSET + 0x0020)
+#define BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB	(RX_START_OFFSET + 0x0024)
+#define BOLERO_CDC_RX_TOP_HPHL_COMP_LUT		(RX_START_OFFSET + 0x0028)
+#define BOLERO_CDC_RX_TOP_HPHL_COMP_RD_LSB	(RX_START_OFFSET + 0x002C)
+#define BOLERO_CDC_RX_TOP_HPHL_COMP_RD_MSB	(RX_START_OFFSET + 0x0030)
+#define BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB	(RX_START_OFFSET + 0x0034)
+#define BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB	(RX_START_OFFSET + 0x0038)
+#define BOLERO_CDC_RX_TOP_HPHR_COMP_LUT		(RX_START_OFFSET + 0x003C)
+#define BOLERO_CDC_RX_TOP_HPHR_COMP_RD_LSB	(RX_START_OFFSET + 0x0040)
+#define BOLERO_CDC_RX_TOP_HPHR_COMP_RD_MSB	(RX_START_OFFSET + 0x0044)
+#define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG0	(RX_START_OFFSET + 0x0070)
+#define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG1	(RX_START_OFFSET + 0x0074)
+#define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG2	(RX_START_OFFSET + 0x0078)
+#define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG3	(RX_START_OFFSET + 0x007C)
+#define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG0	(RX_START_OFFSET + 0x0080)
+#define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG1	(RX_START_OFFSET + 0x0084)
+#define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG2	(RX_START_OFFSET + 0x0088)
+#define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG3	(RX_START_OFFSET + 0x008C)
+#define BOLERO_CDC_RX_TOP_RX_I2S_CTL		(RX_START_OFFSET + 0x0090)
+#define BOLERO_CDC_RX_TOP_TX_I2S2_CTL		(RX_START_OFFSET + 0x0094)
+#define BOLERO_CDC_RX_TOP_I2S_CLK		(RX_START_OFFSET + 0x0098)
+#define BOLERO_CDC_RX_TOP_I2S_RESET		(RX_START_OFFSET + 0x009C)
+#define BOLERO_CDC_RX_TOP_I2S_MUX		(RX_START_OFFSET + 0x00A0)
+#define BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL	(RX_START_OFFSET + 0x0100)
+#define BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL \
+						(RX_START_OFFSET + 0x0104)
+#define BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL	(RX_START_OFFSET + 0x0108)
+#define BOLERO_CDC_RX_CLK_RST_CTRL_DSD_CONTROL	(RX_START_OFFSET + 0x010C)
+#define BOLERO_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL \
+						(RX_START_OFFSET + 0x0110)
+#define BOLERO_CDC_RX_SOFTCLIP_CRC		(RX_START_OFFSET + 0x0140)
+#define BOLERO_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL	(RX_START_OFFSET + 0x0144)
+#define BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0	(RX_START_OFFSET + 0x0180)
+#define BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1	(RX_START_OFFSET + 0x0184)
+#define BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0	(RX_START_OFFSET + 0x0188)
+#define BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1	(RX_START_OFFSET + 0x018C)
+#define BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0	(RX_START_OFFSET + 0x0190)
+#define BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1	(RX_START_OFFSET + 0x0194)
+#define BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4	(RX_START_OFFSET + 0x0198)
+#define BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5	(RX_START_OFFSET + 0x019C)
+#define BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0	(RX_START_OFFSET + 0x01A0)
+#define BOLERO_CDC_RX_CLSH_CRC			(RX_START_OFFSET + 0x0200)
+#define BOLERO_CDC_RX_CLSH_DLY_CTRL		(RX_START_OFFSET + 0x0204)
+#define BOLERO_CDC_RX_CLSH_DECAY_CTRL		(RX_START_OFFSET + 0x0208)
+#define BOLERO_CDC_RX_CLSH_HPH_V_PA		(RX_START_OFFSET + 0x020C)
+#define BOLERO_CDC_RX_CLSH_EAR_V_PA		(RX_START_OFFSET + 0x0210)
+#define BOLERO_CDC_RX_CLSH_HPH_V_HD		(RX_START_OFFSET + 0x0214)
+#define BOLERO_CDC_RX_CLSH_EAR_V_HD		(RX_START_OFFSET + 0x0218)
+#define BOLERO_CDC_RX_CLSH_K1_MSB		(RX_START_OFFSET + 0x021C)
+#define BOLERO_CDC_RX_CLSH_K1_LSB		(RX_START_OFFSET + 0x0220)
+#define BOLERO_CDC_RX_CLSH_K2_MSB		(RX_START_OFFSET + 0x0224)
+#define BOLERO_CDC_RX_CLSH_K2_LSB		(RX_START_OFFSET + 0x0228)
+#define BOLERO_CDC_RX_CLSH_IDLE_CTRL		(RX_START_OFFSET + 0x022C)
+#define BOLERO_CDC_RX_CLSH_IDLE_HPH		(RX_START_OFFSET + 0x0230)
+#define BOLERO_CDC_RX_CLSH_IDLE_EAR		(RX_START_OFFSET + 0x0234)
+#define BOLERO_CDC_RX_CLSH_TEST0		(RX_START_OFFSET + 0x0238)
+#define BOLERO_CDC_RX_CLSH_TEST1		(RX_START_OFFSET + 0x023C)
+#define BOLERO_CDC_RX_CLSH_OVR_VREF		(RX_START_OFFSET + 0x0240)
+#define BOLERO_CDC_RX_CLSH_CLSG_CTL		(RX_START_OFFSET + 0x0244)
+#define BOLERO_CDC_RX_CLSH_CLSG_CFG1		(RX_START_OFFSET + 0x0248)
+#define BOLERO_CDC_RX_CLSH_CLSG_CFG2		(RX_START_OFFSET + 0x024C)
+#define BOLERO_CDC_RX_BCL_VBAT_PATH_CTL		(RX_START_OFFSET + 0x0280)
+#define BOLERO_CDC_RX_BCL_VBAT_CFG		(RX_START_OFFSET + 0x0284)
+#define BOLERO_CDC_RX_BCL_VBAT_ADC_CAL1		(RX_START_OFFSET + 0x0288)
+#define BOLERO_CDC_RX_BCL_VBAT_ADC_CAL2		(RX_START_OFFSET + 0x028C)
+#define BOLERO_CDC_RX_BCL_VBAT_ADC_CAL3		(RX_START_OFFSET + 0x0290)
+#define BOLERO_CDC_RX_BCL_VBAT_PK_EST1		(RX_START_OFFSET + 0x0294)
+#define BOLERO_CDC_RX_BCL_VBAT_PK_EST2		(RX_START_OFFSET + 0x0298)
+#define BOLERO_CDC_RX_BCL_VBAT_PK_EST3		(RX_START_OFFSET + 0x029C)
+#define BOLERO_CDC_RX_BCL_VBAT_RF_PROC1		(RX_START_OFFSET + 0x02A0)
+#define BOLERO_CDC_RX_BCL_VBAT_RF_PROC2		(RX_START_OFFSET + 0x02A4)
+#define BOLERO_CDC_RX_BCL_VBAT_TAC1		(RX_START_OFFSET + 0x02A8)
+#define BOLERO_CDC_RX_BCL_VBAT_TAC2		(RX_START_OFFSET + 0x02AC)
+#define BOLERO_CDC_RX_BCL_VBAT_TAC3		(RX_START_OFFSET + 0x02B0)
+#define BOLERO_CDC_RX_BCL_VBAT_TAC4		(RX_START_OFFSET + 0x02B4)
+#define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD1	(RX_START_OFFSET + 0x02B8)
+#define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD2	(RX_START_OFFSET + 0x02BC)
+#define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD3	(RX_START_OFFSET + 0x02C0)
+#define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD4	(RX_START_OFFSET + 0x02C4)
+#define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD5	(RX_START_OFFSET + 0x02C8)
+#define BOLERO_CDC_RX_BCL_VBAT_DEBUG1		(RX_START_OFFSET + 0x02CC)
+#define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD_MON	(RX_START_OFFSET + 0x02D0)
+#define BOLERO_CDC_RX_BCL_VBAT_GAIN_MON_VAL	(RX_START_OFFSET + 0x02D4)
+#define BOLERO_CDC_RX_BCL_VBAT_BAN		(RX_START_OFFSET + 0x02D8)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1	(RX_START_OFFSET + 0x02DC)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2	(RX_START_OFFSET + 0x02E0)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3	(RX_START_OFFSET + 0x02E4)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4	(RX_START_OFFSET + 0x02E8)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5	(RX_START_OFFSET + 0x02EC)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6	(RX_START_OFFSET + 0x02F0)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7	(RX_START_OFFSET + 0x02F4)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8	(RX_START_OFFSET + 0x02F8)
+#define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9	(RX_START_OFFSET + 0x02FC)
+#define BOLERO_CDC_RX_BCL_VBAT_ATTN1		(RX_START_OFFSET + 0x0300)
+#define BOLERO_CDC_RX_BCL_VBAT_ATTN2		(RX_START_OFFSET + 0x0304)
+#define BOLERO_CDC_RX_BCL_VBAT_ATTN3		(RX_START_OFFSET + 0x0308)
+#define BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL1	(RX_START_OFFSET + 0x030C)
+#define BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL2	(RX_START_OFFSET + 0x0310)
+#define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG1	(RX_START_OFFSET + 0x0314)
+#define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG2	(RX_START_OFFSET + 0x0318)
+#define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG3	(RX_START_OFFSET + 0x031C)
+#define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG4	(RX_START_OFFSET + 0x0320)
+#define BOLERO_CDC_RX_BCL_VBAT_DECODE_ST	(RX_START_OFFSET + 0x0324)
+#define BOLERO_CDC_RX_INTR_CTRL_CFG		(RX_START_OFFSET + 0x0340)
+#define BOLERO_CDC_RX_INTR_CTRL_CLR_COMMIT	(RX_START_OFFSET + 0x0344)
+#define BOLERO_CDC_RX_INTR_CTRL_PIN1_MASK0	(RX_START_OFFSET + 0x0360)
+#define BOLERO_CDC_RX_INTR_CTRL_PIN1_STATUS0	(RX_START_OFFSET + 0x0368)
+#define BOLERO_CDC_RX_INTR_CTRL_PIN1_CLEAR0	(RX_START_OFFSET + 0x0370)
+#define BOLERO_CDC_RX_INTR_CTRL_PIN2_MASK0	(RX_START_OFFSET + 0x0380)
+#define BOLERO_CDC_RX_INTR_CTRL_PIN2_STATUS0	(RX_START_OFFSET + 0x0388)
+#define BOLERO_CDC_RX_INTR_CTRL_PIN2_CLEAR0	(RX_START_OFFSET + 0x0390)
+#define BOLERO_CDC_RX_INTR_CTRL_LEVEL0		(RX_START_OFFSET + 0x03C0)
+#define BOLERO_CDC_RX_INTR_CTRL_BYPASS0		(RX_START_OFFSET + 0x03C8)
+#define BOLERO_CDC_RX_INTR_CTRL_SET0		(RX_START_OFFSET + 0x03D0)
+#define BOLERO_CDC_RX_RX0_RX_PATH_CTL		(RX_START_OFFSET + 0x0400)
+#define BOLERO_CDC_RX_RX0_RX_PATH_CFG0		(RX_START_OFFSET + 0x0404)
+#define BOLERO_CDC_RX_RX0_RX_PATH_CFG1		(RX_START_OFFSET + 0x0408)
+#define BOLERO_CDC_RX_RX0_RX_PATH_CFG2		(RX_START_OFFSET + 0x040C)
+#define BOLERO_CDC_RX_RX0_RX_PATH_CFG3		(RX_START_OFFSET + 0x0410)
+#define BOLERO_CDC_RX_RX0_RX_VOL_CTL		(RX_START_OFFSET + 0x0414)
+#define BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL	(RX_START_OFFSET + 0x0418)
+#define BOLERO_CDC_RX_RX0_RX_PATH_MIX_CFG	(RX_START_OFFSET + 0x041C)
+#define BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL	(RX_START_OFFSET + 0x0420)
+#define BOLERO_CDC_RX_RX0_RX_PATH_SEC1		(RX_START_OFFSET + 0x0424)
+#define BOLERO_CDC_RX_RX0_RX_PATH_SEC2		(RX_START_OFFSET + 0x0428)
+#define BOLERO_CDC_RX_RX0_RX_PATH_SEC3		(RX_START_OFFSET + 0x042C)
+#define BOLERO_CDC_RX_RX0_RX_PATH_SEC4		(RX_START_OFFSET + 0x0430)
+#define BOLERO_CDC_RX_RX0_RX_PATH_SEC7		(RX_START_OFFSET + 0x0434)
+#define BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC0	(RX_START_OFFSET + 0x0438)
+#define BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC1	(RX_START_OFFSET + 0x043C)
+#define BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL	(RX_START_OFFSET + 0x0440)
+#define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA1	(RX_START_OFFSET + 0x0444)
+#define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA2	(RX_START_OFFSET + 0x0448)
+#define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA3	(RX_START_OFFSET + 0x044C)
+#define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA4	(RX_START_OFFSET + 0x0450)
+#define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA5	(RX_START_OFFSET + 0x0454)
+#define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA6	(RX_START_OFFSET + 0x0458)
+#define BOLERO_CDC_RX_RX1_RX_PATH_CTL		(RX_START_OFFSET + 0x0480)
+#define BOLERO_CDC_RX_RX1_RX_PATH_CFG0		(RX_START_OFFSET + 0x0484)
+#define BOLERO_CDC_RX_RX1_RX_PATH_CFG1		(RX_START_OFFSET + 0x0488)
+#define BOLERO_CDC_RX_RX1_RX_PATH_CFG2		(RX_START_OFFSET + 0x048C)
+#define BOLERO_CDC_RX_RX1_RX_PATH_CFG3		(RX_START_OFFSET + 0x0490)
+#define BOLERO_CDC_RX_RX1_RX_VOL_CTL		(RX_START_OFFSET + 0x0494)
+#define BOLERO_CDC_RX_RX1_RX_PATH_MIX_CTL	(RX_START_OFFSET + 0x0498)
+#define BOLERO_CDC_RX_RX1_RX_PATH_MIX_CFG	(RX_START_OFFSET + 0x049C)
+#define BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL	(RX_START_OFFSET + 0x04A0)
+#define BOLERO_CDC_RX_RX1_RX_PATH_SEC1		(RX_START_OFFSET + 0x04A4)
+#define BOLERO_CDC_RX_RX1_RX_PATH_SEC2		(RX_START_OFFSET + 0x04A8)
+#define BOLERO_CDC_RX_RX1_RX_PATH_SEC3		(RX_START_OFFSET + 0x04AC)
+#define BOLERO_CDC_RX_RX1_RX_PATH_SEC4		(RX_START_OFFSET + 0x04B0)
+#define BOLERO_CDC_RX_RX1_RX_PATH_SEC7		(RX_START_OFFSET + 0x04B4)
+#define BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC0	(RX_START_OFFSET + 0x04B8)
+#define BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC1	(RX_START_OFFSET + 0x04BC)
+#define BOLERO_CDC_RX_RX1_RX_PATH_DSM_CTL	(RX_START_OFFSET + 0x04C0)
+#define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA1	(RX_START_OFFSET + 0x04C4)
+#define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA2	(RX_START_OFFSET + 0x04C8)
+#define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA3	(RX_START_OFFSET + 0x04CC)
+#define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA4	(RX_START_OFFSET + 0x04D0)
+#define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA5	(RX_START_OFFSET + 0x04D4)
+#define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA6	(RX_START_OFFSET + 0x04D8)
+#define BOLERO_CDC_RX_RX2_RX_PATH_CTL		(RX_START_OFFSET + 0x0500)
+#define BOLERO_CDC_RX_RX2_RX_PATH_CFG0		(RX_START_OFFSET + 0x0504)
+#define BOLERO_CDC_RX_RX2_RX_PATH_CFG1		(RX_START_OFFSET + 0x0508)
+#define BOLERO_CDC_RX_RX2_RX_PATH_CFG2		(RX_START_OFFSET + 0x050C)
+#define BOLERO_CDC_RX_RX2_RX_PATH_CFG3		(RX_START_OFFSET + 0x0510)
+#define BOLERO_CDC_RX_RX2_RX_VOL_CTL		(RX_START_OFFSET + 0x0514)
+#define BOLERO_CDC_RX_RX2_RX_PATH_MIX_CTL	(RX_START_OFFSET + 0x0518)
+#define BOLERO_CDC_RX_RX2_RX_PATH_MIX_CFG	(RX_START_OFFSET + 0x051C)
+#define BOLERO_CDC_RX_RX2_RX_VOL_MIX_CTL	(RX_START_OFFSET + 0x0520)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC0		(RX_START_OFFSET + 0x0524)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC1		(RX_START_OFFSET + 0x0528)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC2		(RX_START_OFFSET + 0x052C)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC3		(RX_START_OFFSET + 0x0530)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC4		(RX_START_OFFSET + 0x0534)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC5		(RX_START_OFFSET + 0x0538)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC6		(RX_START_OFFSET + 0x053C)
+#define BOLERO_CDC_RX_RX2_RX_PATH_SEC7		(RX_START_OFFSET + 0x0540)
+#define BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC0	(RX_START_OFFSET + 0x0544)
+#define BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC1	(RX_START_OFFSET + 0x0548)
+#define BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL	(RX_START_OFFSET + 0x054C)
+#define BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL	(RX_START_OFFSET + 0x0780)
+#define BOLERO_CDC_RX_IDLE_DETECT_CFG0		(RX_START_OFFSET + 0x0784)
+#define BOLERO_CDC_RX_IDLE_DETECT_CFG1		(RX_START_OFFSET + 0x0788)
+#define BOLERO_CDC_RX_IDLE_DETECT_CFG2		(RX_START_OFFSET + 0x078C)
+#define BOLERO_CDC_RX_IDLE_DETECT_CFG3		(RX_START_OFFSET + 0x0790)
+#define BOLERO_CDC_RX_COMPANDER0_CTL0		(RX_START_OFFSET + 0x0800)
+#define BOLERO_CDC_RX_COMPANDER0_CTL1		(RX_START_OFFSET + 0x0804)
+#define BOLERO_CDC_RX_COMPANDER0_CTL2		(RX_START_OFFSET + 0x0808)
+#define BOLERO_CDC_RX_COMPANDER0_CTL3		(RX_START_OFFSET + 0x080C)
+#define BOLERO_CDC_RX_COMPANDER0_CTL4		(RX_START_OFFSET + 0x0810)
+#define BOLERO_CDC_RX_COMPANDER0_CTL5		(RX_START_OFFSET + 0x0814)
+#define BOLERO_CDC_RX_COMPANDER0_CTL6		(RX_START_OFFSET + 0x0818)
+#define BOLERO_CDC_RX_COMPANDER0_CTL7		(RX_START_OFFSET + 0x081C)
+#define BOLERO_CDC_RX_COMPANDER1_CTL0		(RX_START_OFFSET + 0x0840)
+#define BOLERO_CDC_RX_COMPANDER1_CTL1		(RX_START_OFFSET + 0x0844)
+#define BOLERO_CDC_RX_COMPANDER1_CTL2		(RX_START_OFFSET + 0x0848)
+#define BOLERO_CDC_RX_COMPANDER1_CTL3		(RX_START_OFFSET + 0x084C)
+#define BOLERO_CDC_RX_COMPANDER1_CTL4		(RX_START_OFFSET + 0x0850)
+#define BOLERO_CDC_RX_COMPANDER1_CTL5		(RX_START_OFFSET + 0x0854)
+#define BOLERO_CDC_RX_COMPANDER1_CTL6		(RX_START_OFFSET + 0x0858)
+#define BOLERO_CDC_RX_COMPANDER1_CTL7		(RX_START_OFFSET + 0x085C)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
+						(RX_START_OFFSET + 0x0A00)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
+						(RX_START_OFFSET + 0x0A04)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \
+						(RX_START_OFFSET + 0x0A08)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \
+						(RX_START_OFFSET + 0x0A0C)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \
+						(RX_START_OFFSET + 0x0A10)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \
+						(RX_START_OFFSET + 0x0A14)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \
+						(RX_START_OFFSET + 0x0A18)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \
+						(RX_START_OFFSET + 0x0A1C)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \
+						(RX_START_OFFSET + 0x0A20)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL	(RX_START_OFFSET + 0x0A24)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \
+						(RX_START_OFFSET + 0x0A28)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \
+						(RX_START_OFFSET + 0x0A2C)
+#define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \
+						(RX_START_OFFSET + 0x0A30)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \
+						(RX_START_OFFSET + 0x0A80)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \
+						(RX_START_OFFSET + 0x0A84)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \
+						(RX_START_OFFSET + 0x0A88)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \
+						(RX_START_OFFSET + 0x0A8C)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \
+						(RX_START_OFFSET + 0x0A90)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \
+						(RX_START_OFFSET + 0x0A94)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \
+						(RX_START_OFFSET + 0x0A98)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \
+						(RX_START_OFFSET + 0x0A9C)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \
+						(RX_START_OFFSET + 0x0AA0)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_CTL	(RX_START_OFFSET + 0x0AA4)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \
+						(RX_START_OFFSET + 0x0AA8)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \
+						(RX_START_OFFSET + 0x0AAC)
+#define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \
+						(RX_START_OFFSET + 0x0AB0)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0	(RX_START_OFFSET + 0x0B00)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1	(RX_START_OFFSET + 0x0B04)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2	(RX_START_OFFSET + 0x0B08)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3	(RX_START_OFFSET + 0x0B0C)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0	(RX_START_OFFSET + 0x0B10)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1	(RX_START_OFFSET + 0x0B14)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2	(RX_START_OFFSET + 0x0B18)
+#define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3	(RX_START_OFFSET + 0x0B1C)
+#define BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \
+						(RX_START_OFFSET + 0x0B40)
+#define BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \
+						(RX_START_OFFSET + 0x0B44)
+#define BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \
+						(RX_START_OFFSET + 0x0B50)
+#define BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \
+						(RX_START_OFFSET + 0x0B54)
+#define BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \
+						(RX_START_OFFSET + 0x0C00)
+#define BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0	(RX_START_OFFSET + 0x0C04)
+#define BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \
+						(RX_START_OFFSET + 0x0C40)
+#define BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0	(RX_START_OFFSET + 0x0C44)
+#define BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \
+						(RX_START_OFFSET + 0x0C80)
+#define BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0	(RX_START_OFFSET + 0x0C84)
+#define BOLERO_CDC_RX_EC_ASRC0_CLK_RST_CTL	(RX_START_OFFSET + 0x0D00)
+#define BOLERO_CDC_RX_EC_ASRC0_CTL0		(RX_START_OFFSET + 0x0D04)
+#define BOLERO_CDC_RX_EC_ASRC0_CTL1		(RX_START_OFFSET + 0x0D08)
+#define BOLERO_CDC_RX_EC_ASRC0_FIFO_CTL		(RX_START_OFFSET + 0x0D0C)
+#define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \
+						(RX_START_OFFSET + 0x0D10)
+#define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \
+						(RX_START_OFFSET + 0x0D14)
+#define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \
+						(RX_START_OFFSET + 0x0D18)
+#define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \
+						(RX_START_OFFSET + 0x0D1C)
+#define BOLERO_CDC_RX_EC_ASRC0_STATUS_FIFO	(RX_START_OFFSET + 0x0D20)
+#define BOLERO_CDC_RX_EC_ASRC1_CLK_RST_CTL	(RX_START_OFFSET + 0x0D40)
+#define BOLERO_CDC_RX_EC_ASRC1_CTL0		(RX_START_OFFSET + 0x0D44)
+#define BOLERO_CDC_RX_EC_ASRC1_CTL1		(RX_START_OFFSET + 0x0D48)
+#define BOLERO_CDC_RX_EC_ASRC1_FIFO_CTL		(RX_START_OFFSET + 0x0D4C)
+#define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \
+						(RX_START_OFFSET + 0x0D50)
+#define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \
+						(RX_START_OFFSET + 0x0D54)
+#define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \
+						(RX_START_OFFSET + 0x0D58)
+#define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \
+						(RX_START_OFFSET + 0x0D5C)
+#define BOLERO_CDC_RX_EC_ASRC1_STATUS_FIFO	(RX_START_OFFSET + 0x0D60)
+#define BOLERO_CDC_RX_EC_ASRC2_CLK_RST_CTL	(RX_START_OFFSET + 0x0D80)
+#define BOLERO_CDC_RX_EC_ASRC2_CTL0		(RX_START_OFFSET + 0x0D84)
+#define BOLERO_CDC_RX_EC_ASRC2_CTL1		(RX_START_OFFSET + 0x0D88)
+#define BOLERO_CDC_RX_EC_ASRC2_FIFO_CTL		(RX_START_OFFSET + 0x0D8C)
+#define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \
+						(RX_START_OFFSET + 0x0D90)
+#define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \
+						(RX_START_OFFSET + 0x0D94)
+#define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \
+						(RX_START_OFFSET + 0x0D98)
+#define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \
+						(RX_START_OFFSET + 0x0D9C)
+#define BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO	(RX_START_OFFSET + 0x0DA0)
+#define BOLERO_CDC_RX_DSD0_PATH_CTL		(RX_START_OFFSET + 0x0F00)
+#define BOLERO_CDC_RX_DSD0_CFG0			(RX_START_OFFSET + 0x0F04)
+#define BOLERO_CDC_RX_DSD0_CFG1			(RX_START_OFFSET + 0x0F08)
+#define BOLERO_CDC_RX_DSD0_CFG2			(RX_START_OFFSET + 0x0F0C)
+#define BOLERO_CDC_RX_DSD1_PATH_CTL		(RX_START_OFFSET + 0x0F80)
+#define BOLERO_CDC_RX_DSD1_CFG0			(RX_START_OFFSET + 0x0F84)
+#define BOLERO_CDC_RX_DSD1_CFG1			(RX_START_OFFSET + 0x0F88)
+#define BOLERO_CDC_RX_DSD1_CFG2			(RX_START_OFFSET + 0x0F8C)
+#define RX_MAX_OFFSET				(RX_START_OFFSET + 0x0F8C)
+
+#define BOLERO_CDC_RX_MACRO_MAX 0x3E4 /* F8C/4 = 3E3 + 1 */
+
+/* WSA - macro#2 */
+#define WSA_START_OFFSET			0x2000
+#define BOLERO_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL \
+						(WSA_START_OFFSET + 0x0000)
+#define BOLERO_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL \
+						(WSA_START_OFFSET + 0x0004)
+#define BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL	(WSA_START_OFFSET + 0x0008)
+#define BOLERO_CDC_WSA_TOP_TOP_CFG0		(WSA_START_OFFSET + 0x0080)
+#define BOLERO_CDC_WSA_TOP_TOP_CFG1		(WSA_START_OFFSET + 0x0084)
+#define BOLERO_CDC_WSA_TOP_FREQ_MCLK		(WSA_START_OFFSET + 0x0088)
+#define BOLERO_CDC_WSA_TOP_DEBUG_BUS_SEL	(WSA_START_OFFSET + 0x008C)
+#define BOLERO_CDC_WSA_TOP_DEBUG_EN0		(WSA_START_OFFSET + 0x0090)
+#define BOLERO_CDC_WSA_TOP_DEBUG_EN1		(WSA_START_OFFSET + 0x0094)
+#define BOLERO_CDC_WSA_TOP_DEBUG_DSM_LB		(WSA_START_OFFSET + 0x0098)
+#define BOLERO_CDC_WSA_TOP_RX_I2S_CTL		(WSA_START_OFFSET + 0x009C)
+#define BOLERO_CDC_WSA_TOP_TX_I2S_CTL		(WSA_START_OFFSET + 0x00A0)
+#define BOLERO_CDC_WSA_TOP_I2S_CLK		(WSA_START_OFFSET + 0x00A4)
+#define BOLERO_CDC_WSA_TOP_I2S_RESET		(WSA_START_OFFSET + 0x00A8)
+#define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0	(WSA_START_OFFSET + 0x0100)
+#define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1	(WSA_START_OFFSET + 0x0104)
+#define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0	(WSA_START_OFFSET + 0x0108)
+#define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1	(WSA_START_OFFSET + 0x010C)
+#define BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0	(WSA_START_OFFSET + 0x0110)
+#define BOLERO_CDC_WSA_RX_INP_MUX_RX_EC_CFG0	(WSA_START_OFFSET + 0x0114)
+#define BOLERO_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0	(WSA_START_OFFSET + 0x0118)
+/* VBAT registers  */
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL	(WSA_START_OFFSET + 0x0180)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG	(WSA_START_OFFSET + 0x0184)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1	(WSA_START_OFFSET + 0x0188)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2	(WSA_START_OFFSET + 0x018C)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3	(WSA_START_OFFSET + 0x0190)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST1	(WSA_START_OFFSET + 0x0194)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST2	(WSA_START_OFFSET + 0x0198)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST3	(WSA_START_OFFSET + 0x019C)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1	(WSA_START_OFFSET + 0x01A0)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2	(WSA_START_OFFSET + 0x01A4)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC1	(WSA_START_OFFSET + 0x01A8)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC2	(WSA_START_OFFSET + 0x01AC)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC3	(WSA_START_OFFSET + 0x01B0)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC4	(WSA_START_OFFSET + 0x01B4)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1	(WSA_START_OFFSET + 0x01B8)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2	(WSA_START_OFFSET + 0x01BC)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3	(WSA_START_OFFSET + 0x01C0)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4	(WSA_START_OFFSET + 0x01C4)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5	(WSA_START_OFFSET + 0x01C8)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DEBUG1	(WSA_START_OFFSET + 0x01CC)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON \
+						(WSA_START_OFFSET + 0x01D0)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL \
+						(WSA_START_OFFSET + 0x01D4)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BAN	(WSA_START_OFFSET + 0x01D8)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \
+						(WSA_START_OFFSET + 0x01DC)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \
+						(WSA_START_OFFSET + 0x01E0)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \
+						(WSA_START_OFFSET + 0x01E4)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \
+						(WSA_START_OFFSET + 0x01E8)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \
+						(WSA_START_OFFSET + 0x01EC)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \
+						(WSA_START_OFFSET + 0x01F0)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \
+						(WSA_START_OFFSET + 0x01F4)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \
+						(WSA_START_OFFSET + 0x01F8)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \
+						(WSA_START_OFFSET + 0x01FC)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1	(WSA_START_OFFSET + 0x0200)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2	(WSA_START_OFFSET + 0x0204)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3	(WSA_START_OFFSET + 0x0208)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1 \
+						(WSA_START_OFFSET + 0x020C)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2 \
+						(WSA_START_OFFSET + 0x0210)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1 \
+						(WSA_START_OFFSET + 0x0214)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2 \
+						(WSA_START_OFFSET + 0x0218)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3 \
+						(WSA_START_OFFSET + 0x021C)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4 \
+						(WSA_START_OFFSET + 0x0220)
+#define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST	(WSA_START_OFFSET + 0x0224)
+#define BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL	(WSA_START_OFFSET + 0x0244)
+#define BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0	(WSA_START_OFFSET + 0x0248)
+#define BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL	(WSA_START_OFFSET + 0x0264)
+#define BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0	(WSA_START_OFFSET + 0x0268)
+#define BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL	(WSA_START_OFFSET + 0x0284)
+#define BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0	(WSA_START_OFFSET + 0x0288)
+#define BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL	(WSA_START_OFFSET + 0x02A4)
+#define BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0	(WSA_START_OFFSET + 0x02A8)
+#define BOLERO_CDC_WSA_INTR_CTRL_CFG		(WSA_START_OFFSET + 0x0340)
+#define BOLERO_CDC_WSA_INTR_CTRL_CLR_COMMIT	(WSA_START_OFFSET + 0x0344)
+#define BOLERO_CDC_WSA_INTR_CTRL_PIN1_MASK0	(WSA_START_OFFSET + 0x0360)
+#define BOLERO_CDC_WSA_INTR_CTRL_PIN1_STATUS0	(WSA_START_OFFSET + 0x0368)
+#define BOLERO_CDC_WSA_INTR_CTRL_PIN1_CLEAR0	(WSA_START_OFFSET + 0x0370)
+#define BOLERO_CDC_WSA_INTR_CTRL_PIN2_MASK0	(WSA_START_OFFSET + 0x0380)
+#define BOLERO_CDC_WSA_INTR_CTRL_PIN2_STATUS0	(WSA_START_OFFSET + 0x0388)
+#define BOLERO_CDC_WSA_INTR_CTRL_PIN2_CLEAR0	(WSA_START_OFFSET + 0x0390)
+#define BOLERO_CDC_WSA_INTR_CTRL_LEVEL0		(WSA_START_OFFSET + 0x03C0)
+#define BOLERO_CDC_WSA_INTR_CTRL_BYPASS0	(WSA_START_OFFSET + 0x03C8)
+#define BOLERO_CDC_WSA_INTR_CTRL_SET0		(WSA_START_OFFSET + 0x03D0)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_CTL		(WSA_START_OFFSET + 0x0400)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_CFG0		(WSA_START_OFFSET + 0x0404)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_CFG1		(WSA_START_OFFSET + 0x0408)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_CFG2		(WSA_START_OFFSET + 0x040C)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_CFG3		(WSA_START_OFFSET + 0x0410)
+#define BOLERO_CDC_WSA_RX0_RX_VOL_CTL		(WSA_START_OFFSET + 0x0414)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL	(WSA_START_OFFSET + 0x0418)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CFG	(WSA_START_OFFSET + 0x041C)
+#define BOLERO_CDC_WSA_RX0_RX_VOL_MIX_CTL	(WSA_START_OFFSET + 0x0420)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_SEC0		(WSA_START_OFFSET + 0x0424)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_SEC1		(WSA_START_OFFSET + 0x0428)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_SEC2		(WSA_START_OFFSET + 0x042C)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_SEC3		(WSA_START_OFFSET + 0x0430)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_SEC5		(WSA_START_OFFSET + 0x0438)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_SEC6		(WSA_START_OFFSET + 0x043C)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_SEC7		(WSA_START_OFFSET + 0x0440)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC0	(WSA_START_OFFSET + 0x0444)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC1	(WSA_START_OFFSET + 0x0448)
+#define BOLERO_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL	(WSA_START_OFFSET + 0x044C)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_CTL		(WSA_START_OFFSET + 0x0480)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_CFG0		(WSA_START_OFFSET + 0x0484)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_CFG1		(WSA_START_OFFSET + 0x0488)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_CFG2		(WSA_START_OFFSET + 0x048C)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_CFG3		(WSA_START_OFFSET + 0x0490)
+#define BOLERO_CDC_WSA_RX1_RX_VOL_CTL		(WSA_START_OFFSET + 0x0494)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL	(WSA_START_OFFSET + 0x0498)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CFG	(WSA_START_OFFSET + 0x049C)
+#define BOLERO_CDC_WSA_RX1_RX_VOL_MIX_CTL	(WSA_START_OFFSET + 0x04A0)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_SEC0		(WSA_START_OFFSET + 0x04A4)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_SEC1		(WSA_START_OFFSET + 0x04A8)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_SEC2		(WSA_START_OFFSET + 0x04AC)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_SEC3		(WSA_START_OFFSET + 0x04B0)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_SEC5		(WSA_START_OFFSET + 0x04B8)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_SEC6		(WSA_START_OFFSET + 0x04BC)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_SEC7		(WSA_START_OFFSET + 0x04C0)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC0	(WSA_START_OFFSET + 0x04C4)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC1	(WSA_START_OFFSET + 0x04C8)
+#define BOLERO_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL	(WSA_START_OFFSET + 0x04CC)
+#define BOLERO_CDC_WSA_BOOST0_BOOST_PATH_CTL	(WSA_START_OFFSET + 0x0500)
+#define BOLERO_CDC_WSA_BOOST0_BOOST_CTL		(WSA_START_OFFSET + 0x0504)
+#define BOLERO_CDC_WSA_BOOST0_BOOST_CFG1	(WSA_START_OFFSET + 0x0508)
+#define BOLERO_CDC_WSA_BOOST0_BOOST_CFG2	(WSA_START_OFFSET + 0x050C)
+#define BOLERO_CDC_WSA_BOOST1_BOOST_PATH_CTL	(WSA_START_OFFSET + 0x0540)
+#define BOLERO_CDC_WSA_BOOST1_BOOST_CTL		(WSA_START_OFFSET + 0x0544)
+#define BOLERO_CDC_WSA_BOOST1_BOOST_CFG1	(WSA_START_OFFSET + 0x0548)
+#define BOLERO_CDC_WSA_BOOST1_BOOST_CFG2	(WSA_START_OFFSET + 0x054C)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL0		(WSA_START_OFFSET + 0x0580)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL1		(WSA_START_OFFSET + 0x0584)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL2		(WSA_START_OFFSET + 0x0588)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL3		(WSA_START_OFFSET + 0x058C)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL4		(WSA_START_OFFSET + 0x0590)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL5		(WSA_START_OFFSET + 0x0594)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL6		(WSA_START_OFFSET + 0x0598)
+#define BOLERO_CDC_WSA_COMPANDER0_CTL7		(WSA_START_OFFSET + 0x059C)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL0		(WSA_START_OFFSET + 0x05C0)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL1		(WSA_START_OFFSET + 0x05C4)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL2		(WSA_START_OFFSET + 0x05C8)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL3		(WSA_START_OFFSET + 0x05CC)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL4		(WSA_START_OFFSET + 0x05D0)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL5		(WSA_START_OFFSET + 0x05D4)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL6		(WSA_START_OFFSET + 0x05D8)
+#define BOLERO_CDC_WSA_COMPANDER1_CTL7		(WSA_START_OFFSET + 0x05DC)
+#define BOLERO_CDC_WSA_SOFTCLIP0_CRC		(WSA_START_OFFSET + 0x0600)
+#define BOLERO_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL	(WSA_START_OFFSET + 0x0604)
+#define BOLERO_CDC_WSA_SOFTCLIP1_CRC		(WSA_START_OFFSET + 0x0640)
+#define BOLERO_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL	(WSA_START_OFFSET + 0x0644)
+#define BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL \
+						(WSA_START_OFFSET + 0x0680)
+#define BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0	(WSA_START_OFFSET + 0x0684)
+#define BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL \
+						(WSA_START_OFFSET + 0x06C0)
+#define BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0	(WSA_START_OFFSET + 0x06C4)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL	(WSA_START_OFFSET + 0x0700)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_CTL0	(WSA_START_OFFSET + 0x0704)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_CTL1	(WSA_START_OFFSET + 0x0708)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_FIFO_CTL	(WSA_START_OFFSET + 0x070C)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB \
+						(WSA_START_OFFSET + 0x0710)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB \
+						(WSA_START_OFFSET + 0x0714)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB \
+						(WSA_START_OFFSET + 0x0718)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB \
+						(WSA_START_OFFSET + 0x071C)
+#define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO	(WSA_START_OFFSET + 0x0720)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL	(WSA_START_OFFSET + 0x0740)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_CTL0	(WSA_START_OFFSET + 0x0744)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_CTL1	(WSA_START_OFFSET + 0x0748)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_FIFO_CTL	(WSA_START_OFFSET + 0x074C)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB \
+						(WSA_START_OFFSET + 0x0750)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB \
+						(WSA_START_OFFSET + 0x0754)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB \
+						(WSA_START_OFFSET + 0x0758)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB \
+						(WSA_START_OFFSET + 0x075C)
+#define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO	(WSA_START_OFFSET + 0x0760)
+#define WSA_MAX_OFFSET				(WSA_START_OFFSET + 0x0760)
+
+#define BOLERO_CDC_WSA_MACRO_MAX 0x1D9 /* 0x760/4 = 0x1D8 + 1 registers */
+
+/* VA macro registers */
+#define VA_START_OFFSET				0x3000
+#define BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL	(VA_START_OFFSET + 0x0000)
+#define BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL \
+						(VA_START_OFFSET + 0x0004)
+#define BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL	(VA_START_OFFSET + 0x0008)
+#define BOLERO_CDC_VA_TOP_CSR_TOP_CFG0		(VA_START_OFFSET + 0x0080)
+#define BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL		(VA_START_OFFSET + 0x0084)
+#define BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL		(VA_START_OFFSET + 0x0088)
+#define BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL		(VA_START_OFFSET + 0x008C)
+#define BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL		(VA_START_OFFSET + 0x0090)
+#define BOLERO_CDC_VA_TOP_CSR_DMIC_CFG		(VA_START_OFFSET + 0x0094)
+#define BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS		(VA_START_OFFSET + 0x009C)
+#define BOLERO_CDC_VA_TOP_CSR_DEBUG_EN		(VA_START_OFFSET + 0x00A0)
+#define BOLERO_CDC_VA_TOP_CSR_TX_I2S_CTL	(VA_START_OFFSET + 0x00A4)
+#define BOLERO_CDC_VA_TOP_CSR_I2S_CLK		(VA_START_OFFSET + 0x00A8)
+#define BOLERO_CDC_VA_TOP_CSR_I2S_RESET		(VA_START_OFFSET + 0x00AC)
+#define BOLERO_CDC_VA_TOP_CSR_CORE_ID_0		(VA_START_OFFSET + 0x00C0)
+#define BOLERO_CDC_VA_TOP_CSR_CORE_ID_1		(VA_START_OFFSET + 0x00C4)
+#define BOLERO_CDC_VA_TOP_CSR_CORE_ID_2		(VA_START_OFFSET + 0x00C8)
+#define BOLERO_CDC_VA_TOP_CSR_CORE_ID_3		(VA_START_OFFSET + 0x00CC)
+#define VA_TOP_MAX_OFFSET			(VA_START_OFFSET + 0x00CC)
+
+#define BOLERO_CDC_VA_MACRO_TOP_MAX 0x34 /* 0x0CC/4 = 0x33 + 1 = 0x34 */
+
+#define BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL0	(VA_START_OFFSET + 0x00D0)
+#define BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL1	(VA_START_OFFSET + 0x00D4)
+#define BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL2	(VA_START_OFFSET + 0x00D8)
+#define BOLERO_CDC_VA_TOP_CSR_SWR_CTRL		(VA_START_OFFSET + 0x00DC)
+
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0	(VA_START_OFFSET + 0x0100)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1	(VA_START_OFFSET + 0x0104)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0	(VA_START_OFFSET + 0x0108)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1	(VA_START_OFFSET + 0x010C)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG0	(VA_START_OFFSET + 0x0110)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG1	(VA_START_OFFSET + 0x0114)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG0	(VA_START_OFFSET + 0x0118)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG1	(VA_START_OFFSET + 0x011C)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG0	(VA_START_OFFSET + 0x0120)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG1	(VA_START_OFFSET + 0x0124)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG0	(VA_START_OFFSET + 0x0128)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG1	(VA_START_OFFSET + 0x012C)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG0	(VA_START_OFFSET + 0x0130)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG1	(VA_START_OFFSET + 0x0134)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG0	(VA_START_OFFSET + 0x0138)
+#define BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG1	(VA_START_OFFSET + 0x013C)
+
+#define BOLERO_CDC_VA_TX0_TX_PATH_CTL	(VA_START_OFFSET + 0x0400)
+#define BOLERO_CDC_VA_TX0_TX_PATH_CFG0	(VA_START_OFFSET + 0x0404)
+#define BOLERO_CDC_VA_TX0_TX_PATH_CFG1	(VA_START_OFFSET + 0x0408)
+#define BOLERO_CDC_VA_TX0_TX_VOL_CTL	(VA_START_OFFSET + 0x040C)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC0	(VA_START_OFFSET + 0x0410)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC1	(VA_START_OFFSET + 0x0414)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC2	(VA_START_OFFSET + 0x0418)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC3	(VA_START_OFFSET + 0x041C)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC4	(VA_START_OFFSET + 0x0420)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC5	(VA_START_OFFSET + 0x0424)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC6	(VA_START_OFFSET + 0x0428)
+#define BOLERO_CDC_VA_TX0_TX_PATH_SEC7	(VA_START_OFFSET + 0x042C)
+#define BOLERO_CDC_VA_TX1_TX_PATH_CTL	(VA_START_OFFSET + 0x0480)
+#define BOLERO_CDC_VA_TX1_TX_PATH_CFG0	(VA_START_OFFSET + 0x0484)
+#define BOLERO_CDC_VA_TX1_TX_PATH_CFG1	(VA_START_OFFSET + 0x0488)
+#define BOLERO_CDC_VA_TX1_TX_VOL_CTL	(VA_START_OFFSET + 0x048C)
+#define BOLERO_CDC_VA_TX1_TX_PATH_SEC0	(VA_START_OFFSET + 0x0490)
+#define BOLERO_CDC_VA_TX1_TX_PATH_SEC1	(VA_START_OFFSET + 0x0494)
+#define BOLERO_CDC_VA_TX1_TX_PATH_SEC2	(VA_START_OFFSET + 0x0498)
+#define BOLERO_CDC_VA_TX1_TX_PATH_SEC3	(VA_START_OFFSET + 0x049C)
+#define BOLERO_CDC_VA_TX1_TX_PATH_SEC4	(VA_START_OFFSET + 0x04A0)
+#define BOLERO_CDC_VA_TX1_TX_PATH_SEC5	(VA_START_OFFSET + 0x04A4)
+#define BOLERO_CDC_VA_TX1_TX_PATH_SEC6	(VA_START_OFFSET + 0x04A8)
+#define BOLERO_CDC_VA_TX2_TX_PATH_CTL	(VA_START_OFFSET + 0x0500)
+#define BOLERO_CDC_VA_TX2_TX_PATH_CFG0	(VA_START_OFFSET + 0x0504)
+#define BOLERO_CDC_VA_TX2_TX_PATH_CFG1	(VA_START_OFFSET + 0x0508)
+#define BOLERO_CDC_VA_TX2_TX_VOL_CTL	(VA_START_OFFSET + 0x050C)
+#define BOLERO_CDC_VA_TX2_TX_PATH_SEC0	(VA_START_OFFSET + 0x0510)
+#define BOLERO_CDC_VA_TX2_TX_PATH_SEC1	(VA_START_OFFSET + 0x0514)
+#define BOLERO_CDC_VA_TX2_TX_PATH_SEC2	(VA_START_OFFSET + 0x0518)
+#define BOLERO_CDC_VA_TX2_TX_PATH_SEC3	(VA_START_OFFSET + 0x051C)
+#define BOLERO_CDC_VA_TX2_TX_PATH_SEC4	(VA_START_OFFSET + 0x0520)
+#define BOLERO_CDC_VA_TX2_TX_PATH_SEC5	(VA_START_OFFSET + 0x0524)
+#define BOLERO_CDC_VA_TX2_TX_PATH_SEC6	(VA_START_OFFSET + 0x0528)
+#define BOLERO_CDC_VA_TX3_TX_PATH_CTL	(VA_START_OFFSET + 0x0580)
+#define BOLERO_CDC_VA_TX3_TX_PATH_CFG0	(VA_START_OFFSET + 0x0584)
+#define BOLERO_CDC_VA_TX3_TX_PATH_CFG1	(VA_START_OFFSET + 0x0588)
+#define BOLERO_CDC_VA_TX3_TX_VOL_CTL	(VA_START_OFFSET + 0x058C)
+#define BOLERO_CDC_VA_TX3_TX_PATH_SEC0	(VA_START_OFFSET + 0x0590)
+#define BOLERO_CDC_VA_TX3_TX_PATH_SEC1	(VA_START_OFFSET + 0x0594)
+#define BOLERO_CDC_VA_TX3_TX_PATH_SEC2	(VA_START_OFFSET + 0x0598)
+#define BOLERO_CDC_VA_TX3_TX_PATH_SEC3	(VA_START_OFFSET + 0x059C)
+#define BOLERO_CDC_VA_TX3_TX_PATH_SEC4	(VA_START_OFFSET + 0x05A0)
+#define BOLERO_CDC_VA_TX3_TX_PATH_SEC5	(VA_START_OFFSET + 0x05A4)
+#define BOLERO_CDC_VA_TX3_TX_PATH_SEC6	(VA_START_OFFSET + 0x05A8)
+#define BOLERO_CDC_VA_TX4_TX_PATH_CTL	(VA_START_OFFSET + 0x0600)
+#define BOLERO_CDC_VA_TX4_TX_PATH_CFG0	(VA_START_OFFSET + 0x0604)
+#define BOLERO_CDC_VA_TX4_TX_PATH_CFG1	(VA_START_OFFSET + 0x0608)
+#define BOLERO_CDC_VA_TX4_TX_VOL_CTL	(VA_START_OFFSET + 0x060C)
+#define BOLERO_CDC_VA_TX4_TX_PATH_SEC0	(VA_START_OFFSET + 0x0610)
+#define BOLERO_CDC_VA_TX4_TX_PATH_SEC1	(VA_START_OFFSET + 0x0614)
+#define BOLERO_CDC_VA_TX4_TX_PATH_SEC2	(VA_START_OFFSET + 0x0618)
+#define BOLERO_CDC_VA_TX4_TX_PATH_SEC3	(VA_START_OFFSET + 0x061C)
+#define BOLERO_CDC_VA_TX4_TX_PATH_SEC4	(VA_START_OFFSET + 0x0620)
+#define BOLERO_CDC_VA_TX4_TX_PATH_SEC5	(VA_START_OFFSET + 0x0624)
+#define BOLERO_CDC_VA_TX4_TX_PATH_SEC6	(VA_START_OFFSET + 0x0628)
+#define BOLERO_CDC_VA_TX5_TX_PATH_CTL	(VA_START_OFFSET + 0x0680)
+#define BOLERO_CDC_VA_TX5_TX_PATH_CFG0	(VA_START_OFFSET + 0x0684)
+#define BOLERO_CDC_VA_TX5_TX_PATH_CFG1	(VA_START_OFFSET + 0x0688)
+#define BOLERO_CDC_VA_TX5_TX_VOL_CTL	(VA_START_OFFSET + 0x068C)
+#define BOLERO_CDC_VA_TX5_TX_PATH_SEC0	(VA_START_OFFSET + 0x0690)
+#define BOLERO_CDC_VA_TX5_TX_PATH_SEC1	(VA_START_OFFSET + 0x0694)
+#define BOLERO_CDC_VA_TX5_TX_PATH_SEC2	(VA_START_OFFSET + 0x0698)
+#define BOLERO_CDC_VA_TX5_TX_PATH_SEC3	(VA_START_OFFSET + 0x069C)
+#define BOLERO_CDC_VA_TX5_TX_PATH_SEC4	(VA_START_OFFSET + 0x06A0)
+#define BOLERO_CDC_VA_TX5_TX_PATH_SEC5	(VA_START_OFFSET + 0x06A4)
+#define BOLERO_CDC_VA_TX5_TX_PATH_SEC6	(VA_START_OFFSET + 0x06A8)
+#define BOLERO_CDC_VA_TX6_TX_PATH_CTL	(VA_START_OFFSET + 0x0700)
+#define BOLERO_CDC_VA_TX6_TX_PATH_CFG0	(VA_START_OFFSET + 0x0704)
+#define BOLERO_CDC_VA_TX6_TX_PATH_CFG1	(VA_START_OFFSET + 0x0708)
+#define BOLERO_CDC_VA_TX6_TX_VOL_CTL	(VA_START_OFFSET + 0x070C)
+#define BOLERO_CDC_VA_TX6_TX_PATH_SEC0	(VA_START_OFFSET + 0x0710)
+#define BOLERO_CDC_VA_TX6_TX_PATH_SEC1	(VA_START_OFFSET + 0x0714)
+#define BOLERO_CDC_VA_TX6_TX_PATH_SEC2	(VA_START_OFFSET + 0x0718)
+#define BOLERO_CDC_VA_TX6_TX_PATH_SEC3	(VA_START_OFFSET + 0x071C)
+#define BOLERO_CDC_VA_TX6_TX_PATH_SEC4	(VA_START_OFFSET + 0x0720)
+#define BOLERO_CDC_VA_TX6_TX_PATH_SEC5	(VA_START_OFFSET + 0x0724)
+#define BOLERO_CDC_VA_TX6_TX_PATH_SEC6	(VA_START_OFFSET + 0x0728)
+#define BOLERO_CDC_VA_TX7_TX_PATH_CTL	(VA_START_OFFSET + 0x0780)
+#define BOLERO_CDC_VA_TX7_TX_PATH_CFG0	(VA_START_OFFSET + 0x0784)
+#define BOLERO_CDC_VA_TX7_TX_PATH_CFG1	(VA_START_OFFSET + 0x0788)
+#define BOLERO_CDC_VA_TX7_TX_VOL_CTL	(VA_START_OFFSET + 0x078C)
+#define BOLERO_CDC_VA_TX7_TX_PATH_SEC0	(VA_START_OFFSET + 0x0790)
+#define BOLERO_CDC_VA_TX7_TX_PATH_SEC1	(VA_START_OFFSET + 0x0794)
+#define BOLERO_CDC_VA_TX7_TX_PATH_SEC2	(VA_START_OFFSET + 0x0798)
+#define BOLERO_CDC_VA_TX7_TX_PATH_SEC3	(VA_START_OFFSET + 0x079C)
+#define BOLERO_CDC_VA_TX7_TX_PATH_SEC4	(VA_START_OFFSET + 0x07A0)
+#define BOLERO_CDC_VA_TX7_TX_PATH_SEC5	(VA_START_OFFSET + 0x07A4)
+#define BOLERO_CDC_VA_TX7_TX_PATH_SEC6	(VA_START_OFFSET + 0x07A8)
+#define VA_MAX_OFFSET			(VA_START_OFFSET + 0x07A8)
+
+#define BOLERO_CDC_VA_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 = 1EB */
+
+#define BOLERO_CDC_MAX_REGISTER VA_MAX_OFFSET
+
+#define BOLERO_REG(reg)  (((reg) & 0x0FFF)/4)
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/bolero/bolero-cdc-regmap.c

@@ -0,0 +1,877 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/regmap.h>
+#include "bolero-cdc.h"
+#include "internal.h"
+
+static const struct reg_default bolero_defaults[] = {
+	/* TX Macro */
+	{ BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
+	{ BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
+	{ BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_ANC_CFG, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
+	{ BOLERO_CDC_TX_TOP_CSR_I2S_CLK, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_I2S_RESET, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
+	{ BOLERO_CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
+	{ BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
+	{ BOLERO_CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_MODE_1_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_MODE_2_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_FF_SHIFT, 0x00},
+	{ BOLERO_CDC_TX_ANC0_FB_SHIFT, 0x00},
+	{ BOLERO_CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_LPF_FB_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_SMLPF_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
+	{ BOLERO_CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
+	{ BOLERO_CDC_TX0_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX0_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX0_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX0_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_TX0_TX_PATH_SEC7, 0x25},
+	{ BOLERO_CDC_TX1_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX1_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX1_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX1_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX1_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX1_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX1_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX1_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX1_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX1_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX1_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_TX2_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX2_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX2_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX2_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX2_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX2_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX2_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX2_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX2_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX2_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX2_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_TX3_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX3_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX3_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX3_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX3_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX3_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX3_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX3_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX3_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX3_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX3_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_TX4_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX4_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX4_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX4_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX4_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX4_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX4_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX4_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX4_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX4_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX4_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_TX5_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX5_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX5_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX5_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX5_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX5_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX5_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX5_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX5_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX5_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX5_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_TX6_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX6_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX6_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX6_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX6_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX6_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX6_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX6_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX6_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX6_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX6_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_TX7_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_TX7_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_TX7_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_TX7_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_TX7_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_TX7_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_TX7_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_TX7_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_TX7_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_TX7_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_TX7_TX_PATH_SEC6, 0x00},
+
+	/* RX Macro */
+	{ BOLERO_CDC_RX_TOP_TOP_CFG0, 0x00},
+	{ BOLERO_CDC_RX_TOP_SWR_CTRL, 0x00},
+	{ BOLERO_CDC_RX_TOP_DEBUG, 0x00},
+	{ BOLERO_CDC_RX_TOP_DEBUG_BUS, 0x00},
+	{ BOLERO_CDC_RX_TOP_DEBUG_EN0, 0x00},
+	{ BOLERO_CDC_RX_TOP_DEBUG_EN1, 0x00},
+	{ BOLERO_CDC_RX_TOP_DEBUG_EN2, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHL_COMP_LUT, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHR_COMP_LUT, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00},
+	{ BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11},
+	{ BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20},
+	{ BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00},
+	{ BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00},
+	{ BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11},
+	{ BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20},
+	{ BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00},
+	{ BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00},
+	{ BOLERO_CDC_RX_TOP_RX_I2S_CTL, 0x0C},
+	{ BOLERO_CDC_RX_TOP_TX_I2S2_CTL, 0x0C},
+	{ BOLERO_CDC_RX_TOP_I2S_CLK, 0x0C},
+	{ BOLERO_CDC_RX_TOP_I2S_RESET, 0x00},
+	{ BOLERO_CDC_RX_TOP_I2S_MUX, 0x00},
+	{ BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
+	{ BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
+	{ BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
+	{ BOLERO_CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00},
+	{ BOLERO_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08},
+	{ BOLERO_CDC_RX_SOFTCLIP_CRC, 0x00},
+	{ BOLERO_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38},
+	{ BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00},
+	{ BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00},
+	{ BOLERO_CDC_RX_CLSH_CRC, 0x00},
+	{ BOLERO_CDC_RX_CLSH_DLY_CTRL, 0x03},
+	{ BOLERO_CDC_RX_CLSH_DECAY_CTRL, 0x02},
+	{ BOLERO_CDC_RX_CLSH_HPH_V_PA, 0x1C},
+	{ BOLERO_CDC_RX_CLSH_EAR_V_PA, 0x39},
+	{ BOLERO_CDC_RX_CLSH_HPH_V_HD, 0x0C},
+	{ BOLERO_CDC_RX_CLSH_EAR_V_HD, 0x0C},
+	{ BOLERO_CDC_RX_CLSH_K1_MSB, 0x01},
+	{ BOLERO_CDC_RX_CLSH_K1_LSB, 0x00},
+	{ BOLERO_CDC_RX_CLSH_K2_MSB, 0x00},
+	{ BOLERO_CDC_RX_CLSH_K2_LSB, 0x80},
+	{ BOLERO_CDC_RX_CLSH_IDLE_CTRL, 0x00},
+	{ BOLERO_CDC_RX_CLSH_IDLE_HPH, 0x00},
+	{ BOLERO_CDC_RX_CLSH_IDLE_EAR, 0x00},
+	{ BOLERO_CDC_RX_CLSH_TEST0, 0x07},
+	{ BOLERO_CDC_RX_CLSH_TEST1, 0x00},
+	{ BOLERO_CDC_RX_CLSH_OVR_VREF, 0x00},
+	{ BOLERO_CDC_RX_CLSH_CLSG_CTL, 0x02},
+	{ BOLERO_CDC_RX_CLSH_CLSG_CFG1, 0x9A},
+	{ BOLERO_CDC_RX_CLSH_CLSG_CFG2, 0x10},
+	{ BOLERO_CDC_RX_BCL_VBAT_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_CFG, 0x10},
+	{ BOLERO_CDC_RX_BCL_VBAT_ADC_CAL1, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_ADC_CAL2, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_ADC_CAL3, 0x04},
+	{ BOLERO_CDC_RX_BCL_VBAT_PK_EST1, 0xE0},
+	{ BOLERO_CDC_RX_BCL_VBAT_PK_EST2, 0x01},
+	{ BOLERO_CDC_RX_BCL_VBAT_PK_EST3, 0x40},
+	{ BOLERO_CDC_RX_BCL_VBAT_RF_PROC1, 0x2A},
+	{ BOLERO_CDC_RX_BCL_VBAT_RF_PROC2, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_TAC1, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_TAC2, 0x18},
+	{ BOLERO_CDC_RX_BCL_VBAT_TAC3, 0x18},
+	{ BOLERO_CDC_RX_BCL_VBAT_TAC4, 0x03},
+	{ BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01},
+	{ BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64},
+	{ BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01},
+	{ BOLERO_CDC_RX_BCL_VBAT_DEBUG1, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_BAN, 0x0C},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_ATTN1, 0x04},
+	{ BOLERO_CDC_RX_BCL_VBAT_ATTN2, 0x08},
+	{ BOLERO_CDC_RX_BCL_VBAT_ATTN3, 0x0C},
+	{ BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0},
+	{ BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00},
+	{ BOLERO_CDC_RX_BCL_VBAT_DECODE_ST, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_CFG, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF},
+	{ BOLERO_CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF},
+	{ BOLERO_CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_LEVEL0, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_BYPASS0, 0x00},
+	{ BOLERO_CDC_RX_INTR_CTRL_SET0, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_CFG1, 0x64},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_CFG2, 0x8F},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_CFG3, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E},
+	{ BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x08},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_SEC2, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_SEC3, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_SEC4, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_SEC7, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55},
+	{ BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_CFG1, 0x64},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_CFG2, 0x8F},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_CFG3, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E},
+	{ BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x08},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_SEC2, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_SEC3, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_SEC4, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_SEC7, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55},
+	{ BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_CFG1, 0x64},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_CFG2, 0x8F},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_CFG3, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E},
+	{ BOLERO_CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC0, 0x04},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC1, 0x08},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC2, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC3, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC4, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_SEC7, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00},
+	{ BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00},
+	{ BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_IDLE_DETECT_CFG0, 0x07},
+	{ BOLERO_CDC_RX_IDLE_DETECT_CFG1, 0x3C},
+	{ BOLERO_CDC_RX_IDLE_DETECT_CFG2, 0x00},
+	{ BOLERO_CDC_RX_IDLE_DETECT_CFG3, 0x00},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL0, 0x60},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL1, 0xDB},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL2, 0xFF},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL3, 0x35},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL4, 0xFF},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL5, 0x00},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL6, 0x01},
+	{ BOLERO_CDC_RX_COMPANDER0_CTL7, 0x28},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL0, 0x60},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL1, 0xDB},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL2, 0xFF},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL3, 0x35},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL4, 0xFF},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL5, 0x00},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL6, 0x01},
+	{ BOLERO_CDC_RX_COMPANDER1_CTL7, 0x28},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00},
+	{ BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04},
+	{ BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00},
+	{ BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04},
+	{ BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00},
+	{ BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01},
+	{ BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01},
+	{ BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01},
+	{ BOLERO_CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC0_CTL0, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC0_CTL1, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8},
+	{ BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_CTL0, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_CTL1, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8},
+	{ BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_CTL0, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_CTL1, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8},
+	{ BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00},
+	{ BOLERO_CDC_RX_DSD0_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_DSD0_CFG0, 0x00},
+	{ BOLERO_CDC_RX_DSD0_CFG1, 0x62},
+	{ BOLERO_CDC_RX_DSD0_CFG2, 0x96},
+	{ BOLERO_CDC_RX_DSD1_PATH_CTL, 0x00},
+	{ BOLERO_CDC_RX_DSD1_CFG0, 0x00},
+	{ BOLERO_CDC_RX_DSD1_CFG1, 0x62},
+	{ BOLERO_CDC_RX_DSD1_CFG2, 0x96},
+
+	/* WSA Macro */
+	{ BOLERO_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
+	{ BOLERO_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
+	{ BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
+	{ BOLERO_CDC_WSA_TOP_TOP_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_TOP_TOP_CFG1, 0x00},
+	{ BOLERO_CDC_WSA_TOP_FREQ_MCLK, 0x00},
+	{ BOLERO_CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
+	{ BOLERO_CDC_WSA_TOP_DEBUG_EN0, 0x00},
+	{ BOLERO_CDC_WSA_TOP_DEBUG_EN1, 0x00},
+	{ BOLERO_CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
+	{ BOLERO_CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
+	{ BOLERO_CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
+	{ BOLERO_CDC_WSA_TOP_I2S_CLK, 0x02},
+	{ BOLERO_CDC_WSA_TOP_I2S_RESET, 0x00},
+	{ BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
+	{ BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
+	{ BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, 0x10},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3, 0x04},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST1, 0xE0},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST2, 0x01},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST3, 0x40},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1, 0x2A},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC1, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC2, 0x18},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC3, 0x18},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC4, 0x03},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1, 0x01},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4, 0x64},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5, 0x01},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DEBUG1, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BAN, 0x0C},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2, 0x77},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3, 0x01},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5, 0x4B},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7, 0x01},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1, 0x04},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2, 0x08},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0xE0},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0x00},
+	{ BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST, 0x00},
+	{ BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
+	{ BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
+	{ BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
+	{ BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
+	{ BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_CFG, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
+	{ BOLERO_CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
+	{ BOLERO_CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
+	{ BOLERO_CDC_WSA_INTR_CTRL_SET0, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
+	{ BOLERO_CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
+	{ BOLERO_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
+	{ BOLERO_CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
+	{ BOLERO_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
+	{ BOLERO_CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
+	{ BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
+	{ BOLERO_CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
+	{ BOLERO_CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
+	{ BOLERO_CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
+	{ BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
+	{ BOLERO_CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
+	{ BOLERO_CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL0, 0x60},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL1, 0xDB},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL2, 0xFF},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x35},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL4, 0xFF},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL5, 0x00},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL6, 0x01},
+	{ BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x28},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL0, 0x60},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL1, 0xDB},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL2, 0xFF},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x35},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL4, 0xFF},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL5, 0x00},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL6, 0x01},
+	{ BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x28},
+	{ BOLERO_CDC_WSA_SOFTCLIP0_CRC, 0x00},
+	{ BOLERO_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
+	{ BOLERO_CDC_WSA_SOFTCLIP1_CRC, 0x00},
+	{ BOLERO_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
+	{ BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
+	{ BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
+	{ BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
+	{ BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
+	{ BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
+
+	/* VA macro */
+	{ BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
+	{ BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
+	{ BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
+	{ BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
+	{ BOLERO_CDC_VA_TOP_CSR_I2S_CLK, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_I2S_RESET, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
+	{ BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
+	{ BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
+	{ BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
+	{ BOLERO_CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
+
+	/* VA core */
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG1, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG1, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG1, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG0, 0x00},
+	{ BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG1, 0x00},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX0_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_VA_TX0_TX_PATH_SEC7, 0x25},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX1_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX1_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX2_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX2_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX3_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX3_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX4_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX4_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX5_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX5_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX6_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX6_TX_PATH_SEC6, 0x00},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_CTL, 0x04},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_CFG0, 0x10},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_CFG1, 0x0B},
+	{ BOLERO_CDC_VA_TX7_TX_VOL_CTL, 0x00},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_SEC0, 0x00},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_SEC1, 0x00},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_SEC2, 0x01},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_SEC3, 0x3C},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_SEC4, 0x20},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_SEC5, 0x00},
+	{ BOLERO_CDC_VA_TX7_TX_PATH_SEC6, 0x00},
+};
+
+static bool bolero_is_readable_register(struct device *dev,
+					unsigned int reg)
+{
+	struct bolero_priv *priv = dev_get_drvdata(dev);
+	u16 reg_offset;
+	int macro_id;
+	u8 *reg_tbl = NULL;
+
+	if (!priv)
+		return false;
+
+	macro_id = bolero_get_macro_id(priv->va_without_decimation,
+				       reg);
+	if (macro_id < 0 || !priv->macros_supported[macro_id])
+		return false;
+
+	reg_tbl = bolero_reg_access[macro_id];
+	reg_offset = (reg - macro_id_base_offset[macro_id])/4;
+
+	if (reg_tbl)
+		return (reg_tbl[reg_offset] & RD_REG);
+
+	return false;
+}
+
+static bool bolero_is_writeable_register(struct device *dev,
+					 unsigned int reg)
+{
+	struct bolero_priv *priv = dev_get_drvdata(dev);
+	u16 reg_offset;
+	int macro_id;
+	const u8 *reg_tbl = NULL;
+
+	if (!priv)
+		return false;
+
+	macro_id = bolero_get_macro_id(priv->va_without_decimation,
+				       reg);
+	if (macro_id < 0 || !priv->macros_supported[macro_id])
+		return false;
+
+	reg_tbl = bolero_reg_access[macro_id];
+	reg_offset = (reg - macro_id_base_offset[macro_id])/4;
+
+	if (reg_tbl)
+		return (reg_tbl[reg_offset] & WR_REG);
+
+	return false;
+}
+
+static bool bolero_is_volatile_register(struct device *dev,
+					unsigned int reg)
+{
+	/* Update volatile list for rx/tx macros */
+	switch (reg) {
+	case BOLERO_CDC_VA_TOP_CSR_CORE_ID_0:
+	case BOLERO_CDC_VA_TOP_CSR_CORE_ID_1:
+	case BOLERO_CDC_VA_TOP_CSR_CORE_ID_2:
+	case BOLERO_CDC_VA_TOP_CSR_CORE_ID_3:
+	case BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL:
+	case BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL:
+	case BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL:
+	case BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL:
+	case BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
+	case BOLERO_CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
+	case BOLERO_CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
+	case BOLERO_CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
+	case BOLERO_CDC_TX_TOP_CSR_SWR_MIC0_CTL:
+	case BOLERO_CDC_TX_TOP_CSR_SWR_MIC1_CTL:
+	case BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL:
+	case BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST:
+	case BOLERO_CDC_WSA_INTR_CTRL_PIN1_STATUS0:
+	case BOLERO_CDC_WSA_INTR_CTRL_PIN2_STATUS0:
+	case BOLERO_CDC_WSA_COMPANDER0_CTL6:
+	case BOLERO_CDC_WSA_COMPANDER1_CTL6:
+	case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
+	case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
+	case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
+	case BOLERO_CDC_RX_TOP_HPHL_COMP_RD_LSB:
+	case BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB:
+	case BOLERO_CDC_RX_TOP_HPHL_COMP_RD_MSB:
+	case BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB:
+	case BOLERO_CDC_RX_TOP_HPHR_COMP_RD_LSB:
+	case BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB:
+	case BOLERO_CDC_RX_TOP_HPHR_COMP_RD_MSB:
+	case BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB:
+	case BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG2:
+	case BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG2:
+	case BOLERO_CDC_RX_BCL_VBAT_GAIN_MON_VAL:
+	case BOLERO_CDC_RX_BCL_VBAT_DECODE_ST:
+	case BOLERO_CDC_RX_INTR_CTRL_PIN1_STATUS0:
+	case BOLERO_CDC_RX_INTR_CTRL_PIN2_STATUS0:
+	case BOLERO_CDC_RX_COMPANDER0_CTL6:
+	case BOLERO_CDC_RX_COMPANDER1_CTL6:
+	case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
+	case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
+	case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
+	case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
+	case BOLERO_CDC_RX_EC_ASRC0_STATUS_FIFO:
+	case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
+	case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
+	case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
+	case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
+	case BOLERO_CDC_RX_EC_ASRC1_STATUS_FIFO:
+	case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
+	case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
+	case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
+	case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
+	case BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO:
+	case BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL:
+	case BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL:
+	case BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL:
+	case BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL:
+		return true;
+	}
+	return false;
+}
+
+const struct regmap_config bolero_regmap_config = {
+	.reg_bits = 16,
+	.val_bits = 8,
+	.reg_stride = 4,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_defaults = bolero_defaults,
+	.num_reg_defaults = ARRAY_SIZE(bolero_defaults),
+	.max_register = BOLERO_CDC_MAX_REGISTER,
+	.writeable_reg = bolero_is_writeable_register,
+	.volatile_reg = bolero_is_volatile_register,
+	.readable_reg = bolero_is_readable_register,
+};

qcom/opensource/audio-kernel/asoc/codecs/bolero/bolero-cdc-tables.c

@@ -0,0 +1,982 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include "bolero-cdc.h"
+#include "internal.h"
+
+u8 bolero_tx_reg_access[BOLERO_CDC_TX_MACRO_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX4_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX5_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX6_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX7_TX_PATH_SEC6)] = RD_WR_REG,
+};
+
+u8 bolero_tx_reg_access_v2[BOLERO_CDC_TX_MACRO_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX0_TX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX1_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX2_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_TX3_TX_PATH_SEC6)] = RD_WR_REG,
+};
+
+u8 bolero_rx_reg_access[BOLERO_CDC_RX_MACRO_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_SWR_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DEBUG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DEBUG_BUS)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DEBUG_EN0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DEBUG_EN1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DEBUG_EN2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHL_COMP_LUT)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHL_COMP_RD_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHL_COMP_RD_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHR_COMP_LUT)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHR_COMP_RD_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_HPHR_COMP_RD_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG2)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG2)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_RX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_TX_I2S2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_I2S_CLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_I2S_RESET)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_TOP_I2S_MUX)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLK_RST_CTRL_DSD_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SOFTCLIP_CRC)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_CRC)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_DLY_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_DECAY_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_HPH_V_PA)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_EAR_V_PA)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_HPH_V_HD)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_EAR_V_HD)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_K1_MSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_K1_LSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_K2_MSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_K2_LSB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_IDLE_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_IDLE_HPH)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_IDLE_EAR)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_TEST0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_TEST1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_OVR_VREF)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_CLSG_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_CLSG_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_CLSH_CLSG_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_ADC_CAL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_ADC_CAL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_ADC_CAL3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_PK_EST1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_PK_EST2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_PK_EST3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_RF_PROC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_RF_PROC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_TAC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_TAC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_TAC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_TAC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DEBUG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD_MON)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_GAIN_MON_VAL)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BAN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_ATTN1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_ATTN2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_ATTN3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_BCL_VBAT_DECODE_ST)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_CLR_COMMIT)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_PIN1_STATUS0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_PIN1_CLEAR0)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_PIN2_MASK0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_PIN2_STATUS0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_PIN2_CLEAR0)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_LEVEL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_BYPASS0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_INTR_CTRL_SET0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_MIX_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_MIX_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_DSM_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_MIX_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_VOL_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IDLE_DETECT_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IDLE_DETECT_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL6)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL6)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL)] =
+								RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL)] =
+								RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_CLK_RST_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_FIFO_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC0_STATUS_FIFO)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_CLK_RST_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_FIFO_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC1_STATUS_FIFO)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_CLK_RST_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_FIFO_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD0_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD0_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD1_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_RX_DSD1_CFG2)] = RD_WR_REG,
+};
+
+u8 bolero_va_reg_access[BOLERO_CDC_VA_MACRO_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX4_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX5_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX6_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX7_TX_PATH_SEC6)] = RD_WR_REG,
+};
+
+u8 bolero_va_top_reg_access[BOLERO_CDC_VA_MACRO_TOP_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
+};
+
+u8 bolero_va_reg_access_v2[BOLERO_CDC_VA_MACRO_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
+};
+
+u8 bolero_va_reg_access_v3[BOLERO_CDC_VA_MACRO_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX2_TX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_VA_TX3_TX_PATH_SEC6)] = RD_WR_REG,
+};
+
+u8 bolero_wsa_reg_access[BOLERO_CDC_WSA_MACRO_MAX] = {
+	[BOLERO_REG(BOLERO_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_TOP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_TOP_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_FREQ_MCLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_DEBUG_BUS_SEL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_DEBUG_EN0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_DEBUG_EN1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_DEBUG_DSM_LB)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_RX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_TX_I2S_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_I2S_CLK)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TOP_I2S_RESET)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX_INP_MUX_RX_EC_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DEBUG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BAN)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_CLR_COMMIT)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_PIN1_STATUS0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_PIN1_CLEAR0)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_PIN2_MASK0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_PIN2_STATUS0)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_PIN2_CLEAR0)] = WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_LEVEL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_BYPASS0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_INTR_CTRL_SET0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_VOL_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_CFG3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_VOL_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CFG)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_VOL_MIX_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_SEC2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_SEC3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_SEC5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_SEC6)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_SEC7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST0_BOOST_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST0_BOOST_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST0_BOOST_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST0_BOOST_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST1_BOOST_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST1_BOOST_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST1_BOOST_CFG1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_BOOST1_BOOST_CFG2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL6)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER0_CTL7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL2)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL3)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL4)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL5)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL6)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_COMPANDER1_CTL7)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SOFTCLIP0_CRC)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SOFTCLIP1_CRC)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_FIFO_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_CTL0)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_CTL1)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_FIFO_CTL)] = RD_WR_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB)] = RD_REG,
+	[BOLERO_REG(BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO)] = RD_REG,
+};
+
+u8 *bolero_reg_access[MAX_MACRO] = {
+	[TX_MACRO] = bolero_tx_reg_access,
+	[RX_MACRO] = bolero_rx_reg_access,
+	[WSA_MACRO] = bolero_wsa_reg_access,
+	[VA_MACRO] = bolero_va_reg_access,
+};

qcom/opensource/audio-kernel/asoc/codecs/bolero/bolero-cdc-utils.c

@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+#include "bolero-cdc.h"
+#include "internal.h"
+
+#define REG_BYTES 2
+#define VAL_BYTES 1
+
+const u16 macro_id_base_offset[MAX_MACRO] = {
+	TX_START_OFFSET,
+	RX_START_OFFSET,
+	WSA_START_OFFSET,
+	VA_START_OFFSET,
+};
+
+int bolero_get_macro_id(bool va_no_dec_flag, u16 reg)
+{
+	if (reg >= TX_START_OFFSET
+		&& reg <= TX_MAX_OFFSET)
+		return TX_MACRO;
+	if (reg >= RX_START_OFFSET
+		&& reg <= RX_MAX_OFFSET)
+		return RX_MACRO;
+	if (reg >= WSA_START_OFFSET
+		&& reg <= WSA_MAX_OFFSET)
+		return WSA_MACRO;
+	if (!va_no_dec_flag &&
+		(reg >= VA_START_OFFSET &&
+		reg <= VA_MAX_OFFSET))
+		return VA_MACRO;
+	if (va_no_dec_flag &&
+		(reg >= VA_START_OFFSET &&
+		reg <= VA_TOP_MAX_OFFSET))
+		return VA_MACRO;
+
+	return -EINVAL;
+}
+
+static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
+			   void *val, size_t val_size)
+{
+	struct device *dev = context;
+	struct bolero_priv *priv = dev_get_drvdata(dev);
+	u16 *reg_p;
+	u16 __reg;
+	int macro_id, i;
+	u8 temp = 0;
+	int ret = -EINVAL;
+
+	if (!priv) {
+		dev_err(dev, "%s: priv is NULL\n", __func__);
+		return ret;
+	}
+	if (!reg || !val) {
+		dev_err(dev, "%s: reg or val is NULL\n", __func__);
+		return ret;
+	}
+	if (reg_size != REG_BYTES) {
+		dev_err(dev, "%s: register size %zd bytes, not supported\n",
+			__func__, reg_size);
+		return ret;
+	}
+
+	reg_p = (u16 *)reg;
+	macro_id = bolero_get_macro_id(priv->va_without_decimation,
+					   reg_p[0]);
+	if (macro_id < 0 || !priv->macros_supported[macro_id])
+		return 0;
+
+	mutex_lock(&priv->io_lock);
+	for (i = 0; i < val_size; i++) {
+		__reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id];
+		ret = priv->read_dev(priv, macro_id, __reg, &temp);
+		if (ret < 0) {
+			dev_err_ratelimited(dev,
+			"%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
+			__func__, ret, reg_p[0] + i * 4, val_size);
+			break;
+		}
+		((u8 *)val)[i] = temp;
+		dev_dbg(dev, "%s: Read 0x%02x from reg 0x%x\n",
+			__func__, temp, reg_p[0] + i * 4);
+	}
+	mutex_unlock(&priv->io_lock);
+
+	return ret;
+}
+
+static int regmap_bus_gather_write(void *context,
+				   const void *reg, size_t reg_size,
+				   const void *val, size_t val_size)
+{
+	struct device *dev = context;
+	struct bolero_priv *priv = dev_get_drvdata(dev);
+	u16 *reg_p;
+	u16 __reg;
+	int macro_id, i;
+	int ret = -EINVAL;
+
+	if (!priv) {
+		dev_err(dev, "%s: priv is NULL\n", __func__);
+		return ret;
+	}
+	if (!reg || !val) {
+		dev_err(dev, "%s: reg or val is NULL\n", __func__);
+		return ret;
+	}
+	if (reg_size != REG_BYTES) {
+		dev_err(dev, "%s: register size %zd bytes, not supported\n",
+			__func__, reg_size);
+		return ret;
+	}
+
+	reg_p = (u16 *)reg;
+	macro_id = bolero_get_macro_id(priv->va_without_decimation,
+					reg_p[0]);
+	if (macro_id < 0 || !priv->macros_supported[macro_id])
+		return 0;
+
+	mutex_lock(&priv->io_lock);
+	for (i = 0; i < val_size; i++) {
+		__reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id];
+		ret = priv->write_dev(priv, macro_id, __reg, ((u8 *)val)[i]);
+		if (ret < 0) {
+			dev_err_ratelimited(dev,
+			"%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
+			__func__, ret, reg_p[0] + i * 4, val_size);
+			break;
+		}
+		dev_dbg(dev, "Write %02x to reg 0x%x\n", ((u8 *)val)[i],
+			reg_p[0] + i * 4);
+	}
+	mutex_unlock(&priv->io_lock);
+	return ret;
+}
+
+static int regmap_bus_write(void *context, const void *data, size_t count)
+{
+	struct device *dev = context;
+	struct bolero_priv *priv = dev_get_drvdata(dev);
+
+	if (!priv)
+		return -EINVAL;
+
+	if (count < REG_BYTES) {
+		dev_err(dev, "%s: count %zd bytes < %d, not supported\n",
+			__func__, count, REG_BYTES);
+		return -EINVAL;
+	}
+
+	return regmap_bus_gather_write(context, data, REG_BYTES,
+				       data + REG_BYTES,
+				       count - REG_BYTES);
+}
+
+static struct regmap_bus regmap_bus_config = {
+	.write = regmap_bus_write,
+	.gather_write = regmap_bus_gather_write,
+	.read = regmap_bus_read,
+	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+struct regmap *bolero_regmap_init(struct device *dev,
+				      const struct regmap_config *config)
+{
+	return devm_regmap_init(dev, &regmap_bus_config, dev, config);
+}

qcom/opensource/audio-kernel/asoc/codecs/bolero/bolero-cdc.h

@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef BOLERO_CDC_H
+#define BOLERO_CDC_H
+
+#include <sound/soc.h>
+#include <linux/regmap.h>
+
+#define BOLERO_VERSION_1_0 0x0001
+#define BOLERO_VERSION_1_1 0x0002
+#define BOLERO_VERSION_1_2 0x0003
+#define BOLERO_VERSION_2_0 0x0004
+#define BOLERO_VERSION_2_1 0x0005
+#define BOLERO_VERSION_2_2 0x0006
+
+enum {
+	START_MACRO,
+	TX_MACRO = START_MACRO,
+	RX_MACRO,
+	WSA_MACRO,
+	VA_MACRO,
+	MAX_MACRO
+};
+
+enum mclk_mux {
+	MCLK_MUX0,
+	MCLK_MUX1,
+	MCLK_MUX_MAX
+};
+
+enum {
+	BOLERO_ADC0 = 1,
+	BOLERO_ADC1,
+	BOLERO_ADC2,
+	BOLERO_ADC3,
+	BOLERO_ADC_MAX
+};
+
+enum {
+	CLK_SRC_TX_RCG = 0,
+	CLK_SRC_VA_RCG,
+};
+
+enum {
+	BOLERO_MACRO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
+	BOLERO_MACRO_EVT_IMPED_TRUE, /* for imped true */
+	BOLERO_MACRO_EVT_IMPED_FALSE, /* for imped false */
+	BOLERO_MACRO_EVT_SSR_DOWN,
+	BOLERO_MACRO_EVT_SSR_UP,
+	BOLERO_MACRO_EVT_WAIT_VA_CLK_RESET,
+	BOLERO_MACRO_EVT_CLK_RESET,
+	BOLERO_MACRO_EVT_REG_WAKE_IRQ,
+	BOLERO_MACRO_EVT_RX_COMPANDER_SOFT_RST,
+	BOLERO_MACRO_EVT_BCS_CLK_OFF,
+	BOLERO_MACRO_EVT_SSR_GFMUX_UP,
+	BOLERO_MACRO_EVT_PRE_SSR_UP,
+	BOLERO_MACRO_EVT_RX_PA_GAIN_UPDATE,
+	BOLERO_MACRO_EVT_HPHL_HD2_ENABLE, /* Enable HD2 cfg for HPHL */
+	BOLERO_MACRO_EVT_HPHR_HD2_ENABLE, /* Enable HD2 cfg for HPHR */
+};
+
+enum {
+	DMIC_TX = 0,
+	DMIC_VA = 1,
+
+};
+
+struct macro_ops {
+	int (*init)(struct snd_soc_component *component);
+	int (*exit)(struct snd_soc_component *component);
+	u16 num_dais;
+	struct device *dev;
+	struct snd_soc_dai_driver *dai_ptr;
+	int (*mclk_fn)(struct device *dev, bool enable);
+	int (*event_handler)(struct snd_soc_component *component, u16 event,
+			     u32 data);
+	int (*reg_wake_irq)(struct snd_soc_component *component, u32 data);
+	int (*set_port_map)(struct snd_soc_component *component, u32 uc,
+			    u32 size, void *data);
+	int (*clk_div_get)(struct snd_soc_component *component);
+	int (*clk_switch)(struct snd_soc_component *component, int clk_src);
+	int (*reg_evt_listener)(struct snd_soc_component *component, bool en);
+	int (*clk_enable)(struct snd_soc_component *c, bool en);
+	char __iomem *io_base;
+	u16 clk_id_req;
+	u16 default_clk_id;
+};
+
+typedef int (*rsc_clk_cb_t)(struct device *dev, u16 event);
+
+#if IS_ENABLED(CONFIG_SND_SOC_BOLERO)
+int bolero_register_res_clk(struct device *dev, rsc_clk_cb_t cb);
+void bolero_unregister_res_clk(struct device *dev);
+bool bolero_is_va_macro_registered(struct device *dev);
+int bolero_register_macro(struct device *dev, u16 macro_id,
+			  struct macro_ops *ops);
+void bolero_unregister_macro(struct device *dev, u16 macro_id);
+struct device *bolero_get_device_ptr(struct device *dev, u16 macro_id);
+struct device *bolero_get_rsc_clk_device_ptr(struct device *dev);
+int bolero_info_create_codec_entry(
+		struct snd_info_entry *codec_root,
+		struct snd_soc_component *component);
+int bolero_register_wake_irq(struct snd_soc_component *component, u32 data);
+void bolero_clear_amic_tx_hold(struct device *dev, u16 adc_n);
+int bolero_runtime_resume(struct device *dev);
+int bolero_runtime_suspend(struct device *dev);
+int bolero_set_port_map(struct snd_soc_component *component, u32 size, void *data);
+int bolero_tx_clk_switch(struct snd_soc_component *component, int clk_src);
+int bolero_register_event_listener(struct snd_soc_component *component,
+				   bool enable);
+void bolero_wsa_pa_on(struct device *dev, bool adie_lb);
+bool bolero_check_core_votes(struct device *dev);
+int bolero_tx_mclk_enable(struct snd_soc_component *c, bool enable);
+int bolero_get_version(struct device *dev);
+int bolero_dmic_clk_enable(struct snd_soc_component *component,
+			   u32 dmic, u32 tx_mode, bool enable);
+void bolero_rx_pa_on(struct device *dev);
+#else
+static inline int bolero_register_res_clk(struct device *dev, rsc_clk_cb_t cb)
+{
+	return 0;
+}
+static inline void bolero_unregister_res_clk(struct device *dev)
+{
+}
+
+static bool bolero_is_va_macro_registered(struct device *dev)
+{
+	return false;
+}
+
+static inline int bolero_register_macro(struct device *dev,
+					u16 macro_id,
+					struct macro_ops *ops)
+{
+	return 0;
+}
+
+static inline void bolero_unregister_macro(struct device *dev, u16 macro_id)
+{
+}
+
+static inline struct device *bolero_get_device_ptr(struct device *dev,
+						   u16 macro_id)
+{
+	return NULL;
+}
+
+static int bolero_info_create_codec_entry(
+		struct snd_info_entry *codec_root,
+		struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static inline void bolero_clear_amic_tx_hold(struct device *dev, u16 adc_n)
+{
+}
+
+static inline int bolero_register_wake_irq(struct snd_soc_component *component,
+					   u32 data)
+{
+	return 0;
+}
+
+static inline int bolero_runtime_resume(struct device *dev)
+{
+	return 0;
+}
+
+static int bolero_runtime_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static inline int bolero_set_port_map(struct snd_soc_component *component,
+				u32 size, void *data)
+{
+	return 0;
+}
+
+static inline int bolero_tx_clk_switch(struct snd_soc_component *component,
+					int clk_src)
+{
+	return 0;
+}
+
+static inline int bolero_register_event_listener(
+					struct snd_soc_component *component,
+					bool enable)
+{
+	return 0;
+}
+
+static void bolero_wsa_pa_on(struct device *dev, bool adie_lb)
+{
+}
+
+static inline bool bolero_check_core_votes(struct device *dev)
+{
+	return false;
+}
+
+static int bolero_get_version(struct device *dev)
+{
+	return 0;
+}
+
+static int bolero_dmic_clk_enable(struct snd_soc_component *component,
+			   u32 dmic, u32 tx_mode, bool enable)
+{
+	return 0;
+}
+static int bolero_tx_mclk_enable(struct snd_soc_component *c, bool enable)
+{
+	return 0;
+}
+
+static inline void bolero_rx_pa_on(struct device *dev)
+{
+	return 0;
+}
+
+#endif /* CONFIG_SND_SOC_BOLERO */
+#endif /* BOLERO_CDC_H */

qcom/opensource/audio-kernel/asoc/codecs/bolero/bolero-clk-rsc.c

@@ -0,0 +1,768 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/ratelimit.h>
+#include "bolero-cdc.h"
+#include "bolero-clk-rsc.h"
+
+#define DRV_NAME "bolero-clk-rsc"
+#define BOLERO_CLK_NAME_LENGTH 30
+#define NPL_CLK_OFFSET (TX_NPL_CLK - TX_CORE_CLK)
+
+static char clk_src_name[MAX_CLK][BOLERO_CLK_NAME_LENGTH] = {
+	"tx_core_clk",
+	"rx_core_clk",
+	"wsa_core_clk",
+	"va_core_clk",
+	"tx_npl_clk",
+	"rx_npl_clk",
+	"wsa_npl_clk",
+	"va_npl_clk",
+};
+
+struct bolero_clk_rsc {
+	struct device *dev;
+	struct mutex rsc_clk_lock;
+	struct mutex fs_gen_lock;
+	struct clk *clk[MAX_CLK];
+	int clk_cnt[MAX_CLK];
+	int reg_seq_en_cnt;
+	int va_tx_clk_cnt;
+	bool dev_up;
+	bool dev_up_gfmux;
+	u32 num_fs_reg;
+	u32 *fs_gen_seq;
+	int default_clk_id[MAX_CLK];
+	struct regmap *regmap;
+	char __iomem *rx_clk_muxsel;
+	char __iomem *wsa_clk_muxsel;
+	char __iomem *va_clk_muxsel;
+};
+
+static int bolero_clk_rsc_cb(struct device *dev, u16 event)
+{
+	struct bolero_clk_rsc *priv;
+
+	if (!dev) {
+		pr_err("%s: Invalid device pointer\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	priv = dev_get_drvdata(dev);
+	if (!priv) {
+		pr_err("%s: Invalid clk rsc priviate data\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&priv->rsc_clk_lock);
+	if (event == BOLERO_MACRO_EVT_SSR_UP) {
+		priv->dev_up = true;
+	} else if (event == BOLERO_MACRO_EVT_SSR_DOWN) {
+		priv->dev_up = false;
+		priv->dev_up_gfmux = false;
+	} else if (event == BOLERO_MACRO_EVT_SSR_GFMUX_UP) {
+		priv->dev_up_gfmux = true;
+	}
+	mutex_unlock(&priv->rsc_clk_lock);
+
+	return 0;
+}
+
+static char __iomem *bolero_clk_rsc_get_clk_muxsel(struct bolero_clk_rsc *priv,
+						 int clk_id)
+{
+	switch (clk_id) {
+	case RX_CORE_CLK:
+		return priv->rx_clk_muxsel;
+	case WSA_CORE_CLK:
+		return priv->wsa_clk_muxsel;
+	case VA_CORE_CLK:
+		return priv->va_clk_muxsel;
+	case TX_CORE_CLK:
+	default:
+		dev_err_ratelimited(priv->dev, "%s: Invalid case\n", __func__);
+		break;
+	}
+
+	return NULL;
+}
+
+int bolero_rsc_clk_reset(struct device *dev, int clk_id)
+{
+	struct device *clk_dev = NULL;
+	struct bolero_clk_rsc *priv = NULL;
+	int count = 0;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return -EINVAL;
+	}
+
+	if (clk_id < 0 || clk_id >= MAX_CLK - NPL_CLK_OFFSET) {
+		pr_err("%s: Invalid clk_id: %d\n",
+			__func__, clk_id);
+		return -EINVAL;
+	}
+
+	clk_dev = bolero_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return -EINVAL;
+	}
+
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk priviate data\n", __func__);
+		return -EINVAL;
+	}
+	mutex_lock(&priv->rsc_clk_lock);
+	while (__clk_is_enabled(priv->clk[clk_id])) {
+		clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
+		clk_disable_unprepare(priv->clk[clk_id]);
+		count++;
+	}
+	dev_dbg(priv->dev,
+		"%s: clock reset after ssr, count %d\n", __func__, count);
+
+	while (count--) {
+		clk_prepare_enable(priv->clk[clk_id]);
+		clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]);
+	}
+	mutex_unlock(&priv->rsc_clk_lock);
+	return 0;
+}
+EXPORT_SYMBOL(bolero_rsc_clk_reset);
+
+void bolero_clk_rsc_enable_all_clocks(struct device *dev, bool enable)
+{
+	struct device *clk_dev = NULL;
+	struct bolero_clk_rsc *priv = NULL;
+	int i = 0;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return;
+	}
+
+	clk_dev = bolero_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return;
+	}
+
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk private data\n", __func__);
+		return;
+	}
+	mutex_lock(&priv->rsc_clk_lock);
+	for (i = 0; i < MAX_CLK - NPL_CLK_OFFSET; i++) {
+		if (enable) {
+			if (priv->clk[i])
+				clk_prepare_enable(priv->clk[i]);
+			if (priv->clk[i + NPL_CLK_OFFSET])
+				clk_prepare_enable(
+					priv->clk[i + NPL_CLK_OFFSET]);
+		} else {
+			if (priv->clk[i + NPL_CLK_OFFSET])
+				clk_disable_unprepare(
+					priv->clk[i + NPL_CLK_OFFSET]);
+			if (priv->clk[i])
+				clk_disable_unprepare(priv->clk[i]);
+		}
+	}
+	mutex_unlock(&priv->rsc_clk_lock);
+	return;
+}
+EXPORT_SYMBOL(bolero_clk_rsc_enable_all_clocks);
+
+static int bolero_clk_rsc_mux0_clk_request(struct bolero_clk_rsc *priv,
+					   int clk_id,
+					   bool enable)
+{
+	int ret = 0;
+	static DEFINE_RATELIMIT_STATE(rtl, 1 * HZ, 1);
+
+	if (enable) {
+		/* Enable Requested Core clk */
+		if (priv->clk_cnt[clk_id] == 0) {
+			ret = clk_prepare_enable(priv->clk[clk_id]);
+			if (ret < 0) {
+				if (__ratelimit(&rtl))
+					dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+							__func__, clk_id);
+				goto done;
+			}
+			if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
+				ret = clk_prepare_enable(
+					priv->clk[clk_id + NPL_CLK_OFFSET]);
+				if (ret < 0) {
+					if (__ratelimit(&rtl))
+						dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+						__func__,
+						clk_id + NPL_CLK_OFFSET);
+					goto err;
+				}
+			}
+		}
+		priv->clk_cnt[clk_id]++;
+	} else {
+		if (priv->clk_cnt[clk_id] <= 0) {
+			dev_err_ratelimited(priv->dev, "%s: clk_id: %d is already disabled\n",
+					__func__, clk_id);
+			priv->clk_cnt[clk_id] = 0;
+			goto done;
+		}
+		priv->clk_cnt[clk_id]--;
+		if (priv->clk_cnt[clk_id] == 0) {
+			if (priv->clk[clk_id + NPL_CLK_OFFSET])
+				clk_disable_unprepare(
+					priv->clk[clk_id + NPL_CLK_OFFSET]);
+			clk_disable_unprepare(priv->clk[clk_id]);
+		}
+	}
+	return ret;
+
+err:
+	clk_disable_unprepare(priv->clk[clk_id]);
+done:
+	return ret;
+}
+
+static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
+					   int clk_id,
+					   bool enable)
+{
+	char __iomem *clk_muxsel = NULL;
+	int ret = 0;
+	int default_clk_id = priv->default_clk_id[clk_id];
+	u32 muxsel = 0;
+	static DEFINE_RATELIMIT_STATE(rtl, 1 * HZ, 1);
+
+	clk_muxsel = bolero_clk_rsc_get_clk_muxsel(priv, clk_id);
+	if (!clk_muxsel) {
+		ret = -EINVAL;
+		goto done;
+	}
+
+	if (enable) {
+		if (priv->clk_cnt[clk_id] == 0) {
+			if (clk_id != VA_CORE_CLK) {
+				ret = bolero_clk_rsc_mux0_clk_request(priv,
+								default_clk_id,
+								true);
+				if (ret < 0)
+					goto done;
+			}
+
+			ret = clk_prepare_enable(priv->clk[clk_id]);
+			if (ret < 0) {
+				if (__ratelimit(&rtl))
+					dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+						__func__, clk_id);
+				goto err_clk;
+			}
+			if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
+				ret = clk_prepare_enable(
+					priv->clk[clk_id + NPL_CLK_OFFSET]);
+				if (ret < 0) {
+					if (__ratelimit(&rtl))
+						dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+						__func__,
+						clk_id + NPL_CLK_OFFSET);
+					goto err_npl_clk;
+				}
+			}
+
+			/*
+			 * Temp SW workaround to address a glitch issue of
+			 * VA GFMux instance responsible for switching from
+			 * TX MCLK to VA MCLK. This configuration would be taken
+			 * care in DSP itself
+			 */
+			if (clk_id != VA_CORE_CLK) {
+				if (priv->dev_up_gfmux) {
+					iowrite32(0x1, clk_muxsel);
+					muxsel = ioread32(clk_muxsel);
+				}
+				bolero_clk_rsc_mux0_clk_request(priv,
+							default_clk_id,
+							false);
+			}
+		}
+		priv->clk_cnt[clk_id]++;
+	} else {
+		if (priv->clk_cnt[clk_id] <= 0) {
+			dev_err_ratelimited(priv->dev, "%s: clk_id: %d is already disabled\n",
+				__func__, clk_id);
+			priv->clk_cnt[clk_id] = 0;
+			goto done;
+		}
+		priv->clk_cnt[clk_id]--;
+		if (priv->clk_cnt[clk_id] == 0) {
+			if (clk_id != VA_CORE_CLK) {
+				ret = bolero_clk_rsc_mux0_clk_request(priv,
+						default_clk_id, true);
+
+				if (!ret) {
+					/*
+					 * Temp SW workaround to address a glitch issue
+					 * of VA GFMux instance responsible for
+					 * switching from TX MCLK to VA MCLK.
+					 * This configuration would be taken
+					 * care in DSP itself.
+					 */
+					if (priv->dev_up_gfmux) {
+						iowrite32(0x0, clk_muxsel);
+						muxsel = ioread32(clk_muxsel);
+					}
+				}
+			}
+			if (priv->clk[clk_id + NPL_CLK_OFFSET])
+				clk_disable_unprepare(
+					priv->clk[clk_id + NPL_CLK_OFFSET]);
+			clk_disable_unprepare(priv->clk[clk_id]);
+
+			if (clk_id != VA_CORE_CLK) {
+				if (!ret)
+					bolero_clk_rsc_mux0_clk_request(priv,
+						default_clk_id, false);
+			}
+		}
+	}
+	return ret;
+
+err_npl_clk:
+	clk_disable_unprepare(priv->clk[clk_id]);
+
+err_clk:
+	if (clk_id != VA_CORE_CLK)
+		bolero_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
+done:
+	return ret;
+}
+
+static int bolero_clk_rsc_check_and_update_va_clk(struct bolero_clk_rsc *priv,
+						  bool mux_switch,
+						  int clk_id,
+						  bool enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		if (clk_id == VA_CORE_CLK && mux_switch) {
+			/*
+			 * Handle the following usecase scenarios during enable
+			 * 1. VA only, Active clk is VA_CORE_CLK
+			 * 2. record -> record + VA, Active clk is TX_CORE_CLK
+			 */
+			if (priv->clk_cnt[TX_CORE_CLK] == 0) {
+				ret = bolero_clk_rsc_mux1_clk_request(priv,
+							 VA_CORE_CLK, enable);
+				if (ret < 0)
+					goto err;
+			} else {
+				ret = bolero_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, enable);
+				if (ret < 0)
+					goto err;
+				priv->va_tx_clk_cnt++;
+			}
+		} else if ((priv->clk_cnt[TX_CORE_CLK] > 0) &&
+			   (priv->clk_cnt[VA_CORE_CLK] > 0)) {
+			/*
+			 * Handle following concurrency scenario during enable
+			 * 1. VA-> Record+VA, Increment TX CLK and Disable VA
+			 * 2. VA-> Playback+VA, Increment TX CLK and Disable VA
+			 */
+			while (priv->clk_cnt[VA_CORE_CLK] > 0) {
+				ret = bolero_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, true);
+				if (ret < 0)
+					goto err;
+
+				bolero_clk_rsc_mux1_clk_request(priv,
+							VA_CORE_CLK, false);
+				priv->va_tx_clk_cnt++;
+			}
+		}
+	} else {
+		if (clk_id == VA_CORE_CLK && mux_switch) {
+			/*
+			 * Handle the following usecase scenarios during disable
+			 * 1. VA only, disable VA_CORE_CLK
+			 * 2. Record + VA -> Record, decrement TX CLK count
+			 */
+			if (priv->clk_cnt[VA_CORE_CLK]) {
+				bolero_clk_rsc_mux1_clk_request(priv,
+							VA_CORE_CLK, enable);
+			} else if (priv->va_tx_clk_cnt) {
+				bolero_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, enable);
+				priv->va_tx_clk_cnt--;
+			}
+		} else if (priv->va_tx_clk_cnt == priv->clk_cnt[TX_CORE_CLK]) {
+			/*
+			 * Handle the following usecase scenarios during disable
+			 * Record+VA-> VA: enable VA CLK, decrement TX CLK count
+			 */
+			while (priv->va_tx_clk_cnt) {
+				ret = bolero_clk_rsc_mux1_clk_request(priv,
+							VA_CORE_CLK, true);
+				if (ret < 0)
+					goto err;
+
+				bolero_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, false);
+				priv->va_tx_clk_cnt--;
+			}
+		}
+	}
+
+err:
+	return ret;
+}
+
+/**
+ * bolero_clk_rsc_fs_gen_request - request to enable/disable fs generation
+ * sequence
+ *
+ * @dev: Macro device pointer
+ * @enable: enable or disable flag
+ */
+void bolero_clk_rsc_fs_gen_request(struct device *dev, bool enable)
+{
+	int i;
+	struct regmap *regmap;
+	struct device *clk_dev = NULL;
+	struct bolero_clk_rsc *priv = NULL;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return;
+	}
+	clk_dev = bolero_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return;
+	}
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk priviate data\n", __func__);
+		return;
+	}
+	regmap = dev_get_regmap(priv->dev->parent, NULL);
+	if (!regmap) {
+		pr_err("%s: regmap is null\n", __func__);
+		return;
+	}
+	mutex_lock(&priv->fs_gen_lock);
+	if (enable) {
+		if (priv->reg_seq_en_cnt++ == 0) {
+			for (i = 0; i < (priv->num_fs_reg * 3); i += 3) {
+				dev_dbg(priv->dev, "%s: Register: %d, mask: %d, value %d\n",
+					__func__, priv->fs_gen_seq[i],
+					priv->fs_gen_seq[i + 1],
+					priv->fs_gen_seq[i + 2]);
+				regmap_update_bits(regmap,
+						   priv->fs_gen_seq[i],
+						   priv->fs_gen_seq[i + 1],
+						   priv->fs_gen_seq[i + 2]);
+			}
+		}
+	} else {
+		if (priv->reg_seq_en_cnt <= 0) {
+			dev_err_ratelimited(priv->dev, "%s: req_seq_cnt: %d is already disabled\n",
+				__func__, priv->reg_seq_en_cnt);
+			priv->reg_seq_en_cnt = 0;
+			mutex_unlock(&priv->fs_gen_lock);
+			return;
+		}
+		if (--priv->reg_seq_en_cnt == 0) {
+			for (i = ((priv->num_fs_reg - 1) * 3); i >= 0; i -= 3) {
+				dev_dbg(priv->dev, "%s: Register: %d, mask: %d\n",
+					__func__, priv->fs_gen_seq[i],
+					priv->fs_gen_seq[i + 1]);
+				regmap_update_bits(regmap, priv->fs_gen_seq[i],
+						priv->fs_gen_seq[i + 1], 0x0);
+			}
+		}
+	}
+	mutex_unlock(&priv->fs_gen_lock);
+}
+EXPORT_SYMBOL(bolero_clk_rsc_fs_gen_request);
+
+/**
+ * bolero_clk_rsc_request_clock - request for clock to
+ * enable/disable
+ *
+ * @dev: Macro device pointer.
+ * @default_clk_id: mux0 Core clock ID input.
+ * @clk_id_req: Core clock ID requested to enable/disable
+ * @enable: enable or disable clock flag
+ *
+ * Returns 0 on success or -EINVAL on error.
+ */
+int bolero_clk_rsc_request_clock(struct device *dev,
+				int default_clk_id,
+				int clk_id_req,
+				bool enable)
+{
+	int ret = 0;
+	struct device *clk_dev = NULL;
+	struct bolero_clk_rsc *priv = NULL;
+	bool mux_switch = false;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return -EINVAL;
+	}
+	if ((clk_id_req < 0 || clk_id_req >= MAX_CLK) &&
+		(default_clk_id < 0 || default_clk_id >= MAX_CLK)) {
+		pr_err("%s: Invalid clk_id_req: %d or default_clk_id: %d\n",
+				__func__, clk_id_req, default_clk_id);
+		return -EINVAL;
+	}
+	clk_dev = bolero_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return -EINVAL;
+	}
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk priviate data\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&priv->rsc_clk_lock);
+	if (!priv->dev_up && enable) {
+		dev_err_ratelimited(priv->dev, "%s: SSR is in progress..\n",
+				__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	priv->default_clk_id[clk_id_req] = default_clk_id;
+	if (default_clk_id != clk_id_req)
+		mux_switch = true;
+
+	if (mux_switch) {
+		if (clk_id_req != VA_CORE_CLK) {
+			ret = bolero_clk_rsc_mux1_clk_request(priv, clk_id_req,
+							enable);
+			if (ret < 0)
+				goto err;
+		}
+	} else {
+		ret = bolero_clk_rsc_mux0_clk_request(priv, clk_id_req, enable);
+		if (ret < 0)
+			goto err;
+	}
+
+	ret = bolero_clk_rsc_check_and_update_va_clk(priv, mux_switch,
+						 clk_id_req,
+						 enable);
+	if (ret < 0)
+		goto err;
+
+	dev_dbg(priv->dev, "%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
+		__func__,  priv->clk_cnt[clk_id_req], clk_id_req,
+		enable);
+
+	mutex_unlock(&priv->rsc_clk_lock);
+
+	return 0;
+
+err:
+	mutex_unlock(&priv->rsc_clk_lock);
+	return ret;
+}
+EXPORT_SYMBOL(bolero_clk_rsc_request_clock);
+
+
+static int bolero_clk_rsc_probe(struct platform_device *pdev)
+{
+	int ret = 0, fs_gen_size, i, j;
+	const char **clk_name_array;
+	int clk_cnt;
+	struct clk *clk;
+	struct bolero_clk_rsc *priv = NULL;
+	u32 muxsel = 0;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(struct bolero_clk_rsc),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	/* Get clk fs gen sequence from device tree */
+	if (!of_find_property(pdev->dev.of_node, "qcom,fs-gen-sequence",
+						  &fs_gen_size)) {
+		dev_err(&pdev->dev, "%s: unable to find qcom,fs-gen-sequence property\n",
+			__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	priv->num_fs_reg = fs_gen_size/(3 * sizeof(u32));
+	priv->fs_gen_seq = devm_kzalloc(&pdev->dev, fs_gen_size, GFP_KERNEL);
+	if (!priv->fs_gen_seq) {
+		ret = -ENOMEM;
+		goto err;
+	}
+	dev_dbg(&pdev->dev, "%s: num_fs_reg %d\n", __func__, priv->num_fs_reg);
+	/* Parse fs-gen-sequence */
+	ret = of_property_read_u32_array(pdev->dev.of_node,
+					 "qcom,fs-gen-sequence",
+					 priv->fs_gen_seq,
+					 priv->num_fs_reg * 3);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "%s: unable to parse fs-gen-sequence, ret = %d\n",
+			__func__, ret);
+		goto err;
+	}
+
+	/* Get clk details from device tree */
+	clk_cnt = of_property_count_strings(pdev->dev.of_node, "clock-names");
+	if (clk_cnt <= 0 || clk_cnt > MAX_CLK) {
+		dev_err(&pdev->dev, "%s: Invalid number of clocks %d",
+				__func__, clk_cnt);
+		ret = -EINVAL;
+		goto err;
+	}
+	clk_name_array = devm_kzalloc(&pdev->dev, clk_cnt * sizeof(char *),
+					  GFP_KERNEL);
+	if (!clk_name_array) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	ret = of_property_read_string_array(pdev->dev.of_node, "clock-names",
+					clk_name_array, clk_cnt);
+
+	for (i = 0; i < MAX_CLK; i++) {
+		priv->clk[i] = NULL;
+		for (j = 0; j < clk_cnt; j++) {
+			if (!strcmp(clk_src_name[i], clk_name_array[j])) {
+				clk = devm_clk_get(&pdev->dev, clk_src_name[i]);
+				if (IS_ERR(clk)) {
+					ret = PTR_ERR(clk);
+					dev_err(&pdev->dev, "%s: clk get failed for %s with ret %d\n",
+						__func__, clk_src_name[i], ret);
+					goto err;
+				}
+				priv->clk[i] = clk;
+				dev_dbg(&pdev->dev, "%s: clk get success for clk name %s\n",
+						__func__, clk_src_name[i]);
+			}
+		}
+	}
+	ret = of_property_read_u32(pdev->dev.of_node,
+				 "qcom,rx_mclk_mode_muxsel", &muxsel);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: could not find qcom,rx_mclk_mode_muxsel entry in dt\n",
+			__func__);
+	} else {
+		priv->rx_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
+		if (!priv->rx_clk_muxsel) {
+			dev_err(&pdev->dev, "%s: ioremap failed for rx muxsel\n",
+				__func__);
+			return -ENOMEM;
+		}
+	}
+	ret = of_property_read_u32(pdev->dev.of_node,
+				"qcom,wsa_mclk_mode_muxsel", &muxsel);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: could not find qcom,wsa_mclk_mode_muxsel entry in dt\n",
+			__func__);
+	} else {
+		priv->wsa_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
+		if (!priv->wsa_clk_muxsel) {
+			dev_err(&pdev->dev, "%s: ioremap failed for wsa muxsel\n",
+				__func__);
+			return -ENOMEM;
+		}
+	}
+	ret = of_property_read_u32(pdev->dev.of_node,
+				 "qcom,va_mclk_mode_muxsel", &muxsel);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: could not find qcom,va_mclk_mode_muxsel entry in dt\n",
+			__func__);
+	} else {
+		priv->va_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
+		if (!priv->va_clk_muxsel) {
+			dev_err(&pdev->dev, "%s: ioremap failed for va muxsel\n",
+				__func__);
+			return -ENOMEM;
+		}
+	}
+
+	ret = bolero_register_res_clk(&pdev->dev, bolero_clk_rsc_cb);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "%s: Failed to register cb %d",
+				__func__, ret);
+		goto err;
+	}
+	priv->dev = &pdev->dev;
+	priv->dev_up = true;
+	priv->dev_up_gfmux = true;
+	mutex_init(&priv->rsc_clk_lock);
+	mutex_init(&priv->fs_gen_lock);
+	dev_set_drvdata(&pdev->dev, priv);
+
+err:
+	return ret;
+}
+
+static int bolero_clk_rsc_remove(struct platform_device *pdev)
+{
+	struct bolero_clk_rsc *priv = dev_get_drvdata(&pdev->dev);
+
+	bolero_unregister_res_clk(&pdev->dev);
+	of_platform_depopulate(&pdev->dev);
+	if (!priv)
+		return -EINVAL;
+	mutex_destroy(&priv->rsc_clk_lock);
+	mutex_destroy(&priv->fs_gen_lock);
+
+	return 0;
+}
+
+static const struct of_device_id bolero_clk_rsc_dt_match[] = {
+	{.compatible = "qcom,bolero-clk-rsc-mngr"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, bolero_clk_rsc_dt_match);
+
+static struct platform_driver bolero_clk_rsc_mgr = {
+	.driver = {
+		.name = "bolero-clk-rsc-mngr",
+		.owner = THIS_MODULE,
+		.of_match_table = bolero_clk_rsc_dt_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = bolero_clk_rsc_probe,
+	.remove = bolero_clk_rsc_remove,
+};
+
+int bolero_clk_rsc_mgr_init(void)
+{
+	return platform_driver_register(&bolero_clk_rsc_mgr);
+}
+
+void bolero_clk_rsc_mgr_exit(void)
+{
+	platform_driver_unregister(&bolero_clk_rsc_mgr);
+}
+MODULE_DESCRIPTION("Bolero clock resource manager driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/bolero/bolero-clk-rsc.h

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef BOLERO_CLK_RSC_H
+#define BOLERO_CLK_RSC_H
+
+#include <linux/regmap.h>
+#include <bindings/qcom,bolero-clk-rsc.h>
+
+#if IS_ENABLED(CONFIG_SND_SOC_BOLERO)
+int bolero_clk_rsc_mgr_init(void);
+void bolero_clk_rsc_mgr_exit(void);
+void bolero_clk_rsc_fs_gen_request(struct device *dev,
+						bool enable);
+int bolero_clk_rsc_request_clock(struct device *dev,
+				int default_clk_id,
+				int clk_id_req,
+				bool enable);
+int bolero_rsc_clk_reset(struct device *dev, int clk_id);
+void bolero_clk_rsc_enable_all_clocks(struct device *dev, bool enable);
+#else
+static inline void bolero_clk_rsc_fs_gen_request(struct device *dev,
+						bool enable)
+{
+}
+static inline int bolero_clk_rsc_mgr_init(void)
+{
+	return 0;
+}
+static inline void bolero_clk_rsc_mgr_exit(void)
+{
+}
+static inline int bolero_clk_rsc_request_clock(struct device *dev,
+				int default_clk_id,
+				int clk_id_req,
+				bool enable)
+{
+	return 0;
+}
+static inline int bolero_rsc_clk_reset(struct device *dev, int clk_id)
+{
+	return 0;
+}
+static inline void bolero_clk_rsc_enable_all_clocks(struct device *dev,
+						    bool enable)
+{
+	return;
+}
+#endif /* CONFIG_SND_SOC_BOLERO */
+#endif /* BOLERO_CLK_RSC_H */

qcom/opensource/audio-kernel/asoc/codecs/bolero/internal.h

@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _BOLERO_INTERNAL_H
+#define _BOLERO_INTERNAL_H
+
+#include "bolero-cdc-registers.h"
+
+#define BOLERO_CDC_CHILD_DEVICES_MAX 6
+
+enum {
+	REG_NO_ACCESS,
+	RD_REG,
+	WR_REG,
+	RD_WR_REG
+};
+
+struct wcd_ctrl_platform_data {
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				 struct notifier_block *nblock,
+				 bool enable);
+};
+
+struct bolero_priv {
+	struct device *dev;
+	struct snd_soc_component *component;
+	struct regmap *regmap;
+	struct mutex io_lock;
+	struct mutex clk_lock;
+	struct mutex vote_lock;
+	bool va_without_decimation;
+	bool macros_supported[MAX_MACRO];
+	bool dev_up;
+	bool initial_boot;
+	struct macro_ops macro_params[MAX_MACRO];
+	struct snd_soc_dai_driver *bolero_dais;
+	u16 num_dais;
+	u16 num_macros_registered;
+	u16 num_macros;
+	u16 current_mclk_mux_macro[MAX_MACRO];
+	struct work_struct bolero_add_child_devices_work;
+	u32 version;
+	struct clk *lpass_core_hw_vote;
+	struct clk *lpass_audio_hw_vote;
+	int core_hw_vote_count;
+	int core_audio_vote_count;
+
+	/* Entry for version info */
+	struct snd_info_entry *entry;
+	struct snd_info_entry *version_entry;
+
+	int (*read_dev)(struct bolero_priv *priv,
+			u16 macro_id, u16 reg, u8 *val);
+	int (*write_dev)(struct bolero_priv *priv,
+			 u16 macro_id, u16 reg, u8 val);
+	struct platform_device *pdev_child_devices
+			[BOLERO_CDC_CHILD_DEVICES_MAX];
+	u16 child_count;
+	struct wcd_ctrl_platform_data plat_data;
+	struct device *wcd_dev;
+	struct blocking_notifier_head notifier;
+	struct device *clk_dev;
+	rsc_clk_cb_t rsc_clk_cb;
+	s32 dmic_0_1_clk_cnt;
+	s32 dmic_2_3_clk_cnt;
+	s32 dmic_4_5_clk_cnt;
+	s32 dmic_6_7_clk_cnt;
+	u8 dmic_0_1_clk_div;
+	u8 dmic_2_3_clk_div;
+	u8 dmic_4_5_clk_div;
+	u8 dmic_6_7_clk_div;
+};
+
+struct regmap *bolero_regmap_init(struct device *dev,
+				  const struct regmap_config *config);
+int bolero_get_macro_id(bool va_no_dec_flag, u16 reg);
+
+extern const struct regmap_config bolero_regmap_config;
+extern u8 *bolero_reg_access[MAX_MACRO];
+extern u8 bolero_va_top_reg_access[BOLERO_CDC_VA_MACRO_TOP_MAX];
+extern u8 bolero_va_reg_access_v2[BOLERO_CDC_VA_MACRO_MAX];
+extern u8 bolero_va_reg_access_v3[BOLERO_CDC_VA_MACRO_MAX];
+extern u8 bolero_tx_reg_access_v2[BOLERO_CDC_TX_MACRO_MAX];
+extern const u16 macro_id_base_offset[MAX_MACRO];
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/bolero/wsa-macro.h

@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ */
+#ifndef WSA_MACRO_H
+#define WSA_MACRO_H
+
+/*
+ * Selects compander and smart boost settings
+ * for a given speaker mode
+ */
+enum {
+	WSA_MACRO_SPKR_MODE_DEFAULT,
+	WSA_MACRO_SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
+};
+
+/* Rx path gain offsets */
+enum {
+	WSA_MACRO_GAIN_OFFSET_M1P5_DB,
+	WSA_MACRO_GAIN_OFFSET_0_DB,
+};
+
+
+#if IS_ENABLED(CONFIG_WSA_MACRO)
+extern int wsa_macro_set_spkr_mode(struct snd_soc_component *component,
+				   int mode);
+extern int wsa_macro_set_spkr_gain_offset(struct snd_soc_component *component,
+					  int offset);
+#else /* CONFIG_WSA_MACRO */
+static inline int wsa_macro_set_spkr_mode(struct snd_soc_component *component,
+					  int mode)
+{
+	return 0;
+}
+static inline int wsa_macro_set_spkr_gain_offset(
+				struct snd_soc_component *component,
+				int offset)
+{
+	return 0;
+}
+#endif /* CONFIG_WSA_MACRO */
+#endif

qcom/opensource/audio-kernel/asoc/codecs/cpe_cmi.h

@@ -0,0 +1,484 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __CPE_CMI_H__
+#define __CPE_CMI_H__
+
+#include <linux/types.h>
+
+#define CPE_AFE_PORT_1_TX 1
+#define CPE_AFE_PORT_3_TX 3
+#define CPE_AFE_PORT_ID_2_OUT 0x02
+#define CMI_INBAND_MESSAGE_SIZE 127
+
+/*
+ * Multiple mad types can be supported at once.
+ * these values can be OR'ed to form the set of
+ * supported mad types
+ */
+#define MAD_TYPE_AUDIO (1 << 0)
+#define MAD_TYPE_BEACON (1 << 1)
+#define MAD_TYPE_ULTRASND (1 << 2)
+
+/* Core service command opcodes */
+#define CPE_CORE_SVC_CMD_SHARED_MEM_ALLOC	(0x3001)
+#define CPE_CORE_SVC_CMDRSP_SHARED_MEM_ALLOC	(0x3002)
+#define CPE_CORE_SVC_CMD_SHARED_MEM_DEALLOC	(0x3003)
+#define CPE_CORE_SVC_CMD_DRAM_ACCESS_REQ	(0x3004)
+#define CPE_CORE_SVC_EVENT_SYSTEM_BOOT		(0x3005)
+/* core service command opcodes for WCD9335 */
+#define CPE_CORE_SVC_CMD_CFG_CLK_PLAN		(0x3006)
+#define CPE_CORE_SVC_CMD_CLK_FREQ_REQUEST	(0x3007)
+
+#define CPE_BOOT_SUCCESS 0x00
+#define CPE_BOOT_FAILED 0x01
+
+#define CPE_CORE_VERSION_SYSTEM_BOOT_EVENT 0x01
+
+/* LSM Service command opcodes */
+#define CPE_LSM_SESSION_CMD_OPEN_TX		(0x2000)
+#define CPE_LSM_SESSION_CMD_SET_PARAMS		(0x2001)
+#define CPE_LSM_SESSION_CMD_REGISTER_SOUND_MODEL (0x2002)
+#define CPE_LSM_SESSION_CMD_DEREGISTER_SOUND_MODEL (0x2003)
+#define CPE_LSM_SESSION_CMD_START		(0x2004)
+#define CPE_LSM_SESSION_CMD_STOP		(0x2005)
+#define CPE_LSM_SESSION_EVENT_DETECTION_STATUS_V2 (0x2006)
+#define CPE_LSM_SESSION_CMD_CLOSE_TX		(0x2007)
+#define CPE_LSM_SESSION_CMD_SHARED_MEM_ALLOC	(0x2008)
+#define CPE_LSM_SESSION_CMDRSP_SHARED_MEM_ALLOC (0x2009)
+#define CPE_LSM_SESSION_CMD_SHARED_MEM_DEALLOC	(0x200A)
+#define CPE_LSM_SESSION_CMD_TX_BUFF_OUTPUT_CONFIG (0x200f)
+#define CPE_LSM_SESSION_CMD_OPEN_TX_V2		(0x200D)
+#define CPE_LSM_SESSION_CMD_SET_PARAMS_V2	(0x200E)
+
+/* LSM Service module and param IDs */
+#define CPE_LSM_MODULE_ID_VOICE_WAKEUP		(0x00012C00)
+#define CPE_LSM_MODULE_ID_VOICE_WAKEUP_V2	(0x00012C0D)
+#define CPE_LSM_MODULE_FRAMEWORK		(0x00012C0E)
+
+#define CPE_LSM_PARAM_ID_ENDPOINT_DETECT_THRESHOLD (0x00012C01)
+#define CPE_LSM_PARAM_ID_OPERATION_MODE		(0x00012C02)
+#define CPE_LSM_PARAM_ID_GAIN			(0x00012C03)
+#define CPE_LSM_PARAM_ID_CONNECT_TO_PORT	(0x00012C04)
+#define CPE_LSM_PARAM_ID_MIN_CONFIDENCE_LEVELS	(0x00012C07)
+
+/* LSM LAB command opcodes */
+#define CPE_LSM_SESSION_CMD_EOB		0x0000200B
+#define CPE_LSM_MODULE_ID_LAB		0x00012C08
+/* used for enable/disable lab*/
+#define CPE_LSM_PARAM_ID_LAB_ENABLE	0x00012C09
+/* used for T in LAB config DSP internal buffer*/
+#define CPE_LSM_PARAM_ID_LAB_CONFIG	0x00012C0A
+#define CPE_LSM_PARAM_ID_REGISTER_SOUND_MODEL	(0x00012C14)
+#define CPE_LSM_PARAM_ID_DEREGISTER_SOUND_MODEL	(0x00012C15)
+#define CPE_LSM_PARAM_ID_MEDIA_FMT		(0x00012C1E)
+
+/* AFE Service command opcodes */
+#define CPE_AFE_PORT_CMD_START			(0x1001)
+#define CPE_AFE_PORT_CMD_STOP			(0x1002)
+#define CPE_AFE_PORT_CMD_SUSPEND		(0x1003)
+#define CPE_AFE_PORT_CMD_RESUME			(0x1004)
+#define CPE_AFE_PORT_CMD_SHARED_MEM_ALLOC	(0x1005)
+#define CPE_AFE_PORT_CMDRSP_SHARED_MEM_ALLOC	(0x1006)
+#define CPE_AFE_PORT_CMD_SHARED_MEM_DEALLOC	(0x1007)
+#define CPE_AFE_PORT_CMD_GENERIC_CONFIG		(0x1008)
+#define CPE_AFE_SVC_CMD_LAB_MODE		(0x1009)
+
+/* AFE Service module and param IDs */
+#define CPE_AFE_CMD_SET_PARAM			(0x1000)
+#define CPE_AFE_MODULE_ID_SW_MAD		(0x0001022D)
+#define CPE_AFE_PARAM_ID_SW_MAD_CFG		(0x0001022E)
+#define CPE_AFE_PARAM_ID_SVM_MODEL		(0x0001022F)
+
+#define CPE_AFE_MODULE_HW_MAD			(0x00010230)
+#define CPE_AFE_PARAM_ID_HW_MAD_CTL		(0x00010232)
+#define CPE_AFE_PARAM_ID_HW_MAD_CFG		(0x00010231)
+
+#define CPE_AFE_MODULE_AUDIO_DEV_INTERFACE	(0x0001020C)
+#define CPE_AFE_PARAM_ID_GENERIC_PORT_CONFIG	(0x00010253)
+
+#define CPE_CMI_BASIC_RSP_OPCODE	(0x0001)
+#define CPE_HDR_MAX_PLD_SIZE	(0x7F)
+
+#define CMI_OBM_FLAG_IN_BAND	0
+#define CMI_OBM_FLAG_OUT_BAND	1
+
+#define CMI_SHMEM_ALLOC_FAILED 0xff
+
+/*
+ * Future Service ID's can be added one line
+ * before the CMI_CPE_SERVICE_ID_MAX
+ */
+enum {
+	CMI_CPE_SERVICE_ID_MIN = 0,
+	CMI_CPE_CORE_SERVICE_ID,
+	CMI_CPE_AFE_SERVICE_ID,
+	CMI_CPE_LSM_SERVICE_ID,
+	CMI_CPE_SERVICE_ID_MAX,
+};
+
+#define CPE_LSM_SESSION_ID_MAX 2
+
+#define IS_VALID_SESSION_ID(s_id) \
+	(s_id <= CPE_LSM_SESSION_ID_MAX)
+
+#define IS_VALID_SERVICE_ID(s_id) \
+	(s_id > CMI_CPE_SERVICE_ID_MIN && \
+	 s_id < CMI_CPE_SERVICE_ID_MAX)
+
+#define IS_VALID_PLD_SIZE(p_size) \
+	(p_size <= CPE_HDR_MAX_PLD_SIZE)
+
+#define CMI_HDR_SET_OPCODE(hdr, cmd) (hdr->opcode = cmd)
+
+
+#define CMI_HDR_SET(hdr_info, mask, shift, value) \
+		(hdr_info = (((hdr_info) & ~(mask)) | \
+			((value << shift) & mask)))
+
+#define SVC_ID_SHIFT 4
+#define SVC_ID_MASK (0x07 << SVC_ID_SHIFT)
+
+#define SESSION_ID_SHIFT 0
+#define SESSION_ID_MASK (0x0F << SESSION_ID_SHIFT)
+
+#define PAYLD_SIZE_SHIFT 0
+#define PAYLD_SIZE_MASK (0x7F << PAYLD_SIZE_SHIFT)
+
+#define OBM_FLAG_SHIFT 7
+#define OBM_FLAG_MASK (1 << OBM_FLAG_SHIFT)
+
+#define VERSION_SHIFT 7
+#define VERSION_MASK (1 << VERSION_SHIFT)
+
+#define CMI_HDR_SET_SERVICE(hdr, s_id) \
+		CMI_HDR_SET(hdr->hdr_info, SVC_ID_MASK,\
+			    SVC_ID_SHIFT, s_id)
+#define CMI_HDR_GET_SERVICE(hdr) \
+		((hdr->hdr_info >> SVC_ID_SHIFT) & \
+			(SVC_ID_MASK >> SVC_ID_SHIFT))
+
+
+#define CMI_HDR_SET_SESSION(hdr, s_id) \
+		CMI_HDR_SET(hdr->hdr_info, SESSION_ID_MASK,\
+			    SESSION_ID_SHIFT, s_id)
+
+#define CMI_HDR_GET_SESSION_ID(hdr) \
+		((hdr->hdr_info >> SESSION_ID_SHIFT) & \
+			 (SESSION_ID_MASK >> SESSION_ID_SHIFT))
+
+#define CMI_GET_HEADER(msg)	((struct cmi_hdr *)(msg))
+#define CMI_GET_PAYLOAD(msg)	((void *)(CMI_GET_HEADER(msg) + 1))
+#define CMI_GET_OPCODE(msg)	(CMI_GET_HEADER(msg)->opcode)
+
+#define CMI_HDR_SET_VERSION(hdr, ver) \
+		CMI_HDR_SET(hdr->hdr_info, VERSION_MASK, \
+				VERSION_SHIFT, ver)
+
+#define CMI_HDR_SET_PAYLOAD_SIZE(hdr, p_size) \
+		CMI_HDR_SET(hdr->pld_info, PAYLD_SIZE_MASK, \
+			    PAYLD_SIZE_SHIFT, p_size)
+
+#define CMI_HDR_GET_PAYLOAD_SIZE(hdr) \
+		((hdr->pld_info >> PAYLD_SIZE_SHIFT) & \
+			(PAYLD_SIZE_MASK >> PAYLD_SIZE_SHIFT))
+
+#define CMI_HDR_SET_OBM(hdr, obm_flag) \
+		CMI_HDR_SET(hdr->pld_info, OBM_FLAG_MASK, \
+			    OBM_FLAG_SHIFT, obm_flag)
+
+#define CMI_HDR_GET_OBM_FLAG(hdr) \
+	((hdr->pld_info >> OBM_FLAG_SHIFT) & \
+		(OBM_FLAG_MASK >> OBM_FLAG_SHIFT))
+
+struct cmi_hdr {
+	/*
+	 * bits 0:3 is session id
+	 * bits 4:6 is service id
+	 * bit 7 is the version flag
+	 */
+	u8 hdr_info;
+
+	/*
+	 * bits 0:6 is payload size in case of in-band message
+	 * bits 0:6 is size (OBM message size)
+	 * bit 7 is the OBM flag
+	 */
+	u8 pld_info;
+
+	/* 16 bit command opcode */
+	u16 opcode;
+} __packed;
+
+union cpe_addr {
+	u64 msw_lsw;
+	void *kvaddr;
+} __packed;
+
+struct cmi_obm {
+	u32 version;
+	u32 size;
+	union cpe_addr data_ptr;
+	u32 mem_handle;
+} __packed;
+
+struct cmi_obm_msg {
+	struct cmi_hdr hdr;
+	struct cmi_obm pld;
+} __packed;
+
+struct cmi_core_svc_event_system_boot {
+	u8 status;
+	u8 version;
+	u16 sfr_buff_size;
+	u32 sfr_buff_address;
+} __packed;
+
+struct cmi_core_svc_cmd_shared_mem_alloc {
+	u32 size;
+} __packed;
+
+struct cmi_core_svc_cmdrsp_shared_mem_alloc {
+	u32 addr;
+} __packed;
+
+struct cmi_core_svc_cmd_clk_freq_request {
+	u32 clk_freq;
+} __packed;
+
+struct cmi_msg_transport {
+	u32 size;
+	u32 addr;
+} __packed;
+
+struct cmi_basic_rsp_result {
+	u8 status;
+} __packed;
+
+struct cpe_lsm_cmd_open_tx {
+	struct cmi_hdr	hdr;
+	u16 app_id;
+	u16 reserved;
+	u32 sampling_rate;
+} __packed;
+
+struct cpe_lsm_cmd_open_tx_v2 {
+	struct cmi_hdr hdr;
+	u32 topology_id;
+} __packed;
+
+struct cpe_cmd_shmem_alloc {
+	struct cmi_hdr hdr;
+	u32 size;
+} __packed;
+
+struct cpe_cmdrsp_shmem_alloc {
+	struct cmi_hdr hdr;
+	u32 addr;
+} __packed;
+
+struct cpe_cmd_shmem_dealloc {
+	struct cmi_hdr	hdr;
+	u32 addr;
+} __packed;
+
+struct cpe_lsm_event_detect_v2 {
+	struct cmi_hdr	hdr;
+	u8 detection_status;
+	u8 size;
+	u8 payload[0];
+} __packed;
+
+struct cpe_lsm_psize_res {
+	u16 param_size;
+	u16 reserved;
+} __packed;
+
+union cpe_lsm_param_size {
+	u32 param_size;
+	struct cpe_lsm_psize_res sr;
+} __packed;
+
+struct cpe_param_data {
+	u32 module_id;
+	u32 param_id;
+	union cpe_lsm_param_size p_size;
+} __packed;
+
+struct cpe_lsm_param_epd_thres {
+	struct cmi_hdr hdr;
+	struct cpe_param_data param;
+	u32 minor_version;
+	u32 epd_begin;
+	u32 epd_end;
+} __packed;
+
+struct cpe_lsm_param_gain {
+	struct cmi_hdr hdr;
+	struct cpe_param_data param;
+	u32 minor_version;
+	u16 gain;
+	u16 reserved;
+} __packed;
+
+struct cpe_afe_hw_mad_ctrl {
+	struct cpe_param_data param;
+	u32 minor_version;
+	u16 mad_type;
+	u16 mad_enable;
+} __packed;
+
+struct cpe_afe_port_cfg {
+	struct cpe_param_data param;
+	u32 minor_version;
+	u16 bit_width;
+	u16 num_channels;
+	u32 sample_rate;
+} __packed;
+
+struct cpe_afe_cmd_port_cfg {
+	struct cmi_hdr hdr;
+	u8 bit_width;
+	u8 num_channels;
+	u16 buffer_size;
+	u32 sample_rate;
+} __packed;
+
+struct cpe_afe_params {
+	struct cmi_hdr hdr;
+	struct cpe_afe_hw_mad_ctrl hw_mad_ctrl;
+	struct cpe_afe_port_cfg port_cfg;
+} __packed;
+
+struct cpe_afe_svc_cmd_mode {
+	struct cmi_hdr hdr;
+	u8 mode;
+} __packed;
+
+struct cpe_lsm_param_opmode {
+	struct cmi_hdr hdr;
+	struct cpe_param_data param;
+	u32 minor_version;
+	u16 mode;
+	u16 reserved;
+} __packed;
+
+struct cpe_lsm_param_connectport {
+	struct cmi_hdr hdr;
+	struct cpe_param_data param;
+	u32 minor_version;
+	u16 afe_port_id;
+	u16 reserved;
+} __packed;
+
+/*
+ * This cannot be sent to CPE as is,
+ * need to append the conf_levels dynamically
+ */
+struct cpe_lsm_conf_level {
+	struct cmi_hdr hdr;
+	struct cpe_param_data param;
+	u8 num_active_models;
+} __packed;
+
+struct cpe_lsm_output_format_cfg {
+	struct cmi_hdr hdr;
+	u8 format;
+	u8 packing;
+	u8 data_path_events;
+} __packed;
+
+struct cpe_lsm_lab_enable {
+	struct cpe_param_data param;
+	u16 enable;
+	u16 reserved;
+} __packed;
+
+struct cpe_lsm_control_lab {
+	struct cmi_hdr hdr;
+	struct cpe_lsm_lab_enable lab_enable;
+} __packed;
+
+struct cpe_lsm_lab_config {
+	struct cpe_param_data param;
+	u32 minor_ver;
+	u32 latency;
+} __packed;
+
+struct cpe_lsm_lab_latency_config {
+	struct cmi_hdr hdr;
+	struct cpe_lsm_lab_config latency_cfg;
+} __packed;
+
+struct cpe_lsm_media_fmt_param {
+	struct cmi_hdr hdr;
+	struct cpe_param_data param;
+	u32 minor_version;
+	u32 sample_rate;
+	u16 num_channels;
+	u16 bit_width;
+} __packed;
+
+
+#define CPE_PARAM_LSM_LAB_LATENCY_SIZE (\
+				sizeof(struct cpe_lsm_lab_latency_config) - \
+				sizeof(struct cmi_hdr))
+#define PARAM_SIZE_LSM_LATENCY_SIZE (\
+					sizeof(struct cpe_lsm_lab_config) - \
+					sizeof(struct cpe_param_data))
+#define CPE_PARAM_SIZE_LSM_LAB_CONTROL (\
+				sizeof(struct cpe_lsm_control_lab) - \
+				sizeof(struct cmi_hdr))
+#define PARAM_SIZE_LSM_CONTROL_SIZE (sizeof(struct cpe_lsm_lab_enable) - \
+					sizeof(struct cpe_param_data))
+#define PARAM_SIZE_AFE_HW_MAD_CTRL (sizeof(struct cpe_afe_hw_mad_ctrl) - \
+				sizeof(struct cpe_param_data))
+#define PARAM_SIZE_AFE_PORT_CFG (sizeof(struct cpe_afe_port_cfg) - \
+				 sizeof(struct cpe_param_data))
+#define CPE_AFE_PARAM_PAYLOAD_SIZE (sizeof(struct cpe_afe_params) - \
+				sizeof(struct cmi_hdr))
+
+#define OPEN_CMD_PAYLOAD_SIZE (sizeof(struct cpe_lsm_cmd_open_tx) - \
+			       sizeof(struct cmi_hdr))
+#define OPEN_V2_CMD_PAYLOAD_SIZE (sizeof(struct cpe_lsm_cmd_open_tx_v2) - \
+			       sizeof(struct cmi_hdr))
+#define SHMEM_ALLOC_CMD_PLD_SIZE (sizeof(struct cpe_cmd_shmem_alloc) - \
+				      sizeof(struct cmi_hdr))
+
+#define SHMEM_DEALLOC_CMD_PLD_SIZE (sizeof(struct cpe_cmd_shmem_dealloc) - \
+				      sizeof(struct cmi_hdr))
+#define OUT_FMT_CFG_CMD_PAYLOAD_SIZE ( \
+		sizeof(struct cpe_lsm_output_format_cfg) - \
+		sizeof(struct cmi_hdr))
+
+#define CPE_AFE_CMD_PORT_CFG_PAYLOAD_SIZE \
+		(sizeof(struct cpe_afe_cmd_port_cfg) - \
+		 sizeof(struct cmi_hdr))
+
+#define CPE_AFE_CMD_MODE_PAYLOAD_SIZE \
+		(sizeof(struct cpe_afe_svc_cmd_mode) - \
+		 sizeof(struct cmi_hdr))
+#define CPE_CMD_EPD_THRES_PLD_SIZE (sizeof(struct cpe_lsm_param_epd_thres) - \
+				    sizeof(struct cmi_hdr))
+#define CPE_EPD_THRES_PARAM_SIZE ((CPE_CMD_EPD_THRES_PLD_SIZE) - \
+				  sizeof(struct cpe_param_data))
+#define CPE_CMD_OPMODE_PLD_SIZE (sizeof(struct cpe_lsm_param_opmode) - \
+				 sizeof(struct cmi_hdr))
+#define CPE_OPMODE_PARAM_SIZE ((CPE_CMD_OPMODE_PLD_SIZE) -\
+			       sizeof(struct cpe_param_data))
+#define CPE_CMD_CONNECTPORT_PLD_SIZE \
+	(sizeof(struct cpe_lsm_param_connectport) - \
+	 sizeof(struct cmi_hdr))
+#define CPE_CONNECTPORT_PARAM_SIZE ((CPE_CMD_CONNECTPORT_PLD_SIZE) - \
+				    sizeof(struct cpe_param_data))
+#define CPE_CMD_GAIN_PLD_SIZE (sizeof(struct cpe_lsm_param_gain) - \
+			       sizeof(struct cmi_hdr))
+#define CPE_GAIN_PARAM_SIZE ((CPE_CMD_GAIN_PLD_SIZE) - \
+			     sizeof(struct cpe_param_data))
+#define CPE_MEDIA_FMT_PLD_SIZE (sizeof(struct cpe_lsm_media_fmt_param) - \
+				sizeof(struct cmi_hdr))
+#define CPE_MEDIA_FMT_PARAM_SIZE ((CPE_MEDIA_FMT_PLD_SIZE) - \
+				  sizeof(struct cpe_param_data))
+#endif /* __CPE_CMI_H__ */

qcom/opensource/audio-kernel/asoc/codecs/cpe_err.h

@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __CPE_ERR__
+#define __CPE_ERR__
+
+#include <linux/errno.h>
+
+/* ERROR CODES */
+/* Success. The operation completed with no errors. */
+#define CPE_EOK          0x00000000
+/* General failure. */
+#define CPE_EFAILED      0x00000001
+/* Bad operation parameter. */
+#define CPE_EBADPARAM    0x00000002
+/* Unsupported routine or operation. */
+#define CPE_EUNSUPPORTED 0x00000003
+/* Unsupported version. */
+#define CPE_EVERSION     0x00000004
+/* Unexpected problem encountered. */
+#define CPE_EUNEXPECTED  0x00000005
+/* Unhandled problem occurred. */
+#define CPE_EPANIC       0x00000006
+/* Unable to allocate resource. */
+#define CPE_ENORESOURCE  0x00000007
+/* Invalid handle. */
+#define CPE_EHANDLE      0x00000008
+/* Operation is already processed. */
+#define CPE_EALREADY     0x00000009
+/* Operation is not ready to be processed. */
+#define CPE_ENOTREADY    0x0000000A
+/* Operation is pending completion. */
+#define CPE_EPENDING     0x0000000B
+/* Operation could not be accepted or processed. */
+#define CPE_EBUSY        0x0000000C
+/* Operation aborted due to an error. */
+#define CPE_EABORTED     0x0000000D
+/* Operation preempted by a higher priority. */
+#define CPE_EPREEMPTED   0x0000000E
+/* Operation requests intervention to complete. */
+#define CPE_ECONTINUE    0x0000000F
+/* Operation requests immediate intervention to complete. */
+#define CPE_EIMMEDIATE   0x00000010
+/* Operation is not implemented. */
+#define CPE_ENOTIMPL     0x00000011
+/* Operation needs more data or resources. */
+#define CPE_ENEEDMORE    0x00000012
+/* Operation does not have memory. */
+#define CPE_ENOMEMORY    0x00000014
+/* Item does not exist. */
+#define CPE_ENOTEXIST    0x00000015
+/* Operation is finished. */
+#define CPE_ETERMINATED  0x00000016
+/* Max count for adsp error code sent to HLOS*/
+#define CPE_ERR_MAX      (CPE_ETERMINATED + 1)
+
+
+/* ERROR STRING */
+/* Success. The operation completed with no errors. */
+#define CPE_EOK_STR          "CPE_EOK"
+/* General failure. */
+#define CPE_EFAILED_STR      "CPE_EFAILED"
+/* Bad operation parameter. */
+#define CPE_EBADPARAM_STR    "CPE_EBADPARAM"
+/* Unsupported routine or operation. */
+#define CPE_EUNSUPPORTED_STR "CPE_EUNSUPPORTED"
+/* Unsupported version. */
+#define CPE_EVERSION_STR     "CPE_EVERSION"
+/* Unexpected problem encountered. */
+#define CPE_EUNEXPECTED_STR  "CPE_EUNEXPECTED"
+/* Unhandled problem occurred. */
+#define CPE_EPANIC_STR       "CPE_EPANIC"
+/* Unable to allocate resource. */
+#define CPE_ENORESOURCE_STR  "CPE_ENORESOURCE"
+/* Invalid handle. */
+#define CPE_EHANDLE_STR      "CPE_EHANDLE"
+/* Operation is already processed. */
+#define CPE_EALREADY_STR     "CPE_EALREADY"
+/* Operation is not ready to be processed. */
+#define CPE_ENOTREADY_STR    "CPE_ENOTREADY"
+/* Operation is pending completion. */
+#define CPE_EPENDING_STR     "CPE_EPENDING"
+/* Operation could not be accepted or processed. */
+#define CPE_EBUSY_STR        "CPE_EBUSY"
+/* Operation aborted due to an error. */
+#define CPE_EABORTED_STR     "CPE_EABORTED"
+/* Operation preempted by a higher priority. */
+#define CPE_EPREEMPTED_STR   "CPE_EPREEMPTED"
+/* Operation requests intervention to complete. */
+#define CPE_ECONTINUE_STR    "CPE_ECONTINUE"
+/* Operation requests immediate intervention to complete. */
+#define CPE_EIMMEDIATE_STR   "CPE_EIMMEDIATE"
+/* Operation is not implemented. */
+#define CPE_ENOTIMPL_STR     "CPE_ENOTIMPL"
+/* Operation needs more data or resources. */
+#define CPE_ENEEDMORE_STR    "CPE_ENEEDMORE"
+/* Operation does not have memory. */
+#define CPE_ENOMEMORY_STR    "CPE_ENOMEMORY"
+/* Item does not exist. */
+#define CPE_ENOTEXIST_STR    "CPE_ENOTEXIST"
+/* Operation is finished. */
+#define CPE_ETERMINATED_STR  "CPE_ETERMINATED"
+/* Unexpected error code. */
+#define CPE_ERR_MAX_STR      "CPE_ERR_MAX"
+
+
+struct cpe_err_code {
+	int     lnx_err_code;
+	char    *cpe_err_str;
+};
+
+
+static struct cpe_err_code cpe_err_code_info[CPE_ERR_MAX+1] = {
+	{ 0, CPE_EOK_STR},
+	{ -ENOTRECOVERABLE, CPE_EFAILED_STR},
+	{ -EINVAL, CPE_EBADPARAM_STR},
+	{ -EOPNOTSUPP, CPE_EUNSUPPORTED_STR},
+	{ -ENOPROTOOPT, CPE_EVERSION_STR},
+	{ -ENOTRECOVERABLE, CPE_EUNEXPECTED_STR},
+	{ -ENOTRECOVERABLE, CPE_EPANIC_STR},
+	{ -ENOSPC, CPE_ENORESOURCE_STR},
+	{ -EBADR, CPE_EHANDLE_STR},
+	{ -EALREADY, CPE_EALREADY_STR},
+	{ -EPERM, CPE_ENOTREADY_STR},
+	{ -EINPROGRESS, CPE_EPENDING_STR},
+	{ -EBUSY, CPE_EBUSY_STR},
+	{ -ECANCELED, CPE_EABORTED_STR},
+	{ -EAGAIN, CPE_EPREEMPTED_STR},
+	{ -EAGAIN, CPE_ECONTINUE_STR},
+	{ -EAGAIN, CPE_EIMMEDIATE_STR},
+	{ -EAGAIN, CPE_ENOTIMPL_STR},
+	{ -ENODATA, CPE_ENEEDMORE_STR},
+	{ -EADV, CPE_ERR_MAX_STR},
+	{ -ENOMEM, CPE_ENOMEMORY_STR},
+	{ -ENODEV, CPE_ENOTEXIST_STR},
+	{ -EADV, CPE_ETERMINATED_STR},
+	{ -EADV, CPE_ERR_MAX_STR},
+};
+
+static inline int cpe_err_get_lnx_err_code(u32 cpe_error)
+{
+	if (cpe_error > CPE_ERR_MAX)
+		return cpe_err_code_info[CPE_ERR_MAX].lnx_err_code;
+	else
+		return cpe_err_code_info[cpe_error].lnx_err_code;
+}
+
+static inline char *cpe_err_get_err_str(u32 cpe_error)
+{
+	if (cpe_error > CPE_ERR_MAX)
+		return cpe_err_code_info[CPE_ERR_MAX].cpe_err_str;
+	else
+		return cpe_err_code_info[cpe_error].cpe_err_str;
+}
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/csra66x0/Kbuild

@@ -0,0 +1,105 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_QCS405), y)
+		include $(AUDIO_ROOT)/config/qcs405auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/qcs405autoconf.h
+	endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ CSRA66X0 ############
+
+# for CSRA66X0 Codec
+ifdef CONFIG_SND_SOC_CSRA66X0
+	CSRA66X0_OBJS += csra66x0.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+#EXTRA_CFLAGS += $(INCS)
+ccflags-y += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+#EXTRA_CFLAGS += -Wmaybe-uninitialized
+ccflags-y += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+#EXTRA_CFLAGS += -Wheader-guard
+ccflags-y += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
+endif
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_CSRA66X0) += csra66x0_dlkm.o
+csra66x0_dlkm-y := $(CSRA66X0_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/codecs/csra66x0/csra66x0.h

@@ -0,0 +1,231 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _CSRA66X0_H
+#define _CSRA66X0_H
+
+/* CSRA66X0 register addresses */
+#define CSRA66X0_BASE 0x7000
+
+#define CSRA66X0_AUDIO_IF_RX_CONFIG1            (CSRA66X0_BASE+0x0000)
+#define CSRA66X0_AUDIO_IF_RX_CONFIG2            (CSRA66X0_BASE+0x0001)
+#define CSRA66X0_AUDIO_IF_RX_CONFIG3            (CSRA66X0_BASE+0x0002)
+#define CSRA66X0_AUDIO_IF_TX_EN                 (CSRA66X0_BASE+0x0003)
+#define CSRA66X0_AUDIO_IF_TX_CONFIG1            (CSRA66X0_BASE+0x0004)
+#define CSRA66X0_AUDIO_IF_TX_CONFIG2            (CSRA66X0_BASE+0x0005)
+#define CSRA66X0_I2C_DEVICE_ADDRESS             (CSRA66X0_BASE+0x0006)
+#define CSRA66X0_CHIP_ID_FA                     (CSRA66X0_BASE+0x0007)
+#define CSRA66X0_ROM_VER_FA                     (CSRA66X0_BASE+0x0008)
+#define CSRA66X0_CHIP_REV_0_FA                  (CSRA66X0_BASE+0x0009)
+#define CSRA66X0_CHIP_REV_1_FA                  (CSRA66X0_BASE+0x000A)
+#define CSRA66X0_CH1_MIX_SEL                    (CSRA66X0_BASE+0x000B)
+#define CSRA66X0_CH2_MIX_SEL                    (CSRA66X0_BASE+0x000C)
+#define CSRA66X0_CH1_SAMPLE1_SCALE_0            (CSRA66X0_BASE+0x000D)
+#define CSRA66X0_CH1_SAMPLE1_SCALE_1            (CSRA66X0_BASE+0x000E)
+#define CSRA66X0_CH1_SAMPLE3_SCALE_0            (CSRA66X0_BASE+0x000F)
+#define CSRA66X0_CH1_SAMPLE3_SCALE_1            (CSRA66X0_BASE+0x0010)
+#define CSRA66X0_CH1_SAMPLE5_SCALE_0            (CSRA66X0_BASE+0x0011)
+#define CSRA66X0_CH1_SAMPLE5_SCALE_1            (CSRA66X0_BASE+0x0012)
+#define CSRA66X0_CH1_SAMPLE7_SCALE_0            (CSRA66X0_BASE+0x0013)
+#define CSRA66X0_CH1_SAMPLE7_SCALE_1            (CSRA66X0_BASE+0x0014)
+#define CSRA66X0_CH1_SAMPLE2_SCALE_0            (CSRA66X0_BASE+0x0015)
+#define CSRA66X0_CH1_SAMPLE2_SCALE_1            (CSRA66X0_BASE+0x0016)
+#define CSRA66X0_CH1_SAMPLE4_SCALE_0            (CSRA66X0_BASE+0x0017)
+#define CSRA66X0_CH1_SAMPLE4_SCALE_1            (CSRA66X0_BASE+0x0018)
+#define CSRA66X0_CH1_SAMPLE6_SCALE_0            (CSRA66X0_BASE+0x0019)
+#define CSRA66X0_CH1_SAMPLE6_SCALE_1            (CSRA66X0_BASE+0x001A)
+#define CSRA66X0_CH1_SAMPLE8_SCALE_0            (CSRA66X0_BASE+0x001B)
+#define CSRA66X0_CH1_SAMPLE8_SCALE_1            (CSRA66X0_BASE+0x001C)
+#define CSRA66X0_CH2_SAMPLE1_SCALE_0            (CSRA66X0_BASE+0x001D)
+#define CSRA66X0_CH2_SAMPLE1_SCALE_1            (CSRA66X0_BASE+0x001E)
+#define CSRA66X0_CH2_SAMPLE3_SCALE_0            (CSRA66X0_BASE+0x001F)
+#define CSRA66X0_CH2_SAMPLE3_SCALE_1            (CSRA66X0_BASE+0x0020)
+#define CSRA66X0_CH2_SAMPLE5_SCALE_0            (CSRA66X0_BASE+0x0021)
+#define CSRA66X0_CH2_SAMPLE5_SCALE_1            (CSRA66X0_BASE+0x0022)
+#define CSRA66X0_CH2_SAMPLE7_SCALE_0            (CSRA66X0_BASE+0x0023)
+#define CSRA66X0_CH2_SAMPLE7_SCALE_1            (CSRA66X0_BASE+0x0024)
+#define CSRA66X0_CH2_SAMPLE2_SCALE_0            (CSRA66X0_BASE+0x0025)
+#define CSRA66X0_CH2_SAMPLE2_SCALE_1            (CSRA66X0_BASE+0x0026)
+#define CSRA66X0_CH2_SAMPLE4_SCALE_0            (CSRA66X0_BASE+0x0027)
+#define CSRA66X0_CH2_SAMPLE4_SCALE_1            (CSRA66X0_BASE+0x0028)
+#define CSRA66X0_CH2_SAMPLE6_SCALE_0            (CSRA66X0_BASE+0x0029)
+#define CSRA66X0_CH2_SAMPLE6_SCALE_1            (CSRA66X0_BASE+0x002A)
+#define CSRA66X0_CH2_SAMPLE8_SCALE_0            (CSRA66X0_BASE+0x002B)
+#define CSRA66X0_CH2_SAMPLE8_SCALE_1            (CSRA66X0_BASE+0x002C)
+#define CSRA66X0_VOLUME_CONFIG_FA               (CSRA66X0_BASE+0x002D)
+#define CSRA66X0_STARTUP_DELAY_FA               (CSRA66X0_BASE+0x002E)
+#define CSRA66X0_CH1_VOLUME_0_FA                (CSRA66X0_BASE+0x002F)
+#define CSRA66X0_CH1_VOLUME_1_FA                (CSRA66X0_BASE+0x0030)
+#define CSRA66X0_CH2_VOLUME_0_FA                (CSRA66X0_BASE+0x0031)
+#define CSRA66X0_CH2_VOLUME_1_FA                (CSRA66X0_BASE+0x0032)
+#define CSRA66X0_QUAD_ENC_COUNT_0_FA            (CSRA66X0_BASE+0x0033)
+#define CSRA66X0_QUAD_ENC_COUNT_1_FA            (CSRA66X0_BASE+0x0034)
+#define CSRA66X0_SOFT_CLIP_CONFIG               (CSRA66X0_BASE+0x0035)
+#define CSRA66X0_CH1_HARD_CLIP_THRESH           (CSRA66X0_BASE+0x0036)
+#define CSRA66X0_CH2_HARD_CLIP_THRESH           (CSRA66X0_BASE+0x0037)
+#define CSRA66X0_SOFT_CLIP_THRESH               (CSRA66X0_BASE+0x0038)
+#define CSRA66X0_DS_ENABLE_THRESH_0             (CSRA66X0_BASE+0x0039)
+#define CSRA66X0_DS_ENABLE_THRESH_1             (CSRA66X0_BASE+0x003A)
+#define CSRA66X0_DS_TARGET_COUNT_0              (CSRA66X0_BASE+0x003B)
+#define CSRA66X0_DS_TARGET_COUNT_1              (CSRA66X0_BASE+0x003C)
+#define CSRA66X0_DS_TARGET_COUNT_2              (CSRA66X0_BASE+0x003D)
+#define CSRA66X0_DS_DISABLE_THRESH_0            (CSRA66X0_BASE+0x003E)
+#define CSRA66X0_DS_DISABLE_THRESH_1            (CSRA66X0_BASE+0x003F)
+#define CSRA66X0_DCA_CTRL                       (CSRA66X0_BASE+0x0040)
+#define CSRA66X0_CH1_DCA_THRESH                 (CSRA66X0_BASE+0x0041)
+#define CSRA66X0_CH2_DCA_THRESH                 (CSRA66X0_BASE+0x0042)
+#define CSRA66X0_DCA_ATTACK_RATE                (CSRA66X0_BASE+0x0043)
+#define CSRA66X0_DCA_RELEASE_RATE               (CSRA66X0_BASE+0x0044)
+#define CSRA66X0_CH1_OUTPUT_INVERT_EN           (CSRA66X0_BASE+0x0045)
+#define CSRA66X0_CH2_OUTPUT_INVERT_EN           (CSRA66X0_BASE+0x0046)
+#define CSRA66X0_CH1_176P4K_DELAY               (CSRA66X0_BASE+0x0047)
+#define CSRA66X0_CH2_176P4K_DELAY               (CSRA66X0_BASE+0x0048)
+#define CSRA66X0_CH1_192K_DELAY                 (CSRA66X0_BASE+0x0049)
+#define CSRA66X0_CH2_192K_DELAY                 (CSRA66X0_BASE+0x004A)
+#define CSRA66X0_DEEMP_CONFIG_FA                (CSRA66X0_BASE+0x004B)
+#define CSRA66X0_CH1_TREBLE_GAIN_CTRL_FA        (CSRA66X0_BASE+0x004C)
+#define CSRA66X0_CH2_TREBLE_GAIN_CTRL_FA        (CSRA66X0_BASE+0x004D)
+#define CSRA66X0_CH1_TREBLE_FC_CTRL_FA          (CSRA66X0_BASE+0x004E)
+#define CSRA66X0_CH2_TREBLE_FC_CTRL_FA          (CSRA66X0_BASE+0x004F)
+#define CSRA66X0_CH1_BASS_GAIN_CTRL_FA          (CSRA66X0_BASE+0x0050)
+#define CSRA66X0_CH2_BASS_GAIN_CTRL_FA          (CSRA66X0_BASE+0x0051)
+#define CSRA66X0_CH1_BASS_FC_CTRL_FA            (CSRA66X0_BASE+0x0052)
+#define CSRA66X0_CH2_BASS_FC_CTRL_FA            (CSRA66X0_BASE+0x0053)
+#define CSRA66X0_FILTER_SEL_8K                  (CSRA66X0_BASE+0x0054)
+#define CSRA66X0_FILTER_SEL_11P025K             (CSRA66X0_BASE+0x0055)
+#define CSRA66X0_FILTER_SEL_16K                 (CSRA66X0_BASE+0x0056)
+#define CSRA66X0_FILTER_SEL_22P05K              (CSRA66X0_BASE+0x0057)
+#define CSRA66X0_FILTER_SEL_32K                 (CSRA66X0_BASE+0x0058)
+#define CSRA66X0_FILTER_SEL_44P1K_48K           (CSRA66X0_BASE+0x0059)
+#define CSRA66X0_FILTER_SEL_88P2K_96K           (CSRA66X0_BASE+0x005A)
+#define CSRA66X0_FILTER_SEL_176P4K_192K         (CSRA66X0_BASE+0x005B)
+/* RESERVED (CSRA66X0_BASE+0x005C) */
+#define CSRA66X0_USER_DSP_CTRL                  (CSRA66X0_BASE+0x005D)
+#define CSRA66X0_TEST_TONE_CTRL                 (CSRA66X0_BASE+0x005E)
+#define CSRA66X0_TEST_TONE_FREQ_0               (CSRA66X0_BASE+0x005F)
+#define CSRA66X0_TEST_TONE_FREQ_1               (CSRA66X0_BASE+0x0060)
+#define CSRA66X0_TEST_TONE_FREQ_2               (CSRA66X0_BASE+0x0061)
+#define CSRA66X0_AUDIO_RATE_CTRL_FA             (CSRA66X0_BASE+0x0062)
+#define CSRA66X0_MODULATION_INDEX_CTRL          (CSRA66X0_BASE+0x0063)
+#define CSRA66X0_MODULATION_INDEX_COUNT         (CSRA66X0_BASE+0x0064)
+#define CSRA66X0_MIN_MODULATION_PULSE_WIDTH     (CSRA66X0_BASE+0x0065)
+#define CSRA66X0_DEAD_TIME_CTRL                 (CSRA66X0_BASE+0x0066)
+#define CSRA66X0_DEAD_TIME_THRESHOLD_0          (CSRA66X0_BASE+0x0067)
+#define CSRA66X0_DEAD_TIME_THRESHOLD_1          (CSRA66X0_BASE+0x0068)
+#define CSRA66X0_DEAD_TIME_THRESHOLD_2          (CSRA66X0_BASE+0x0069)
+#define CSRA66X0_CH1_LOW_SIDE_DLY               (CSRA66X0_BASE+0x006A)
+#define CSRA66X0_CH2_LOW_SIDE_DLY               (CSRA66X0_BASE+0x006B)
+#define CSRA66X0_SPECTRUM_CTRL                  (CSRA66X0_BASE+0x006C)
+/* RESERVED (CSRA66X0_BASE+0x006D) */
+#define CSRA66X0_SPECTRUM_SPREAD_CTRL           (CSRA66X0_BASE+0x006E)
+/* RESERVED (CSRA66X0_BASE+0x006F) */
+/* ... */
+/* RESERVED (CSRA66X0_BASE+0x007C) */
+#define CSRA66X0_EXT_PA_PROTECT_POLARITY        (CSRA66X0_BASE+0x007D)
+#define CSRA66X0_TEMP0_BACKOFF_COMP_VALUE       (CSRA66X0_BASE+0x007E)
+#define CSRA66X0_TEMP0_SHUTDOWN_COMP_VALUE      (CSRA66X0_BASE+0x007F)
+#define CSRA66X0_TEMP1_BACKOFF_COMP_VALUE       (CSRA66X0_BASE+0x0080)
+#define CSRA66X0_TEMP1_SHUTDOWN_COMP_VALUE      (CSRA66X0_BASE+0x0081)
+#define CSRA66X0_TEMP_PROT_BACKOFF              (CSRA66X0_BASE+0x0082)
+#define CSRA66X0_TEMP_READ0_FA                  (CSRA66X0_BASE+0x0083)
+#define CSRA66X0_TEMP_READ1_FA                  (CSRA66X0_BASE+0x0084)
+#define CSRA66X0_CHIP_STATE_CTRL_FA             (CSRA66X0_BASE+0x0085)
+/* RESERVED (CSRA66X0_BASE+0x0086) */
+#define CSRA66X0_PWM_OUTPUT_CONFIG              (CSRA66X0_BASE+0x0087)
+#define CSRA66X0_MISC_CONTROL_STATUS_0          (CSRA66X0_BASE+0x0088)
+#define CSRA66X0_MISC_CONTROL_STATUS_1_FA       (CSRA66X0_BASE+0x0089)
+#define CSRA66X0_PIO0_SELECT                    (CSRA66X0_BASE+0x008A)
+#define CSRA66X0_PIO1_SELECT                    (CSRA66X0_BASE+0x008B)
+#define CSRA66X0_PIO2_SELECT                    (CSRA66X0_BASE+0x008C)
+#define CSRA66X0_PIO3_SELECT                    (CSRA66X0_BASE+0x008D)
+#define CSRA66X0_PIO4_SELECT                    (CSRA66X0_BASE+0x008E)
+#define CSRA66X0_PIO5_SELECT                    (CSRA66X0_BASE+0x008F)
+#define CSRA66X0_PIO6_SELECT                    (CSRA66X0_BASE+0x0090)
+#define CSRA66X0_PIO7_SELECT                    (CSRA66X0_BASE+0x0091)
+#define CSRA66X0_PIO8_SELECT                    (CSRA66X0_BASE+0x0092)
+#define CSRA66X0_PIO_DIRN0                      (CSRA66X0_BASE+0x0093)
+#define CSRA66X0_PIO_DIRN1                      (CSRA66X0_BASE+0x0094)
+#define CSRA66X0_PIO_PULL_EN0                   (CSRA66X0_BASE+0x0095)
+#define CSRA66X0_PIO_PULL_EN1                   (CSRA66X0_BASE+0x0096)
+#define CSRA66X0_PIO_PULL_DIR0                  (CSRA66X0_BASE+0x0097)
+#define CSRA66X0_PIO_PULL_DIR1                  (CSRA66X0_BASE+0x0098)
+#define CSRA66X0_PIO_DRIVE_OUT0_FA              (CSRA66X0_BASE+0x0099)
+#define CSRA66X0_PIO_DRIVE_OUT1_FA              (CSRA66X0_BASE+0x009A)
+#define CSRA66X0_PIO_STATUS_IN0_FA              (CSRA66X0_BASE+0x009B)
+#define CSRA66X0_PIO_STATUS_IN1_FA              (CSRA66X0_BASE+0x009C)
+/* RESERVED (CSRA66X0_BASE+0x009D) */
+#define CSRA66X0_IRQ_OUTPUT_ENABLE              (CSRA66X0_BASE+0x009E)
+#define CSRA66X0_IRQ_OUTPUT_POLARITY            (CSRA66X0_BASE+0x009F)
+#define CSRA66X0_IRQ_OUTPUT_STATUS_FA           (CSRA66X0_BASE+0x00A0)
+#define CSRA66X0_CLIP_DCA_STATUS_FA             (CSRA66X0_BASE+0x00A1)
+#define CSRA66X0_CHIP_STATE_STATUS_FA           (CSRA66X0_BASE+0x00A2)
+#define CSRA66X0_FAULT_STATUS_FA                (CSRA66X0_BASE+0x00A3)
+#define CSRA66X0_OTP_STATUS_FA                  (CSRA66X0_BASE+0x00A4)
+#define CSRA66X0_AUDIO_IF_STATUS_FA             (CSRA66X0_BASE+0x00A5)
+/* RESERVED (CSRA66X0_BASE+0x00A6) */
+#define CSRA66X0_DSP_SATURATION_STATUS_FA       (CSRA66X0_BASE+0x00A7)
+#define CSRA66X0_AUDIO_RATE_STATUS_FA           (CSRA66X0_BASE+0x00A8)
+/* RESERVED (CSRA66X0_BASE+0x00A9) */
+/* ... */
+/* RESERVED (CSRA66X0_BASE+0x00AB) */
+#define CSRA66X0_DISABLE_PWM_OUTPUT             (CSRA66X0_BASE+0x00AC)
+/* RESERVED (CSRA66X0_BASE+0x00AD) */
+/* ... */
+/* RESERVED (CSRA66X0_BASE+0x00B0) */
+#define CSRA66X0_OTP_VER_FA                     (CSRA66X0_BASE+0x00B1)
+#define CSRA66X0_RAM_VER_FA                     (CSRA66X0_BASE+0x00B2)
+/* RESERVED (CSRA66X0_BASE+0x00B3) */
+#define CSRA66X0_AUDIO_SATURATION_FLAGS_FA      (CSRA66X0_BASE+0x00B4)
+#define CSRA66X0_DCOFFSET_CHAN_1_01_FA          (CSRA66X0_BASE+0x00B5)
+#define CSRA66X0_DCOFFSET_CHAN_1_02_FA          (CSRA66X0_BASE+0x00B6)
+#define CSRA66X0_DCOFFSET_CHAN_1_03_FA          (CSRA66X0_BASE+0x00B7)
+#define CSRA66X0_DCOFFSET_CHAN_2_01_FA          (CSRA66X0_BASE+0x00B8)
+#define CSRA66X0_DCOFFSET_CHAN_2_02_FA          (CSRA66X0_BASE+0x00B9)
+#define CSRA66X0_DCOFFSET_CHAN_2_03_FA          (CSRA66X0_BASE+0x00BA)
+#define CSRA66X0_FORCED_PA_SWITCHING_CTRL       (CSRA66X0_BASE+0x00BB)
+#define CSRA66X0_PA_FORCE_PULSE_WIDTH           (CSRA66X0_BASE+0x00BC)
+#define CSRA66X0_PA_HIGH_MODULATION_CTRL_CH1    (CSRA66X0_BASE+0x00BD)
+/* RESERVED (CSRA66X0_BASE+0x00BE) */
+/* RESERVED (CSRA66X0_BASE+0x00BF) */
+#define CSRA66X0_HIGH_MODULATION_THRESHOLD_LOW  (CSRA66X0_BASE+0x00C0)
+#define CSRA66X0_HIGH_MODULATION_THRESHOLD_HIGH (CSRA66X0_BASE+0x00C1)
+/* RESERVED (CSRA66X0_BASE+0x00C2) */
+/* RESERVED (CSRA66X0_BASE+0x00C3) */
+#define CSRA66X0_PA_FREEZE_CTRL                 (CSRA66X0_BASE+0x00C4)
+#define CSRA66X0_DCA_FREEZE_CTRL                (CSRA66X0_BASE+0x00C5)
+/* RESERVED (CSRA66X0_BASE+0x00C6) */
+/* ... */
+/* RESERVED (CSRA66X0_BASE+0x00FF) */
+#define CSRA66X0_MAX_REGISTER_ADDR CSRA66X0_DCA_FREEZE_CTRL
+
+#define CSRA66X0_COEFF_BASE     0xD000
+#define CSRA66X0_MAX_COEFF_ADDR 0xD6DF
+
+#define EXPECTED_CSRA66X0_CHIP_ID 0x39
+
+#define SPK_VOLUME_M20DB 0x119
+#define SPK_VOLUME_M20DB_LSB (SPK_VOLUME_M20DB & 0x0FF)
+#define SPK_VOLUME_M20DB_MSB ((SPK_VOLUME_M20DB & 0x100)>>8)
+#define SPK_VOLUME_LSB_MSK 0x00FF
+#define SPK_VOLUME_MSB_MSK 0x0100
+
+#define SET_CONFIG_STATE    0x0
+#define SET_RUN_STATE       0x1
+#define SET_STDBY_STATE     0x2
+
+#define CONFIG_STATE_ID 0x3
+#define WAIT_FOR_CONFIG_STATE_TIMEOUT_MS 2000
+#define SYSFS_RESET 1
+
+#define FAULT_STATUS_INTERNAL       0x01
+#define FAULT_STATUS_OTP_INTEGRITY  0x02
+#define FAULT_STATUS_PADS2          0x04
+#define FAULT_STATUS_SMPS           0x08
+#define FAULT_STATUS_TEMP           0x10
+#define FAULT_STATUS_PROTECT        0x20
+
+
+void csra66x0_hw_free_mute(struct snd_soc_component *component);
+#endif /* _CSRA66X0_H */

qcom/opensource/audio-kernel/asoc/codecs/ep92/Kbuild

@@ -0,0 +1,106 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_QCS405), y)
+		include $(AUDIO_ROOT)/config/qcs405auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/qcs405autoconf.h
+	endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ EP92 ############
+
+# for EP92 Codec
+ifdef CONFIG_SND_SOC_EP92
+	EP92_OBJS += ep92.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+#EXTRA_CFLAGS += $(INCS)
+ccflags-y += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+#EXTRA_CFLAGS += -Wmaybe-uninitialized
+ccflags-y += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+#EXTRA_CFLAGS += -Wheader-guard
+ccflags-y += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
+endif
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_EP92) += ep92_dlkm.o
+ep92_dlkm-y := $(EP92_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/codecs/ep92/ep92.h

@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __EP92_H__
+#define __EP92_H__
+
+/* EP92 register addresses */
+/* BI = Basic Info */
+#define   EP92_BI_VENDOR_ID_0                   0x00
+#define   EP92_BI_VENDOR_ID_1                   0x01
+#define   EP92_BI_DEVICE_ID_0                   0x02
+#define   EP92_BI_DEVICE_ID_1                   0x03
+#define   EP92_BI_VERSION_NUM                   0x04
+#define   EP92_BI_VERSION_YEAR                  0x05
+#define   EP92_BI_VERSION_MONTH                 0x06
+#define   EP92_BI_VERSION_DATE                  0x07
+#define   EP92_BI_GENERAL_INFO_0                0x08
+#define   EP92_BI_GENERAL_INFO_1                0x09
+#define   EP92_BI_GENERAL_INFO_2                0x0A
+#define   EP92_BI_GENERAL_INFO_3                0x0B
+#define   EP92_BI_GENERAL_INFO_4                0x0C
+#define   EP92_BI_GENERAL_INFO_5                0x0D
+#define   EP92_BI_GENERAL_INFO_6                0x0E
+
+#define   EP92_ISP_MODE_ENTER_ISP               0x0F
+
+#define   EP92_GENERAL_CONTROL_0                0x10
+#define   EP92_GENERAL_CONTROL_1                0x11
+#define   EP92_GENERAL_CONTROL_2                0x12
+#define   EP92_GENERAL_CONTROL_3                0x13
+#define   EP92_GENERAL_CONTROL_4                0x14
+
+#define   EP92_CEC_EVENT_CODE                   0x15
+#define   EP92_CEC_EVENT_PARAM_1                0x16
+#define   EP92_CEC_EVENT_PARAM_2                0x17
+#define   EP92_CEC_EVENT_PARAM_3                0x18
+#define   EP92_CEC_EVENT_PARAM_4                0x19
+/*        RESERVED                              0x1A */
+/*        ...                                   ...  */
+/*        RESERVED                              0x1F */
+#define   EP92_AUDIO_INFO_SYSTEM_STATUS_0       0x20
+#define   EP92_AUDIO_INFO_SYSTEM_STATUS_1       0x21
+#define   EP92_AUDIO_INFO_AUDIO_STATUS          0x22
+#define   EP92_AUDIO_INFO_CHANNEL_STATUS_0      0x23
+#define   EP92_AUDIO_INFO_CHANNEL_STATUS_1      0x24
+#define   EP92_AUDIO_INFO_CHANNEL_STATUS_2      0x25
+#define   EP92_AUDIO_INFO_CHANNEL_STATUS_3      0x26
+#define   EP92_AUDIO_INFO_CHANNEL_STATUS_4      0x27
+#define   EP92_AUDIO_INFO_ADO_INFO_FRAME_0      0x28
+#define   EP92_AUDIO_INFO_ADO_INFO_FRAME_1      0x29
+#define   EP92_AUDIO_INFO_ADO_INFO_FRAME_2      0x2A
+#define   EP92_AUDIO_INFO_ADO_INFO_FRAME_3      0x2B
+#define   EP92_AUDIO_INFO_ADO_INFO_FRAME_4      0x2C
+#define   EP92_AUDIO_INFO_ADO_INFO_FRAME_5      0x2D
+
+#define   EP92_OTHER_PACKETS_HDMI_VS_0          0x2E
+#define   EP92_OTHER_PACKETS_HDMI_VS_1          0x2F
+#define   EP92_OTHER_PACKETS_ACP_PACKET         0x30
+#define   EP92_OTHER_PACKETS_AVI_INFO_FRAME_0   0x31
+#define   EP92_OTHER_PACKETS_AVI_INFO_FRAME_1   0x32
+#define   EP92_OTHER_PACKETS_AVI_INFO_FRAME_2   0x33
+#define   EP92_OTHER_PACKETS_AVI_INFO_FRAME_3   0x34
+#define   EP92_OTHER_PACKETS_AVI_INFO_FRAME_4   0x35
+#define   EP92_OTHER_PACKETS_GC_PACKET_0        0x36
+#define   EP92_OTHER_PACKETS_GC_PACKET_1        0x37
+#define   EP92_OTHER_PACKETS_GC_PACKET_2        0x38
+
+#define   EP92_MAX_REGISTER_ADDR                EP92_OTHER_PACKETS_GC_PACKET_2
+
+/* shift/masks for register bits
+ * GI = General Info
+ * GC = General Control
+ * AI = Audio Info
+ */
+#define EP92_GI_ADO_CHF_MASK        0x01
+#define EP92_GI_CEC_ECF_MASK        0x02
+#define EP92_GI_TX_HOT_PLUG_SHIFT   7
+#define EP92_GI_TX_HOT_PLUG_MASK    0x80
+#define EP92_GI_VIDEO_LATENCY_SHIFT 0
+#define EP92_GI_VIDEO_LATENCY_MASK  0xff
+
+#define EP92_GC_POWER_SHIFT      7
+#define EP92_GC_POWER_MASK       0x80
+#define EP92_GC_AUDIO_PATH_SHIFT 5
+#define EP92_GC_AUDIO_PATH_MASK  0x20
+#define EP92_GC_CEC_MUTE_SHIFT   1
+#define EP92_GC_CEC_MUTE_MASK    0x02
+#define EP92_GC_ARC_EN_SHIFT     0
+#define EP92_GC_ARC_EN_MASK      0x01
+#define EP92_GC_ARC_DIS_SHIFT    6
+#define EP92_GC_ARC_DIS_MASK     0x40
+#define EP92_GC_RX_SEL_SHIFT     0
+#define EP92_GC_RX_SEL_MASK      0x07
+#define EP92_GC_CEC_VOLUME_SHIFT 0
+#define EP92_GC_CEC_VOLUME_MASK  0xff
+#define EP92_GC_LINK_ON0_SHIFT   0
+#define EP92_GC_LINK_ON0_MASK    0x01
+#define EP92_GC_LINK_ON1_SHIFT   1
+#define EP92_GC_LINK_ON1_MASK    0x02
+#define EP92_GC_LINK_ON2_SHIFT   2
+#define EP92_GC_LINK_ON2_MASK    0x04
+
+#define EP92_AI_MCLK_ON_SHIFT    6
+#define EP92_AI_MCLK_ON_MASK     0x40
+#define EP92_AI_AVMUTE_SHIFT     5
+#define EP92_AI_AVMUTE_MASK      0x20
+#define EP92_AI_LAYOUT_SHIFT     0
+#define EP92_AI_LAYOUT_MASK      0x01
+#define EP92_AI_HBR_ADO_SHIFT    5
+#define EP92_AI_HBR_ADO_MASK     0x20
+#define EP92_AI_STD_ADO_SHIFT    3
+#define EP92_AI_STD_ADO_MASK     0x08
+#define EP92_AI_RATE_MASK        0x07
+#define EP92_AI_NPCM_MASK        0x02
+#define EP92_AI_PREEMPH_SHIFT    3
+#define EP92_AI_PREEMPH_MASK     0x38
+#define EP92_AI_CH_COUNT_MASK    0x07
+#define EP92_AI_CH_ALLOC_MASK    0xff
+#define EP92_AI_DSD_ADO_SHIFT    4
+#define EP92_AI_DSD_ADO_MASK     0x10
+#define EP92_AI_DSD_RATE_SHIFT   4
+#define EP92_AI_DSD_RATE_MASK    0x30
+
+#define EP92_2CHOICE_MASK        1
+#define EP92_GC_CEC_VOLUME_MIN   0
+#define EP92_GC_CEC_VOLUME_MAX   100
+#define EP92_AI_RATE_MIN         0
+#define EP92_AI_RATE_MAX         768000
+#define EP92_AI_CH_COUNT_MIN     0
+#define EP92_AI_CH_COUNT_MAX     8
+#define EP92_AI_CH_ALLOC_MIN     0
+#define EP92_AI_CH_ALLOC_MAX     0xff
+
+#define EP92_STATUS_NO_SIGNAL           0
+#define EP92_STATUS_AUDIO_ACTIVE        1
+
+/* kcontrol storage indices */
+enum {
+	EP92_KCTL_POWER = 0,
+	EP92_KCTL_AUDIO_PATH,
+	EP92_KCTL_CEC_MUTE,
+	EP92_KCTL_ARC_EN,
+	EP92_KCTL_RX_SEL,
+	EP92_KCTL_CEC_VOLUME,
+	EP92_KCTL_STATE,
+	EP92_KCTL_AVMUTE,
+	EP92_KCTL_LAYOUT,
+	EP92_KCTL_MODE,
+	EP92_KCTL_RATE,
+	EP92_KCTL_CH_COUNT,
+	EP92_KCTL_CH_ALLOC,
+	EP92_KCTL_MAX
+};
+
+int ep92_set_ext_mclk(struct snd_soc_codec *codec, uint32_t mclk_freq);
+
+#endif /* __EP92_H__ */

qcom/opensource/audio-kernel/asoc/codecs/lpass-bt-swr.c

@@ -0,0 +1,672 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/pm_runtime.h>
+#include <soc/swr-common.h>
+#include <asoc/msm-cdc-pinctrl.h>
+#include <dsp/digital-cdc-rsc-mgr.h>
+#include <soc/swr-wcd.h>
+#include <soc/snd_event.h>
+
+#define DRV_NAME "lpass-bt-swr"
+
+/* pm runtime auto suspend timer in msecs */
+#define LPASS_BT_SWR_AUTO_SUSPEND_DELAY          100 /* delay in msec */
+
+#define LPASS_BT_SWR_STRING_LEN 80
+
+#define LPASS_BT_SWR_CHILD_DEVICES_MAX 1
+
+/* Hold instance to soundwire platform device */
+struct lpass_bt_swr_ctrl_data {
+	struct platform_device *lpass_bt_swr_pdev;
+};
+
+struct lpass_bt_swr_ctrl_platform_data {
+	void *handle; /* holds parent private data */
+	int (*read)(void *handle, int reg);
+	int (*write)(void *handle, int reg, int val);
+	int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
+	int (*clk)(void *handle, bool enable);
+	int (*core_vote)(void *handle, bool enable);
+	int (*handle_irq)(void *handle,
+			  irqreturn_t (*swrm_irq_handler)(int irq,
+							  void *data),
+			  void *swrm_handle,
+			  int action);
+};
+
+struct lpass_bt_swr_priv {
+	struct device *dev;
+	struct mutex vote_lock;
+	struct mutex swr_clk_lock;
+	struct mutex ssr_lock;
+	bool dev_up;
+	bool initial_boot;
+
+	struct clk *lpass_core_hw_vote;
+	struct clk *lpass_audio_hw_vote;
+	int core_hw_vote_count;
+	int core_audio_vote_count;
+	int swr_clk_users;
+	struct clk *clk_handle;
+	struct clk *clk_handle_2x;
+
+	struct lpass_bt_swr_ctrl_data *swr_ctrl_data;
+	struct lpass_bt_swr_ctrl_platform_data swr_plat_data;
+	struct work_struct lpass_bt_swr_add_child_devices_work;
+	struct platform_device *pdev_child_devices
+			[LPASS_BT_SWR_CHILD_DEVICES_MAX];
+	int child_count;
+
+	struct device_node *bt_swr_gpio_p;
+
+	/* Entry for version info */
+	struct snd_info_entry *entry;
+	struct snd_info_entry *version_entry;
+
+	struct blocking_notifier_head notifier;
+	struct device *clk_dev;
+};
+
+static struct lpass_bt_swr_priv *lpass_bt_priv;
+
+static void lpass_bt_swr_add_child_devices(struct work_struct *work)
+{
+	struct lpass_bt_swr_priv *priv;
+	struct platform_device *pdev;
+	struct device_node *node;
+	struct lpass_bt_swr_ctrl_data *swr_ctrl_data = NULL, *temp;
+	int ret;
+	u16 count = 0, ctrl_num = 0;
+	struct lpass_bt_swr_ctrl_platform_data *platdata;
+	char plat_dev_name[LPASS_BT_SWR_STRING_LEN];
+
+	priv = container_of(work, struct lpass_bt_swr_priv,
+			     lpass_bt_swr_add_child_devices_work);
+	if (!priv) {
+		pr_err("%s: Memory for priv does not exist\n",
+			__func__);
+		return;
+	}
+	if (!priv->dev || !priv->dev->of_node) {
+		dev_err(priv->dev,
+			"%s: DT node for priv does not exist\n", __func__);
+		return;
+	}
+
+	platdata = &priv->swr_plat_data;
+	priv->child_count = 0;
+
+	for_each_available_child_of_node(priv->dev->of_node, node) {
+		if (strnstr(node->name, "bt_swr_mstr",
+				strlen("bt_swr_mstr")) != NULL)
+			strscpy(plat_dev_name, "bt_swr_mstr",
+				(LPASS_BT_SWR_STRING_LEN - 1));
+		else
+			continue;
+
+		pdev = platform_device_alloc(plat_dev_name, -1);
+		if (!pdev) {
+			dev_err(priv->dev, "%s: pdev memory alloc failed\n",
+				__func__);
+			ret = -ENOMEM;
+			return;
+		}
+		pdev->dev.parent = priv->dev;
+		pdev->dev.of_node = node;
+
+		ret = platform_device_add_data(pdev, platdata,
+					       sizeof(*platdata));
+		if (ret) {
+			dev_err(&pdev->dev,
+				"%s: cannot add plat data ctrl:%d\n",
+				__func__, ctrl_num);
+			goto fail_pdev_add;
+		}
+
+		temp = krealloc(swr_ctrl_data,
+				(ctrl_num + 1) * sizeof(
+				struct lpass_bt_swr_ctrl_data),
+				GFP_KERNEL);
+		if (!temp) {
+			dev_err(&pdev->dev, "out of memory\n");
+			ret = -ENOMEM;
+			goto fail_pdev_add;
+		}
+		swr_ctrl_data = temp;
+		swr_ctrl_data[ctrl_num].lpass_bt_swr_pdev = pdev;
+		ctrl_num++;
+
+		dev_dbg(&pdev->dev, "%s: Adding soundwire ctrl device(s)\n",
+			__func__);
+		priv->swr_ctrl_data = swr_ctrl_data;
+
+		ret = platform_device_add(pdev);
+		if (ret) {
+			dev_err(&pdev->dev,
+				"%s: Cannot add platform device\n",
+				__func__);
+			goto fail_pdev_add;
+		}
+
+		if (priv->child_count < LPASS_BT_SWR_CHILD_DEVICES_MAX)
+			priv->pdev_child_devices[
+					priv->child_count++] = pdev;
+		else
+			return;
+	}
+
+	return;
+fail_pdev_add:
+	for (count = 0; count < priv->child_count; count++)
+		platform_device_put(priv->pdev_child_devices[count]);
+}
+
+
+bool lpass_bt_swr_check_core_votes(struct lpass_bt_swr_priv *priv)
+{
+	bool ret = true;
+
+	mutex_lock(&priv->vote_lock);
+	if (!priv->dev_up ||
+		(priv->lpass_core_hw_vote && !priv->core_hw_vote_count) ||
+		(priv->lpass_audio_hw_vote && !priv->core_audio_vote_count))
+		ret = false;
+	mutex_unlock(&priv->vote_lock);
+
+	return ret;
+}
+
+static int lpass_bt_swr_core_vote(void *handle, bool enable)
+{
+	int rc = 0;
+	struct lpass_bt_swr_priv *priv = (struct lpass_bt_swr_priv *) handle;
+
+	if (priv == NULL) {
+		pr_err_ratelimited("%s: priv data is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (!priv->dev_up && enable) {
+		pr_err("%s: adsp is not up\n", __func__);
+		return -EINVAL;
+	}
+
+	if (enable) {
+		pm_runtime_get_sync(priv->dev);
+		if (lpass_bt_swr_check_core_votes(priv))
+			rc = 0;
+		else
+			rc = -ENOTSYNC;
+	} else {
+		pm_runtime_put_autosuspend(priv->dev);
+		pm_runtime_mark_last_busy(priv->dev);
+	}
+	return rc;
+}
+
+static int lpass_bt_swr_mclk_enable(
+				struct lpass_bt_swr_priv *priv,
+				bool mclk_enable)
+{
+	int ret = 0;
+
+	dev_dbg(priv->dev, "%s: mclk_enable = %u\n",
+		__func__, mclk_enable);
+
+	ret = lpass_bt_swr_core_vote(priv, true);
+	if (ret < 0) {
+		dev_err_ratelimited(priv->dev,
+			"%s: request core vote failed\n",
+			__func__);
+		goto exit;
+	}
+
+	if (mclk_enable) {
+		ret = clk_prepare_enable(priv->clk_handle);
+		if (ret < 0) {
+			dev_err_ratelimited(priv->dev,
+				"%s: bt_swr_clk enable failed\n", __func__);
+			goto error;
+		}
+
+		if (priv->clk_handle_2x) {
+			ret = clk_prepare_enable(priv->clk_handle_2x);
+			if (ret < 0) {
+				dev_err_ratelimited(priv->dev,
+				  "%s: bt_swr_2x_clk enable failed\n", __func__);
+				clk_disable_unprepare(priv->clk_handle);
+			}
+		}
+	} else {
+		clk_disable_unprepare(priv->clk_handle);
+		if (priv->clk_handle_2x)
+			clk_disable_unprepare(priv->clk_handle_2x);
+	}
+
+error:
+	lpass_bt_swr_core_vote(priv, false);
+exit:
+	return ret;
+}
+
+static int lpass_bt_swrm_clock(void *handle, bool enable)
+{
+	struct lpass_bt_swr_priv *priv = (struct lpass_bt_swr_priv *) handle;
+	int ret = 0;
+
+	mutex_lock(&priv->swr_clk_lock);
+
+	dev_dbg(priv->dev, "%s: swrm clock %s\n",
+		__func__, (enable ? "enable" : "disable"));
+	if (enable) {
+		pm_runtime_get_sync(priv->dev);
+		if (priv->swr_clk_users == 0) {
+			ret = msm_cdc_pinctrl_select_active_state(
+						priv->bt_swr_gpio_p);
+			if (ret < 0) {
+				dev_err_ratelimited(priv->dev,
+					"%s: bt swr pinctrl enable failed\n",
+					__func__);
+				pm_runtime_mark_last_busy(priv->dev);
+				pm_runtime_put_autosuspend(priv->dev);
+				goto exit;
+			}
+			ret = lpass_bt_swr_mclk_enable(priv, true);
+			if (ret < 0) {
+				msm_cdc_pinctrl_select_sleep_state(
+						priv->bt_swr_gpio_p);
+				dev_err_ratelimited(priv->dev,
+					"%s: lpass bt swr request clock enable failed\n",
+					__func__);
+				pm_runtime_mark_last_busy(priv->dev);
+				pm_runtime_put_autosuspend(priv->dev);
+				goto exit;
+			}
+		}
+		priv->swr_clk_users++;
+		pm_runtime_mark_last_busy(priv->dev);
+		pm_runtime_put_autosuspend(priv->dev);
+	} else {
+		if (priv->swr_clk_users <= 0) {
+			dev_err_ratelimited(priv->dev, "%s: clock already disabled\n",
+			__func__);
+			priv->swr_clk_users = 0;
+			goto exit;
+		}
+		priv->swr_clk_users--;
+		if (priv->swr_clk_users == 0) {
+			lpass_bt_swr_mclk_enable(priv, false);
+			ret = msm_cdc_pinctrl_select_sleep_state(
+						priv->bt_swr_gpio_p);
+			if (ret < 0) {
+				dev_err_ratelimited(priv->dev,
+					"%s: bt swr pinctrl disable failed\n",
+					__func__);
+				goto exit;
+			}
+		}
+	}
+	dev_dbg(priv->dev, "%s: swrm clock users %d\n",
+		__func__, priv->swr_clk_users);
+exit:
+	mutex_unlock(&priv->swr_clk_lock);
+	return ret;
+}
+
+static void lpass_bt_swr_ssr_disable(struct device *dev, void *data)
+{
+	struct lpass_bt_swr_priv *priv = data;
+
+	if (!priv->dev_up) {
+		dev_err_ratelimited(priv->dev,
+				    "%s: already disabled\n", __func__);
+		return;
+	}
+
+	mutex_lock(&priv->ssr_lock);
+	priv->dev_up = false;
+	mutex_unlock(&priv->ssr_lock);
+
+	swrm_wcd_notify(priv->swr_ctrl_data->lpass_bt_swr_pdev,
+				 SWR_DEVICE_SSR_DOWN, NULL);
+
+}
+
+static int lpass_bt_swr_ssr_enable(struct device *dev, void *data)
+{
+	struct lpass_bt_swr_priv *priv = data;
+	int ret;
+
+	if (priv->initial_boot) {
+		priv->initial_boot = false;
+		return 0;
+	}
+
+	mutex_lock(&priv->ssr_lock);
+	priv->dev_up = true;
+	mutex_unlock(&priv->ssr_lock);
+
+	mutex_lock(&priv->swr_clk_lock);
+
+	dev_dbg(priv->dev, "%s: swrm clock users %d\n",
+		__func__, priv->swr_clk_users);
+
+	lpass_bt_swr_mclk_enable(priv, false);
+	ret = msm_cdc_pinctrl_select_sleep_state(
+				priv->bt_swr_gpio_p);
+	if (ret < 0) {
+		dev_err_ratelimited(priv->dev,
+			"%s: bt swr pinctrl disable failed\n",
+			__func__);
+	}
+
+	if (priv->swr_clk_users > 0) {
+		lpass_bt_swr_mclk_enable(priv, true);
+		ret = msm_cdc_pinctrl_select_active_state(
+					priv->bt_swr_gpio_p);
+		if (ret < 0) {
+			dev_err_ratelimited(priv->dev,
+				"%s: bt swr pinctrl enable failed\n",
+				__func__);
+		}
+	}
+	mutex_unlock(&priv->swr_clk_lock);
+
+	swrm_wcd_notify(priv->swr_ctrl_data->lpass_bt_swr_pdev,
+				 SWR_DEVICE_SSR_UP, NULL);
+
+	return 0;
+}
+
+static const struct snd_event_ops lpass_bt_swr_ssr_ops = {
+	.enable = lpass_bt_swr_ssr_enable,
+	.disable = lpass_bt_swr_ssr_disable,
+};
+
+static int lpass_bt_swr_probe(struct platform_device *pdev)
+{
+	struct lpass_bt_swr_priv *priv;
+	int ret;
+	struct clk *lpass_core_hw_vote = NULL;
+	struct clk *lpass_audio_hw_vote = NULL;
+	struct clk *bt_swr_clk = NULL;
+	struct clk *bt_swr_2x_clk = NULL;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_bt_swr_priv),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	BLOCKING_INIT_NOTIFIER_HEAD(&priv->notifier);
+	priv->dev = &pdev->dev;
+	priv->dev_up = true;
+	priv->core_hw_vote_count = 0;
+	priv->core_audio_vote_count = 0;
+
+	dev_set_drvdata(&pdev->dev, priv);
+	mutex_init(&priv->vote_lock);
+	mutex_init(&priv->swr_clk_lock);
+	mutex_init(&priv->ssr_lock);
+
+	priv->bt_swr_gpio_p = of_parse_phandle(pdev->dev.of_node,
+					"qcom,bt-swr-gpios", 0);
+	if (!priv->bt_swr_gpio_p) {
+		dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n",
+			__func__);
+		return -EINVAL;
+	}
+	if (msm_cdc_pinctrl_get_state(priv->bt_swr_gpio_p) < 0) {
+		dev_info(&pdev->dev, "%s: failed to get swr pin state\n",
+			__func__);
+		return -EPROBE_DEFER;
+	}
+
+	/* Register LPASS core hw vote */
+	lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote");
+	if (IS_ERR(lpass_core_hw_vote)) {
+		ret = PTR_ERR(lpass_core_hw_vote);
+		dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
+			__func__, "lpass_core_hw_vote", ret);
+		lpass_core_hw_vote = NULL;
+		ret = 0;
+	}
+	priv->lpass_core_hw_vote = lpass_core_hw_vote;
+
+	/* Register LPASS audio hw vote */
+	lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote");
+	if (IS_ERR(lpass_audio_hw_vote)) {
+		ret = PTR_ERR(lpass_audio_hw_vote);
+		dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
+			__func__, "lpass_audio_hw_vote", ret);
+		lpass_audio_hw_vote = NULL;
+		ret = 0;
+	}
+	priv->lpass_audio_hw_vote = lpass_audio_hw_vote;
+
+	/* Register bt swr clk vote */
+	bt_swr_clk = devm_clk_get(&pdev->dev, "bt_swr_mclk_clk");
+	if (IS_ERR(bt_swr_clk)) {
+		ret = PTR_ERR(bt_swr_clk);
+		dev_err(&pdev->dev, "%s: clk get %s failed %d\n",
+			__func__, "bt_swr_clk", ret);
+		return -EINVAL;
+	}
+	priv->clk_handle = bt_swr_clk;
+
+	/* Register bt swr 2x clk vote */
+	bt_swr_2x_clk = devm_clk_get(&pdev->dev, "bt_swr_mclk_clk_2x");
+	if (IS_ERR(bt_swr_2x_clk)) {
+		ret = PTR_ERR(bt_swr_2x_clk);
+		dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
+			__func__, "bt_swr_2x_clk", ret);
+		bt_swr_2x_clk = NULL;
+		ret = 0;
+	}
+	priv->clk_handle_2x = bt_swr_2x_clk;
+
+	/* Add soundwire child devices. */
+	INIT_WORK(&priv->lpass_bt_swr_add_child_devices_work,
+		 lpass_bt_swr_add_child_devices);
+
+	priv->swr_plat_data.handle = (void *)priv;
+	priv->swr_plat_data.read = NULL;
+	priv->swr_plat_data.write = NULL;
+	priv->swr_plat_data.bulk_write = NULL;
+	priv->swr_plat_data.clk = lpass_bt_swrm_clock;
+	priv->swr_plat_data.core_vote = lpass_bt_swr_core_vote;
+	priv->swr_plat_data.handle_irq = NULL;
+
+	lpass_bt_priv = priv;
+
+	pm_runtime_set_autosuspend_delay(&pdev->dev, LPASS_BT_SWR_AUTO_SUSPEND_DELAY);
+	pm_runtime_use_autosuspend(&pdev->dev);
+	pm_runtime_set_suspended(&pdev->dev);
+	pm_suspend_ignore_children(&pdev->dev, true);
+	pm_runtime_enable(&pdev->dev);
+
+	/* call scheduler to add child devices. */
+	schedule_work(&priv->lpass_bt_swr_add_child_devices_work);
+
+	priv->initial_boot = true;
+	ret = snd_event_client_register(priv->dev, &lpass_bt_swr_ssr_ops, priv);
+	if (!ret) {
+		snd_event_notify(priv->dev, SND_EVENT_UP);
+		dev_err(&pdev->dev, "%s: Registered SSR ops\n", __func__);
+	} else {
+		dev_err(&pdev->dev,
+			"%s: Registration with SND event FWK failed ret = %d\n",
+			__func__, ret);
+	}
+
+	return 0;
+}
+
+static int lpass_bt_swr_remove(struct platform_device *pdev)
+{
+	struct lpass_bt_swr_priv *priv = dev_get_drvdata(&pdev->dev);
+
+	if (!priv)
+		return -EINVAL;
+
+	pm_runtime_disable(&pdev->dev);
+	pm_runtime_set_suspended(&pdev->dev);
+	of_platform_depopulate(&pdev->dev);
+	mutex_destroy(&priv->vote_lock);
+	mutex_destroy(&priv->swr_clk_lock);
+	mutex_destroy(&priv->ssr_lock);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+int lpass_bt_swr_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct lpass_bt_swr_priv *priv = platform_get_drvdata(pdev);
+	int ret = 0;
+
+	dev_dbg(dev, "%s, enter\n", __func__);
+	mutex_lock(&priv->vote_lock);
+	if (priv->lpass_core_hw_vote == NULL) {
+		dev_dbg(dev, "%s: Invalid lpass core hw node\n", __func__);
+		goto audio_vote;
+	}
+
+	if (priv->core_hw_vote_count == 0) {
+		ret = digital_cdc_rsc_mgr_hw_vote_enable(priv->lpass_core_hw_vote, dev);
+		if (ret < 0) {
+			dev_err_ratelimited(dev, "%s:lpass core hw enable failed\n",
+				__func__);
+			goto audio_vote;
+		}
+	}
+	priv->core_hw_vote_count++;
+
+audio_vote:
+	if (priv->lpass_audio_hw_vote == NULL) {
+		dev_dbg(dev, "%s: Invalid lpass audio hw node\n", __func__);
+		goto done;
+	}
+
+	if (priv->core_audio_vote_count == 0) {
+		ret = digital_cdc_rsc_mgr_hw_vote_enable(priv->lpass_audio_hw_vote, dev);
+		if (ret < 0) {
+			dev_err_ratelimited(dev, "%s:lpass audio hw enable failed\n",
+				__func__);
+			goto done;
+		}
+	}
+	priv->core_audio_vote_count++;
+
+done:
+	mutex_unlock(&priv->vote_lock);
+	dev_dbg(dev, "%s, leave, hw_vote %d, audio_vote %d\n", __func__,
+			priv->core_hw_vote_count, priv->core_audio_vote_count);
+	pm_runtime_set_autosuspend_delay(priv->dev, LPASS_BT_SWR_AUTO_SUSPEND_DELAY);
+
+	return 0;
+}
+
+int lpass_bt_swr_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct lpass_bt_swr_priv *priv = platform_get_drvdata(pdev);
+
+	dev_dbg(dev, "%s, enter\n", __func__);
+	mutex_lock(&priv->vote_lock);
+	if (priv->lpass_core_hw_vote != NULL) {
+		if (--priv->core_hw_vote_count == 0)
+			digital_cdc_rsc_mgr_hw_vote_disable(
+					priv->lpass_core_hw_vote, dev);
+		if (priv->core_hw_vote_count < 0)
+			priv->core_hw_vote_count = 0;
+	} else {
+		dev_dbg(dev, "%s: Invalid lpass core hw node\n",
+			__func__);
+	}
+
+	if (priv->lpass_audio_hw_vote != NULL) {
+		if (--priv->core_audio_vote_count == 0)
+			digital_cdc_rsc_mgr_hw_vote_disable(
+					priv->lpass_audio_hw_vote, dev);
+		if (priv->core_audio_vote_count < 0)
+			priv->core_audio_vote_count = 0;
+	} else {
+		dev_dbg(dev, "%s: Invalid lpass audio hw node\n",
+			__func__);
+	}
+
+	mutex_unlock(&priv->vote_lock);
+	dev_dbg(dev, "%s, leave, hw_vote %d, audio_vote %d\n", __func__,
+		priv->core_hw_vote_count, priv->core_audio_vote_count);
+
+	return 0;
+}
+#endif /* CONFIG_PM */
+
+static const struct of_device_id lpass_bt_swr_dt_match[] = {
+	{.compatible = "qcom,lpass-bt-swr"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, lpass_bt_swr_dt_match);
+
+static const struct dev_pm_ops lpass_bt_swr_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(
+		pm_runtime_force_suspend,
+		pm_runtime_force_resume
+	)
+	SET_RUNTIME_PM_OPS(
+		lpass_bt_swr_runtime_suspend,
+		lpass_bt_swr_runtime_resume,
+		NULL
+	)
+};
+
+static struct platform_driver lpass_bt_swr_drv = {
+	.driver = {
+		.name = "lpass-bt-swr",
+		.pm = &lpass_bt_swr_pm_ops,
+		.of_match_table = lpass_bt_swr_dt_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = lpass_bt_swr_probe,
+	.remove = lpass_bt_swr_remove,
+};
+
+static int lpass_bt_swr_drv_init(void)
+{
+	return platform_driver_register(&lpass_bt_swr_drv);
+}
+
+static void lpass_bt_swr_drv_exit(void)
+{
+	platform_driver_unregister(&lpass_bt_swr_drv);
+}
+
+static int __init lpass_bt_swr_init(void)
+{
+	lpass_bt_swr_drv_init();
+	return 0;
+}
+module_init(lpass_bt_swr_init);
+
+static void __exit lpass_bt_swr_exit(void)
+{
+	lpass_bt_swr_drv_exit();
+}
+module_exit(lpass_bt_swr_exit);
+
+MODULE_SOFTDEP("pre: bt_fm_swr");
+MODULE_DESCRIPTION("LPASS BT SWR driver");
+MODULE_LICENSE("GPL");

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/Kbuild

@@ -0,0 +1,183 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_SM6150), y)
+		include $(AUDIO_ROOT)/config/sm6150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_TRINKET), y)
+		include $(AUDIO_ROOT)/config/sm6150auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/sm6150autoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KONA), y)
+		include $(AUDIO_ROOT)/config/konaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/konaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_WAIPIO), y)
+		include $(AUDIO_ROOT)/config/waipioauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/waipioautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_KALAMA), y)
+		include $(AUDIO_ROOT)/config/kalamaauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/kalamaautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
+		include $(AUDIO_ROOT)/config/pineappleauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_PITTI), y)
+		include $(AUDIO_ROOT)/config/pittiauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pittiautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_LITO), y)
+		include $(AUDIO_ROOT)/config/litoauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/litoautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_BENGAL), y)
+		include $(AUDIO_ROOT)/config/bengalauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/bengalautoconf.h
+	endif
+	ifeq ($(CONFIG_ARCH_QCS405), y)
+		include $(AUDIO_ROOT)/config/qcs405auto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/qcs405autoconf.h
+	endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi/audio
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ LPASS_CDC ############
+
+# for LPASS_CDC Codec
+ifdef CONFIG_SND_SOC_LPASS_CDC
+	LPASS_CDC_OBJS += lpass-cdc.o
+	LPASS_CDC_OBJS += lpass-cdc-comp.o
+	LPASS_CDC_OBJS += lpass-cdc-utils.o
+	LPASS_CDC_OBJS += lpass-cdc-regmap.o
+	LPASS_CDC_OBJS += lpass-cdc-tables.o
+	LPASS_CDC_OBJS += lpass-cdc-clk-rsc.o
+endif
+
+ifdef CONFIG_LPASS_CDC_WSA2_MACRO
+	WSA2_OBJS += lpass-cdc-wsa2-macro.o
+endif
+
+ifdef CONFIG_LPASS_CDC_WSA_MACRO
+	WSA_OBJS += lpass-cdc-wsa-macro.o
+endif
+
+ifdef CONFIG_LPASS_CDC_VA_MACRO
+	VA_OBJS += lpass-cdc-va-macro.o
+endif
+
+ifdef CONFIG_LPASS_CDC_TX_MACRO
+	TX_OBJS += lpass-cdc-tx-macro.o
+endif
+
+ifdef CONFIG_LPASS_CDC_RX_MACRO
+	RX_OBJS += lpass-cdc-rx-macro.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+EXTRA_CFLAGS += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
+endif
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_LPASS_CDC) += lpass_cdc_dlkm.o
+lpass_cdc_dlkm-y := $(LPASS_CDC_OBJS)
+
+obj-$(CONFIG_LPASS_CDC_WSA2_MACRO) += lpass_cdc_wsa2_macro_dlkm.o
+lpass_cdc_wsa2_macro_dlkm-y := $(WSA2_OBJS)
+
+obj-$(CONFIG_LPASS_CDC_WSA_MACRO) += lpass_cdc_wsa_macro_dlkm.o
+lpass_cdc_wsa_macro_dlkm-y := $(WSA_OBJS)
+
+obj-$(CONFIG_LPASS_CDC_VA_MACRO) += lpass_cdc_va_macro_dlkm.o
+lpass_cdc_va_macro_dlkm-y := $(VA_OBJS)
+
+obj-$(CONFIG_LPASS_CDC_TX_MACRO) += lpass_cdc_tx_macro_dlkm.o
+lpass_cdc_tx_macro_dlkm-y := $(TX_OBJS)
+
+obj-$(CONFIG_LPASS_CDC_RX_MACRO) += lpass_cdc_rx_macro_dlkm.o
+lpass_cdc_rx_macro_dlkm-y := $(RX_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/Makefile

@@ -0,0 +1,6 @@
+modules:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/internal.h

@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _LPASS_CDC_INTERNAL_H
+#define _LPASS_CDC_INTERNAL_H
+
+#include "lpass-cdc-registers.h"
+
+#define LPASS_CDC_CHILD_DEVICES_MAX 6
+
+/* from lpass_cdc to WCD events */
+enum {
+	LPASS_CDC_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
+	LPASS_CDC_WCD_EVT_PA_OFF_PRE_SSR,
+	LPASS_CDC_WCD_EVT_SSR_DOWN,
+	LPASS_CDC_WCD_EVT_SSR_UP,
+	LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK,
+	LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK_ADIE_LB,
+	LPASS_CDC_WCD_EVT_CLK_NOTIFY,
+};
+
+enum {
+	REG_NO_ACCESS,
+	RD_REG,
+	WR_REG,
+	RD_WR_REG
+};
+
+/* from WCD to lpass_cdc events */
+enum {
+	WCD_LPASS_CDC_EVT_RX_MUTE = 1, /* for RX mute/unmute */
+	WCD_LPASS_CDC_EVT_IMPED_TRUE,   /* for imped true */
+	WCD_LPASS_CDC_EVT_IMPED_FALSE,  /* for imped false */
+	WCD_LPASS_CDC_EVT_RX_COMPANDER_SOFT_RST,
+	WCD_LPASS_CDC_EVT_BCS_CLK_OFF,
+	WCD_LPASS_CDC_EVT_RX_PA_GAIN_UPDATE,
+	WCD_LPASS_CDC_EVT_HPHL_HD2_ENABLE, /* to enable hd2 config for hphl */
+	WCD_LPASS_CDC_EVT_HPHR_HD2_ENABLE, /* to enable hd2 config for hphr */
+};
+
+struct wcd_ctrl_platform_data {
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				 struct notifier_block *nblock,
+				 bool enable);
+};
+
+struct lpass_cdc_priv {
+	struct device *dev;
+	struct snd_soc_component *component;
+	struct regmap *regmap;
+	struct mutex macro_lock;
+	struct mutex io_lock;
+	struct mutex clk_lock;
+	struct mutex vote_lock;
+	bool va_without_decimation;
+	bool macros_supported[MAX_MACRO];
+	bool dev_up;
+	bool pre_dev_up;
+	bool initial_boot;
+	struct macro_ops macro_params[MAX_MACRO];
+	struct snd_soc_dai_driver *lpass_cdc_dais;
+	u16 num_dais;
+	u16 num_macros_registered;
+	u16 num_macros;
+	u16 current_mclk_mux_macro[MAX_MACRO];
+	struct work_struct lpass_cdc_add_child_devices_work;
+	u32 version;
+	struct clk *lpass_core_hw_vote;
+	struct clk *lpass_audio_hw_vote;
+	int core_hw_vote_count;
+	int core_audio_vote_count;
+	int core_clk_vote_count;
+
+	/* Entry for version info */
+	struct snd_info_entry *entry;
+	struct snd_info_entry *version_entry;
+
+	int (*read_dev)(struct lpass_cdc_priv *priv,
+			u16 macro_id, u16 reg, u8 *val);
+	int (*write_dev)(struct lpass_cdc_priv *priv,
+			 u16 macro_id, u16 reg, u8 val);
+	struct platform_device *pdev_child_devices
+			[LPASS_CDC_CHILD_DEVICES_MAX];
+	u16 child_count;
+	struct wcd_ctrl_platform_data plat_data;
+	struct device *wcd_dev;
+	struct blocking_notifier_head notifier;
+	struct device *clk_dev;
+	rsc_clk_cb_t rsc_clk_cb;
+	s32 dmic_0_1_clk_cnt;
+	s32 dmic_2_3_clk_cnt;
+	s32 dmic_4_5_clk_cnt;
+	s32 dmic_6_7_clk_cnt;
+	u8 dmic_0_1_clk_div;
+	u8 dmic_2_3_clk_div;
+	u8 dmic_4_5_clk_div;
+	u8 dmic_6_7_clk_div;
+};
+
+struct regmap *lpass_cdc_regmap_init(struct device *dev,
+				  const struct regmap_config *config);
+int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg);
+
+extern const struct regmap_config lpass_cdc_regmap_config;
+extern u8 *lpass_cdc_reg_access[MAX_MACRO];
+extern const u16 macro_id_base_offset[MAX_MACRO];
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c

@@ -0,0 +1,785 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include "lpass-cdc.h"
+#include "lpass-cdc-clk-rsc.h"
+
+#define DRV_NAME "lpass-cdc-clk-rsc"
+#define LPASS_CDC_CLK_NAME_LENGTH 30
+#define NPL_CLK_OFFSET (TX_NPL_CLK  - TX_CORE_CLK)
+
+static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = {
+	"tx_core_clk",
+	"rx_core_clk",
+	"wsa_core_clk",
+	"va_core_clk",
+	"wsa2_core_clk",
+	"rx_tx_core_clk",
+	"wsa_tx_core_clk",
+	"wsa2_tx_core_clk",
+	"tx_npl_clk",
+	"rx_npl_clk",
+	"wsa_npl_clk",
+	"va_npl_clk",
+};
+
+struct lpass_cdc_clk_rsc {
+	struct device *dev;
+	struct mutex rsc_clk_lock;
+	struct mutex fs_gen_lock;
+	struct clk *clk[MAX_CLK];
+	int clk_cnt[MAX_CLK];
+	int reg_seq_en_cnt;
+	int va_tx_clk_cnt;
+	bool dev_up;
+	bool dev_up_gfmux;
+	u32 num_fs_reg;
+	u32 *fs_gen_seq;
+	int default_clk_id[MAX_CLK];
+	struct regmap *regmap;
+	char __iomem *rx_clk_muxsel;
+	char __iomem *wsa_clk_muxsel;
+	char __iomem *va_clk_muxsel;
+};
+
+static int lpass_cdc_clk_rsc_cb(struct device *dev, u16 event)
+{
+	struct lpass_cdc_clk_rsc *priv;
+
+	if (!dev) {
+		pr_err("%s: Invalid device pointer\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	priv = dev_get_drvdata(dev);
+	if (!priv) {
+		pr_err("%s: Invalid clk rsc priviate data\n",
+				__func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&priv->rsc_clk_lock);
+	if (event == LPASS_CDC_MACRO_EVT_SSR_UP) {
+		priv->dev_up = true;
+	} else if (event == LPASS_CDC_MACRO_EVT_SSR_DOWN) {
+		priv->dev_up = false;
+		priv->dev_up_gfmux = false;
+	} else if (event == LPASS_CDC_MACRO_EVT_SSR_GFMUX_UP) {
+		priv->dev_up_gfmux = true;
+	}
+	mutex_unlock(&priv->rsc_clk_lock);
+
+	return 0;
+}
+
+static char __iomem *lpass_cdc_clk_rsc_get_clk_muxsel(struct lpass_cdc_clk_rsc *priv,
+						 int clk_id)
+{
+	switch (clk_id) {
+	case RX_CORE_CLK:
+		return priv->rx_clk_muxsel;
+	case WSA_CORE_CLK:
+	case WSA2_CORE_CLK:
+		return priv->wsa_clk_muxsel;
+	case VA_CORE_CLK:
+		return priv->va_clk_muxsel;
+	case TX_CORE_CLK:
+	case RX_TX_CORE_CLK:
+	case WSA_TX_CORE_CLK:
+	case WSA2_TX_CORE_CLK:
+	default:
+		dev_err_ratelimited(priv->dev, "%s: Invalid case\n", __func__);
+		break;
+	}
+
+	return NULL;
+}
+
+int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
+{
+	struct device *clk_dev = NULL;
+	struct lpass_cdc_clk_rsc *priv = NULL;
+	int count = 0;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_BOLERO_VER_2P1
+	if (clk_id < 0 || clk_id >= MAX_CLK - NPL_CLK_OFFSET) {
+#else
+	if (clk_id < 0 || clk_id >= MAX_CLK) {
+#endif
+		pr_err("%s: Invalid clk_id: %d\n",
+			__func__, clk_id);
+		return -EINVAL;
+	}
+
+	clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return -EINVAL;
+	}
+
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk priviate data\n", __func__);
+		return -EINVAL;
+	}
+	mutex_lock(&priv->rsc_clk_lock);
+	while (__clk_is_enabled(priv->clk[clk_id])) {
+#ifdef CONFIG_BOLERO_VER_2P1
+		clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
+#endif
+		clk_disable_unprepare(priv->clk[clk_id]);
+		count++;
+	}
+	dev_dbg(priv->dev,
+		"%s: clock reset after ssr, count %d\n", __func__, count);
+
+	while (count--) {
+		clk_prepare_enable(priv->clk[clk_id]);
+#ifdef CONFIG_BOLERO_VER_2P1
+		clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]);
+#endif
+	}
+	mutex_unlock(&priv->rsc_clk_lock);
+	return 0;
+}
+EXPORT_SYMBOL(lpass_cdc_rsc_clk_reset);
+
+void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev, bool enable)
+{
+	struct device *clk_dev = NULL;
+	struct lpass_cdc_clk_rsc *priv = NULL;
+	int i = 0;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return;
+	}
+
+	clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return;
+	}
+
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk private data\n", __func__);
+		return;
+	}
+	mutex_lock(&priv->rsc_clk_lock);
+#ifdef CONFIG_BOLERO_VER_2P1
+	for (i = 0; i < MAX_CLK - NPL_CLK_OFFSET; i++) {
+#else
+	for (i = 0; i < MAX_CLK; i++) {
+#endif
+		if (enable) {
+			if (priv->clk[i])
+				clk_prepare_enable(priv->clk[i]);
+#ifdef CONFIG_BOLERO_VER_2P1
+			if (priv->clk[i + NPL_CLK_OFFSET])
+				clk_prepare_enable(
+					priv->clk[i + NPL_CLK_OFFSET]);
+#endif
+		} else {
+#ifdef CONFIG_BOLERO_VER_2P1
+			if (priv->clk[i + NPL_CLK_OFFSET] &&
+					__clk_is_enabled(priv->clk[i + NPL_CLK_OFFSET]))
+				clk_disable_unprepare(
+					priv->clk[i + NPL_CLK_OFFSET]);
+#endif
+			if (priv->clk[i] && __clk_is_enabled(priv->clk[i]))
+				clk_disable_unprepare(priv->clk[i]);
+		}
+	}
+	mutex_unlock(&priv->rsc_clk_lock);
+	return;
+}
+EXPORT_SYMBOL(lpass_cdc_clk_rsc_enable_all_clocks);
+
+static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
+					   int clk_id,
+					   bool enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		/* Enable Requested Core clk */
+		if (priv->clk_cnt[clk_id] == 0) {
+			ret = clk_prepare_enable(priv->clk[clk_id]);
+			if (ret < 0) {
+				dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+							__func__, clk_id);
+				goto done;
+			}
+#ifdef CONFIG_BOLERO_VER_2P1
+			if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
+				ret = clk_prepare_enable(
+						priv->clk[clk_id + NPL_CLK_OFFSET]);
+				if (ret < 0) {
+					dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+							__func__, clk_id + NPL_CLK_OFFSET);
+					goto err;
+				}
+			}
+#endif
+		}
+		priv->clk_cnt[clk_id]++;
+	} else {
+		if (priv->clk_cnt[clk_id] <= 0) {
+			dev_err_ratelimited(priv->dev, "%s: clk_id: %d is already disabled\n",
+					__func__, clk_id);
+			priv->clk_cnt[clk_id] = 0;
+			goto done;
+		}
+		priv->clk_cnt[clk_id]--;
+		if (priv->clk_cnt[clk_id] == 0) {
+#ifdef CONFIG_BOLERO_VER_2P1
+			if (priv->clk[clk_id + NPL_CLK_OFFSET])
+				clk_disable_unprepare(
+						priv->clk[clk_id + NPL_CLK_OFFSET]);
+#endif
+			clk_disable_unprepare(priv->clk[clk_id]);
+		}
+	}
+return ret;
+#ifdef CONFIG_BOLERO_VER_2P1
+err:
+	clk_disable_unprepare(priv->clk[clk_id]);
+#endif
+done:
+	return ret;
+}
+
+static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
+					   int clk_id,
+					   bool enable)
+{
+	char __iomem *clk_muxsel = NULL;
+	int ret = 0;
+	int default_clk_id = priv->default_clk_id[clk_id];
+	u32 muxsel = 0;
+
+	clk_muxsel = lpass_cdc_clk_rsc_get_clk_muxsel(priv, clk_id);
+	if (!clk_muxsel) {
+		ret = -EINVAL;
+		goto done;
+	}
+
+	if (enable) {
+		if (priv->clk_cnt[clk_id] == 0) {
+			if (clk_id != VA_CORE_CLK) {
+				ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
+							default_clk_id,
+							true);
+				if (ret < 0)
+					goto done;
+			}
+
+			ret = clk_prepare_enable(priv->clk[clk_id]);
+			if (ret < 0) {
+				dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+					__func__, clk_id);
+				goto err_clk;
+			}
+#ifdef CONFIG_BOLERO_VER_2P1
+			if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
+				ret = clk_prepare_enable(
+						priv->clk[clk_id + NPL_CLK_OFFSET]);
+				if (ret < 0) {
+					dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
+							__func__, clk_id + NPL_CLK_OFFSET);
+					goto err_npl_clk;
+				}
+			}
+#endif
+			/*
+			 * Temp SW workaround to address a glitch issue of
+			 * VA GFMux instance responsible for switching from
+			 * TX MCLK to VA MCLK. This configuration would be taken
+			 * care in DSP itself
+			 */
+			if (clk_id != VA_CORE_CLK) {
+				if (priv->dev_up_gfmux) {
+					iowrite32(0x1, clk_muxsel);
+					muxsel = ioread32(clk_muxsel);
+				}
+				lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
+							   false);
+			}
+		}
+		priv->clk_cnt[clk_id]++;
+	} else {
+		if (priv->clk_cnt[clk_id] <= 0) {
+			dev_err_ratelimited(priv->dev, "%s: clk_id: %d is already disabled\n",
+				__func__, clk_id);
+			priv->clk_cnt[clk_id] = 0;
+			goto done;
+		}
+		priv->clk_cnt[clk_id]--;
+		if (priv->clk_cnt[clk_id] == 0) {
+			/*
+			 * Temp SW workaround to address a glitch issue
+			 * of VA GFMux instance responsible for
+			 * switching from TX MCLK to VA MCLK.
+			 * This configuration would be taken
+			 * care in DSP itself.
+			 */
+			if (clk_id != VA_CORE_CLK) {
+				ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
+						default_clk_id, true);
+				if (!ret && priv->dev_up_gfmux) {
+					iowrite32(0x0, clk_muxsel);
+					muxsel = ioread32(clk_muxsel);
+				}
+			}
+#ifdef CONFIG_BOLERO_VER_2P1
+			if (priv->clk[clk_id + NPL_CLK_OFFSET])
+				clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
+#endif
+			clk_disable_unprepare(priv->clk[clk_id]);
+			if (clk_id != VA_CORE_CLK && !ret)
+				lpass_cdc_clk_rsc_mux0_clk_request(priv,
+						default_clk_id, false);
+		}
+	}
+	return ret;
+#ifdef CONFIG_BOLERO_VER_2P1
+err_npl_clk:
+	clk_disable_unprepare(priv->clk[clk_id]);
+#endif
+err_clk:
+	if (clk_id != VA_CORE_CLK)
+		lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
+done:
+	return ret;
+}
+
+static int lpass_cdc_clk_rsc_check_and_update_va_clk(struct lpass_cdc_clk_rsc *priv,
+						  bool mux_switch,
+						  int clk_id,
+						  bool enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		if (clk_id == VA_CORE_CLK && mux_switch) {
+			/*
+			 * Handle the following usecase scenarios during enable
+			 * 1. VA only, Active clk is VA_CORE_CLK
+			 * 2. record -> record + VA, Active clk is TX_CORE_CLK
+			 */
+			if (priv->clk_cnt[TX_CORE_CLK] == 0) {
+				ret = lpass_cdc_clk_rsc_mux1_clk_request(priv,
+							 VA_CORE_CLK, enable);
+				if (ret < 0)
+					goto err;
+			} else {
+				ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, enable);
+				if (ret < 0)
+					goto err;
+				priv->va_tx_clk_cnt++;
+			}
+		} else if ((priv->clk_cnt[TX_CORE_CLK] > 0) &&
+			   (priv->clk_cnt[VA_CORE_CLK] > 0)) {
+			/*
+			 * Handle following concurrency scenario during enable
+			 * 1. VA-> Record+VA, Increment TX CLK and Disable VA
+			 * 2. VA-> Playback+VA, Increment TX CLK and Disable VA
+			 */
+			while (priv->clk_cnt[VA_CORE_CLK] > 0) {
+				ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, true);
+				if (ret < 0)
+					goto err;
+
+				lpass_cdc_clk_rsc_mux1_clk_request(priv,
+							VA_CORE_CLK, false);
+				priv->va_tx_clk_cnt++;
+			}
+		}
+	} else {
+		if (clk_id == VA_CORE_CLK && mux_switch) {
+			/*
+			 * Handle the following usecase scenarios during disable
+			 * 1. VA only, disable VA_CORE_CLK
+			 * 2. Record + VA -> Record, decrement TX CLK count
+			 */
+			if (priv->clk_cnt[VA_CORE_CLK]) {
+				lpass_cdc_clk_rsc_mux1_clk_request(priv,
+							VA_CORE_CLK, enable);
+			} else if (priv->va_tx_clk_cnt) {
+				lpass_cdc_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, enable);
+				priv->va_tx_clk_cnt--;
+			}
+		} else if (priv->va_tx_clk_cnt == priv->clk_cnt[TX_CORE_CLK]) {
+			/*
+			 * Handle the following usecase scenarios during disable
+			 * Record+VA-> VA: enable VA CLK, decrement TX CLK count
+			 */
+			while (priv->va_tx_clk_cnt) {
+				ret = lpass_cdc_clk_rsc_mux1_clk_request(priv,
+							VA_CORE_CLK, true);
+				if (ret < 0)
+					goto err;
+
+				lpass_cdc_clk_rsc_mux0_clk_request(priv,
+							TX_CORE_CLK, false);
+				priv->va_tx_clk_cnt--;
+			}
+		}
+	}
+
+err:
+	return ret;
+}
+
+/**
+ * lpass_cdc_clk_rsc_fs_gen_request - request to enable/disable fs generation
+ * sequence
+ *
+ * @dev: Macro device pointer
+ * @enable: enable or disable flag
+ */
+void lpass_cdc_clk_rsc_fs_gen_request(struct device *dev, bool enable)
+{
+	int i;
+	struct regmap *regmap;
+	struct device *clk_dev = NULL;
+	struct lpass_cdc_clk_rsc *priv = NULL;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return;
+	}
+	clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return;
+	}
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk priviate data\n", __func__);
+		return;
+	}
+	regmap = dev_get_regmap(priv->dev->parent, NULL);
+	if (!regmap) {
+		pr_err("%s: regmap is null\n", __func__);
+		return;
+	}
+	mutex_lock(&priv->fs_gen_lock);
+	if (enable) {
+		if (priv->reg_seq_en_cnt++ == 0) {
+			for (i = 0; i < (priv->num_fs_reg * 3); i += 3) {
+				dev_dbg(priv->dev, "%s: Register: %d, mask: %d, value: %d\n",
+					__func__, priv->fs_gen_seq[i],
+					priv->fs_gen_seq[i + 1],
+					priv->fs_gen_seq[i + 2]);
+				regmap_update_bits(regmap,
+						   priv->fs_gen_seq[i],
+						   priv->fs_gen_seq[i + 1],
+						   priv->fs_gen_seq[i + 2]);
+			}
+		}
+	} else {
+		if (priv->reg_seq_en_cnt <= 0) {
+			dev_err_ratelimited(priv->dev, "%s: req_seq_cnt: %d is already disabled\n",
+				__func__, priv->reg_seq_en_cnt);
+			priv->reg_seq_en_cnt = 0;
+			mutex_unlock(&priv->fs_gen_lock);
+			return;
+		}
+		if (--priv->reg_seq_en_cnt == 0) {
+			for (i = ((priv->num_fs_reg - 1) * 3); i >= 0; i -= 3) {
+				dev_dbg(priv->dev, "%s: Register: %d, mask: %d\n",
+					__func__, priv->fs_gen_seq[i],
+					priv->fs_gen_seq[i + 1]);
+				regmap_update_bits(regmap, priv->fs_gen_seq[i],
+						priv->fs_gen_seq[i + 1], 0x0);
+			}
+		}
+	}
+	mutex_unlock(&priv->fs_gen_lock);
+}
+EXPORT_SYMBOL(lpass_cdc_clk_rsc_fs_gen_request);
+
+/**
+ * lpass_cdc_clk_rsc_request_clock - request for clock to
+ * enable/disable
+ *
+ * @dev: Macro device pointer.
+ * @default_clk_id: mux0 Core clock ID input.
+ * @clk_id_req: Core clock ID requested to enable/disable
+ * @enable: enable or disable clock flag
+ *
+ * Returns 0 on success or -EINVAL on error.
+ */
+int lpass_cdc_clk_rsc_request_clock(struct device *dev,
+				int default_clk_id,
+				int clk_id_req,
+				bool enable)
+{
+	int ret = 0;
+	struct device *clk_dev = NULL;
+	struct lpass_cdc_clk_rsc *priv = NULL;
+	bool mux_switch = false;
+
+	if (!dev) {
+		pr_err("%s: dev is null\n", __func__);
+		return -EINVAL;
+	}
+	if ((clk_id_req < 0 || clk_id_req >= MAX_CLK) &&
+		(default_clk_id < 0 || default_clk_id >= MAX_CLK)) {
+		pr_err("%s: Invalid clk_id_req: %d or default_clk_id: %d\n",
+				__func__, clk_id_req, default_clk_id);
+		return -EINVAL;
+	}
+	clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
+	if (!clk_dev) {
+		pr_err("%s: Invalid rsc clk device\n", __func__);
+		return -EINVAL;
+	}
+	priv = dev_get_drvdata(clk_dev);
+	if (!priv) {
+		pr_err("%s: Invalid rsc clk priviate data\n", __func__);
+		return -EINVAL;
+	}
+
+	mutex_lock(&priv->rsc_clk_lock);
+	if (!priv->dev_up && enable) {
+		dev_err_ratelimited(priv->dev, "%s: SSR is in progress..\n",
+				__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	priv->default_clk_id[clk_id_req] = default_clk_id;
+	if (default_clk_id != clk_id_req)
+		mux_switch = true;
+
+	if (mux_switch) {
+		if (clk_id_req != VA_CORE_CLK) {
+			ret = lpass_cdc_clk_rsc_mux1_clk_request(priv, clk_id_req,
+							enable);
+			if (ret < 0)
+				goto err;
+		}
+	} else {
+		ret = lpass_cdc_clk_rsc_mux0_clk_request(priv, clk_id_req, enable);
+		if (ret < 0)
+			goto err;
+	}
+
+	ret = lpass_cdc_clk_rsc_check_and_update_va_clk(priv, mux_switch,
+						 clk_id_req,
+						 enable);
+	if (ret < 0)
+		goto err;
+
+	dev_dbg(priv->dev, "%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
+		__func__,  priv->clk_cnt[clk_id_req], clk_id_req,
+		enable);
+
+	mutex_unlock(&priv->rsc_clk_lock);
+
+	return 0;
+
+err:
+	mutex_unlock(&priv->rsc_clk_lock);
+	return ret;
+}
+EXPORT_SYMBOL(lpass_cdc_clk_rsc_request_clock);
+
+
+static int lpass_cdc_clk_rsc_probe(struct platform_device *pdev)
+{
+	int ret = 0, fs_gen_size, i, j;
+	const char **clk_name_array;
+	int clk_cnt;
+	struct clk *clk;
+	struct lpass_cdc_clk_rsc *priv = NULL;
+	u32 muxsel = 0;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_clk_rsc),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	/* Get clk fs gen sequence from device tree */
+	if (!of_find_property(pdev->dev.of_node, "qcom,fs-gen-sequence",
+						  &fs_gen_size)) {
+		dev_err(&pdev->dev, "%s: unable to find qcom,fs-gen-sequence property\n",
+			__func__);
+		ret = -EINVAL;
+		goto err;
+	}
+	priv->num_fs_reg = fs_gen_size/(3 * sizeof(u32));
+	priv->fs_gen_seq = devm_kzalloc(&pdev->dev, fs_gen_size, GFP_KERNEL);
+	if (!priv->fs_gen_seq) {
+		ret = -ENOMEM;
+		goto err;
+	}
+	dev_dbg(&pdev->dev, "%s: num_fs_reg %d\n", __func__, priv->num_fs_reg);
+	/* Parse fs-gen-sequence */
+	ret = of_property_read_u32_array(pdev->dev.of_node,
+					 "qcom,fs-gen-sequence",
+					 priv->fs_gen_seq,
+					 priv->num_fs_reg * 3);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "%s: unable to parse fs-gen-sequence, ret = %d\n",
+			__func__, ret);
+		goto err;
+	}
+
+	/* Get clk details from device tree */
+	clk_cnt = of_property_count_strings(pdev->dev.of_node, "clock-names");
+	if (clk_cnt <= 0 || clk_cnt > MAX_CLK) {
+		dev_err(&pdev->dev, "%s: Invalid number of clocks %d",
+				__func__, clk_cnt);
+		ret = -EINVAL;
+		goto err;
+	}
+	clk_name_array = devm_kzalloc(&pdev->dev, clk_cnt * sizeof(char *),
+					  GFP_KERNEL);
+	if (!clk_name_array) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	ret = of_property_read_string_array(pdev->dev.of_node, "clock-names",
+					clk_name_array, clk_cnt);
+
+	for (i = 0; i < MAX_CLK; i++) {
+		priv->clk[i] = NULL;
+		for (j = 0; j < clk_cnt; j++) {
+			if (!strcmp(clk_src_name[i], clk_name_array[j])) {
+				clk = devm_clk_get(&pdev->dev, clk_src_name[i]);
+				if (IS_ERR(clk)) {
+					ret = PTR_ERR(clk);
+					dev_err(&pdev->dev, "%s: clk get failed for %s with ret %d\n",
+						__func__, clk_src_name[i], ret);
+					goto err;
+				}
+				priv->clk[i] = clk;
+				dev_dbg(&pdev->dev, "%s: clk get success for clk name %s\n",
+						__func__, clk_src_name[i]);
+				break;
+			}
+		}
+	}
+	ret = of_property_read_u32(pdev->dev.of_node,
+				 "qcom,rx_mclk_mode_muxsel", &muxsel);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: could not find qcom,rx_mclk_mode_muxsel entry in dt\n",
+			__func__);
+	} else {
+		priv->rx_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
+		if (!priv->rx_clk_muxsel) {
+			dev_err(&pdev->dev, "%s: ioremap failed for rx muxsel\n",
+				__func__);
+			return -ENOMEM;
+		}
+	}
+	ret = of_property_read_u32(pdev->dev.of_node,
+				"qcom,wsa_mclk_mode_muxsel", &muxsel);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: could not find qcom,wsa_mclk_mode_muxsel entry in dt\n",
+			__func__);
+	} else {
+		priv->wsa_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
+		if (!priv->wsa_clk_muxsel) {
+			dev_err(&pdev->dev, "%s: ioremap failed for wsa muxsel\n",
+				__func__);
+			return -ENOMEM;
+		}
+	}
+	ret = of_property_read_u32(pdev->dev.of_node,
+				 "qcom,va_mclk_mode_muxsel", &muxsel);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: could not find qcom,va_mclk_mode_muxsel entry in dt\n",
+			__func__);
+	} else {
+		priv->va_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
+		if (!priv->va_clk_muxsel) {
+			dev_err(&pdev->dev, "%s: ioremap failed for va muxsel\n",
+				__func__);
+			return -ENOMEM;
+		}
+	}
+
+	ret = lpass_cdc_register_res_clk(&pdev->dev, lpass_cdc_clk_rsc_cb);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "%s: Failed to register cb %d",
+				__func__, ret);
+		goto err;
+	}
+	priv->dev = &pdev->dev;
+	priv->dev_up = true;
+	priv->dev_up_gfmux = true;
+	mutex_init(&priv->rsc_clk_lock);
+	mutex_init(&priv->fs_gen_lock);
+	dev_set_drvdata(&pdev->dev, priv);
+
+err:
+	return ret;
+}
+
+static int lpass_cdc_clk_rsc_remove(struct platform_device *pdev)
+{
+	struct lpass_cdc_clk_rsc *priv = dev_get_drvdata(&pdev->dev);
+
+	lpass_cdc_unregister_res_clk(&pdev->dev);
+	of_platform_depopulate(&pdev->dev);
+	if (!priv)
+		return -EINVAL;
+	mutex_destroy(&priv->rsc_clk_lock);
+	mutex_destroy(&priv->fs_gen_lock);
+
+	return 0;
+}
+
+static const struct of_device_id lpass_cdc_clk_rsc_dt_match[] = {
+	{.compatible = "qcom,lpass-cdc-clk-rsc-mngr"},
+	{}
+};
+MODULE_DEVICE_TABLE(of, lpass_cdc_clk_rsc_dt_match);
+
+static struct platform_driver lpass_cdc_clk_rsc_mgr = {
+	.driver = {
+		.name = "lpass-cdc-clk-rsc-mngr",
+		.owner = THIS_MODULE,
+		.of_match_table = lpass_cdc_clk_rsc_dt_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = lpass_cdc_clk_rsc_probe,
+	.remove = lpass_cdc_clk_rsc_remove,
+};
+
+int lpass_cdc_clk_rsc_mgr_init(void)
+{
+	return platform_driver_register(&lpass_cdc_clk_rsc_mgr);
+}
+
+void lpass_cdc_clk_rsc_mgr_exit(void)
+{
+	platform_driver_unregister(&lpass_cdc_clk_rsc_mgr);
+}
+MODULE_DESCRIPTION("LPASS codec clock resource manager driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.h

@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef LPASS_CDC_CLK_RSC_H
+#define LPASS_CDC_CLK_RSC_H
+
+#include <linux/regmap.h>
+#include <bindings/qcom,lpass-cdc-clk-rsc.h>
+
+#if IS_ENABLED(CONFIG_SND_SOC_LPASS_CDC)
+int lpass_cdc_clk_rsc_mgr_init(void);
+void lpass_cdc_clk_rsc_mgr_exit(void);
+void lpass_cdc_clk_rsc_fs_gen_request(struct device *dev,
+						bool enable);
+int lpass_cdc_clk_rsc_request_clock(struct device *dev,
+				int default_clk_id,
+				int clk_id_req,
+				bool enable);
+int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id);
+void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev, bool enable);
+#else
+static inline void lpass_cdc_clk_rsc_fs_gen_request(struct device *dev,
+						bool enable)
+{
+}
+static inline int lpass_cdc_clk_rsc_mgr_init(void)
+{
+	return 0;
+}
+static inline void lpass_cdc_clk_rsc_mgr_exit(void)
+{
+}
+static inline int lpass_cdc_clk_rsc_request_clock(struct device *dev,
+				int default_clk_id,
+				int clk_id_req,
+				bool enable)
+{
+	return 0;
+}
+static inline int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
+{
+	return 0;
+}
+static inline void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev,
+						    bool enable)
+{
+	return;
+}
+#endif /* CONFIG_SND_SOC_LPASS_CDC */
+#endif /* LPASS_CDC_CLK_RSC_H */

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc-comp.c

@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+#include "lpass-cdc-comp.h"
+
+int lpass_cdc_load_compander_coeff(struct snd_soc_component *component,
+				   u16 lsb_reg, u16 msb_reg,
+				   struct comp_coeff_val *comp_coeff_table,
+				   u16 arr_size)
+{
+	int i = 0;
+
+	/* Load Compander Coeff */
+	for (i = 0; i < arr_size; i++) {
+		snd_soc_component_write(component, lsb_reg,
+				comp_coeff_table[i].lsb);
+		snd_soc_component_write(component, msb_reg,
+				comp_coeff_table[i].msb);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(lpass_cdc_load_compander_coeff);
+
+int lpass_cdc_update_compander_setting(struct snd_soc_component *component,
+				u16 start_addr,
+				struct lpass_cdc_comp_setting *comp_setting)
+{
+	int zone2_rms, zone3_rms, zone4_rms, zone5_rms, zone6_rms;
+	int path_gain;
+	int max_attn;
+	int zone1_rms = 6;
+	int upper_gain_int = comp_setting->upper_gain_int;
+	int lower_gain_int = comp_setting->lower_gain_int;
+	int ana_addr_map = comp_setting->ana_addr_map;
+	int upper_gain_dig_int = upper_gain_int - lower_gain_int;
+
+	/* skip comp_ctl8, comp_ctl9 default settings is fine */
+
+	/* apply zone settings */
+	snd_soc_component_write(component,
+				start_addr + 8,
+				zone1_rms);
+
+	if (upper_gain_dig_int >= 24)
+		zone2_rms = 18;
+	else if (upper_gain_dig_int >= 18)
+		zone2_rms = 12;
+	else
+		zone2_rms = upper_gain_dig_int;
+	snd_soc_component_write(component,
+				start_addr + 0xC,
+				zone2_rms);
+
+	if (upper_gain_dig_int >= 66)
+		zone3_rms = 33;
+	else if (upper_gain_dig_int >= 36)
+		zone3_rms = 30;
+	else if (upper_gain_dig_int >= 30)
+		zone3_rms = 24;
+	else
+		zone3_rms = upper_gain_dig_int;
+	snd_soc_component_write(component,
+				start_addr + 0x10,
+				zone3_rms);
+
+	if (upper_gain_dig_int >= 66)
+		zone4_rms = 48;
+	else if (upper_gain_dig_int >= 48)
+		zone4_rms = 42;
+	else if (upper_gain_dig_int >= 42)
+		zone4_rms = 36;
+	else
+		zone4_rms = upper_gain_dig_int;
+	snd_soc_component_write(component,
+				start_addr + 0x14,
+				zone4_rms);
+
+	if (upper_gain_dig_int >= 69)
+		zone5_rms = 63;
+	else if (upper_gain_dig_int >= 66)
+		zone5_rms = 60;
+	else if (upper_gain_dig_int >= 60)
+		zone5_rms = 54;
+	else if (upper_gain_dig_int >= 54)
+		zone5_rms = 48;
+	else
+		zone5_rms = upper_gain_dig_int;
+	snd_soc_component_write(component,
+				start_addr + 0x18,
+				zone5_rms);
+
+	zone6_rms = upper_gain_dig_int;
+	snd_soc_component_write(component,
+				start_addr + 0x1C,
+				zone6_rms);
+
+	if (lower_gain_int < 0)
+		max_attn = 256 + lower_gain_int;
+	else
+		max_attn = lower_gain_int;
+	snd_soc_component_write(component,
+				start_addr + 0x20,
+				max_attn);
+
+	path_gain = zone6_rms - abs(lower_gain_int);
+	snd_soc_component_write(component,
+				start_addr + 0x24,
+				path_gain);
+
+	snd_soc_component_write(component,
+				start_addr + 0x28,
+				ana_addr_map);
+
+	return 0;
+}
+EXPORT_SYMBOL(lpass_cdc_update_compander_setting);

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc-comp.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+#ifndef LPASS_CDC_COMP_H
+#define LPASS_CDC_COMP_H
+
+#include <sound/soc.h>
+
+struct comp_coeff_val {
+	u8 lsb;
+	u8 msb;
+};
+
+struct lpass_cdc_comp_setting {
+	int upper_gain_int;
+	int lower_gain_int;
+	int ana_addr_map;
+};
+
+int lpass_cdc_load_compander_coeff(struct snd_soc_component *component,
+				   u16 lsb_reg, u16 msb_reg,
+				   struct comp_coeff_val *comp_coeff_table,
+				   u16 arr_size);
+int lpass_cdc_update_compander_setting(struct snd_soc_component *component,
+				u16 start_addr,
+				struct lpass_cdc_comp_setting *comp_setting);
+#endif

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc-utils.c

@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/regmap.h>
+#include "lpass-cdc.h"
+#include "internal.h"
+
+#define REG_BYTES 2
+#define VAL_BYTES 1
+
+const u16 macro_id_base_offset[MAX_MACRO] = {
+	TX_START_OFFSET,
+	RX_START_OFFSET,
+	WSA_START_OFFSET,
+	VA_START_OFFSET,
+	WSA2_START_OFFSET,
+};
+
+int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg)
+{
+	if (reg >= TX_START_OFFSET
+		&& reg <= TX_MAX_OFFSET)
+		return TX_MACRO;
+	if (reg >= RX_START_OFFSET
+		&& reg <= RX_MAX_OFFSET)
+		return RX_MACRO;
+	if (reg >= WSA_START_OFFSET
+		&& reg <= WSA_MAX_OFFSET)
+		return WSA_MACRO;
+	if (reg >= WSA2_START_OFFSET
+		&& reg <= WSA2_MAX_OFFSET)
+		return WSA2_MACRO;
+	if (reg >= VA_START_OFFSET &&
+		reg <= VA_MAX_OFFSET)
+		return VA_MACRO;
+
+	return -EINVAL;
+}
+
+static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
+			   void *val, size_t val_size)
+{
+	struct device *dev = context;
+	struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
+	u16 *reg_p;
+	u16 __reg;
+	int macro_id, i;
+	u8 temp = 0;
+	int ret = -EINVAL;
+
+	if (!priv) {
+		dev_err_ratelimited(dev, "%s: priv is NULL\n", __func__);
+		return ret;
+	}
+	if (!reg || !val) {
+		dev_err_ratelimited(dev, "%s: reg or val is NULL\n", __func__);
+		return ret;
+	}
+	if (reg_size != REG_BYTES) {
+		dev_err_ratelimited(dev, "%s: register size %zd bytes, not supported\n",
+			__func__, reg_size);
+		return ret;
+	}
+
+	reg_p = (u16 *)reg;
+	macro_id = lpass_cdc_get_macro_id(priv->va_without_decimation,
+					   reg_p[0]);
+	if (macro_id < 0 || !priv->macros_supported[macro_id])
+		return 0;
+
+	mutex_lock(&priv->io_lock);
+	for (i = 0; i < val_size; i++) {
+		__reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id];
+		ret = priv->read_dev(priv, macro_id, __reg, &temp);
+		if (ret < 0) {
+			dev_err_ratelimited(dev,
+			"%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
+			__func__, ret, reg_p[0] + i * 4, val_size);
+			break;
+		}
+		((u8 *)val)[i] = temp;
+		dev_dbg(dev, "%s: Read 0x%02x from reg 0x%x\n",
+			__func__, temp, reg_p[0] + i * 4);
+	}
+	mutex_unlock(&priv->io_lock);
+
+	return ret;
+}
+
+static int regmap_bus_gather_write(void *context,
+				   const void *reg, size_t reg_size,
+				   const void *val, size_t val_size)
+{
+	struct device *dev = context;
+	struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
+	u16 *reg_p;
+	u16 __reg;
+	int macro_id, i;
+	int ret = -EINVAL;
+
+	if (!priv) {
+		dev_err_ratelimited(dev, "%s: priv is NULL\n", __func__);
+		return ret;
+	}
+	if (!reg || !val) {
+		dev_err_ratelimited(dev, "%s: reg or val is NULL\n", __func__);
+		return ret;
+	}
+	if (reg_size != REG_BYTES) {
+		dev_err_ratelimited(dev, "%s: register size %zd bytes, not supported\n",
+			__func__, reg_size);
+		return ret;
+	}
+
+	reg_p = (u16 *)reg;
+	macro_id = lpass_cdc_get_macro_id(priv->va_without_decimation,
+					reg_p[0]);
+	if (macro_id < 0 || !priv->macros_supported[macro_id])
+		return 0;
+
+	mutex_lock(&priv->io_lock);
+	for (i = 0; i < val_size; i++) {
+		__reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id];
+		ret = priv->write_dev(priv, macro_id, __reg, ((u8 *)val)[i]);
+		if (ret < 0) {
+			dev_err_ratelimited(dev,
+			"%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
+			__func__, ret, reg_p[0] + i * 4, val_size);
+			break;
+		}
+		dev_dbg(dev, "Write %02x to reg 0x%x\n", ((u8 *)val)[i],
+			reg_p[0] + i * 4);
+	}
+	mutex_unlock(&priv->io_lock);
+	return ret;
+}
+
+static int regmap_bus_write(void *context, const void *data, size_t count)
+{
+	struct device *dev = context;
+	struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
+
+	if (!priv)
+		return -EINVAL;
+
+	if (count < REG_BYTES) {
+		dev_err_ratelimited(dev, "%s: count %zd bytes < %d, not supported\n",
+			__func__, count, REG_BYTES);
+		return -EINVAL;
+	}
+
+	return regmap_bus_gather_write(context, data, REG_BYTES,
+				       data + REG_BYTES,
+				       count - REG_BYTES);
+}
+
+static struct regmap_bus regmap_bus_config = {
+	.write = regmap_bus_write,
+	.gather_write = regmap_bus_gather_write,
+	.read = regmap_bus_read,
+	.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+	.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+struct regmap *lpass_cdc_regmap_init(struct device *dev,
+				      const struct regmap_config *config)
+{
+	return devm_regmap_init(dev, &regmap_bus_config, dev, config);
+}

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+#ifndef LPASS_CDC_WSA_MACRO_H
+#define LPASS_CDC_WSA_MACRO_H
+
+/*
+ * Selects compander and smart boost settings
+ * for a given speaker mode
+ */
+enum {
+	LPASS_CDC_WSA_MACRO_SPKR_MODE_DEFAULT,
+	LPASS_CDC_WSA_MACRO_SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
+};
+
+/* Rx path gain offsets */
+enum {
+	LPASS_CDC_WSA_MACRO_GAIN_OFFSET_M1P5_DB,
+	LPASS_CDC_WSA_MACRO_GAIN_OFFSET_0_DB,
+};
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc-wsa2-macro.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+#ifndef LPASS_CDC_WSA2_MACRO_H
+#define LPASS_CDC_WSA2_MACRO_H
+
+/*
+ * Selects compander and smart boost settings
+ * for a given speaker mode
+ */
+enum {
+	LPASS_CDC_WSA2_MACRO_SPKR_MODE_DEFAULT,
+	LPASS_CDC_WSA2_MACRO_SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
+};
+
+/* Rx path gain offsets */
+enum {
+	LPASS_CDC_WSA2_MACRO_GAIN_OFFSET_M1P5_DB,
+	LPASS_CDC_WSA2_MACRO_GAIN_OFFSET_0_DB,
+};
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/lpass-cdc/lpass-cdc.h

@@ -0,0 +1,394 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef LPASS_CDC_H
+#define LPASS_CDC_H
+
+#include <sound/soc.h>
+#include <linux/regmap.h>
+
+#define LPASS_CDC_VERSION_1_0 0x0001
+#define LPASS_CDC_VERSION_1_1 0x0002
+#define LPASS_CDC_VERSION_1_2 0x0003
+#define LPASS_CDC_VERSION_2_0 0x0004
+#define LPASS_CDC_VERSION_2_1 0x0005
+#define LPASS_CDC_VERSION_2_5 0x0006
+#define LPASS_CDC_VERSION_2_6 0x0007
+#define LPASS_CDC_VERSION_2_7 0x0008
+#define LPASS_CDC_VERSION_2_8 0x0009
+
+enum {
+	START_MACRO,
+	TX_MACRO = START_MACRO,
+	RX_MACRO,
+	WSA_MACRO,
+	VA_MACRO,
+	WSA2_MACRO,
+	MAX_MACRO
+};
+
+enum mclk_mux {
+	MCLK_MUX0,
+	MCLK_MUX1,
+	MCLK_MUX_MAX
+};
+
+enum {
+	LPASS_CDC_ADC0 = 1,
+	LPASS_CDC_ADC1,
+	LPASS_CDC_ADC2,
+	LPASS_CDC_ADC3,
+	LPASS_CDC_ADC_MAX
+};
+
+enum {
+	LPASS_CDC_MACRO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
+	LPASS_CDC_MACRO_EVT_IMPED_TRUE, /* for imped true */
+	LPASS_CDC_MACRO_EVT_IMPED_FALSE, /* for imped false */
+	LPASS_CDC_MACRO_EVT_SSR_DOWN,
+	LPASS_CDC_MACRO_EVT_SSR_UP,
+	LPASS_CDC_MACRO_EVT_WAIT_VA_CLK_RESET,
+	LPASS_CDC_MACRO_EVT_CLK_RESET,
+	LPASS_CDC_MACRO_EVT_REG_WAKE_IRQ,
+	LPASS_CDC_MACRO_EVT_RX_COMPANDER_SOFT_RST,
+	LPASS_CDC_MACRO_EVT_BCS_CLK_OFF,
+	LPASS_CDC_MACRO_EVT_SSR_GFMUX_UP,
+	LPASS_CDC_MACRO_EVT_PRE_SSR_UP,
+	LPASS_CDC_MACRO_EVT_RX_PA_GAIN_UPDATE,
+	LPASS_CDC_MACRO_EVT_HPHL_HD2_ENABLE, /* Enable HD2 cfg for HPHL */
+	LPASS_CDC_MACRO_EVT_HPHR_HD2_ENABLE, /* Enable HD2 cfg for HPHR */
+};
+
+enum {
+	DMIC_TX = 0,
+	DMIC_VA = 1,
+
+};
+
+struct macro_ops {
+	int (*init)(struct snd_soc_component *component);
+	int (*exit)(struct snd_soc_component *component);
+	u16 num_dais;
+	struct device *dev;
+	struct snd_soc_dai_driver *dai_ptr;
+	int (*mclk_fn)(struct device *dev, bool enable);
+	int (*event_handler)(struct snd_soc_component *component, u16 event,
+			     u32 data);
+	int (*reg_wake_irq)(struct snd_soc_component *component, u32 data);
+	int (*set_port_map)(struct snd_soc_component *component, u32 uc,
+			    u32 size, void *data);
+	int (*clk_div_get)(struct snd_soc_component *component);
+	int (*reg_evt_listener)(struct snd_soc_component *component, bool en);
+	int (*clk_enable)(struct snd_soc_component *c, bool en);
+	char __iomem *io_base;
+	u16 clk_id_req;
+	u16 default_clk_id;
+};
+
+enum {
+	G_21_DB = 0,
+	G_19P5_DB,
+	G_18_DB,
+	G_16P5_DB,
+	G_15_DB,
+	G_13P5_DB,
+	G_12_DB,
+	G_10P5_DB,
+	G_9_DB,
+	G_7P5_DB,
+	G_6_DB,
+	G_4P5_DB,
+	G_3_DB,
+	G_1P5_DB,
+	G_0_DB,
+	G_M1P5_DB,
+	G_M3_DB,
+	G_M4P5_DB,
+	G_M6_DB,
+	G_MAX_DB,
+};
+
+enum {
+	EXT_ABOVE_3S,
+	CONFIG_1S,
+	CONFIG_2S,
+	CONFIG_3S,
+	EXT_1S,
+	EXT_2S,
+	EXT_3S,
+	CONFIG_MAX,
+};
+
+enum {
+	WSA_4_OHMS = 0,
+	WSA_6_OHMS,
+	WSA_8_OHMS,
+	WSA_32_OHMS,
+	WSA_MAX_OHMS,
+};
+
+/*
+ * PBR Thresholds from system_gain, bat_cfg, and rload
+ * EXT_ABOVE_3S: WSA_4_OHMS, WSA_6_OHMS, WSA_8_OHMS, WSA_32_OHMS, CONFIG_1S: ...
+ */
+static const int pbr_vth1_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	/* G_21_DB */
+	{
+		{0, 0, 0, 0}, {81, 92, 106, 0},
+		{121, 148, 144, 0}, {158, 193, 192, 0}
+	},
+	/* G_19P5_DB */
+	{
+		{0, 0, 0, 0}, {96, 109, 126, 0},
+		{143, 148, 203, 0}, {188, 198, 255, 0}
+	},
+	/* G_18_DB */
+	{
+		{0, 0, 0, 0}, {106, 130, 150, 0},
+		{144, 209, 241, 0}, {192, 255, 255, 0}
+	},
+	/* G_16P5_DB */
+	{
+		{0, 0, 0, 0}, {135, 154, 178, 0},
+		{202, 248, 255, 0}, {255, 255, 255, 0}
+	},
+	/* G_15_DB */
+	{
+		{0, 0, 0, 0}, {160, 183, 211, 0},
+		{240, 255, 255, 0}, {255, 255, 255, 0}
+	},
+	 /* G_13P5_DB */
+	{
+		{0, 0, 0, 0}, {190, 217, 251, 0},
+		{255, 255, 255, 0}, {255, 255, 255, 0}
+	},
+	/* G_12_DB */
+	{
+		{0, 0, 0, 0}, {226, 255, 255, 0},
+		{225, 255, 255, 0}, {255, 255, 255, 0}
+	},
+};
+static const int pbr_vth2_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 112, 0}, {0, 0, 151, 0}, {0, 0, 196, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 115, 0, 0}, {0, 155, 0, 0},  {0, 201, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {112, 0, 0, 0}, {150, 0, 0, 0},  {195, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth3_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 118, 0}, {0, 0, 157, 0}, {0, 0, 199, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 122, 0, 0},  {0, 162, 0, 0}, {0, 205, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {118, 0, 0, 0},  {157, 0, 0, 0},  {199, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth4_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 125, 0}, {0, 0, 163, 0}, {0, 0, 202, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 129, 0, 0},  {0, 168, 0, 0}, {0, 208, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {125, 0, 0, 0},   {163, 0, 0, 0},  {202, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth5_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 131, 0}, {0, 0, 170, 0}, {0, 0, 205, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 135, 0, 0},  {0, 175, 0, 0}, {0, 211, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {131, 0, 0, 0},   {170, 0, 0, 0},  {205, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth6_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 138, 0}, {0, 0, 176, 0}, {0, 0, 208, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 142, 0, 0}, {0, 182, 0, 0}, {0, 215, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {138, 0, 0, 0},  {176, 0, 0, 0},  {208, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth7_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 144, 0}, {0, 0, 183, 0}, {0, 0, 212, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 148, 0, 0}, {0, 188, 0, 0}, {0, 218, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {0, 0, 144, 0}, {0, 0, 183, 0}, {0, 0, 212, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth8_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 151, 0}, {0, 0, 189, 0}, {0, 0, 215, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 155, 0, 0}, {0, 195, 0, 0}, {0, 221, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {150, 0, 0, 0},  {189, 0, 0, 0}, {215, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth9_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 157, 0}, {0, 0, 196, 0}, {0, 0, 218, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 162, 0, 0}, {0, 201, 0, 0}, {0, 225, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {157, 0, 0, 0}, {195, 0, 0, 0}, {218, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth10_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 163, 0}, {0, 0, 202, 0}, {0, 0, 221, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 168, 0, 0}, {0, 208, 0, 0}, {0, 228, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {163, 0, 0, 0}, {202, 0, 0, 0}, {221, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth11_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 170, 0}, {0, 0, 208, 0}, {0, 0, 225, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 175, 0, 0}, {0, 215, 0, 0}, {0, 231, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {170, 0, 0, 0}, {208, 0, 0, 0}, {224, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth12_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 176, 0}, {0, 0, 215, 0}, {0, 0, 228, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 182, 0, 0}, {0, 221, 0, 0}, {0, 234, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {176, 0, 0, 0}, {215, 0, 0, 0}, {228, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth13_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 183, 0}, {0, 0, 221, 0}, {0, 0, 231, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 188, 0, 0}, {0, 228, 0, 0}, {0, 238, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {183, 0, 0, 0}, {221, 0, 0, 0}, {231, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth14_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 189, 0}, {0, 0, 228, 0}, {0, 0, 234, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 195, 0, 0}, {0, 234, 0, 0}, {0, 241, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {189, 0, 0, 0}, {228, 0, 0, 0}, {234, 0, 0, 0} }, /* G_18_DB   */
+};
+
+static const int pbr_vth15_data[G_MAX_DB][CONFIG_MAX][WSA_MAX_OHMS] = {
+	{ {0, 0, 0, 0}, {0, 0, 196, 0}, {0, 0, 234, 0}, {0, 0, 237, 0} }, /* G_21_DB   */
+	{ {0, 0, 0, 0}, {0, 201, 0, 0}, {0, 241, 0, 0}, {0, 244, 0, 0} }, /* G_19P5_DB */
+	{ {0, 0, 0, 0}, {195, 0, 0, 0}, {234, 0, 0, 0}, {237, 0, 0, 0} }, /* G_18_DB   */
+};
+
+typedef int (*rsc_clk_cb_t)(struct device *dev, u16 event);
+
+#if IS_ENABLED(CONFIG_SND_SOC_LPASS_CDC)
+int lpass_cdc_register_res_clk(struct device *dev, rsc_clk_cb_t cb);
+void lpass_cdc_unregister_res_clk(struct device *dev);
+bool lpass_cdc_is_va_macro_registered(struct device *dev);
+int lpass_cdc_register_macro(struct device *dev, u16 macro_id,
+			  struct macro_ops *ops);
+void lpass_cdc_unregister_macro(struct device *dev, u16 macro_id);
+struct device *lpass_cdc_get_device_ptr(struct device *dev, u16 macro_id);
+struct device *lpass_cdc_get_rsc_clk_device_ptr(struct device *dev);
+int lpass_cdc_info_create_codec_entry(
+		struct snd_info_entry *codec_root,
+		struct snd_soc_component *component);
+int lpass_cdc_register_wake_irq(struct snd_soc_component *component, u32 data);
+void lpass_cdc_clear_amic_tx_hold(struct device *dev, u16 adc_n);
+int lpass_cdc_runtime_resume(struct device *dev);
+int lpass_cdc_runtime_suspend(struct device *dev);
+int lpass_cdc_set_port_map(struct snd_soc_component *component, u32 size, void *data);
+int lpass_cdc_register_event_listener(struct snd_soc_component *component,
+				   bool enable);
+void lpass_cdc_wsa_pa_on(struct device *dev, bool adie_lb);
+void lpass_cdc_notify_wcd_rx_clk(struct device *dev, bool is_native_on);
+bool lpass_cdc_check_core_votes(struct device *dev);
+int lpass_cdc_tx_mclk_enable(struct snd_soc_component *c, bool enable);
+int lpass_cdc_get_version(struct device *dev);
+int lpass_cdc_dmic_clk_enable(struct snd_soc_component *component,
+			   u32 dmic, u32 tx_mode, bool enable);
+
+/* RX MACRO utilities */
+int lpass_cdc_rx_set_fir_capability(struct snd_soc_component *component,
+					bool capable);
+#else
+static inline int lpass_cdc_register_res_clk(struct device *dev, rsc_clk_cb_t cb)
+{
+	return 0;
+}
+static inline void lpass_cdc_unregister_res_clk(struct device *dev)
+{
+}
+
+static bool lpass_cdc_is_va_macro_registered(struct device *dev)
+{
+	return false;
+}
+
+static inline int lpass_cdc_register_macro(struct device *dev,
+					u16 macro_id,
+					struct macro_ops *ops)
+{
+	return 0;
+}
+
+static inline void lpass_cdc_unregister_macro(struct device *dev, u16 macro_id)
+{
+}
+
+static inline struct device *lpass_cdc_get_device_ptr(struct device *dev,
+						   u16 macro_id)
+{
+	return NULL;
+}
+
+static int lpass_cdc_info_create_codec_entry(
+		struct snd_info_entry *codec_root,
+		struct snd_soc_component *component)
+{
+	return 0;
+}
+
+static inline void lpass_cdc_clear_amic_tx_hold(struct device *dev, u16 adc_n)
+{
+}
+
+static inline int lpass_cdc_register_wake_irq(struct snd_soc_component *component,
+					   u32 data)
+{
+	return 0;
+}
+
+static inline int lpass_cdc_runtime_resume(struct device *dev)
+{
+	return 0;
+}
+
+static int lpass_cdc_runtime_suspend(struct device *dev)
+{
+	return 0;
+}
+
+static inline int lpass_cdc_set_port_map(struct snd_soc_component *component,
+				u32 size, void *data)
+{
+	return 0;
+}
+
+static inline int lpass_cdc_register_event_listener(
+					struct snd_soc_component *component,
+					bool enable)
+{
+	return 0;
+}
+
+static void lpass_cdc_wsa_pa_on(struct device *dev, bool adie_lb)
+{
+}
+
+static void lpass_cdc_notify_wcd_rx_clk(struct device *dev, bool is_native_on)
+{
+}
+
+static inline bool lpass_cdc_check_core_votes(struct device *dev)
+{
+	return false;
+}
+
+static int lpass_cdc_get_version(struct device *dev)
+{
+	return 0;
+}
+
+static int lpass_cdc_dmic_clk_enable(struct snd_soc_component *component,
+			   u32 dmic, u32 tx_mode, bool enable)
+{
+	return 0;
+}
+static int lpass_cdc_tx_mclk_enable(struct snd_soc_component *c, bool enable)
+{
+	return 0;
+}
+/* RX MACRO utilities */
+static int lpass_cdc_rx_set_fir_capability(struct snd_soc_component *component,
+						bool capable)
+{
+	return 0;
+}
+#endif /* CONFIG_SND_SOC_LPASS_CDC */
+#endif /* LPASS_CDC_H */

qcom/opensource/audio-kernel/asoc/codecs/msm-cdc-pinctrl.c

@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/qcom-pinctrl.h>
+#include <asoc/msm-cdc-pinctrl.h>
+
+#define MAX_GPIOS 16
+
+struct msm_cdc_pinctrl_info {
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *pinctrl_active;
+	struct pinctrl_state *pinctrl_sleep;
+	struct pinctrl_state *pinctrl_alt_active;
+	int gpio;
+	bool state;
+	u32 tlmm_gpio[MAX_GPIOS];
+	char __iomem *chip_wakeup_register[MAX_GPIOS];
+	u32 chip_wakeup_maskbit[MAX_GPIOS];
+	u32 count;
+	u32 wakeup_reg_count;
+	bool wakeup_capable;
+	bool chip_wakeup_reg;
+};
+
+static struct msm_cdc_pinctrl_info *msm_cdc_pinctrl_get_gpiodata(
+						struct device_node *np)
+{
+	struct platform_device *pdev;
+	struct msm_cdc_pinctrl_info *gpio_data;
+
+	if (!np) {
+		pr_err_ratelimited("%s: device node is null\n", __func__);
+		return NULL;
+	}
+
+	pdev = of_find_device_by_node(np);
+	if (!pdev) {
+		pr_err_ratelimited("%s: platform device not found!\n", __func__);
+		return NULL;
+	}
+
+	gpio_data = dev_get_drvdata(&pdev->dev);
+	if (!gpio_data)
+		dev_err_ratelimited(&pdev->dev, "%s: cannot find cdc gpio info\n",
+			__func__);
+
+	return gpio_data;
+}
+
+/*
+ * msm_cdc_get_gpio_state: select pinctrl sleep state
+ * @np: pointer to struct device_node
+ *
+ * Returns error code for failure and GPIO value on success
+ */
+int msm_cdc_get_gpio_state(struct device_node *np)
+{
+	struct msm_cdc_pinctrl_info *gpio_data;
+	int value = -EINVAL;
+
+	gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+	if (!gpio_data)
+		return value;
+
+	if (gpio_is_valid(gpio_data->gpio))
+		value = gpio_get_value_cansleep(gpio_data->gpio);
+
+	return value;
+}
+EXPORT_SYMBOL(msm_cdc_get_gpio_state);
+
+/*
+ * msm_cdc_pinctrl_select_sleep_state: select pinctrl sleep state
+ * @np: pointer to struct device_node
+ *
+ * Returns error code for failure
+ */
+int msm_cdc_pinctrl_select_sleep_state(struct device_node *np)
+{
+	struct msm_cdc_pinctrl_info *gpio_data;
+
+	gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+	if (!gpio_data)
+		return -EINVAL;
+
+	if (!gpio_data->pinctrl_sleep) {
+		pr_err_ratelimited("%s: pinctrl sleep state is null\n", __func__);
+		return -EINVAL;
+	}
+	gpio_data->state = false;
+
+	return pinctrl_select_state(gpio_data->pinctrl,
+				    gpio_data->pinctrl_sleep);
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_select_sleep_state);
+
+/*
+ * msm_cdc_pinctrl_select_alt_active_state: select pinctrl alt_active state
+ * @np: pointer to struct device_node
+ *
+ * Returns error code for failure
+ */
+int msm_cdc_pinctrl_select_alt_active_state(struct device_node *np)
+{
+	struct msm_cdc_pinctrl_info *gpio_data;
+
+	gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+	if (!gpio_data)
+		return -EINVAL;
+
+	if (!gpio_data->pinctrl_alt_active) {
+		pr_err_ratelimited("%s: pinctrl alt_active state is null\n", __func__);
+		return -EINVAL;
+	}
+	gpio_data->state = true;
+
+	return pinctrl_select_state(gpio_data->pinctrl,
+				    gpio_data->pinctrl_alt_active);
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_select_alt_active_state);
+
+/*
+ * msm_cdc_pinctrl_select_active_state: select pinctrl active state
+ * @np: pointer to struct device_node
+ *
+ * Returns error code for failure
+ */
+int msm_cdc_pinctrl_select_active_state(struct device_node *np)
+{
+	struct msm_cdc_pinctrl_info *gpio_data;
+
+	gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+	if (!gpio_data)
+		return -EINVAL;
+
+	if (!gpio_data->pinctrl_active) {
+		pr_err_ratelimited("%s: pinctrl active state is null\n", __func__);
+		return -EINVAL;
+	}
+	gpio_data->state = true;
+
+	return pinctrl_select_state(gpio_data->pinctrl,
+				    gpio_data->pinctrl_active);
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_select_active_state);
+
+/*
+ * msm_cdc_pinctrl_get_state: get curren pinctrl state
+ * @np: pointer to struct device_node
+ *
+ * Returns 0 for sleep state, 1 for active state,
+ * error code for failure
+ */
+int msm_cdc_pinctrl_get_state(struct device_node *np)
+{
+	struct msm_cdc_pinctrl_info *gpio_data;
+
+	gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+	if (!gpio_data)
+		return -EINVAL;
+
+	return gpio_data->state;
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_get_state);
+
+/*
+ * msm_cdc_pinctrl_set_wakeup_capable: Set a pinctrl to wakeup capable
+ * @np: pointer to struct device_node
+ * @enable: wakeup capable when set to true
+ *
+ * Returns 0 for success and error code for failure
+ */
+int msm_cdc_pinctrl_set_wakeup_capable(struct device_node *np, bool enable)
+{
+	struct msm_cdc_pinctrl_info *gpio_data;
+	int ret = 0;
+	u32 i = 0, temp = 0;
+
+	gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+	if (!gpio_data)
+		return -EINVAL;
+
+	if (gpio_data->wakeup_capable) {
+		for (i = 0; i < gpio_data->count; i++) {
+			ret = msm_gpio_mpm_wake_set(gpio_data->tlmm_gpio[i],
+						    enable);
+			if (ret < 0)
+				goto exit;
+		}
+	}
+	if (gpio_data->chip_wakeup_reg) {
+		for (i = 0; i < gpio_data->wakeup_reg_count; i++) {
+			temp = ioread32(gpio_data->chip_wakeup_register[i]);
+			if (enable)
+				temp |= (1 <<
+					 gpio_data->chip_wakeup_maskbit[i]);
+			else
+				temp &= ~(1 <<
+					  gpio_data->chip_wakeup_maskbit[i]);
+			iowrite32(temp, gpio_data->chip_wakeup_register[i]);
+		}
+	}
+exit:
+	return ret;
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_set_wakeup_capable);
+
+static int msm_cdc_pinctrl_probe(struct platform_device *pdev)
+{
+	int ret = 0;
+	struct msm_cdc_pinctrl_info *gpio_data;
+	u32 tlmm_gpio[MAX_GPIOS] = {0};
+	u32 chip_wakeup_reg[MAX_GPIOS] = {0};
+	u32 chip_wakeup_default_val[MAX_GPIOS] = {0};
+	u32 i = 0, temp = 0;
+	int count = 0;
+
+	gpio_data = devm_kzalloc(&pdev->dev,
+				 sizeof(struct msm_cdc_pinctrl_info),
+				 GFP_KERNEL);
+	if (!gpio_data)
+		return -ENOMEM;
+
+	gpio_data->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (IS_ERR_OR_NULL(gpio_data->pinctrl)) {
+		dev_err(&pdev->dev, "%s: Cannot get cdc gpio pinctrl:%ld\n",
+			__func__, PTR_ERR(gpio_data->pinctrl));
+		ret = PTR_ERR(gpio_data->pinctrl);
+		goto err_pctrl_get;
+	}
+
+	gpio_data->pinctrl_active = pinctrl_lookup_state(
+					gpio_data->pinctrl, "aud_active");
+	if (IS_ERR_OR_NULL(gpio_data->pinctrl_active)) {
+		dev_err(&pdev->dev, "%s: Cannot get aud_active pinctrl state:%ld\n",
+			__func__, PTR_ERR(gpio_data->pinctrl_active));
+		ret = PTR_ERR(gpio_data->pinctrl_active);
+		goto err_lookup_state;
+	}
+
+	gpio_data->pinctrl_sleep = pinctrl_lookup_state(
+					gpio_data->pinctrl, "aud_sleep");
+	if (IS_ERR_OR_NULL(gpio_data->pinctrl_sleep)) {
+		dev_err(&pdev->dev, "%s: Cannot get aud_sleep pinctrl state:%ld\n",
+			__func__, PTR_ERR(gpio_data->pinctrl_sleep));
+		ret = PTR_ERR(gpio_data->pinctrl_sleep);
+		goto err_lookup_state;
+	}
+
+	gpio_data->pinctrl_alt_active = pinctrl_lookup_state(
+					gpio_data->pinctrl, "aud_alt_active");
+	if (IS_ERR_OR_NULL(gpio_data->pinctrl_alt_active)) {
+		dev_dbg(&pdev->dev, "%s: Cannot get aud_alt_active pinctrl state:%ld\n",
+			__func__, PTR_ERR(gpio_data->pinctrl_alt_active));
+	}
+
+	/* skip setting to sleep state for LPI_TLMM GPIOs */
+	if (!of_property_read_bool(pdev->dev.of_node, "qcom,lpi-gpios")) {
+		/* Set pinctrl state to aud_sleep by default */
+		ret = pinctrl_select_state(gpio_data->pinctrl,
+					   gpio_data->pinctrl_sleep);
+		if (ret)
+			dev_err(&pdev->dev, "%s: set cdc gpio sleep state fail: %d\n",
+				__func__, ret);
+	}
+
+
+	count = of_property_count_u32_elems(pdev->dev.of_node, "qcom,chip-wakeup-reg");
+	if (count <= 0)
+		goto cdc_tlmm_gpio;
+	if (!of_property_read_u32_array(pdev->dev.of_node, "qcom,chip-wakeup-reg",
+				chip_wakeup_reg, count)) {
+		if (of_property_read_u32_array(pdev->dev.of_node,
+					   "qcom,chip-wakeup-maskbit",
+					   gpio_data->chip_wakeup_maskbit, count)) {
+			dev_err(&pdev->dev,
+				"chip-wakeup-maskbit needed if chip-wakeup-reg is defined!\n");
+			goto cdc_tlmm_gpio;
+		}
+		gpio_data->chip_wakeup_reg = true;
+		for (i = 0; i < count; i++) {
+			gpio_data->chip_wakeup_register[i] =
+				devm_ioremap(&pdev->dev, chip_wakeup_reg[i], 0x4);
+		}
+		if (!of_property_read_u32_array(pdev->dev.of_node,
+					"qcom,chip-wakeup-default-val",
+					chip_wakeup_default_val, count)) {
+			for (i = 0; i < count; i++) {
+				temp = ioread32(gpio_data->chip_wakeup_register[i]);
+				if (chip_wakeup_default_val[i])
+					temp |= (1 <<
+						 gpio_data->chip_wakeup_maskbit[i]);
+				else
+					temp &= ~(1 <<
+						  gpio_data->chip_wakeup_maskbit[i]);
+				iowrite32(temp, gpio_data->chip_wakeup_register[i]);
+			}
+		}
+		gpio_data->wakeup_reg_count = count;
+	}
+
+cdc_tlmm_gpio:
+	count = of_property_count_u32_elems(pdev->dev.of_node, "qcom,tlmm-pins");
+	if (count <= 0)
+		goto cdc_rst;
+	if (!of_property_read_u32_array(pdev->dev.of_node, "qcom,tlmm-pins",
+				tlmm_gpio, count)) {
+		gpio_data->wakeup_capable = true;
+		for (i = 0; i < count; i++)
+			gpio_data->tlmm_gpio[i] = tlmm_gpio[i];
+		gpio_data->count = count;
+	}
+
+cdc_rst:
+	gpio_data->gpio = of_get_named_gpio(pdev->dev.of_node,
+					    "qcom,cdc-rst-n-gpio", 0);
+	if (gpio_is_valid(gpio_data->gpio)) {
+		ret = gpio_request(gpio_data->gpio, "MSM_CDC_RESET");
+		if (ret) {
+			dev_err(&pdev->dev, "%s: Failed to request gpio %d\n",
+				__func__, gpio_data->gpio);
+			goto err_lookup_state;
+		}
+	}
+
+	dev_set_drvdata(&pdev->dev, gpio_data);
+	return 0;
+
+err_lookup_state:
+	devm_pinctrl_put(gpio_data->pinctrl);
+err_pctrl_get:
+	devm_kfree(&pdev->dev, gpio_data);
+	return ret;
+}
+
+static int msm_cdc_pinctrl_remove(struct platform_device *pdev)
+{
+	struct msm_cdc_pinctrl_info *gpio_data;
+
+	gpio_data = dev_get_drvdata(&pdev->dev);
+
+	/* to free the requested gpio before exiting */
+	if (gpio_data) {
+		if (gpio_is_valid(gpio_data->gpio))
+			gpio_free(gpio_data->gpio);
+
+		if (gpio_data->pinctrl)
+			devm_pinctrl_put(gpio_data->pinctrl);
+	}
+
+	devm_kfree(&pdev->dev, gpio_data);
+
+	return 0;
+}
+
+static const struct of_device_id msm_cdc_pinctrl_match[] = {
+	{.compatible = "qcom,msm-cdc-pinctrl"},
+	{}
+};
+
+static struct platform_driver msm_cdc_pinctrl_driver = {
+	.driver = {
+		.name = "msm-cdc-pinctrl",
+		.owner = THIS_MODULE,
+		.of_match_table = msm_cdc_pinctrl_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = msm_cdc_pinctrl_probe,
+	.remove = msm_cdc_pinctrl_remove,
+};
+
+int msm_cdc_pinctrl_drv_init(void)
+{
+	return platform_driver_register(&msm_cdc_pinctrl_driver);
+}
+
+void msm_cdc_pinctrl_drv_exit(void)
+{
+	platform_driver_unregister(&msm_cdc_pinctrl_driver);
+}
+MODULE_DESCRIPTION("MSM CODEC pin control platform driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/msm-cdc-supply.c

@@ -0,0 +1,932 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+#include <asoc/msm-cdc-supply.h>
+#include <sound/soc.h>
+
+#define CODEC_DT_MAX_PROP_SIZE 40
+
+static int msm_cdc_dt_parse_vreg_info(struct device *dev,
+				      struct cdc_regulator *cdc_vreg,
+				      const char *name, bool is_ond)
+{
+	char prop_name[CODEC_DT_MAX_PROP_SIZE];
+	struct device_node *regulator_node = NULL;
+	const __be32 *prop;
+	int len, rc;
+	u32 prop_val;
+
+	/* Parse supply name */
+	snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply", name);
+
+	regulator_node = of_parse_phandle(dev->of_node, prop_name, 0);
+	if (!regulator_node) {
+		dev_err(dev, "%s: Looking up %s property in node %s failed",
+			__func__, prop_name, dev->of_node->full_name);
+		rc = -EINVAL;
+		goto done;
+	}
+	cdc_vreg->name = name;
+	cdc_vreg->ondemand = is_ond;
+
+	/* Parse supply - voltage */
+	snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "qcom,%s-voltage", name);
+	prop = of_get_property(dev->of_node, prop_name, &len);
+	if (!prop || (len != (2 * sizeof(__be32)))) {
+		dev_err(dev, "%s: %s %s property\n", __func__,
+			prop ? "invalid format" : "no", prop_name);
+		rc = -EINVAL;
+		goto done;
+	} else {
+		cdc_vreg->min_uV = be32_to_cpup(&prop[0]);
+		cdc_vreg->max_uV = be32_to_cpup(&prop[1]);
+	}
+
+	/* Parse supply - current */
+	snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "qcom,%s-current", name);
+	rc = of_property_read_u32(dev->of_node, prop_name, &prop_val);
+	if (rc) {
+		dev_err(dev, "%s: Looking up %s property in node %s failed",
+			__func__, prop_name, dev->of_node->full_name);
+		goto done;
+	}
+	cdc_vreg->optimum_uA = prop_val;
+
+	/* Parse supply - LPM or NOM mode(default NOM) */
+	snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "qcom,%s-lpm-supported", name);
+	rc = of_property_read_u32(dev->of_node, prop_name, &prop_val);
+	if (rc) {
+		dev_dbg(dev, "%s: Looking up %s property in node %s failed",
+			__func__, prop_name, dev->of_node->full_name);
+		cdc_vreg->lpm_supported = 0;
+		rc = 0;
+	} else {
+		cdc_vreg->lpm_supported = prop_val;
+	}
+
+	/* Parse supply - retention mode */
+	snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "qcom,%s-rem-supported", name);
+	rc = of_property_read_u32(dev->of_node, prop_name, &prop_val);
+	if (rc) {
+		dev_dbg(dev, "%s: Looking up %s property in node %s failed",
+			__func__, prop_name, dev->of_node->full_name);
+		cdc_vreg->rem_supported = 0;
+		rc = 0;
+	} else {
+		cdc_vreg->rem_supported = prop_val;
+	}
+
+	dev_info(dev, "%s: %s: vol=[%d %d]uV, curr=[%d]uA, ond %d lpm %d rem %d\n",
+		 __func__, cdc_vreg->name, cdc_vreg->min_uV, cdc_vreg->max_uV,
+		 cdc_vreg->optimum_uA, cdc_vreg->ondemand,
+		 cdc_vreg->lpm_supported, cdc_vreg->rem_supported);
+
+done:
+	return rc;
+}
+
+static int msm_cdc_parse_supplies(struct device *dev,
+				  struct cdc_regulator *cdc_reg,
+				  const char *sup_list, int sup_cnt,
+				  bool is_ond)
+{
+	int idx, rc = 0;
+	const char *name = NULL;
+
+	for (idx = 0; idx < sup_cnt; idx++) {
+		rc = of_property_read_string_index(dev->of_node, sup_list, idx,
+						   &name);
+		if (rc) {
+			dev_err(dev, "%s: read string %s[%d] error (%d)\n",
+				__func__, sup_list, idx, rc);
+			goto done;
+		}
+
+		dev_dbg(dev, "%s: Found cdc supply %s as part of %s\n",
+			__func__, name, sup_list);
+
+		rc = msm_cdc_dt_parse_vreg_info(dev, &cdc_reg[idx], name,
+						is_ond);
+		if (rc) {
+			dev_err(dev, "%s: parse %s vreg info failed (%d)\n",
+				__func__, name, rc);
+			goto done;
+		}
+	}
+
+done:
+	return rc;
+}
+
+static int msm_cdc_check_supply_param(struct device *dev,
+				      struct cdc_regulator *cdc_vreg,
+				      int num_supplies)
+{
+	if (!dev) {
+		pr_err_ratelimited("%s: device is NULL\n", __func__);
+		return -ENODEV;
+	}
+
+	if (!cdc_vreg || (num_supplies <= 0)) {
+		dev_err_ratelimited(dev, "%s: supply check failed: vreg: %pK, num_supplies: %d\n",
+			__func__, cdc_vreg, num_supplies);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * msm_cdc_is_ondemand_supply:
+ *	return if ondemand supply true or not
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @supply_name: supply name to be checked
+ *
+ * Return true/false
+ */
+bool msm_cdc_is_ondemand_supply(struct device *dev,
+				struct regulator_bulk_data *supplies,
+				struct cdc_regulator *cdc_vreg,
+				int num_supplies,
+				char *supply_name)
+{
+	bool rc = false;
+	int ret, i;
+
+	if ((!supply_name) || (!supplies)) {
+		pr_err_ratelimited("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return rc;
+	}
+	/* input parameter validation */
+	ret = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (ret)
+		return rc;
+
+	for (i = 0; i < num_supplies; i++) {
+		if (cdc_vreg[i].ondemand &&
+			!strcmp(cdc_vreg[i].name, supply_name))
+			return true;
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_is_ondemand_supply);
+
+/*
+ * msm_cdc_supply_supports_retention_mode:
+ *	On certain hardware configurations, This means that the
+ *	PM will disable the supply and remove its power vote
+ *	if the PM enters into a suspended state.
+ *
+ *	return if supply supports retention mode or not
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @supply_name: supply name to be checked
+ *
+ * Return true/false
+ */
+bool msm_cdc_supply_supports_retention_mode(struct device *dev,
+				struct regulator_bulk_data *supplies,
+				struct cdc_regulator *cdc_vreg,
+				int num_supplies, char *supply_name)
+{
+	bool rc = false;
+	int ret, i;
+
+	if ((!supply_name) || (!supplies)) {
+		pr_err_ratelimited("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return rc;
+	}
+	/* input parameter validation */
+	ret = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (ret)
+		return rc;
+
+	for (i = 0; i < num_supplies; i++) {
+		if (cdc_vreg[i].rem_supported &&
+			!strcmp(cdc_vreg[i].name, supply_name))
+			return true;
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_supply_supports_retention_mode);
+
+/*
+ * msm_cdc_check_supply_vote:
+ *
+ *	return true if supply has voted for regulator enable
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @supply_name: supply name to be checked
+ *
+ * Return true/false
+ */
+bool msm_cdc_check_supply_vote(struct device *dev,
+				struct regulator_bulk_data *supplies,
+				struct cdc_regulator *cdc_vreg,
+				int num_supplies,
+				char *supply_name)
+{
+	bool rc = false;
+	int ret, i;
+
+	if ((!supply_name) || (!supplies)) {
+		pr_err_ratelimited("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return rc;
+	}
+
+	/* input parameter validation */
+	ret = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (ret)
+		return rc;
+
+	for (i = 0; i < num_supplies; i++) {
+		if (strcmp(cdc_vreg[i].name, supply_name) != 0)
+			continue;
+
+		return cdc_vreg[i].vote;
+	}
+
+	dev_err_ratelimited(dev,
+		"%s: Unable to find vote for supply %s\n",
+		__func__, supply_name);
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL(msm_cdc_check_supply_vote);
+
+/*
+ * msm_cdc_set_supply_min_voltage:
+ *	Set min supply voltage for particular supply
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @supply_name: Supply name to change voltage for
+ * @vval_min: Min voltage to be set in uV
+ * @override_min_vol: True if override min voltage from default
+ * Return error code if unable to set voltage
+ */
+int msm_cdc_set_supply_min_voltage(struct device *dev,
+				    struct regulator_bulk_data *supplies,
+				    struct cdc_regulator *cdc_vreg,
+				    int num_supplies, char *supply_name,
+				    int vval_min, bool override_min_vol)
+{
+	int rc = 0, i;
+
+	if ((!supply_name) || (!supplies)) {
+		pr_err_ratelimited("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+	for (i = 0; i < num_supplies; i++) {
+		if (!strcmp(cdc_vreg[i].name, supply_name)) {
+			if (override_min_vol)
+				regulator_set_voltage(supplies[i].consumer,
+					vval_min, cdc_vreg[i].max_uV);
+			else
+				regulator_set_voltage(supplies[i].consumer,
+				    cdc_vreg[i].min_uV, cdc_vreg[i].max_uV);
+			break;
+		}
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_set_supply_min_voltage);
+
+/*
+ * msm_cdc_disable_ondemand_supply:
+ *	Disable codec ondemand supply
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @supply_name: Ondemand supply name to be enabled
+ *
+ * Return error code if supply disable is failed
+ */
+int msm_cdc_disable_ondemand_supply(struct device *dev,
+				    struct regulator_bulk_data *supplies,
+				    struct cdc_regulator *cdc_vreg,
+				    int num_supplies,
+				    char *supply_name)
+{
+	int rc, i;
+
+	if ((!supply_name) || (!supplies)) {
+		pr_err_ratelimited("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+
+	dev_dbg(dev, "%s: Disabling on-demand supply %s\n",
+		__func__, supply_name);
+
+	for (i = 0; i < num_supplies; i++) {
+		if (cdc_vreg[i].ondemand &&
+			!strcmp(cdc_vreg[i].name, supply_name)) {
+			if (!cdc_vreg[i].vote) {
+				dev_err_ratelimited(dev,
+					"%s: Attempted to disable already disabled supply %s\n",
+					__func__, supplies[i].supply);
+				break;
+			}
+
+			rc = regulator_disable(supplies[i].consumer);
+			if (rc)
+				dev_err_ratelimited(dev,
+					"%s: failed to disable supply %s, err:%d\n",
+					__func__, supplies[i].supply, rc);
+			else
+				cdc_vreg[i].vote = false;
+			break;
+		}
+	}
+	if (i == num_supplies) {
+		dev_err_ratelimited(dev, "%s: not able to find supply %s\n",
+			__func__, supply_name);
+		rc = -EINVAL;
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_disable_ondemand_supply);
+
+/*
+ * msm_cdc_enable_ondemand_supply:
+ *	Enable codec ondemand supply
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @supply_name: Ondemand supply name to be enabled
+ *
+ * Return error code if supply enable is failed
+ */
+int msm_cdc_enable_ondemand_supply(struct device *dev,
+				   struct regulator_bulk_data *supplies,
+				   struct cdc_regulator *cdc_vreg,
+				   int num_supplies,
+				   char *supply_name)
+{
+	int rc, i;
+
+	if ((!supply_name) || (!supplies)) {
+		pr_err_ratelimited("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+
+	dev_dbg(dev, "%s: Enabling on-demand supply %s\n",
+		__func__, supply_name);
+
+	for (i = 0; i < num_supplies; i++) {
+		if (cdc_vreg[i].ondemand &&
+			!strcmp(cdc_vreg[i].name, supply_name)) {
+			if (cdc_vreg[i].vote) {
+				dev_err_ratelimited(dev,
+					"%s: Attempted to enable already enabled supply %s\n",
+					__func__, supplies[i].supply);
+				break;
+			}
+
+			rc = regulator_enable(supplies[i].consumer);
+			if (rc)
+				dev_err_ratelimited(dev, "%s: failed to enable supply %s, rc: %d\n",
+					__func__, supplies[i].supply, rc);
+			else
+				cdc_vreg[i].vote = true;
+			break;
+		}
+	}
+	if (i == num_supplies) {
+		dev_err_ratelimited(dev, "%s: not able to find supply %s\n",
+			__func__, supply_name);
+		rc = -EINVAL;
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_enable_ondemand_supply);
+
+/*
+ * msm_cdc_set_supplies_lpm_mode:
+ *	Update load for given supply string
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @supply_name: supply name to be checked
+ * @min_max: Apply optimum or 0 current
+ *
+ * Return error code if set current fail
+ */
+int msm_cdc_set_supplies_lpm_mode(struct device *dev,
+				struct regulator_bulk_data *supplies,
+				struct cdc_regulator *cdc_vreg,
+				int num_supplies,
+				bool flag)
+{
+	int rc = 0, i;
+
+	if (!supplies) {
+		pr_err_ratelimited("%s: supplies is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+
+	for (i = 0; i < num_supplies; i++) {
+		if (cdc_vreg[i].lpm_supported) {
+			rc = regulator_set_load(
+				supplies[i].consumer,
+				flag ? 0 : cdc_vreg[i].optimum_uA);
+			if (rc)
+				dev_err_ratelimited(dev,
+					"%s: failed to set supply %s to %s, err:%d\n",
+					__func__, supplies[i].supply,
+					flag ? "LPM" : "NOM",
+					rc);
+			else
+				dev_dbg(dev, "%s: regulator %s load set to %s\n",
+					__func__, supplies[i].supply,
+					flag ? "LPM" : "NOM");
+		}
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_set_supplies_lpm_mode);
+
+/*
+ * msm_cdc_disable_static_supplies:
+ *	Disable codec static supplies
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply disable is failed
+ */
+int msm_cdc_disable_static_supplies(struct device *dev,
+				    struct regulator_bulk_data *supplies,
+				    struct cdc_regulator *cdc_vreg,
+				    int num_supplies)
+{
+	int rc, i;
+
+	if ((!dev) || (!supplies) || (!cdc_vreg)) {
+		pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+
+	for (i = 0; i < num_supplies; i++) {
+		if (cdc_vreg[i].ondemand)
+			continue;
+
+		rc = regulator_disable(supplies[i].consumer);
+		if (rc)
+			dev_err(dev, "%s: failed to disable supply %s, err:%d\n",
+				__func__, supplies[i].supply, rc);
+		else {
+			cdc_vreg[i].vote = false;
+			dev_dbg(dev, "%s: disabled regulator %s\n",
+				__func__, supplies[i].supply);
+		}
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_disable_static_supplies);
+
+/*
+ * msm_cdc_release_supplies:
+ *	Release codec power supplies
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply disable is failed
+ */
+int msm_cdc_release_supplies(struct device *dev,
+			     struct regulator_bulk_data *supplies,
+			     struct cdc_regulator *cdc_vreg,
+			     int num_supplies)
+{
+	int rc = 0;
+	int i;
+
+	if ((!dev) || (!supplies) || (!cdc_vreg)) {
+		pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+
+	msm_cdc_disable_static_supplies(dev, supplies, cdc_vreg,
+					num_supplies);
+	for (i = 0; i < num_supplies; i++) {
+		if (regulator_count_voltages(supplies[i].consumer) < 0)
+			continue;
+
+		regulator_set_voltage(supplies[i].consumer, 0,
+				      cdc_vreg[i].max_uV);
+		regulator_set_load(supplies[i].consumer, 0);
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_release_supplies);
+
+/*
+ * msm_cdc_enable_static_supplies:
+ *	Enable codec static supplies
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply enable is failed
+ */
+int msm_cdc_enable_static_supplies(struct device *dev,
+				   struct regulator_bulk_data *supplies,
+				   struct cdc_regulator *cdc_vreg,
+				   int num_supplies)
+{
+	int rc, i;
+
+	if ((!dev) || (!supplies) || (!cdc_vreg)) {
+		pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+
+	for (i = 0; i < num_supplies; i++) {
+		if (cdc_vreg[i].ondemand)
+			continue;
+
+		rc = regulator_enable(supplies[i].consumer);
+		if (rc) {
+			dev_err(dev, "%s: failed to enable supply %s, rc: %d\n",
+				__func__, supplies[i].supply, rc);
+			break;
+		} else
+			cdc_vreg[i].vote = true;
+	}
+
+	if (rc) {
+		while (i--) {
+			if (cdc_vreg[i].ondemand)
+				continue;
+
+			if (regulator_disable(supplies[i].consumer) == 0)
+				cdc_vreg[i].vote = false;
+			else
+				dev_err(dev, "%s: failed to disable supply %s during unwind\n",
+					__func__, supplies[i].supply);
+		}
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_enable_static_supplies);
+
+/*
+ * msm_cdc_init_supplies:
+ *	Initialize codec static supplies
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply init is failed
+ */
+int msm_cdc_init_supplies(struct device *dev,
+			  struct regulator_bulk_data **supplies,
+			  struct cdc_regulator *cdc_vreg,
+			  int num_supplies)
+{
+	return msm_cdc_init_supplies_v2(dev, supplies, cdc_vreg,
+					num_supplies, false);
+}
+EXPORT_SYMBOL(msm_cdc_init_supplies);
+
+/*
+ * msm_cdc_init_supplies_v2:
+ *	Initialize codec static supplies.
+ *	Initialize codec dynamic supplies based on vote_regulator_on_demand
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ * @vote_regulator_on_demand: initialize codec dynamic supplies at runtime
+ *
+ * Return error code if supply init is failed
+ */
+int msm_cdc_init_supplies_v2(struct device *dev,
+			  struct regulator_bulk_data **supplies,
+			  struct cdc_regulator *cdc_vreg,
+			  int num_supplies, u32 vote_regulator_on_demand)
+{
+	struct regulator_bulk_data *vsup;
+	int rc;
+	int i;
+
+	if (!dev || !cdc_vreg) {
+		pr_err("%s: device pointer or dce_vreg is NULL\n",
+				__func__);
+		return -EINVAL;
+	}
+	/* input parameter validation */
+	rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+	if (rc)
+		return rc;
+
+	vsup = devm_kcalloc(dev, num_supplies,
+			    sizeof(struct regulator_bulk_data),
+			    GFP_KERNEL);
+	if (!vsup)
+		return -ENOMEM;
+
+	for (i = 0; i < num_supplies; i++) {
+		if (!cdc_vreg[i].name) {
+			dev_err(dev, "%s: supply name not defined\n",
+				__func__);
+			rc = -EINVAL;
+			goto err_supply;
+		}
+		vsup[i].supply = cdc_vreg[i].name;
+	}
+
+	rc = devm_regulator_bulk_get(dev, num_supplies, vsup);
+	if (rc) {
+		dev_err(dev, "%s: failed to get supplies (%d)\n",
+			__func__, rc);
+		goto err_supply;
+	}
+
+	/* Set voltage and current on regulators */
+	for (i = 0; i < num_supplies; i++) {
+		if (regulator_count_voltages(vsup[i].consumer) < 0)
+			continue;
+
+		if (cdc_vreg[i].ondemand && vote_regulator_on_demand)
+			continue;
+
+		cdc_vreg[i].regulator = vsup[i].consumer;
+
+		rc = regulator_set_voltage(vsup[i].consumer,
+					   cdc_vreg[i].min_uV,
+					   cdc_vreg[i].max_uV);
+		if (rc) {
+			dev_err(dev, "%s: set regulator voltage failed for %s, err:%d\n",
+				__func__, vsup[i].supply, rc);
+			goto err_supply;
+		}
+		rc = regulator_set_load(vsup[i].consumer,
+					cdc_vreg[i].optimum_uA);
+		if (rc < 0) {
+			dev_err(dev, "%s: set regulator optimum mode failed for %s, err:%d\n",
+				__func__, vsup[i].supply, rc);
+			goto err_supply;
+		}
+	}
+
+	*supplies = vsup;
+
+	return 0;
+
+err_supply:
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_init_supplies_v2);
+
+/*
+ * msm_cdc_get_power_supplies:
+ *	Get codec power supplies from device tree.
+ *	Allocate memory to hold regulator data for
+ *	all power supplies.
+ *
+ * @dev: pointer to codec device
+ * @cdc_vreg: pointer to codec regulator
+ * @total_num_supplies: total number of supplies read from DT
+ *
+ * Return error code if supply disable is failed
+ */
+int msm_cdc_get_power_supplies(struct device *dev,
+			       struct cdc_regulator **cdc_vreg,
+			       int *total_num_supplies)
+{
+	const char *static_prop_name = "qcom,cdc-static-supplies";
+	const char *ond_prop_name = "qcom,cdc-on-demand-supplies";
+	const char *cp_prop_name = "qcom,cdc-cp-supplies";
+	int static_sup_cnt = 0;
+	int ond_sup_cnt = 0;
+	int cp_sup_cnt = 0;
+	int num_supplies = 0;
+	struct cdc_regulator *cdc_reg;
+	int rc;
+
+	if (!dev) {
+		pr_err_ratelimited("%s: device pointer is NULL\n", __func__);
+		return -EINVAL;
+	}
+	static_sup_cnt = of_property_count_strings(dev->of_node,
+						   static_prop_name);
+	if (static_sup_cnt < 0) {
+		dev_err_ratelimited(dev, "%s: Failed to get static supplies(%d)\n",
+			__func__, static_sup_cnt);
+		rc = static_sup_cnt;
+		goto err_supply_cnt;
+	}
+	ond_sup_cnt = of_property_count_strings(dev->of_node, ond_prop_name);
+	if (ond_sup_cnt < 0)
+		ond_sup_cnt = 0;
+
+	cp_sup_cnt = of_property_count_strings(dev->of_node,
+					       cp_prop_name);
+	if (cp_sup_cnt < 0)
+		cp_sup_cnt = 0;
+
+	num_supplies = static_sup_cnt + ond_sup_cnt + cp_sup_cnt;
+	if (num_supplies <= 0) {
+		dev_err_ratelimited(dev, "%s: supply count is 0 or negative\n", __func__);
+		rc = -EINVAL;
+		goto err_supply_cnt;
+	}
+
+	cdc_reg = devm_kcalloc(dev, num_supplies,
+			       sizeof(struct cdc_regulator),
+			       GFP_KERNEL);
+	if (!cdc_reg) {
+		rc = -ENOMEM;
+		goto err_mem_alloc;
+	}
+
+	rc = msm_cdc_parse_supplies(dev, cdc_reg, static_prop_name,
+				    static_sup_cnt, false);
+	if (rc) {
+		dev_err_ratelimited(dev, "%s: failed to parse static supplies(%d)\n",
+				__func__, rc);
+		goto err_sup;
+	}
+
+	rc = msm_cdc_parse_supplies(dev, &cdc_reg[static_sup_cnt],
+				    ond_prop_name, ond_sup_cnt,
+				    true);
+	if (rc) {
+		dev_err_ratelimited(dev, "%s: failed to parse demand supplies(%d)\n",
+				__func__, rc);
+		goto err_sup;
+	}
+
+	rc = msm_cdc_parse_supplies(dev,
+				    &cdc_reg[static_sup_cnt + ond_sup_cnt],
+				    cp_prop_name, cp_sup_cnt, true);
+	if (rc) {
+		dev_err_ratelimited(dev, "%s: failed to parse cp supplies(%d)\n",
+				__func__, rc);
+		goto err_sup;
+	}
+
+	*cdc_vreg = cdc_reg;
+	*total_num_supplies = num_supplies;
+
+	return 0;
+
+err_sup:
+err_supply_cnt:
+err_mem_alloc:
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_get_power_supplies);
+
+/*
+ * msm_cdc_init_wcd_supply:
+ *	Initialize wcd supply parameters.
+ *
+ * @np: device node pointer to codec device
+ * @name: power supply name
+ * @cdc_supply: codec supply struct to hold wcd params
+ *
+ * Return error code if init failed
+ */
+int msm_cdc_init_wcd_supply(struct device_node *np, const char *name,
+			    struct cdc_wcd_supply *cdc_supply)
+{
+	struct platform_device *pdev = NULL;
+
+	if (!np || !cdc_supply)
+		return -EINVAL;
+
+	pdev = of_find_device_by_node(np);
+	if (!pdev)
+		return -EINVAL;
+
+	cdc_supply->dev = &pdev->dev;
+	cdc_supply->name = name;
+	cdc_supply->component = snd_soc_lookup_component(&pdev->dev, NULL);
+
+	return 0;
+}
+EXPORT_SYMBOL(msm_cdc_init_wcd_supply);
+
+/*
+ * msm_cdc_enable_wcd_supply:
+ *	Enable/Disable wcd supply.
+ *
+ * @cdc_supply: codec supply struct to hold wcd params
+ * @enable: bool to inform whether to enable or disable
+ *
+ * Return error code if enable/disable failed
+ */
+int msm_cdc_enable_wcd_supply(struct cdc_wcd_supply *cdc_supply, bool enable)
+{
+	struct snd_soc_component *component = cdc_supply->component;
+	int rc;
+
+	if (!component) {
+		pr_err_ratelimited("%s: Component memory is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	if (enable)
+		rc = snd_soc_dapm_force_enable_pin(
+					snd_soc_component_get_dapm(component),
+					cdc_supply->name);
+	else
+		rc = snd_soc_dapm_disable_pin(
+					snd_soc_component_get_dapm(component),
+					cdc_supply->name);
+
+	if (!rc)
+		snd_soc_dapm_sync(snd_soc_component_get_dapm(component));
+	else
+		dev_err_ratelimited(component->dev, "%s: micbias %s force %s pin failed\n",
+			__func__, cdc_supply->name, (enable ? "enable" : "disable"));
+
+	return rc;
+}
+EXPORT_SYMBOL(msm_cdc_enable_wcd_supply);

qcom/opensource/audio-kernel/asoc/codecs/msm_hdmi_codec_rx.c

@@ -0,0 +1,946 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/err.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <linux/soc/qcom/msm_ext_display.h>
+
+#define DRV_NAME "HDMI_codec"
+
+#define MSM_EXT_DISP_PCM_RATES	SNDRV_PCM_RATE_48000
+#define AUD_EXT_DISP_ACK_DISCONNECT (AUDIO_ACK_CONNECT ^ AUDIO_ACK_CONNECT)
+#define AUD_EXT_DISP_ACK_CONNECT    (AUDIO_ACK_CONNECT)
+#define AUD_EXT_DISP_ACK_ENABLE     (AUDIO_ACK_SET_ENABLE | AUDIO_ACK_ENABLE)
+
+#define SOC_EXT_DISP_AUDIO_TYPE(index) \
+	static SOC_ENUM_SINGLE_DECL(ext_disp_audio_type##index, SND_SOC_NOPM, \
+				    index, ext_disp_audio_type_text)
+#define SOC_EXT_DISP_AUDIO_ACK_STATE(index) \
+	static SOC_ENUM_SINGLE_DECL(ext_disp_audio_ack_state##index, \
+			    SND_SOC_NOPM, index, ext_disp_audio_ack_text)
+
+#define SWITCH_DP_CODEC(codec_info, codec_data, dai_id, type) \
+	codec_info.type = type; \
+	codec_info.ctrl_id = codec_data->ctl[dai_id]; \
+	codec_info.stream_id = codec_data->stream[dai_id]; \
+
+enum {
+        DP_CONTROLLER0 = 0,
+        DP_CONTROLLER_MAX,
+};
+
+enum {
+	DP_STREAM0 = 0,
+	DP_STREAM1,
+	HDMI,
+	DP_STREAM_MAX,
+};
+
+/*
+ * Dai id cannot be zero, if component has more than one dai and dai id
+ * is used to differentiate between them
+ */
+enum {
+	DP_DAI1 = 1,
+	DP_DAI2,
+	HDMI_DAI,
+	HDMI_MS_DAI,
+	DP_DAI_MAX,
+};
+
+static const char *const ext_disp_audio_type_text[] = {"None", "HDMI", "DP"};
+static const char *const ext_disp_audio_ack_text[] = {"Disconnect",  "Connect",
+						      "Ack_Enable"};
+
+static const struct snd_pcm_hardware dummy_dma_hardware = {
+	/* Random values to keep userspace happy when checking constraints */
+	.info               = SNDRV_PCM_INFO_INTERLEAVED |
+					SNDRV_PCM_INFO_BLOCK_TRANSFER,
+	.buffer_bytes_max   = 128*1024,
+	.period_bytes_min   = PAGE_SIZE,
+	.period_bytes_max   = PAGE_SIZE*2,
+	.periods_min        = 2,
+	.periods_max        = 128,
+};
+
+SOC_EXT_DISP_AUDIO_TYPE(1);
+SOC_EXT_DISP_AUDIO_ACK_STATE(1);
+SOC_EXT_DISP_AUDIO_TYPE(2);
+SOC_EXT_DISP_AUDIO_ACK_STATE(2);
+SOC_EXT_DISP_AUDIO_TYPE(3);
+SOC_EXT_DISP_AUDIO_ACK_STATE(3);
+
+struct msm_ext_disp_audio_codec_rx_data {
+	struct platform_device *ext_disp_core_pdev;
+	struct msm_ext_disp_audio_codec_ops ext_disp_ops;
+	struct mutex dp_ops_lock;
+	int cable_status[DP_DAI_MAX];
+	int stream[DP_DAI_MAX];
+	int ctl[DP_DAI_MAX];
+};
+
+static int msm_ext_disp_edid_ctl_info(struct snd_kcontrol *kcontrol,
+			struct snd_ctl_elem_info *uinfo)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+	struct msm_ext_disp_audio_edid_blk edid_blk;
+	int rc = 0;
+	struct msm_ext_disp_codec_id codec_info;
+	int dai_id = kcontrol->private_value;
+	int type;
+
+	codec_data = snd_soc_component_get_drvdata(component);
+	if (!codec_data) {
+		dev_err_ratelimited(component->dev, "%s: codec_data is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	dev_dbg(component->dev, "%s: DP ctl id %d Stream id %d\n", __func__,
+		codec_data->ctl[dai_id], codec_data->stream[dai_id]);
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	if (dai_id == HDMI_MS_DAI)
+		type = EXT_DISPLAY_TYPE_HDMI;
+	else
+		type = EXT_DISPLAY_TYPE_DP;
+	SWITCH_DP_CODEC(codec_info, codec_data, dai_id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+	if (!codec_data->ext_disp_ops.get_audio_edid_blk || rc) {
+		dev_dbg(component->dev, "%s: get_audio_edid_blk() is NULL\n",
+			__func__);
+		uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+		uinfo->count = 0;
+		mutex_unlock(&codec_data->dp_ops_lock);
+		return 0;
+	}
+
+	rc = codec_data->ext_disp_ops.get_audio_edid_blk(
+				codec_data->ext_disp_core_pdev, &edid_blk);
+	mutex_unlock(&codec_data->dp_ops_lock);
+	if (rc >= 0) {
+		uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
+		uinfo->count = edid_blk.audio_data_blk_size +
+			edid_blk.spk_alloc_data_blk_size;
+	}
+
+	dev_dbg(component->dev, "%s: count: %d\n", __func__, uinfo->count);
+
+	return rc;
+}
+
+static int msm_ext_disp_edid_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol) {
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+	struct msm_ext_disp_audio_edid_blk edid_blk;
+	struct msm_ext_disp_codec_id codec_info;
+	int rc = 0;
+	int dai_id = kcontrol->private_value;
+	int type;
+
+	codec_data = snd_soc_component_get_drvdata(component);
+	if (!codec_data) {
+		dev_err_ratelimited(component->dev, "%s: codec_data is NULL\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	dev_dbg(component->dev, "%s: DP ctl id %d Stream id %d\n", __func__,
+		codec_data->ctl[dai_id], codec_data->stream[dai_id]);
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	if (dai_id == HDMI_MS_DAI)
+		type = EXT_DISPLAY_TYPE_HDMI;
+	else
+		type = EXT_DISPLAY_TYPE_DP;
+	SWITCH_DP_CODEC(codec_info, codec_data, dai_id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+	if (!codec_data->ext_disp_ops.get_audio_edid_blk || rc) {
+		dev_err_ratelimited(component->dev,
+			"%s: codec_data or get_audio_edid_blk() is NULL\n",
+			__func__);
+		mutex_unlock(&codec_data->dp_ops_lock);
+		return -EINVAL;
+	}
+	rc = codec_data->ext_disp_ops.get_audio_edid_blk(
+			codec_data->ext_disp_core_pdev, &edid_blk);
+	mutex_unlock(&codec_data->dp_ops_lock);
+	if (rc >= 0) {
+		if (sizeof(ucontrol->value.bytes.data) <
+			  (edid_blk.audio_data_blk_size +
+			   edid_blk.spk_alloc_data_blk_size)) {
+			dev_err_ratelimited(component->dev,
+				"%s: Not enough memory to copy EDID data\n",
+				__func__);
+			return -ENOMEM;
+		}
+
+		memcpy(ucontrol->value.bytes.data,
+		       edid_blk.audio_data_blk,
+		       edid_blk.audio_data_blk_size);
+		memcpy((ucontrol->value.bytes.data +
+		       edid_blk.audio_data_blk_size),
+		       edid_blk.spk_alloc_data_blk,
+		       edid_blk.spk_alloc_data_blk_size);
+
+		dev_dbg(component->dev, "%s: data_blk_size:%d, spk_alloc_data_blk_size:%d\n",
+			__func__, edid_blk.audio_data_blk_size,
+			edid_blk.spk_alloc_data_blk_size);
+	}
+
+	return rc;
+}
+
+static int msm_ext_disp_audio_type_get(struct snd_kcontrol *kcontrol,
+				       struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+	enum msm_ext_disp_cable_state cable_state;
+	enum msm_ext_disp_type disp_type;
+	struct msm_ext_disp_codec_id codec_info;
+	int rc = 0;
+	int dai_id = ((struct soc_enum *) kcontrol->private_value)->shift_l;
+	int type;
+
+	codec_data = snd_soc_component_get_drvdata(component);
+	if (!codec_data) {
+		dev_err_ratelimited(component->dev, "%s: codec_data is NULL\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	dev_dbg(component->dev, "%s: DP ctl id %d Stream id %d\n", __func__,
+		codec_data->ctl[dai_id], codec_data->stream[dai_id]);
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	if (dai_id == HDMI_MS_DAI)
+		type = EXT_DISPLAY_TYPE_HDMI;
+	else
+		type = EXT_DISPLAY_TYPE_DP;
+	SWITCH_DP_CODEC(codec_info, codec_data, dai_id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+
+	if (!codec_data->ext_disp_ops.get_audio_edid_blk ||
+	    !codec_data->ext_disp_ops.get_intf_id || rc) {
+		dev_err_ratelimited(component->dev, "%s: get_audio_edid_blk() or get_intf_id is NULL\n",
+			__func__);
+		rc = -EINVAL;
+		goto cable_err;
+	}
+
+	cable_state = codec_data->ext_disp_ops.cable_status(
+				codec_data->ext_disp_core_pdev, 1);
+	if (cable_state < 0) {
+		dev_err_ratelimited(component->dev, "%s: Error retrieving cable state from ext_disp, err:%d\n",
+			__func__, cable_state);
+		rc = cable_state;
+		goto cable_err;
+	}
+
+	codec_data->cable_status[dai_id] = cable_state;
+	if (cable_state == EXT_DISPLAY_CABLE_DISCONNECT) {
+		dev_err_ratelimited(component->dev, "%s: Display cable disconnected\n",
+			__func__);
+		ucontrol->value.integer.value[0] = 0;
+		rc = 0;
+		goto cable_err;
+	}
+
+	disp_type = codec_data->ext_disp_ops.get_intf_id(
+						codec_data->ext_disp_core_pdev);
+	mutex_unlock(&codec_data->dp_ops_lock);
+	if (disp_type >= 0) {
+		switch (disp_type) {
+		case EXT_DISPLAY_TYPE_DP:
+			ucontrol->value.integer.value[0] = 2;
+			rc = 0;
+			break;
+		case EXT_DISPLAY_TYPE_HDMI:
+			ucontrol->value.integer.value[0] = 1;
+			rc = 0;
+			break;
+		default:
+			rc = -EINVAL;
+			dev_err_ratelimited(component->dev, "%s: Invalid disp_type:%d\n",
+			       __func__, disp_type);
+			goto done;
+		}
+		dev_dbg(component->dev, "%s: Display type: %d\n",
+			__func__, disp_type);
+	} else {
+		dev_err_ratelimited(component->dev, "%s: Error retrieving disp_type from ext_disp, err:%d\n",
+			__func__, disp_type);
+		rc = disp_type;
+	}
+	return rc;
+
+cable_err:
+	mutex_unlock(&codec_data->dp_ops_lock);
+done:
+	return rc;
+}
+
+static int msm_ext_disp_audio_ack_set(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+	u32 ack_state = 0;
+	struct msm_ext_disp_codec_id codec_info;
+	int rc = 0;
+	int dai_id = ((struct soc_enum *) kcontrol->private_value)->shift_l;
+	int type;
+
+	codec_data = snd_soc_component_get_drvdata(component);
+	if (!codec_data) {
+		dev_err_ratelimited(component->dev,
+			"%s: codec_data is NULL\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	dev_dbg(component->dev, "%s: DP ctl id %d Stream id %d\n", __func__,
+		codec_data->ctl[dai_id], codec_data->stream[dai_id]);
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	if (dai_id == HDMI_MS_DAI)
+		type = EXT_DISPLAY_TYPE_HDMI;
+	else
+		type = EXT_DISPLAY_TYPE_DP;
+	SWITCH_DP_CODEC(codec_info, codec_data, dai_id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+
+	if (!codec_data->ext_disp_ops.acknowledge || rc) {
+		dev_err_ratelimited(component->dev,
+			"%s: codec_data ops acknowledge() is NULL\n",
+			__func__);
+		rc = -EINVAL;
+		goto err;
+	}
+
+	switch (ucontrol->value.enumerated.item[0]) {
+	case 0:
+		ack_state = AUD_EXT_DISP_ACK_DISCONNECT;
+		break;
+	case 1:
+		ack_state = AUD_EXT_DISP_ACK_CONNECT;
+		break;
+	case 2:
+		ack_state = AUD_EXT_DISP_ACK_ENABLE;
+		break;
+	default:
+		rc = -EINVAL;
+		dev_err_ratelimited(component->dev,
+			"%s: invalid value %d for mixer ctl\n",
+			__func__, ucontrol->value.enumerated.item[0]);
+		goto err;
+	}
+	dev_dbg(component->dev, "%s: control %d, ack set value 0x%x\n",
+		__func__, ucontrol->value.enumerated.item[0], ack_state);
+
+	rc = codec_data->ext_disp_ops.acknowledge(
+			 codec_data->ext_disp_core_pdev, ack_state);
+	mutex_unlock(&codec_data->dp_ops_lock);
+	if (rc < 0) {
+		dev_err_ratelimited(component->dev, "%s: error from acknowledge(), err:%d\n",
+			__func__, rc);
+	}
+	return rc;
+
+err:
+	mutex_unlock(&codec_data->dp_ops_lock);
+	return rc;
+}
+
+static int msm_ext_disp_audio_device_get(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+	int rc = 0;
+	int dai_id = ((struct soc_multi_mixer_control *)
+				kcontrol->private_value)->shift;
+
+	if (dai_id < 0 || dai_id > DP_DAI2) {
+		dev_err_ratelimited(component->dev,
+			"%s: invalid dai id: %d\n", __func__, dai_id);
+		rc = -EINVAL;
+		goto done;
+	}
+
+	codec_data = snd_soc_component_get_drvdata(component);
+	if (!codec_data) {
+		dev_err_ratelimited(component->dev,
+			"%s: codec_data or ops acknowledge() is NULL\n",
+			__func__);
+		rc = -EINVAL;
+		goto done;
+	}
+	ucontrol->value.integer.value[0] = codec_data->ctl[dai_id];
+	ucontrol->value.integer.value[1] = codec_data->stream[dai_id];
+
+done:
+	return rc;
+}
+
+static int msm_ext_disp_audio_device_set(struct snd_kcontrol *kcontrol,
+				      struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+			snd_soc_kcontrol_component(kcontrol);
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+	int rc = 0;
+	int dai_id = ((struct soc_multi_mixer_control *)
+				kcontrol->private_value)->shift;
+
+	if (dai_id < 0 || dai_id > DP_DAI2) {
+		dev_err_ratelimited(component->dev,
+			"%s: invalid dai id: %d\n", __func__, dai_id);
+		rc = -EINVAL;
+		goto done;
+	}
+
+	codec_data = snd_soc_component_get_drvdata(component);
+	if (!codec_data) {
+		dev_err_ratelimited(component->dev,
+			"%s: codec_data or ops acknowledge() is NULL\n",
+			__func__);
+		rc = -EINVAL;
+		goto done;
+	}
+
+	if ((ucontrol->value.integer.value[0] > (DP_CONTROLLER_MAX - 1)) ||
+		(ucontrol->value.integer.value[1] > (DP_STREAM_MAX - 1)) ||
+		(ucontrol->value.integer.value[0] < 0) ||
+		(ucontrol->value.integer.value[1] < 0)) {
+		dev_err_ratelimited(component->dev,
+			"%s: DP audio control index invalid\n",
+			__func__);
+		rc = -EINVAL;
+		goto done;
+	}
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	codec_data->ctl[dai_id] = ucontrol->value.integer.value[0];
+	codec_data->stream[dai_id] = ucontrol->value.integer.value[1];
+	mutex_unlock(&codec_data->dp_ops_lock);
+
+done:
+	return rc;
+}
+
+static const struct snd_kcontrol_new msm_ext_disp_codec_rx_controls[] = {
+	{
+		.access = SNDRV_CTL_ELEM_ACCESS_READ |
+			  SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.iface  = SNDRV_CTL_ELEM_IFACE_PCM,
+		.name   = "HDMI EDID",
+		.info   = msm_ext_disp_edid_ctl_info,
+		.get    = msm_ext_disp_edid_get,
+		.private_value = HDMI_DAI,
+	},
+	{
+		.access = SNDRV_CTL_ELEM_ACCESS_READ |
+			  SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.iface  = SNDRV_CTL_ELEM_IFACE_PCM,
+		.name   = "HDMI MS EDID",
+		.info   = msm_ext_disp_edid_ctl_info,
+		.get    = msm_ext_disp_edid_get,
+		.private_value = HDMI_MS_DAI,
+	},
+	{
+		.access = SNDRV_CTL_ELEM_ACCESS_READ |
+			  SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.iface  = SNDRV_CTL_ELEM_IFACE_PCM,
+		.name   = "Display Port EDID",
+		.info   = msm_ext_disp_edid_ctl_info,
+		.get    = msm_ext_disp_edid_get,
+		.private_value = DP_DAI1,
+	},
+	{
+		.access = SNDRV_CTL_ELEM_ACCESS_READ |
+			  SNDRV_CTL_ELEM_ACCESS_VOLATILE,
+		.iface  = SNDRV_CTL_ELEM_IFACE_PCM,
+		.name   = "Display Port1 EDID",
+		.info   = msm_ext_disp_edid_ctl_info,
+		.get    = msm_ext_disp_edid_get,
+		.private_value = DP_DAI2,
+	},
+	SOC_ENUM_EXT("External Display Type",
+		     ext_disp_audio_type1,
+		     msm_ext_disp_audio_type_get, NULL),
+	SOC_ENUM_EXT("External Display1 Type",
+		     ext_disp_audio_type2,
+		     msm_ext_disp_audio_type_get, NULL),
+	SOC_ENUM_EXT("External HDMI Type",
+		     ext_disp_audio_type3,
+		     msm_ext_disp_audio_type_get, NULL),
+	SOC_ENUM_EXT("External Display Audio Ack",
+		     ext_disp_audio_ack_state1,
+		     NULL, msm_ext_disp_audio_ack_set),
+	SOC_ENUM_EXT("External Display1 Audio Ack",
+		     ext_disp_audio_ack_state2,
+		     NULL, msm_ext_disp_audio_ack_set),
+	SOC_ENUM_EXT("External HDMI Audio Ack",
+		     ext_disp_audio_ack_state3,
+		     NULL, msm_ext_disp_audio_ack_set),
+
+	SOC_SINGLE_MULTI_EXT("External Display Audio Device",
+			SND_SOC_NOPM, DP_DAI1, DP_STREAM_MAX - 1, 0, 2,
+			msm_ext_disp_audio_device_get,
+			msm_ext_disp_audio_device_set),
+	SOC_SINGLE_MULTI_EXT("External Display1 Audio Device",
+			SND_SOC_NOPM, DP_DAI2, DP_STREAM_MAX - 1, 0, 2,
+			msm_ext_disp_audio_device_get,
+			msm_ext_disp_audio_device_set),
+	SOC_SINGLE_MULTI_EXT("External HDMI Device",
+			SND_SOC_NOPM, HDMI_MS_DAI, DP_STREAM_MAX - 1, 0, 2,
+			msm_ext_disp_audio_device_get,
+			msm_ext_disp_audio_device_set),
+
+};
+
+static int msm_ext_disp_audio_codec_rx_dai_startup(
+		struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	int ret = 0, rc = 0;
+	struct msm_ext_disp_codec_id codec_info;
+	struct msm_ext_disp_audio_codec_rx_data *codec_data =
+			dev_get_drvdata(dai->component->dev);
+	int type;
+	struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+
+	if (!codec_data) {
+		dev_err_ratelimited(dai->dev, "%s() codec_data is null\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	if (!rtd->dai_link->no_pcm)
+		snd_soc_set_runtime_hwparams(substream, &dummy_dma_hardware);
+
+	dev_dbg(dai->component->dev, "%s: DP ctl id %d Stream id %d\n",
+		__func__,
+		codec_data->ctl[dai->id], codec_data->stream[dai->id]);
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	if (dai->id == HDMI_MS_DAI)
+		type = EXT_DISPLAY_TYPE_HDMI;
+	else
+		type = EXT_DISPLAY_TYPE_DP;
+	SWITCH_DP_CODEC(codec_info, codec_data, dai->id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+
+	if (!codec_data->ext_disp_ops.cable_status || rc) {
+		dev_err_ratelimited(dai->dev, "%s() cable_status is null\n",
+			__func__);
+		mutex_unlock(&codec_data->dp_ops_lock);
+		return -EINVAL;
+	}
+
+	codec_data->cable_status[dai->id] =
+		codec_data->ext_disp_ops.cable_status(
+		codec_data->ext_disp_core_pdev, 1);
+	mutex_unlock(&codec_data->dp_ops_lock);
+	if (codec_data->cable_status[dai->id] < 0) {
+		dev_err_ratelimited(dai->dev,
+			"%s() ext disp core is not ready (ret val = %d)\n",
+			__func__, codec_data->cable_status[dai->id]);
+		ret = codec_data->cable_status[dai->id];
+	} else if (!codec_data->cable_status[dai->id]) {
+		dev_err_ratelimited(dai->dev,
+			"%s() ext disp cable is not connected (ret val = %d)\n",
+			__func__, codec_data->cable_status[dai->id]);
+		ret = -ENODEV;
+	}
+
+	return ret;
+}
+
+static int msm_ext_disp_audio_codec_rx_dai_hw_params(
+		struct snd_pcm_substream *substream,
+		struct snd_pcm_hw_params *params,
+		struct snd_soc_dai *dai)
+{
+	u32 channel_allocation = 0;
+	u32 level_shift  = 0; /* 0dB */
+	bool down_mix = 0;
+	u32 num_channels = params_channels(params);
+	struct msm_ext_disp_codec_id codec_info;
+	int rc = 0;
+	struct msm_ext_disp_audio_setup_params audio_setup_params = {0};
+	int type;
+	struct msm_ext_disp_audio_codec_rx_data *codec_data =
+			dev_get_drvdata(dai->component->dev);
+
+	if (!codec_data) {
+		dev_err_ratelimited(dai->dev, "%s() codec_data is null\n",
+			__func__);
+		return -EINVAL;
+	}
+
+	dev_dbg(dai->component->dev, "%s: DP ctl id %d Stream id %d\n",
+		__func__,
+		codec_data->ctl[dai->id], codec_data->stream[dai->id]);
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	if (dai->id == HDMI_MS_DAI)
+		type = EXT_DISPLAY_TYPE_HDMI;
+	else
+		type = EXT_DISPLAY_TYPE_DP;
+	SWITCH_DP_CODEC(codec_info, codec_data, dai->id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+
+	if (!codec_data->ext_disp_ops.audio_info_setup || rc) {
+		dev_err_ratelimited(dai->dev, "%s: audio_info_setup is null\n",
+			__func__);
+		mutex_unlock(&codec_data->dp_ops_lock);
+		return -EINVAL;
+	}
+	mutex_unlock(&codec_data->dp_ops_lock);
+
+	if (codec_data->cable_status[dai->id] < 0) {
+		dev_err_ratelimited(dai->dev,
+			"%s() ext disp core is not ready (ret val = %d)\n",
+			__func__, codec_data->cable_status[dai->id]);
+		return codec_data->cable_status[dai->id];
+	} else if (!codec_data->cable_status[dai->id]) {
+		dev_err_ratelimited(dai->dev,
+			"%s() ext disp cable is not connected (ret val = %d)\n",
+			__func__, codec_data->cable_status[dai->id]);
+		return -ENODEV;
+	}
+
+	/*refer to HDMI spec CEA-861-E: Table 28 Audio InfoFrame Data Byte 4*/
+	switch (num_channels) {
+	case 2:
+		channel_allocation  = 0;
+		break;
+	case 3:
+		channel_allocation  = 0x02;/*default to FL/FR/FC*/
+		audio_setup_params.sample_present = 0x3;
+		break;
+	case 4:
+		channel_allocation  = 0x06;/*default to FL/FR/FC/RC*/
+		audio_setup_params.sample_present = 0x7;
+		break;
+	case 5:
+		channel_allocation  = 0x0A;/*default to FL/FR/FC/RR/RL*/
+		audio_setup_params.sample_present = 0x7;
+		break;
+	case 6:
+		channel_allocation  = 0x0B;
+		audio_setup_params.sample_present = 0x7;
+		break;
+	case 7:
+		channel_allocation  = 0x12;/*default to FL/FR/FC/RL/RR/RRC/RLC*/
+		audio_setup_params.sample_present = 0xf;
+		break;
+	case 8:
+		channel_allocation  = 0x13;
+		audio_setup_params.sample_present = 0xf;
+		break;
+	default:
+		dev_err_ratelimited(dai->dev, "invalid Channels = %u\n", num_channels);
+		return -EINVAL;
+	}
+
+	dev_dbg(dai->dev,
+		"%s() num_ch %u  samplerate %u channel_allocation = %u\n",
+		__func__, num_channels, params_rate(params),
+		channel_allocation);
+
+	audio_setup_params.sample_rate_hz = params_rate(params);
+	audio_setup_params.num_of_channels = num_channels;
+	audio_setup_params.channel_allocation = channel_allocation;
+	audio_setup_params.level_shift = level_shift;
+	audio_setup_params.down_mix = down_mix;
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	SWITCH_DP_CODEC(codec_info, codec_data, dai->id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+	if (rc)
+		goto end;
+	rc = codec_data->ext_disp_ops.audio_info_setup(
+			codec_data->ext_disp_core_pdev, &audio_setup_params);
+end:
+	mutex_unlock(&codec_data->dp_ops_lock);
+	if (rc < 0) {
+		dev_err_ratelimited(dai->dev,
+			"%s() ext disp core is not ready, rc: %d\n",
+			__func__, rc);
+	}
+
+	return rc;
+}
+
+static void msm_ext_disp_audio_codec_rx_dai_shutdown(
+		struct snd_pcm_substream *substream,
+		struct snd_soc_dai *dai)
+{
+	int rc = 0;
+	struct msm_ext_disp_codec_id codec_info;
+
+	struct msm_ext_disp_audio_codec_rx_data *codec_data =
+			dev_get_drvdata(dai->component->dev);
+	int type;
+
+	if (!codec_data) {
+		dev_err_ratelimited(dai->dev, "%s() codec_data is null\n",
+			__func__);
+		return;
+	}
+
+	dev_dbg(dai->component->dev, "%s: DP ctl id %d Stream id %d\n",
+		__func__,
+		codec_data->ctl[dai->id], codec_data->stream[dai->id]);
+
+	mutex_lock(&codec_data->dp_ops_lock);
+	if (dai->id == HDMI_MS_DAI)
+		type = EXT_DISPLAY_TYPE_HDMI;
+	else
+		type = EXT_DISPLAY_TYPE_DP;
+	SWITCH_DP_CODEC(codec_info, codec_data, dai->id, type);
+	rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev,
+						 &codec_info);
+
+	if (!codec_data->ext_disp_ops.teardown_done ||
+	    !codec_data->ext_disp_ops.cable_status || rc) {
+		dev_err_ratelimited(dai->dev, "%s: teardown_done or cable_status is null\n",
+			__func__);
+		mutex_unlock(&codec_data->dp_ops_lock);
+		return;
+	}
+
+	rc = codec_data->ext_disp_ops.cable_status(
+			codec_data->ext_disp_core_pdev, 0);
+	if (rc < 0) {
+		dev_err_ratelimited(dai->dev,
+			"%s: ext disp core had problems releasing audio flag\n",
+			__func__);
+	}
+
+	codec_data->ext_disp_ops.teardown_done(
+		codec_data->ext_disp_core_pdev);
+	mutex_unlock(&codec_data->dp_ops_lock);
+}
+
+static int msm_ext_disp_audio_codec_rx_probe(
+		struct snd_soc_component *component)
+{
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+	struct device_node *of_node_parent = NULL;
+
+	codec_data = kzalloc(sizeof(struct msm_ext_disp_audio_codec_rx_data),
+		GFP_KERNEL);
+
+	if (!codec_data) {
+		dev_err(component->dev, "%s(): fail to allocate dai data\n",
+				__func__);
+		return -ENOMEM;
+	}
+
+	of_node_parent = of_get_parent(component->dev->of_node);
+	if (!of_node_parent) {
+		dev_err(component->dev, "%s(): Parent device tree node not found\n",
+				__func__);
+		kfree(codec_data);
+		return -ENODEV;
+	}
+
+	codec_data->ext_disp_core_pdev = of_find_device_by_node(of_node_parent);
+	if (!codec_data->ext_disp_core_pdev) {
+		dev_err(component->dev, "%s(): can't get parent pdev\n",
+			__func__);
+		kfree(codec_data);
+		return -ENODEV;
+	}
+
+	if (msm_ext_disp_register_audio_codec(codec_data->ext_disp_core_pdev,
+				&codec_data->ext_disp_ops)) {
+		dev_err(component->dev, "%s(): can't register with ext disp core",
+				__func__);
+		kfree(codec_data);
+		return -ENODEV;
+	}
+
+	mutex_init(&codec_data->dp_ops_lock);
+	dev_set_drvdata(component->dev, codec_data);
+
+	dev_dbg(component->dev, "%s(): registered %s with ext disp core\n",
+		__func__, component->name);
+
+	return 0;
+}
+
+static void msm_ext_disp_audio_codec_rx_remove(
+		struct snd_soc_component *component)
+{
+	struct msm_ext_disp_audio_codec_rx_data *codec_data;
+
+	codec_data = dev_get_drvdata(component->dev);
+	mutex_destroy(&codec_data->dp_ops_lock);
+	kfree(codec_data);
+
+	return;
+}
+
+static struct snd_soc_dai_ops msm_ext_disp_audio_codec_rx_dai_ops = {
+	.startup   = msm_ext_disp_audio_codec_rx_dai_startup,
+	.hw_params = msm_ext_disp_audio_codec_rx_dai_hw_params,
+	.shutdown  = msm_ext_disp_audio_codec_rx_dai_shutdown
+};
+
+static struct snd_soc_dai_driver msm_ext_disp_audio_codec_rx_dais[] = {
+	{
+		.name = "msm_hdmi_audio_codec_rx_dai",
+		.id = HDMI_DAI,
+		.playback = {
+			.stream_name = "HDMI Playback",
+			.channels_min = 1,
+			.channels_max = 8,
+			.rate_min = 48000,
+			.rate_max = 48000,
+			.rates = MSM_EXT_DISP_PCM_RATES,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		.ops = &msm_ext_disp_audio_codec_rx_dai_ops,
+	},
+	{
+		.name = "msm_hdmi_ms_audio_codec_rx_dai",
+		.id = HDMI_MS_DAI,
+		.playback = {
+			.stream_name = "HDMI MS Playback",
+			.channels_min = 1,
+			.channels_max = 8,
+			.rate_min = 48000,
+			.rate_max = 48000,
+			.rates = MSM_EXT_DISP_PCM_RATES,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		.ops = &msm_ext_disp_audio_codec_rx_dai_ops,
+	},
+	{
+		.name = "msm_dp_audio_codec_rx_dai",
+		.id = DP_DAI1,
+		.playback = {
+			.stream_name = "Display Port Playback",
+			.channels_min = 1,
+			.channels_max = 8,
+			.rate_min = 32000,
+			.rate_max = 192000,
+			.rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
+				SNDRV_PCM_RATE_192000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |
+                                SNDRV_PCM_RATE_176400,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE |
+				SNDRV_PCM_FMTBIT_S24_LE |
+				SNDRV_PCM_FMTBIT_S24_3LE,
+		},
+		.ops = &msm_ext_disp_audio_codec_rx_dai_ops,
+	},
+	{
+		.name = "msm_dp_audio_codec_rx1_dai",
+		.id = DP_DAI2,
+		.playback = {
+			.stream_name = "Display Port1 Playback",
+			.channels_min = 1,
+			.channels_max = 8,
+			.rate_min = 48000,
+			.rate_max = 192000,
+			.rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
+				SNDRV_PCM_RATE_192000,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE |
+				SNDRV_PCM_FMTBIT_S24_LE |
+				SNDRV_PCM_FMTBIT_S24_3LE,
+		},
+		.ops = &msm_ext_disp_audio_codec_rx_dai_ops,
+	},
+};
+
+static const struct snd_soc_component_driver msm_ext_disp_codec_rx_driver = {
+	.name = DRV_NAME,
+	.probe = msm_ext_disp_audio_codec_rx_probe,
+	.remove =  msm_ext_disp_audio_codec_rx_remove,
+	.controls = msm_ext_disp_codec_rx_controls,
+	.num_controls = ARRAY_SIZE(msm_ext_disp_codec_rx_controls),
+};
+
+static int msm_ext_disp_audio_codec_rx_plat_probe(
+		struct platform_device *pdev)
+{
+	dev_dbg(&pdev->dev, "%s(): dev name %s\n", __func__,
+		dev_name(&pdev->dev));
+
+	return snd_soc_register_component(&pdev->dev,
+		&msm_ext_disp_codec_rx_driver,
+		msm_ext_disp_audio_codec_rx_dais,
+		ARRAY_SIZE(msm_ext_disp_audio_codec_rx_dais));
+}
+
+static int msm_ext_disp_audio_codec_rx_plat_remove(
+		struct platform_device *pdev)
+{
+	snd_soc_unregister_component(&pdev->dev);
+	return 0;
+}
+static const struct of_device_id msm_ext_disp_audio_codec_rx_dt_match[] = {
+	{ .compatible = "qcom,msm-ext-disp-audio-codec-rx", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, msm_ext_disp_audio_codec_rx_dt_match);
+
+static struct platform_driver msm_ext_disp_audio_codec_rx_driver = {
+	.driver = {
+		.name = "msm-ext-disp-audio-codec-rx",
+		.owner = THIS_MODULE,
+		.of_match_table = msm_ext_disp_audio_codec_rx_dt_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = msm_ext_disp_audio_codec_rx_plat_probe,
+	.remove = msm_ext_disp_audio_codec_rx_plat_remove,
+};
+
+static int __init msm_ext_disp_audio_codec_rx_init(void)
+{
+	int rc = 0;
+
+	rc = platform_driver_register(&msm_ext_disp_audio_codec_rx_driver);
+	if (rc) {
+		pr_err("%s: failed to register ext disp codec driver err:%d\n",
+		       __func__, rc);
+	}
+
+	return rc;
+}
+module_init(msm_ext_disp_audio_codec_rx_init);
+
+static void __exit msm_ext_disp_audio_codec_rx_exit(void)
+{
+	platform_driver_unregister(&msm_ext_disp_audio_codec_rx_driver);
+}
+module_exit(msm_ext_disp_audio_codec_rx_exit);
+
+MODULE_DESCRIPTION("MSM External Display Audio CODEC Driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/msm_stub.c

@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2011-2014, 2017-2019 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+
+#define DRV_NAME "msm-stub-codec"
+
+/* A dummy driver useful only to advertise hardware parameters */
+static struct snd_soc_dai_driver msm_stub_dais[] = {
+	{
+		.name = "msm-stub-rx",
+		.playback = { /* Support maximum range */
+			.stream_name = "Playback",
+			.channels_min = 1,
+			.channels_max = 32,
+			.rates = SNDRV_PCM_RATE_8000_96000,
+			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
+				    SNDRV_PCM_FMTBIT_S24_LE |
+				    SNDRV_PCM_FMTBIT_S24_3LE |
+				    SNDRV_PCM_FMTBIT_S32_LE),
+		},
+	},
+	{
+		.name = "msm-stub-tx",
+		.capture = { /* Support maximum range */
+			.stream_name = "Record",
+			.channels_min = 1,
+			.channels_max = 32,
+			.rates = SNDRV_PCM_RATE_8000_96000,
+			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
+				    SNDRV_PCM_FMTBIT_S24_LE |
+				    SNDRV_PCM_FMTBIT_S24_3LE |
+				    SNDRV_PCM_FMTBIT_S32_LE),
+		},
+	},
+};
+
+static const struct snd_soc_component_driver soc_msm_stub = {
+	.name = DRV_NAME,
+};
+
+static int msm_stub_dev_probe(struct platform_device *pdev)
+{
+	dev_dbg(&pdev->dev, "dev name %s\n", dev_name(&pdev->dev));
+
+	return snd_soc_register_component(&pdev->dev,
+	&soc_msm_stub, msm_stub_dais, ARRAY_SIZE(msm_stub_dais));
+}
+
+static int msm_stub_dev_remove(struct platform_device *pdev)
+{
+	snd_soc_unregister_component(&pdev->dev);
+	return 0;
+}
+static const struct of_device_id msm_stub_codec_dt_match[] = {
+	{ .compatible = "qcom,msm-stub-codec", },
+	{}
+};
+
+static struct platform_driver msm_stub_driver = {
+	.driver = {
+		.name = "msm-stub-codec",
+		.owner = THIS_MODULE,
+		.of_match_table = msm_stub_codec_dt_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = msm_stub_dev_probe,
+	.remove = msm_stub_dev_remove,
+};
+
+static int __init msm_stub_init(void)
+{
+	return platform_driver_register(&msm_stub_driver);
+}
+module_init(msm_stub_init);
+
+static void __exit msm_stub_exit(void)
+{
+	platform_driver_unregister(&msm_stub_driver);
+}
+module_exit(msm_stub_exit);
+
+MODULE_DESCRIPTION("Generic MSM CODEC driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/rouleur/Kbuild

@@ -0,0 +1,120 @@
+# We can build either as part of a standalone Kernel build or as
+# an external module.  Determine which mechanism is being used
+ifeq ($(MODNAME),)
+	KERNEL_BUILD := 1
+else
+	KERNEL_BUILD := 0
+endif
+
+
+
+ifeq ($(KERNEL_BUILD), 1)
+	# These are configurable via Kconfig for kernel-based builds
+	# Need to explicitly configure for Android-based builds
+	AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/kernel/msm-4.19
+	AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+	ifeq ($(CONFIG_ARCH_BENGAL), y)
+		include $(AUDIO_ROOT)/config/bengalauto.conf
+		export
+		INCS    +=  -include $(AUDIO_ROOT)/config/bengalautoconf.h
+	endif
+endif
+
+# As per target team, build is done as follows:
+# Defconfig : build with default flags
+# Slub      : defconfig  + CONFIG_SLUB_DEBUG := y +
+#	      CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
+# Perf      : Using appropriate msmXXXX-perf_defconfig
+#
+# Shipment builds (user variants) should not have any debug feature
+# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
+# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
+# there is no other way to identify defconfig builds, QTI internal
+# representation of perf builds (identified using the string 'perf'),
+# is used to identify if the build is a slub or defconfig one. This
+# way no critical debug feature will be enabled for perf and shipment
+# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
+# config.
+
+############ UAPI ############
+UAPI_DIR :=	uapi
+UAPI_INC :=	-I$(AUDIO_ROOT)/include/$(UAPI_DIR)
+
+############ COMMON ############
+COMMON_DIR :=	include
+COMMON_INC :=	-I$(AUDIO_ROOT)/$(COMMON_DIR)
+
+############ ROULEUR ############
+
+# for ROULEUR Codec
+ifdef CONFIG_SND_SOC_ROULEUR
+	ROULEUR_OBJS += rouleur.o
+	ROULEUR_OBJS += rouleur-regmap.o
+	ROULEUR_OBJS += rouleur-tables.o
+	ROULEUR_OBJS += rouleur-mbhc.o
+endif
+
+ifdef CONFIG_PM2250_SPMI
+	PM2250_SPMI_OBJS += pm2250_spmi.o
+endif
+
+ifdef CONFIG_SND_SOC_ROULEUR_SLAVE
+	ROULEUR_SLAVE_OBJS += rouleur_slave.o
+endif
+
+LINUX_INC +=	-Iinclude/linux
+
+INCS +=		$(COMMON_INC) \
+		$(UAPI_INC)
+
+EXTRA_CFLAGS += $(INCS)
+
+
+CDEFINES +=	-DANI_LITTLE_BYTE_ENDIAN \
+		-DANI_LITTLE_BIT_ENDIAN \
+		-DDOT11F_LITTLE_ENDIAN_HOST \
+		-DANI_COMPILER_TYPE_GCC \
+		-DANI_OS_TYPE_ANDROID=6 \
+		-DPTT_SOCK_SVC_ENABLE \
+		-Wall\
+		-Werror\
+		-D__linux__
+
+KBUILD_CPPFLAGS += $(CDEFINES)
+
+# Currently, for versions of gcc which support it, the kernel Makefile
+# is disabling the maybe-uninitialized warning.  Re-enable it for the
+# AUDIO driver.  Note that we must use EXTRA_CFLAGS here so that it
+# will override the kernel settings.
+ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
+EXTRA_CFLAGS += -Wmaybe-uninitialized
+endif
+#EXTRA_CFLAGS += -Wmissing-prototypes
+
+ifeq ($(call cc-option-yn, -Wheader-guard),y)
+EXTRA_CFLAGS += -Wheader-guard
+endif
+
+ifeq ($(KERNEL_BUILD), 0)
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
+KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
+endif
+
+# Module information used by KBuild framework
+obj-$(CONFIG_SND_SOC_ROULEUR) += rouleur_dlkm.o
+rouleur_dlkm-y := $(ROULEUR_OBJS)
+
+obj-$(CONFIG_SND_SOC_ROULEUR_SLAVE) += rouleur_slave_dlkm.o
+rouleur_slave_dlkm-y := $(ROULEUR_SLAVE_OBJS)
+
+obj-$(CONFIG_PM2250_SPMI) += pm2250_spmi_dlkm.o
+pm2250_spmi_dlkm-y := $(PM2250_SPMI_OBJS)
+
+# inject some build related information
+DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

qcom/opensource/audio-kernel/asoc/codecs/rouleur/internal.h

@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _ROULEUR_INTERNAL_H
+#define _ROULEUR_INTERNAL_H
+
+#include <asoc/wcd-clsh.h>
+#include <asoc/wcd-mbhc-v2.h>
+#include <asoc/wcd-irq.h>
+#include "rouleur-mbhc.h"
+
+#define ROULEUR_MAX_MICBIAS 3
+
+/* Convert from vout ctl to micbias voltage in mV */
+#define  WCD_VOUT_CTL_TO_MICB(v)  (1600 + v * 50)
+#define MAX_PORT 8
+#define MAX_CH_PER_PORT 8
+
+extern struct regmap_config rouleur_regmap_config;
+
+struct codec_port_info {
+	u32 slave_port_type;
+	u32 master_port_type;
+	u32 ch_mask;
+	u32 num_ch;
+	u32 ch_rate;
+};
+
+struct rouleur_priv {
+	struct device *dev;
+
+	int variant;
+	struct snd_soc_component *component;
+	struct device_node *spmi_np;
+	struct regmap *regmap;
+
+	struct swr_device *rx_swr_dev;
+	struct swr_device *tx_swr_dev;
+
+	s32 micb_ref[ROULEUR_MAX_MICBIAS];
+	s32 pullup_ref[ROULEUR_MAX_MICBIAS];
+
+	struct fw_info *fw_data;
+
+	struct mutex micb_lock;
+	s32 dmic_0_1_clk_cnt;
+	/* mbhc module */
+	struct rouleur_mbhc *mbhc;
+
+	bool comp1_enable;
+	bool comp2_enable;
+	bool dapm_bias_off;
+
+	struct irq_domain *virq;
+	struct wcd_irq_info irq_info;
+	u32 rx_clk_cnt;
+	int num_irq_regs;
+	/* to track the status */
+	unsigned long status_mask;
+
+	u8 num_tx_ports;
+	u8 num_rx_ports;
+	struct codec_port_info
+			tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
+	struct codec_port_info
+			rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
+	struct regulator_bulk_data *supplies;
+	struct notifier_block nblock;
+	/* wcd callback to bolero */
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				struct notifier_block *nblock,
+				bool enable);
+	int (*wakeup)(void *handle, bool enable);
+	u32 version;
+	/* Entry for version info */
+	struct snd_info_entry *entry;
+	struct snd_info_entry *version_entry;
+	struct device *spmi_dev;
+	int reset_reg;
+	int mbias_cnt;
+	struct mutex rx_clk_lock;
+	struct mutex main_bias_lock;
+	bool dev_up;
+	bool usbc_hs_status;
+	struct notifier_block psy_nb;
+	struct work_struct soc_eval_work;
+	bool low_soc;
+	int foundry_id_reg;
+	int foundry_id;
+};
+
+struct rouleur_micbias_setting {
+	u32 micb1_mv;
+	u32 micb2_mv;
+	u32 micb3_mv;
+};
+
+struct rouleur_pdata {
+	struct device_node *spmi_np;
+	struct device_node *rx_slave;
+	struct device_node *tx_slave;
+	struct rouleur_micbias_setting micbias;
+
+	struct cdc_regulator *regulator;
+	int num_supplies;
+	int reset_reg;
+	int foundry_id_reg;
+};
+
+struct wcd_ctrl_platform_data {
+	void *handle;
+	int (*update_wcd_event)(void *handle, u16 event, u32 data);
+	int (*register_notifier)(void *handle,
+				 struct notifier_block *nblock,
+				 bool enable);
+};
+
+enum {
+	WCD_RX1,
+	WCD_RX2,
+	WCD_RX3
+};
+
+enum {
+	/* INTR_CTRL_INT_MASK_0 */
+	ROULEUR_IRQ_MBHC_BUTTON_PRESS_DET = 0,
+	ROULEUR_IRQ_MBHC_BUTTON_RELEASE_DET,
+	ROULEUR_IRQ_MBHC_ELECT_INS_REM_DET,
+	ROULEUR_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
+	ROULEUR_IRQ_MBHC_SW_DET,
+	ROULEUR_IRQ_HPHR_OCP_INT,
+	ROULEUR_IRQ_HPHR_CNP_INT,
+	ROULEUR_IRQ_HPHL_OCP_INT,
+
+	/* INTR_CTRL_INT_MASK_1 */
+	ROULEUR_IRQ_HPHL_CNP_INT,
+	ROULEUR_IRQ_EAR_CNP_INT,
+	ROULEUR_IRQ_EAR_OCP_INT,
+	ROULEUR_IRQ_LO_CNP_INT,
+	ROULEUR_IRQ_LO_OCP_INT,
+	ROULEUR_IRQ_HPHL_PDM_WD_INT,
+	ROULEUR_IRQ_HPHR_PDM_WD_INT,
+	ROULEUR_IRQ_RESERVED_0,
+
+	/* INTR_CTRL_INT_MASK_2 */
+	ROULEUR_IRQ_RESERVED_1,
+	ROULEUR_IRQ_RESERVED_2,
+	ROULEUR_IRQ_HPHL_SURGE_DET_INT,
+	ROULEUR_IRQ_HPHR_SURGE_DET_INT,
+	ROULEUR_NUM_IRQS,
+};
+
+extern void rouleur_disable_bcs_before_slow_insert(
+				struct snd_soc_component *component,
+				bool bcs_disable);
+extern struct rouleur_mbhc *rouleur_soc_get_mbhc(
+				struct snd_soc_component *component);
+extern int rouleur_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
+					int volt, int micb_num);
+extern int rouleur_get_micb_vout_ctl_val(u32 micb_mv);
+extern int rouleur_micbias_control(struct snd_soc_component *component,
+			int micb_num, int req, bool is_dapm);
+extern int rouleur_global_mbias_enable(struct snd_soc_component *component);
+extern int rouleur_global_mbias_disable(struct snd_soc_component *component);
+#endif

qcom/opensource/audio-kernel/asoc/codecs/rouleur/pm2250-spmi.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _PM2250_SPMI_H
+#define _PM2250_SPMI_H
+
+#ifdef CONFIG_PM2250_SPMI
+int pm2250_spmi_write(struct device *dev, int reg, int value);
+int pm2250_spmi_read(struct device *dev, int reg, int *value);
+#else
+int pm2250_spmi_write(struct device *dev, int reg, int value)
+{
+	return 0;
+}
+int pm2250_spmi_read(struct device *dev, int reg, int *value);
+{
+	return 0;
+}
+#endif	/* CONFIG_PM2250_SPMI */
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/rouleur/pm2250_spmi.c

@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+/**
+ * @regmap: regmap used to access PMIC registers
+ */
+struct pm2250_spmi {
+	struct regmap *regmap;
+};
+
+static const struct of_device_id pm2250_id_table[] = {
+	{ .compatible = "qcom,pm2250-spmi" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, pm2250_id_table);
+
+/**
+ * pm2250_spmi_write: Function to write to PMIC register
+ * @device: node for rouleur device
+ * @reg: PMIC register to write value
+ * @value: Value to be written to PMIC register
+ */
+int pm2250_spmi_write(struct device *dev, int reg, int value)
+{
+	int rc;
+	struct pm2250_spmi *spmi_dd;
+
+	if (!of_device_is_compatible(dev->of_node, "qcom,pm2250-spmi")) {
+		pr_err("%s: Device node is invalid\n", __func__);
+		return -EINVAL;
+	}
+
+	spmi_dd = dev_get_drvdata(dev);
+	if (!spmi_dd)
+		return -EINVAL;
+
+	rc = regmap_write(spmi_dd->regmap, reg, value);
+	if (rc)
+		dev_err(dev, "%s: Write to PMIC register failed\n", __func__);
+
+	return rc;
+}
+EXPORT_SYMBOL(pm2250_spmi_write);
+
+/**
+ * pm2250_spmi_read: Function to read PMIC register
+ * @device: node for rouleur device
+ * @reg: PMIC register to read value
+ * @value: Pointer to value of reg to be read
+ */
+int pm2250_spmi_read(struct device *dev, int reg, int *value)
+{
+	int rc;
+	struct pm2250_spmi *spmi_dd;
+
+	if (!of_device_is_compatible(dev->of_node, "qcom,pm2250-spmi")) {
+		pr_err("%s: Device node is invalid\n", __func__);
+		return -EINVAL;
+	}
+
+	spmi_dd = dev_get_drvdata(dev);
+	if (!spmi_dd)
+		return -EINVAL;
+
+	rc = regmap_read(spmi_dd->regmap, reg, value);
+	if (rc)
+		dev_err(dev, "%s: Read from PMIC register failed\n", __func__);
+
+	return rc;
+}
+EXPORT_SYMBOL(pm2250_spmi_read);
+
+static int pm2250_spmi_probe(struct platform_device *pdev)
+{
+	struct pm2250_spmi *spmi_dd;
+	const struct of_device_id *match;
+
+	match = of_match_node(pm2250_id_table, pdev->dev.of_node);
+	if (!match)
+		return -ENXIO;
+
+	spmi_dd = devm_kzalloc(&pdev->dev, sizeof(*spmi_dd), GFP_KERNEL);
+	if (spmi_dd == NULL)
+		return -ENOMEM;
+
+	spmi_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+	if (!spmi_dd->regmap) {
+		dev_err(&pdev->dev, "Parent regmap unavailable.\n");
+		return -ENXIO;
+	}
+
+	platform_set_drvdata(pdev, spmi_dd);
+
+	dev_dbg(&pdev->dev, "Probe success !!\n");
+
+	return 0;
+}
+
+static int pm2250_spmi_remove(struct platform_device *pdev)
+{
+	of_platform_depopulate(&pdev->dev);
+	return 0;
+}
+
+static struct platform_driver pm2250_spmi_driver = {
+	.probe		= pm2250_spmi_probe,
+	.remove		= pm2250_spmi_remove,
+	.driver	= {
+		.name		= "pm2250-spmi",
+		.of_match_table	= pm2250_id_table,
+	},
+};
+module_platform_driver(pm2250_spmi_driver);
+
+MODULE_ALIAS("platform:pm2250-spmi");
+MODULE_DESCRIPTION("PMIC SPMI driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/rouleur/rouleur-mbhc.h

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+#ifndef __ROULEUR_MBHC_H__
+#define __ROULEUR_MBHC_H__
+#include <asoc/wcd-mbhc-v2.h>
+
+struct rouleur_mbhc {
+	struct wcd_mbhc wcd_mbhc;
+	struct blocking_notifier_head notifier;
+	struct fw_info *fw_data;
+};
+
+#if IS_ENABLED(CONFIG_SND_SOC_ROULEUR)
+extern int rouleur_mbhc_init(struct rouleur_mbhc **mbhc,
+			   struct snd_soc_component *component,
+			   struct fw_info *fw_data);
+extern void rouleur_mbhc_hs_detect_exit(struct snd_soc_component *component);
+extern int rouleur_mbhc_hs_detect(struct snd_soc_component *component,
+				struct wcd_mbhc_config *mbhc_cfg);
+extern void rouleur_mbhc_deinit(struct snd_soc_component *component);
+extern int rouleur_mbhc_post_ssr_init(struct rouleur_mbhc *mbhc,
+				    struct snd_soc_component *component);
+extern void rouleur_mbhc_ssr_down(struct rouleur_mbhc *mbhc,
+				    struct snd_soc_component *component);
+extern int rouleur_mbhc_get_impedance(struct rouleur_mbhc *rouleur_mbhc,
+				    uint32_t *zl, uint32_t *zr);
+#else
+static inline int rouleur_mbhc_init(struct rouleur_mbhc **mbhc,
+				  struct snd_soc_component *component,
+				  struct fw_info *fw_data)
+{
+	return 0;
+}
+static inline void rouleur_mbhc_hs_detect_exit(
+			struct snd_soc_component *component)
+{
+}
+static inline int rouleur_mbhc_hs_detect(struct snd_soc_component *component,
+				       struct wcd_mbhc_config *mbhc_cfg)
+{
+		return 0;
+}
+static inline void rouleur_mbhc_deinit(struct snd_soc_component *component)
+{
+}
+static inline int rouleur_mbhc_post_ssr_init(struct rouleur_mbhc *mbhc,
+					   struct snd_soc_component *component)
+{
+	return 0;
+}
+static inline void rouleur_mbhc_ssr_down(struct rouleur_mbhc *mbhc,
+					   struct snd_soc_component *component)
+{
+}
+static inline int rouleur_mbhc_get_impedance(struct rouleur_mbhc *rouleur_mbhc,
+					   uint32_t *zl, uint32_t *zr)
+{
+	if (zl)
+		*zl = 0;
+	if (zr)
+		*zr = 0;
+	return -EINVAL;
+}
+#endif
+
+#endif /* __ROULEUR_MBHC_H__ */

qcom/opensource/audio-kernel/asoc/codecs/rouleur/rouleur-registers.h

@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _ROULEUR_REGISTERS_H
+#define _ROULEUR_REGISTERS_H
+
+#define ROULEUR_ANA_BASE_ADDR 0x3000
+#define ROULEUR_DIG_BASE_ADDR 0x3400
+
+#define ROULEUR_REG(reg)  ((reg > ROULEUR_DIG_BASE_ADDR) ? \
+			   (reg - ROULEUR_DIG_BASE_ADDR) : \
+			   (reg - ROULEUR_ANA_BASE_ADDR))
+
+enum {
+	REG_NO_ACCESS,
+	RD_REG,
+	WR_REG,
+	RD_WR_REG
+};
+
+#define ROULEUR_ANA_MICBIAS_MICB_1_2_EN       (ROULEUR_ANA_BASE_ADDR+0x040)
+#define ROULEUR_ANA_MICBIAS_MICB_3_EN         (ROULEUR_ANA_BASE_ADDR+0x041)
+#define ROULEUR_ANA_MICBIAS_LDO_1_SETTING     (ROULEUR_ANA_BASE_ADDR+0x042)
+#define ROULEUR_ANA_MICBIAS_LDO_1_CTRL        (ROULEUR_ANA_BASE_ADDR+0x043)
+#define ROULEUR_ANA_TX_AMIC1                  (ROULEUR_ANA_BASE_ADDR+0x047)
+#define ROULEUR_ANA_TX_AMIC2                  (ROULEUR_ANA_BASE_ADDR+0x048)
+#define ROULEUR_ANA_MBHC_MECH                 (ROULEUR_ANA_BASE_ADDR+0x05A)
+#define ROULEUR_ANA_MBHC_ELECT                (ROULEUR_ANA_BASE_ADDR+0x05B)
+#define ROULEUR_ANA_MBHC_ZDET                 (ROULEUR_ANA_BASE_ADDR+0x05C)
+#define ROULEUR_ANA_MBHC_RESULT_1             (ROULEUR_ANA_BASE_ADDR+0x05D)
+#define ROULEUR_ANA_MBHC_RESULT_2             (ROULEUR_ANA_BASE_ADDR+0x05E)
+#define ROULEUR_ANA_MBHC_RESULT_3             (ROULEUR_ANA_BASE_ADDR+0x05F)
+#define ROULEUR_ANA_MBHC_BTN0_ZDET_VREF1      (ROULEUR_ANA_BASE_ADDR+0x060)
+#define ROULEUR_ANA_MBHC_BTN1_ZDET_VREF2      (ROULEUR_ANA_BASE_ADDR+0x061)
+#define ROULEUR_ANA_MBHC_BTN2_ZDET_VREF3      (ROULEUR_ANA_BASE_ADDR+0x062)
+#define ROULEUR_ANA_MBHC_BTN3_ZDET_DBG_400    (ROULEUR_ANA_BASE_ADDR+0x063)
+#define ROULEUR_ANA_MBHC_BTN4_ZDET_DBG_1400   (ROULEUR_ANA_BASE_ADDR+0x064)
+#define ROULEUR_ANA_MBHC_MICB2_RAMP           (ROULEUR_ANA_BASE_ADDR+0x065)
+#define ROULEUR_ANA_MBHC_CTL_1                (ROULEUR_ANA_BASE_ADDR+0x066)
+#define ROULEUR_ANA_MBHC_CTL_2                (ROULEUR_ANA_BASE_ADDR+0x067)
+#define ROULEUR_ANA_MBHC_PLUG_DETECT_CTL      (ROULEUR_ANA_BASE_ADDR+0x068)
+#define ROULEUR_ANA_MBHC_ZDET_ANA_CTL         (ROULEUR_ANA_BASE_ADDR+0x069)
+#define ROULEUR_ANA_MBHC_ZDET_RAMP_CTL        (ROULEUR_ANA_BASE_ADDR+0x06A)
+#define ROULEUR_ANA_MBHC_FSM_STATUS           (ROULEUR_ANA_BASE_ADDR+0x06B)
+#define ROULEUR_ANA_MBHC_ADC_RESULT           (ROULEUR_ANA_BASE_ADDR+0x06C)
+#define ROULEUR_ANA_MBHC_CTL_CLK              (ROULEUR_ANA_BASE_ADDR+0x06D)
+#define ROULEUR_ANA_MBHC_ZDET_CALIB_RESULT    (ROULEUR_ANA_BASE_ADDR+0x072)
+#define ROULEUR_ANA_NCP_EN                    (ROULEUR_ANA_BASE_ADDR+0x077)
+#define ROULEUR_ANA_NCP_VCTRL                 (ROULEUR_ANA_BASE_ADDR+0x07C)
+#define ROULEUR_ANA_HPHPA_CNP_CTL_1           (ROULEUR_ANA_BASE_ADDR+0x083)
+#define ROULEUR_ANA_HPHPA_CNP_CTL_2           (ROULEUR_ANA_BASE_ADDR+0x084)
+#define ROULEUR_ANA_HPHPA_PA_STATUS           (ROULEUR_ANA_BASE_ADDR+0x087)
+#define ROULEUR_ANA_HPHPA_FSM_CLK             (ROULEUR_ANA_BASE_ADDR+0x088)
+#define ROULEUR_ANA_HPHPA_L_GAIN              (ROULEUR_ANA_BASE_ADDR+0x08B)
+#define ROULEUR_ANA_HPHPA_R_GAIN              (ROULEUR_ANA_BASE_ADDR+0x08C)
+#define ROULEUR_ANA_HPHPA_SPARE_CTL           (ROULEUR_ANA_BASE_ADDR+0x08E)
+#define ROULEUR_SWR_HPHPA_HD2                 (ROULEUR_ANA_BASE_ADDR+0x090)
+#define ROULEUR_ANA_SURGE_EN                  (ROULEUR_ANA_BASE_ADDR+0x097)
+#define ROULEUR_ANA_COMBOPA_CTL               (ROULEUR_ANA_BASE_ADDR+0x09B)
+#define ROULEUR_ANA_COMBOPA_CTL_4             (ROULEUR_ANA_BASE_ADDR+0x09F)
+#define ROULEUR_ANA_COMBOPA_CTL_5             (ROULEUR_ANA_BASE_ADDR+0x0A0)
+#define ROULEUR_ANA_RXLDO_CTL                 (ROULEUR_ANA_BASE_ADDR+0x0B2)
+#define ROULEUR_ANA_MBIAS_EN                  (ROULEUR_ANA_BASE_ADDR+0x0B4)
+
+#define ROULEUR_DIG_SWR_CHIP_ID0              (ROULEUR_DIG_BASE_ADDR+0x001)
+#define ROULEUR_DIG_SWR_CHIP_ID1              (ROULEUR_DIG_BASE_ADDR+0x002)
+#define ROULEUR_DIG_SWR_CHIP_ID2              (ROULEUR_DIG_BASE_ADDR+0x003)
+#define ROULEUR_DIG_SWR_CHIP_ID3              (ROULEUR_DIG_BASE_ADDR+0x004)
+#define ROULEUR_DIG_SWR_SWR_TX_CLK_RATE       (ROULEUR_DIG_BASE_ADDR+0x040)
+#define ROULEUR_DIG_SWR_CDC_RST_CTL           (ROULEUR_DIG_BASE_ADDR+0x041)
+#define ROULEUR_DIG_SWR_TOP_CLK_CFG           (ROULEUR_DIG_BASE_ADDR+0x042)
+#define ROULEUR_DIG_SWR_CDC_RX_CLK_CTL        (ROULEUR_DIG_BASE_ADDR+0x043)
+#define ROULEUR_DIG_SWR_CDC_TX_CLK_CTL        (ROULEUR_DIG_BASE_ADDR+0x044)
+#define ROULEUR_DIG_SWR_SWR_RST_EN            (ROULEUR_DIG_BASE_ADDR+0x045)
+#define ROULEUR_DIG_SWR_CDC_RX_RST            (ROULEUR_DIG_BASE_ADDR+0x047)
+#define ROULEUR_DIG_SWR_CDC_RX0_CTL           (ROULEUR_DIG_BASE_ADDR+0x048)
+#define ROULEUR_DIG_SWR_CDC_RX1_CTL           (ROULEUR_DIG_BASE_ADDR+0x049)
+#define ROULEUR_DIG_SWR_CDC_TX_ANA_MODE_0_1   (ROULEUR_DIG_BASE_ADDR+0x04B)
+#define ROULEUR_DIG_SWR_CDC_COMP_CTL_0        (ROULEUR_DIG_BASE_ADDR+0x04F)
+#define ROULEUR_DIG_SWR_CDC_RX_DELAY_CTL      (ROULEUR_DIG_BASE_ADDR+0x052)
+#define ROULEUR_DIG_SWR_CDC_RX_GAIN_0         (ROULEUR_DIG_BASE_ADDR+0x053)
+#define ROULEUR_DIG_SWR_CDC_RX_GAIN_1         (ROULEUR_DIG_BASE_ADDR+0x054)
+#define ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL       (ROULEUR_DIG_BASE_ADDR+0x057)
+#define ROULEUR_DIG_SWR_CDC_TX0_CTL           (ROULEUR_DIG_BASE_ADDR+0x060)
+#define ROULEUR_DIG_SWR_CDC_TX1_CTL           (ROULEUR_DIG_BASE_ADDR+0x061)
+#define ROULEUR_DIG_SWR_CDC_TX_RST            (ROULEUR_DIG_BASE_ADDR+0x063)
+#define ROULEUR_DIG_SWR_CDC_REQ0_CTL          (ROULEUR_DIG_BASE_ADDR+0x064)
+#define ROULEUR_DIG_SWR_CDC_REQ1_CTL          (ROULEUR_DIG_BASE_ADDR+0x065)
+#define ROULEUR_DIG_SWR_CDC_RST               (ROULEUR_DIG_BASE_ADDR+0x067)
+#define ROULEUR_DIG_SWR_CDC_AMIC_CTL          (ROULEUR_DIG_BASE_ADDR+0x06A)
+#define ROULEUR_DIG_SWR_CDC_DMIC_CTL          (ROULEUR_DIG_BASE_ADDR+0x06B)
+#define ROULEUR_DIG_SWR_CDC_DMIC1_CTL         (ROULEUR_DIG_BASE_ADDR+0x06C)
+#define ROULEUR_DIG_SWR_CDC_DMIC1_RATE        (ROULEUR_DIG_BASE_ADDR+0x06D)
+#define ROULEUR_DIG_SWR_PDM_WD_CTL0           (ROULEUR_DIG_BASE_ADDR+0x070)
+#define ROULEUR_DIG_SWR_PDM_WD_CTL1           (ROULEUR_DIG_BASE_ADDR+0x071)
+#define ROULEUR_DIG_SWR_INTR_MODE             (ROULEUR_DIG_BASE_ADDR+0x080)
+#define ROULEUR_DIG_SWR_INTR_MASK_0           (ROULEUR_DIG_BASE_ADDR+0x081)
+#define ROULEUR_DIG_SWR_INTR_MASK_1           (ROULEUR_DIG_BASE_ADDR+0x082)
+#define ROULEUR_DIG_SWR_INTR_MASK_2           (ROULEUR_DIG_BASE_ADDR+0x083)
+#define ROULEUR_DIG_SWR_INTR_STATUS_0         (ROULEUR_DIG_BASE_ADDR+0x084)
+#define ROULEUR_DIG_SWR_INTR_STATUS_1         (ROULEUR_DIG_BASE_ADDR+0x085)
+#define ROULEUR_DIG_SWR_INTR_STATUS_2         (ROULEUR_DIG_BASE_ADDR+0x086)
+#define ROULEUR_DIG_SWR_INTR_CLEAR_0          (ROULEUR_DIG_BASE_ADDR+0x087)
+#define ROULEUR_DIG_SWR_INTR_CLEAR_1          (ROULEUR_DIG_BASE_ADDR+0x088)
+#define ROULEUR_DIG_SWR_INTR_CLEAR_2          (ROULEUR_DIG_BASE_ADDR+0x089)
+#define ROULEUR_DIG_SWR_INTR_LEVEL_0          (ROULEUR_DIG_BASE_ADDR+0x08A)
+#define ROULEUR_DIG_SWR_INTR_LEVEL_1          (ROULEUR_DIG_BASE_ADDR+0x08B)
+#define ROULEUR_DIG_SWR_INTR_LEVEL_2          (ROULEUR_DIG_BASE_ADDR+0x08C)
+#define ROULEUR_DIG_SWR_CDC_CONN_RX0_CTL      (ROULEUR_DIG_BASE_ADDR+0x093)
+#define ROULEUR_DIG_SWR_CDC_CONN_RX1_CTL      (ROULEUR_DIG_BASE_ADDR+0x094)
+#define ROULEUR_DIG_SWR_LOOP_BACK_MODE        (ROULEUR_DIG_BASE_ADDR+0x097)
+#define ROULEUR_DIG_SWR_DRIVE_STRENGTH_0      (ROULEUR_DIG_BASE_ADDR+0x0A0)
+#define ROULEUR_DIG_SWR_DIG_DEBUG_CTL         (ROULEUR_DIG_BASE_ADDR+0x0AB)
+#define ROULEUR_DIG_SWR_DIG_DEBUG_EN          (ROULEUR_DIG_BASE_ADDR+0x0AC)
+#define ROULEUR_DIG_SWR_DEM_BYPASS_DATA0      (ROULEUR_DIG_BASE_ADDR+0x0B0)
+#define ROULEUR_DIG_SWR_DEM_BYPASS_DATA1      (ROULEUR_DIG_BASE_ADDR+0x0B1)
+#define ROULEUR_DIG_SWR_DEM_BYPASS_DATA2      (ROULEUR_DIG_BASE_ADDR+0x0B2)
+#define ROULEUR_DIG_SWR_DEM_BYPASS_DATA3      (ROULEUR_DIG_BASE_ADDR+0x0B3)
+
+#define ROULEUR_ANALOG_REGISTERS_MAX_SIZE (ROULEUR_ANA_BASE_ADDR+0x0B5)
+#define ROULEUR_DIGITAL_REGISTERS_MAX_SIZE (ROULEUR_DIG_BASE_ADDR+0x0B4)
+#define ROULEUR_ANALOG_MAX_REGISTER (ROULEUR_ANALOG_REGISTERS_MAX_SIZE - 1)
+#define ROULEUR_DIGITAL_MAX_REGISTER (ROULEUR_DIGITAL_REGISTERS_MAX_SIZE - 1)
+#endif

qcom/opensource/audio-kernel/asoc/codecs/rouleur/rouleur-regmap.c

@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "rouleur-registers.h"
+
+extern const u8 rouleur_reg_access_analog[
+			ROULEUR_REG(ROULEUR_ANALOG_REGISTERS_MAX_SIZE)];
+extern const u8 rouleur_reg_access_digital[
+			ROULEUR_REG(ROULEUR_DIGITAL_REGISTERS_MAX_SIZE)];
+
+static const struct reg_default rouleur_defaults[] = {
+	{ ROULEUR_ANA_MICBIAS_MICB_1_2_EN,        0x01 },
+	{ ROULEUR_ANA_MICBIAS_MICB_3_EN,          0x00 },
+	{ ROULEUR_ANA_MICBIAS_LDO_1_SETTING,      0x21 },
+	{ ROULEUR_ANA_MICBIAS_LDO_1_CTRL,         0x01 },
+	{ ROULEUR_ANA_TX_AMIC1,                   0x00 },
+	{ ROULEUR_ANA_TX_AMIC2,                   0x00 },
+	{ ROULEUR_ANA_MBHC_MECH,                  0x39 },
+	{ ROULEUR_ANA_MBHC_ELECT,                 0x08 },
+	{ ROULEUR_ANA_MBHC_ZDET,                  0x10 },
+	{ ROULEUR_ANA_MBHC_RESULT_1,              0x00 },
+	{ ROULEUR_ANA_MBHC_RESULT_2,              0x00 },
+	{ ROULEUR_ANA_MBHC_RESULT_3,              0x00 },
+	{ ROULEUR_ANA_MBHC_BTN0_ZDET_VREF1,       0x00 },
+	{ ROULEUR_ANA_MBHC_BTN1_ZDET_VREF2,       0x10 },
+	{ ROULEUR_ANA_MBHC_BTN2_ZDET_VREF3,       0x20 },
+	{ ROULEUR_ANA_MBHC_BTN3_ZDET_DBG_400,     0x30 },
+	{ ROULEUR_ANA_MBHC_BTN4_ZDET_DBG_1400,    0x40 },
+	{ ROULEUR_ANA_MBHC_MICB2_RAMP,            0x00 },
+	{ ROULEUR_ANA_MBHC_CTL_1,                 0x02 },
+	{ ROULEUR_ANA_MBHC_CTL_2,                 0x05 },
+	{ ROULEUR_ANA_MBHC_PLUG_DETECT_CTL,       0xE9 },
+	{ ROULEUR_ANA_MBHC_ZDET_ANA_CTL,          0x0F },
+	{ ROULEUR_ANA_MBHC_ZDET_RAMP_CTL,         0x00 },
+	{ ROULEUR_ANA_MBHC_FSM_STATUS,            0x00 },
+	{ ROULEUR_ANA_MBHC_ADC_RESULT,            0x00 },
+	{ ROULEUR_ANA_MBHC_CTL_CLK,               0x30 },
+	{ ROULEUR_ANA_MBHC_ZDET_CALIB_RESULT,     0x00 },
+	{ ROULEUR_ANA_NCP_EN,                     0x00 },
+	{ ROULEUR_ANA_NCP_VCTRL,                  0xA7 },
+	{ ROULEUR_ANA_HPHPA_CNP_CTL_1,            0x54 },
+	{ ROULEUR_ANA_HPHPA_CNP_CTL_2,            0x2B },
+	{ ROULEUR_ANA_HPHPA_PA_STATUS,            0x00 },
+	{ ROULEUR_ANA_HPHPA_FSM_CLK,              0x12 },
+	{ ROULEUR_ANA_HPHPA_L_GAIN,               0x00 },
+	{ ROULEUR_ANA_HPHPA_R_GAIN,               0x00 },
+	{ ROULEUR_SWR_HPHPA_HD2,                  0x1B },
+	{ ROULEUR_ANA_HPHPA_SPARE_CTL,            0x02 },
+	{ ROULEUR_ANA_SURGE_EN,                   0x38 },
+	{ ROULEUR_ANA_COMBOPA_CTL,                0x35 },
+	{ ROULEUR_ANA_COMBOPA_CTL_4,              0x84 },
+	{ ROULEUR_ANA_COMBOPA_CTL_5,              0x05 },
+	{ ROULEUR_ANA_RXLDO_CTL,                  0x86 },
+	{ ROULEUR_ANA_MBIAS_EN,                   0x00 },
+	{ ROULEUR_DIG_SWR_CHIP_ID0,               0x00 },
+	{ ROULEUR_DIG_SWR_CHIP_ID1,               0x00 },
+	{ ROULEUR_DIG_SWR_CHIP_ID2,               0x0C },
+	{ ROULEUR_DIG_SWR_CHIP_ID3,               0x01 },
+	{ ROULEUR_DIG_SWR_SWR_TX_CLK_RATE,        0x00 },
+	{ ROULEUR_DIG_SWR_CDC_RST_CTL,            0x03 },
+	{ ROULEUR_DIG_SWR_TOP_CLK_CFG,            0x00 },
+	{ ROULEUR_DIG_SWR_CDC_RX_CLK_CTL,         0x00 },
+	{ ROULEUR_DIG_SWR_CDC_TX_CLK_CTL,         0x33 },
+	{ ROULEUR_DIG_SWR_SWR_RST_EN,             0x00 },
+	{ ROULEUR_DIG_SWR_CDC_RX_RST,             0x00 },
+	{ ROULEUR_DIG_SWR_CDC_RX0_CTL,            0xFC },
+	{ ROULEUR_DIG_SWR_CDC_RX1_CTL,            0xFC },
+	{ ROULEUR_DIG_SWR_CDC_TX_ANA_MODE_0_1,    0x00 },
+	{ ROULEUR_DIG_SWR_CDC_COMP_CTL_0,         0x00 },
+	{ ROULEUR_DIG_SWR_CDC_RX_DELAY_CTL,       0x66 },
+	{ ROULEUR_DIG_SWR_CDC_RX_GAIN_0,          0x55 },
+	{ ROULEUR_DIG_SWR_CDC_RX_GAIN_1,          0xA9 },
+	{ ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL,        0x00 },
+	{ ROULEUR_DIG_SWR_CDC_TX0_CTL,            0x68 },
+	{ ROULEUR_DIG_SWR_CDC_TX1_CTL,            0x68 },
+	{ ROULEUR_DIG_SWR_CDC_TX_RST,             0x00 },
+	{ ROULEUR_DIG_SWR_CDC_REQ0_CTL,           0x01 },
+	{ ROULEUR_DIG_SWR_CDC_REQ1_CTL,           0x01 },
+	{ ROULEUR_DIG_SWR_CDC_RST,                0x00 },
+	{ ROULEUR_DIG_SWR_CDC_AMIC_CTL,           0x02 },
+	{ ROULEUR_DIG_SWR_CDC_DMIC_CTL,           0x00 },
+	{ ROULEUR_DIG_SWR_CDC_DMIC1_CTL,          0x00 },
+	{ ROULEUR_DIG_SWR_CDC_DMIC1_RATE,         0x01 },
+	{ ROULEUR_DIG_SWR_PDM_WD_CTL0,            0x00 },
+	{ ROULEUR_DIG_SWR_PDM_WD_CTL1,            0x00 },
+	{ ROULEUR_DIG_SWR_INTR_MODE,              0x00 },
+	{ ROULEUR_DIG_SWR_INTR_MASK_0,            0xFF },
+	{ ROULEUR_DIG_SWR_INTR_MASK_1,            0x7F },
+	{ ROULEUR_DIG_SWR_INTR_MASK_2,            0x0C },
+	{ ROULEUR_DIG_SWR_INTR_STATUS_0,          0x00 },
+	{ ROULEUR_DIG_SWR_INTR_STATUS_1,          0x00 },
+	{ ROULEUR_DIG_SWR_INTR_STATUS_2,          0x00 },
+	{ ROULEUR_DIG_SWR_INTR_CLEAR_0,           0x00 },
+	{ ROULEUR_DIG_SWR_INTR_CLEAR_1,           0x00 },
+	{ ROULEUR_DIG_SWR_INTR_CLEAR_2,           0x00 },
+	{ ROULEUR_DIG_SWR_INTR_LEVEL_0,           0x00 },
+	{ ROULEUR_DIG_SWR_INTR_LEVEL_1,           0x2A },
+	{ ROULEUR_DIG_SWR_INTR_LEVEL_2,           0x00 },
+	{ ROULEUR_DIG_SWR_CDC_CONN_RX0_CTL,       0x00 },
+	{ ROULEUR_DIG_SWR_CDC_CONN_RX1_CTL,       0x00 },
+	{ ROULEUR_DIG_SWR_LOOP_BACK_MODE,         0x00 },
+	{ ROULEUR_DIG_SWR_DRIVE_STRENGTH_0,       0x00 },
+	{ ROULEUR_DIG_SWR_DIG_DEBUG_CTL,          0x00 },
+	{ ROULEUR_DIG_SWR_DIG_DEBUG_EN,           0x00 },
+	{ ROULEUR_DIG_SWR_DEM_BYPASS_DATA0,       0x55 },
+	{ ROULEUR_DIG_SWR_DEM_BYPASS_DATA1,       0x55 },
+	{ ROULEUR_DIG_SWR_DEM_BYPASS_DATA2,       0x55 },
+	{ ROULEUR_DIG_SWR_DEM_BYPASS_DATA3,       0x01 },
+};
+
+static bool rouleur_readable_register(struct device *dev, unsigned int reg)
+{
+	if (reg > ROULEUR_ANA_BASE_ADDR && reg <
+				ROULEUR_ANALOG_REGISTERS_MAX_SIZE)
+		return rouleur_reg_access_analog[ROULEUR_REG(reg)] & RD_REG;
+	if (reg > ROULEUR_DIG_BASE_ADDR && reg <
+				ROULEUR_DIGITAL_REGISTERS_MAX_SIZE)
+		return rouleur_reg_access_digital[ROULEUR_REG(reg)] & RD_REG;
+	return 0;
+}
+
+static bool rouleur_writeable_register(struct device *dev, unsigned int reg)
+{
+	if (reg > ROULEUR_ANA_BASE_ADDR && reg <
+					ROULEUR_ANALOG_REGISTERS_MAX_SIZE)
+		return rouleur_reg_access_analog[ROULEUR_REG(reg)] & WR_REG;
+	if (reg > ROULEUR_DIG_BASE_ADDR && reg <
+					ROULEUR_DIGITAL_REGISTERS_MAX_SIZE)
+		return rouleur_reg_access_digital[ROULEUR_REG(reg)] & WR_REG;
+	return 0;
+}
+
+static bool rouleur_volatile_register(struct device *dev, unsigned int reg)
+{
+	if (reg > ROULEUR_ANA_BASE_ADDR && reg <
+					ROULEUR_ANALOG_REGISTERS_MAX_SIZE)
+		if ((rouleur_reg_access_analog[ROULEUR_REG(reg)] & RD_REG)
+		    && !(rouleur_reg_access_analog[ROULEUR_REG(reg)] & WR_REG))
+			return true;
+	if (reg > ROULEUR_DIG_BASE_ADDR && reg <
+					ROULEUR_DIGITAL_REGISTERS_MAX_SIZE)
+		if ((rouleur_reg_access_digital[ROULEUR_REG(reg)] & RD_REG)
+		    && !(rouleur_reg_access_digital[ROULEUR_REG(reg)] & WR_REG))
+			return true;
+	return 0;
+}
+
+struct regmap_config rouleur_regmap_config = {
+	.name = "rouleur_csr",
+	.reg_bits = 16,
+	.val_bits = 8,
+	.cache_type = REGCACHE_RBTREE,
+	.reg_defaults = rouleur_defaults,
+	.num_reg_defaults = ARRAY_SIZE(rouleur_defaults),
+	.max_register = ROULEUR_ANALOG_MAX_REGISTER +
+				ROULEUR_DIGITAL_MAX_REGISTER,
+	.readable_reg = rouleur_readable_register,
+	.writeable_reg = rouleur_writeable_register,
+	.volatile_reg = rouleur_volatile_register,
+	.can_multi_write = true,
+};

qcom/opensource/audio-kernel/asoc/codecs/rouleur/rouleur-tables.c

@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include "rouleur-registers.h"
+
+const u8 rouleur_reg_access_analog[ROULEUR_REG(
+			ROULEUR_ANALOG_REGISTERS_MAX_SIZE)] = {
+	[ROULEUR_REG(ROULEUR_ANA_MICBIAS_MICB_1_2_EN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MICBIAS_MICB_3_EN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MICBIAS_LDO_1_SETTING)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MICBIAS_LDO_1_CTRL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_TX_AMIC1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_TX_AMIC2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_MECH)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_ELECT)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_ZDET)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_RESULT_1)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_RESULT_2)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_RESULT_3)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_BTN0_ZDET_VREF1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_BTN1_ZDET_VREF2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_BTN2_ZDET_VREF3)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_BTN3_ZDET_DBG_400)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_BTN4_ZDET_DBG_1400)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_MICB2_RAMP)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_CTL_1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_CTL_2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_PLUG_DETECT_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_ZDET_ANA_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_ZDET_RAMP_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_FSM_STATUS)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_ADC_RESULT)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_CTL_CLK)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBHC_ZDET_CALIB_RESULT)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_ANA_NCP_EN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_NCP_VCTRL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_HPHPA_CNP_CTL_1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_HPHPA_CNP_CTL_2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_HPHPA_PA_STATUS)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_ANA_HPHPA_FSM_CLK)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_HPHPA_L_GAIN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_HPHPA_R_GAIN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_HPHPA_SPARE_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_SWR_HPHPA_HD2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_SURGE_EN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_COMBOPA_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_COMBOPA_CTL_4)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_COMBOPA_CTL_5)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_RXLDO_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_ANA_MBIAS_EN)] = RD_WR_REG,
+};
+
+const u8 rouleur_reg_access_digital[ROULEUR_REG(
+			ROULEUR_DIGITAL_REGISTERS_MAX_SIZE)] = {
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CHIP_ID0)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CHIP_ID1)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CHIP_ID2)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CHIP_ID3)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_SWR_TX_CLK_RATE)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RST_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_TOP_CLK_CFG)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX_CLK_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_TX_CLK_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_SWR_RST_EN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX_RST)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX0_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX1_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_TX_ANA_MODE_0_1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_COMP_CTL_0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX_DELAY_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX_GAIN_0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX_GAIN_1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RX_GAIN_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_TX0_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_TX1_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_TX_RST)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_REQ0_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_REQ1_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_RST)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_AMIC_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_DMIC_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_DMIC1_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_DMIC1_RATE)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_PDM_WD_CTL0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_PDM_WD_CTL1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_MODE)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_MASK_0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_MASK_1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_MASK_2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_STATUS_0)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_STATUS_1)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_STATUS_2)] = RD_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_CLEAR_0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_CLEAR_1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_CLEAR_2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_LEVEL_0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_LEVEL_1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_INTR_LEVEL_2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_CONN_RX0_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_CDC_CONN_RX1_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_LOOP_BACK_MODE)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_DRIVE_STRENGTH_0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_DIG_DEBUG_CTL)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_DIG_DEBUG_EN)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_DEM_BYPASS_DATA0)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_DEM_BYPASS_DATA1)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_DEM_BYPASS_DATA2)] = RD_WR_REG,
+	[ROULEUR_REG(ROULEUR_DIG_SWR_DEM_BYPASS_DATA3)] = RD_WR_REG,
+};

qcom/opensource/audio-kernel/asoc/codecs/rouleur/rouleur.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _ROULEUR_H
+#define _ROULEUR_H
+
+#ifdef CONFIG_SND_SOC_ROULEUR
+extern int rouleur_info_create_codec_entry(struct snd_info_entry *codec_root,
+				    struct snd_soc_component *component);
+#else
+extern int rouleur_info_create_codec_entry(struct snd_info_entry *codec_root,
+				    struct snd_soc_component *component)
+{
+	return 0;
+}
+#endif /* CONFIG_SND_SOC_ROULEUR */
+
+#endif

qcom/opensource/audio-kernel/asoc/codecs/rouleur/rouleur_slave.c

@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/component.h>
+#include <soc/soundwire.h>
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+
+#define SWR_SLV_MAX_REG_ADDR    0x2009
+#define SWR_SLV_START_REG_ADDR  0x40
+#define SWR_SLV_MAX_BUF_LEN     20
+#define BYTES_PER_LINE          12
+#define SWR_SLV_RD_BUF_LEN      8
+#define SWR_SLV_WR_BUF_LEN      32
+#define SWR_SLV_MAX_DEVICES     2
+#endif /* CONFIG_DEBUG_FS */
+
+struct rouleur_slave_priv {
+	struct swr_device *swr_slave;
+#ifdef CONFIG_DEBUG_FS
+	struct dentry *debugfs_rouleur_dent;
+	struct dentry *debugfs_peek;
+	struct dentry *debugfs_poke;
+	struct dentry *debugfs_reg_dump;
+	unsigned int read_data;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_FS
+static int codec_debug_open(struct inode *inode, struct file *file)
+{
+	file->private_data = inode->i_private;
+	return 0;
+}
+
+static int get_parameters(char *buf, u32 *param1, int num_of_par)
+{
+	char *token = NULL;
+	int base = 0, cnt = 0;
+
+	token = strsep(&buf, " ");
+	for (cnt = 0; cnt < num_of_par; cnt++) {
+		if (token) {
+			if ((token[1] == 'x') || (token[1] == 'X'))
+				base = 16;
+			else
+				base = 10;
+
+			if (kstrtou32(token, base, &param1[cnt]) != 0)
+				return -EINVAL;
+
+			token = strsep(&buf, " ");
+		} else {
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+static bool is_swr_slv_reg_readable(int reg)
+{
+	int ret = true;
+
+	if (((reg > 0x46) && (reg < 0x4A)) ||
+	    ((reg > 0x4A) && (reg < 0x50)) ||
+	    ((reg > 0x55) && (reg < 0xD0)) ||
+	    ((reg > 0xD0) && (reg < 0xE0)) ||
+	    ((reg > 0xE0) && (reg < 0xF0)) ||
+	    ((reg > 0xF0) && (reg < 0x100)) ||
+	    ((reg > 0x105) && (reg < 0x120)) ||
+	    ((reg > 0x205) && (reg < 0x220)) ||
+	    ((reg > 0x305) && (reg < 0x320)) ||
+	    ((reg > 0x405) && (reg < 0x420)) ||
+	    ((reg > 0x128) && (reg < 0x130)) ||
+	    ((reg > 0x228) && (reg < 0x230)) ||
+	    ((reg > 0x328) && (reg < 0x330)) ||
+	    ((reg > 0x428) && (reg < 0x430)) ||
+	    ((reg > 0x138) && (reg < 0x205)) ||
+	    ((reg > 0x238) && (reg < 0x305)) ||
+	    ((reg > 0x338) && (reg < 0x405)) ||
+	    ((reg > 0x405) && (reg < 0xF00)) ||
+	    ((reg > 0xF05) && (reg < 0xF20)) ||
+	    ((reg > 0xF25) && (reg < 0xF30)) ||
+	    ((reg > 0xF35) && (reg < 0x2000)))
+		ret = false;
+
+	return ret;
+}
+
+static ssize_t rouleur_swrslave_reg_show(struct swr_device *pdev,
+					char __user *ubuf,
+					size_t count, loff_t *ppos)
+{
+	int i, reg_val, len;
+	ssize_t total = 0;
+	char tmp_buf[SWR_SLV_MAX_BUF_LEN];
+
+	if (!ubuf || !ppos)
+		return 0;
+
+	for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
+		i <= SWR_SLV_MAX_REG_ADDR; i++) {
+		if (!is_swr_slv_reg_readable(i))
+			continue;
+		swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
+		len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
+			       (reg_val & 0xFF));
+		if (len < 0) {
+			pr_err("%s: fail to fill the buffer\n", __func__);
+			total = -EFAULT;
+			goto copy_err;
+		}
+		if (((total + len) >= count - 1) || (len < 0))
+			break;
+		if (copy_to_user((ubuf + total), tmp_buf, len)) {
+			pr_err("%s: fail to copy reg dump\n", __func__);
+			total = -EFAULT;
+			goto copy_err;
+		}
+		total += len;
+		*ppos += len;
+	}
+
+copy_err:
+	*ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
+	return total;
+}
+
+static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	struct swr_device *pdev;
+
+	if (!count || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	return rouleur_swrslave_reg_show(pdev, ubuf, count, ppos);
+}
+
+static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
+				size_t count, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_RD_BUF_LEN];
+	struct swr_device *pdev = NULL;
+	struct rouleur_slave_priv *rouleur_slave = NULL;
+
+	if (!count || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	rouleur_slave = swr_get_dev_data(pdev);
+	if (!rouleur_slave)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	snprintf(lbuf, sizeof(lbuf), "0x%x\n",
+			(rouleur_slave->read_data & 0xFF));
+
+	return simple_read_from_buffer(ubuf, count, ppos, lbuf,
+					       strnlen(lbuf, 7));
+}
+
+static ssize_t codec_debug_peek_write(struct file *file,
+	const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_WR_BUF_LEN];
+	int rc = 0;
+	u32 param[5];
+	struct swr_device *pdev = NULL;
+	struct rouleur_slave_priv *rouleur_slave = NULL;
+
+	if (!cnt || !file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	rouleur_slave = swr_get_dev_data(pdev);
+	if (!rouleur_slave)
+		return -EINVAL;
+
+	if (*ppos < 0)
+		return -EINVAL;
+
+	if (cnt > sizeof(lbuf) - 1)
+		return -EINVAL;
+
+	rc = copy_from_user(lbuf, ubuf, cnt);
+	if (rc)
+		return -EFAULT;
+
+	lbuf[cnt] = '\0';
+	rc = get_parameters(lbuf, param, 1);
+	if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
+		return -EINVAL;
+	swr_read(pdev, pdev->dev_num, param[0], &rouleur_slave->read_data, 1);
+	if (rc == 0)
+		rc = cnt;
+	else
+		pr_err("%s: rc = %d\n", __func__, rc);
+
+	return rc;
+}
+
+static ssize_t codec_debug_write(struct file *file,
+	const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+	char lbuf[SWR_SLV_WR_BUF_LEN];
+	int rc = 0;
+	u32 param[5];
+	struct swr_device *pdev;
+
+	if (!file || !ppos || !ubuf)
+		return -EINVAL;
+
+	pdev = file->private_data;
+	if (!pdev)
+		return -EINVAL;
+
+	if (cnt > sizeof(lbuf) - 1)
+		return -EINVAL;
+
+	rc = copy_from_user(lbuf, ubuf, cnt);
+	if (rc)
+		return -EFAULT;
+
+	lbuf[cnt] = '\0';
+	rc = get_parameters(lbuf, param, 2);
+	if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
+		(param[1] <= 0xFF) && (rc == 0)))
+		return -EINVAL;
+	swr_write(pdev, pdev->dev_num, param[0], &param[1]);
+	if (rc == 0)
+		rc = cnt;
+	else
+		pr_err("%s: rc = %d\n", __func__, rc);
+
+	return rc;
+}
+
+static const struct file_operations codec_debug_write_ops = {
+	.open = codec_debug_open,
+	.write = codec_debug_write,
+};
+
+static const struct file_operations codec_debug_read_ops = {
+	.open = codec_debug_open,
+	.read = codec_debug_read,
+	.write = codec_debug_peek_write,
+};
+
+static const struct file_operations codec_debug_dump_ops = {
+	.open = codec_debug_open,
+	.read = codec_debug_dump,
+};
+#endif
+
+static int rouleur_slave_bind(struct device *dev,
+				struct device *master, void *data)
+{
+	int ret = 0;
+	uint8_t devnum = 0;
+	struct swr_device *pdev = to_swr_device(dev);
+
+	if (pdev == NULL) {
+		dev_err(dev, "%s: pdev is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
+	if (ret) {
+		dev_dbg(&pdev->dev,
+				"%s get devnum %d for dev addr %lx failed\n",
+				__func__, devnum, pdev->addr);
+		swr_remove_device(pdev);
+		return ret;
+	}
+	pdev->dev_num = devnum;
+
+	return ret;
+}
+
+static void rouleur_slave_unbind(struct device *dev,
+				struct device *master, void *data)
+{
+	struct rouleur_slave_priv *rouleur_slave = NULL;
+	struct swr_device *pdev = to_swr_device(dev);
+
+	if (pdev == NULL) {
+		dev_err(dev, "%s: pdev is NULL\n", __func__);
+		return;
+	}
+
+	rouleur_slave = swr_get_dev_data(pdev);
+	if (!rouleur_slave) {
+		dev_err(&pdev->dev, "%s: rouleur_slave is NULL\n", __func__);
+		return;
+	}
+
+}
+
+static const struct swr_device_id rouleur_swr_id[] = {
+	{"rouleur-slave", 0},
+	{}
+};
+
+static const struct of_device_id rouleur_swr_dt_match[] = {
+	{
+		.compatible = "qcom,rouleur-slave",
+	},
+	{}
+};
+
+static const struct component_ops rouleur_slave_comp_ops = {
+	.bind   = rouleur_slave_bind,
+	.unbind = rouleur_slave_unbind,
+};
+
+static int rouleur_swr_up(struct swr_device *pdev)
+{
+	return 0;
+}
+
+static int rouleur_swr_down(struct swr_device *pdev)
+{
+	return 0;
+}
+
+static int rouleur_swr_reset(struct swr_device *pdev)
+{
+	return 0;
+}
+
+static int rouleur_swr_probe(struct swr_device *pdev)
+{
+	struct rouleur_slave_priv *rouleur_slave = NULL;
+
+	rouleur_slave = devm_kzalloc(&pdev->dev,
+				sizeof(struct rouleur_slave_priv), GFP_KERNEL);
+	if (!rouleur_slave)
+		return -ENOMEM;
+
+	swr_set_dev_data(pdev, rouleur_slave);
+
+	rouleur_slave->swr_slave = pdev;
+#ifdef CONFIG_DEBUG_FS
+	if (!rouleur_slave->debugfs_rouleur_dent) {
+		rouleur_slave->debugfs_rouleur_dent = debugfs_create_dir(
+						dev_name(&pdev->dev), 0);
+		if (!IS_ERR(rouleur_slave->debugfs_rouleur_dent)) {
+			rouleur_slave->debugfs_peek =
+					debugfs_create_file("swrslave_peek",
+					S_IFREG | 0444,
+					rouleur_slave->debugfs_rouleur_dent,
+					(void *) pdev,
+					&codec_debug_read_ops);
+
+			rouleur_slave->debugfs_poke =
+					debugfs_create_file("swrslave_poke",
+					S_IFREG | 0444,
+					rouleur_slave->debugfs_rouleur_dent,
+					(void *) pdev,
+					&codec_debug_write_ops);
+
+			rouleur_slave->debugfs_reg_dump =
+					debugfs_create_file(
+					"swrslave_reg_dump",
+					S_IFREG | 0444,
+					rouleur_slave->debugfs_rouleur_dent,
+					(void *) pdev,
+					&codec_debug_dump_ops);
+                }
+        }
+#endif
+	return component_add(&pdev->dev, &rouleur_slave_comp_ops);
+}
+
+static int rouleur_swr_remove(struct swr_device *pdev)
+{
+#ifdef CONFIG_DEBUG_FS
+	struct rouleur_slave_priv *rouleur_slave = swr_get_dev_data(pdev);
+
+	if (rouleur_slave) {
+		debugfs_remove_recursive(rouleur_slave->debugfs_rouleur_dent);
+		rouleur_slave->debugfs_rouleur_dent = NULL;
+	}
+#endif
+	component_del(&pdev->dev, &rouleur_slave_comp_ops);
+	swr_set_dev_data(pdev, NULL);
+	swr_remove_device(pdev);
+	return 0;
+}
+
+static struct swr_driver rouleur_slave_driver = {
+	.driver = {
+		.name = "rouleur-slave",
+		.owner = THIS_MODULE,
+		.of_match_table = rouleur_swr_dt_match,
+	},
+	.probe = rouleur_swr_probe,
+	.remove = rouleur_swr_remove,
+	.id_table = rouleur_swr_id,
+	.device_up = rouleur_swr_up,
+	.device_down = rouleur_swr_down,
+	.reset_device = rouleur_swr_reset,
+};
+
+static int __init rouleur_slave_init(void)
+{
+	return swr_driver_register(&rouleur_slave_driver);
+}
+
+static void __exit rouleur_slave_exit(void)
+{
+	swr_driver_unregister(&rouleur_slave_driver);
+}
+
+module_init(rouleur_slave_init);
+module_exit(rouleur_slave_exit);
+
+MODULE_DESCRIPTION("Rouleur Swr Slave driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/swr-dmic.c

@@ -0,0 +1,937 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/printk.h>
+#include <linux/bitops.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/debugfs.h>
+#include <soc/soundwire.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/tlv.h>
+#include <asoc/msm-cdc-pinctrl.h>
+#include <asoc/msm-cdc-supply.h>
+#include <bindings/audio-codec-port-types.h>
+#ifdef CONFIG_SND_SOC_WCD939X
+#include "wcd939x/wcd939x.h"
+#else
+#include "wcd938x/wcd938x.h"
+#endif
+#include "swr-dmic.h"
+
+#define NUM_ATTEMPTS 5
+#define SWRS_SCP_CONTROL    0x44
+
+#define MAX_NAME_LEN 40
+
+static int swr_master_channel_map[] = {
+	ZERO,
+	SWRM_TX_PCM_OUT,
+	SWRM_TX1_CH1,
+	SWRM_TX1_CH2,
+	SWRM_TX1_CH3,
+	SWRM_TX1_CH4,
+	SWRM_TX2_CH1,
+	SWRM_TX2_CH2,
+	SWRM_TX2_CH3,
+	SWRM_TX2_CH4,
+	SWRM_TX3_CH1,
+	SWRM_TX3_CH2,
+	SWRM_TX3_CH3,
+	SWRM_TX3_CH4,
+	SWRM_TX_PCM_IN,
+};
+
+/*
+ * Private data Structure for swr-dmic. All parameters related to
+ * external mic codec needs to be defined here.
+ */
+struct swr_dmic_priv {
+	struct device *dev;
+	struct swr_device *swr_slave;
+	struct snd_soc_component *component;
+	struct snd_soc_component_driver *driver;
+	struct snd_soc_dai_driver *dai_driver;
+	struct snd_soc_component *supply_component;
+	u32 micb_num;
+	struct device_node *wcd_handle;
+	bool is_wcd_supply;
+	int is_en_supply;
+	u8 tx_master_port_map[SWR_DMIC_MAX_PORTS];
+	struct swr_port_params tx_port_params[SWR_UC_MAX][SWR_DMIC_MAX_PORTS];
+	struct swr_dev_frame_config swr_tx_port_params[SWR_UC_MAX];
+	struct notifier_block nblock;
+};
+
+const char *codec_name_list[] = {
+	"swr-dmic.01",
+	"swr-dmic.02",
+	"swr-dmic.03",
+	"swr-dmic.04",
+};
+
+const char *dai_name_list[] = {
+	"swr_dmic_tx0",
+	"swr_dmic_tx1",
+	"swr_dmic_tx2",
+	"swr_dmic_tx3",
+};
+
+const char *aif_name_list[] = {
+	"SWR_DMIC_AIF0 Capture",
+	"SWR_DMIC_AIF1 Capture",
+	"SWR_DMIC_AIF2 Capture",
+	"SWR_DMIC_AIF3 Capture",
+};
+
+static int swr_dmic_reset(struct swr_device *pdev);
+static int swr_dmic_up(struct swr_device *pdev);
+static int swr_dmic_down(struct swr_device *pdev);
+static int swr_dmic_event_notify(struct notifier_block *block,
+				unsigned long val,
+				void *data);
+
+static inline int swr_dmic_tx_get_slave_port_type_idx(const char *wname,
+				      unsigned int *port_idx)
+{
+	u8 port_type;
+
+	if (strnstr(wname, "HIFI", strlen(wname)))
+		port_type = SWR_DMIC_HIFI_PORT;
+	else if (strnstr(wname, "LP", strlen(wname)))
+		port_type = SWR_DMIC_LP_PORT;
+	else
+		return -EINVAL;
+
+	*port_idx = port_type;
+	return 0;
+}
+
+static inline int swr_dmic_get_master_port_val(int port)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(swr_master_channel_map); i++)
+		if (port == swr_master_channel_map[i])
+			return i;
+	return 0;
+}
+
+static int swr_dmic_tx_master_port_get(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct swr_dmic_priv *swr_dmic = NULL;
+	int ret = 0;
+	unsigned int slave_port_idx = SWR_DMIC_MAX_PORTS;
+
+	if (NULL == component) {
+		pr_err_ratelimited("%s: swr dmic component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	swr_dmic = snd_soc_component_get_drvdata(component);
+	if (NULL == swr_dmic) {
+		pr_err_ratelimited("%s: swr_dmic_priv is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = swr_dmic_tx_get_slave_port_type_idx(kcontrol->id.name,
+							&slave_port_idx);
+	if (ret) {
+		dev_dbg(component->dev, "%s: invalid port string\n", __func__);
+		return ret;
+	}
+
+	if (slave_port_idx >= SWR_DMIC_MAX_PORTS) {
+		pr_err_ratelimited("%s: invalid slave port id\n", __func__);
+		return -EINVAL;
+	}
+
+	ucontrol->value.integer.value[0] =
+			swr_dmic_get_master_port_val(
+				swr_dmic->tx_master_port_map[slave_port_idx]);
+
+	dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
+			__func__, ucontrol->value.integer.value[0]);
+
+	return 0;
+}
+
+static int swr_dmic_tx_master_port_put(struct snd_kcontrol *kcontrol,
+					struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+				snd_soc_kcontrol_component(kcontrol);
+	struct swr_dmic_priv *swr_dmic = NULL;
+	int ret = 0;
+	unsigned int slave_port_idx = SWR_DMIC_MAX_PORTS;
+	unsigned int idx = 0;
+
+	if (NULL == component) {
+		pr_err_ratelimited("%s: swr dmic component is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	swr_dmic = snd_soc_component_get_drvdata(component);
+	if (NULL == swr_dmic) {
+		pr_err_ratelimited("%s: swr_dmic_priv is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	ret  = swr_dmic_tx_get_slave_port_type_idx(kcontrol->id.name,
+							&slave_port_idx);
+	if (ret) {
+		dev_dbg(component->dev, "%s: invalid port string\n", __func__);
+		return ret;
+	}
+
+	if (slave_port_idx >= SWR_DMIC_MAX_PORTS) {
+		pr_err_ratelimited("%s: invalid slave port id\n", __func__);
+		return -EINVAL;
+	}
+
+	idx = ucontrol->value.enumerated.item[0];
+	if (idx < 0 || idx >= ARRAY_SIZE(swr_master_channel_map))
+		return -EINVAL;
+
+	swr_dmic->tx_master_port_map[slave_port_idx] =
+			swr_master_channel_map[idx];
+	dev_dbg(component->dev, "%s: slv port id: %d, master_port_type: %d\n",
+		__func__, slave_port_idx,
+		swr_dmic->tx_master_port_map[slave_port_idx]);
+
+	return 0;
+}
+
+static int swr_dmic_port_enable(struct snd_soc_dapm_widget *w,
+			 struct snd_kcontrol *kcontrol, int event)
+{
+	int ret = 0;
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct swr_dmic_priv *swr_dmic =
+			snd_soc_component_get_drvdata(component);
+
+	u8 ch_mask = 0x01; /* only DpnChannelEN1 register is available */
+	u8 num_port = 1;
+	u8 port_id = w->shift;
+	u8 port_type = swr_dmic->tx_master_port_map[port_id];
+
+	switch (event) {
+	case SND_SOC_DAPM_POST_PMU:
+		ret = swr_slvdev_datapath_control(swr_dmic->swr_slave,
+			swr_dmic->swr_slave->dev_num, true);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		ret = swr_disconnect_port(swr_dmic->swr_slave,
+				&port_id, num_port, &ch_mask, &port_type);
+		break;
+	};
+
+	return ret;
+}
+
+static int dmic_swr_ctrl(struct snd_soc_dapm_widget *w,
+			 struct snd_kcontrol *kcontrol, int event)
+{
+	int ret = 0;
+	struct snd_soc_component *component =
+			snd_soc_dapm_to_component(w->dapm);
+	struct swr_dmic_priv *swr_dmic =
+			snd_soc_component_get_drvdata(component);
+
+	u8 num_ch = 1;
+	u8 ch_mask = 0x01; /* only DpnChannelEN1 register is available */
+	u32 ch_rate = SWR_CLK_RATE_4P8MHZ;
+	u8 num_port = 1;
+	u8 port_type = 0;
+	u8 port_id = w->shift;
+
+	if (port_id >= SWR_DMIC_MAX_PORTS)
+	{
+		dev_err_ratelimited(component->dev, "%s: invalid port id: %d\n",
+			__func__, port_id);
+		return -EINVAL;
+	}
+
+	/*
+	 * Port 1 is high quality / 2.4 or 3.072 Mbps
+	 * Port 2 is listen low power / 0.6 or 0.768 Mbps
+	 */
+	if (port_id == SWR_DMIC_HIFI_PORT)
+		ch_rate = SWR_CLK_RATE_2P4MHZ;
+	else
+		ch_rate = SWR_CLK_RATE_0P6MHZ;
+
+	port_type = swr_dmic->tx_master_port_map[port_id];
+
+	dev_dbg(component->dev, "%s port_type: %d event: %d\n", __func__,
+		port_type, event);
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		ret = swr_connect_port(swr_dmic->swr_slave, &port_id,
+					num_port, &ch_mask, &ch_rate,
+					&num_ch, &port_type);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		ret = swr_slvdev_datapath_control(swr_dmic->swr_slave,
+			swr_dmic->swr_slave->dev_num, false);
+		break;
+	};
+
+	return ret;
+}
+
+/* qcom,swr-tx-port-params = <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL5 LANE0>, *UC0*
+			<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, *UC1*
+			<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC2*
+			<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, *UC3 */
+static int swr_dmic_parse_port_params(struct device *dev,
+				      char *prop)
+{
+	int i, j;
+	u32 *dt_array, map_size, max_uc;
+	int ret = 0;
+	u32 cnt = 0;
+	struct swr_port_params (*map)[SWR_UC_MAX][SWR_DMIC_MAX_PORTS];
+	struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
+	struct swr_dmic_priv *swr_dmic = dev_get_drvdata(dev);
+
+	map = &swr_dmic->tx_port_params;
+	map_uc = &swr_dmic->swr_tx_port_params;
+
+	if (!of_find_property(dev->of_node, prop,
+				&map_size)) {
+		dev_err(dev, "missing port mapping prop %s\n", prop);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+
+	max_uc = map_size / (SWR_DMIC_MAX_PORTS * SWR_PORT_PARAMS * sizeof(u32));
+
+	if (max_uc != SWR_UC_MAX) {
+		dev_err(dev,
+			"%s:port params not provided for all usecases\n",
+			__func__);
+		ret = -EINVAL;
+		goto err_port_map;
+	}
+	dt_array = kzalloc(map_size, GFP_KERNEL);
+
+	if (!dt_array) {
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+	ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
+				SWR_DMIC_MAX_PORTS * SWR_PORT_PARAMS * max_uc);
+	if (ret) {
+		dev_err(dev, "%s: Failed to read  port mapping from prop %s\n",
+					__func__, prop);
+		goto err_pdata_fail;
+	}
+
+	for (i = 0; i < max_uc; i++) {
+		for (j = 0; j < SWR_DMIC_MAX_PORTS; j++) {
+			cnt = (i * SWR_DMIC_MAX_PORTS + j) * SWR_PORT_PARAMS;
+			(*map)[i][j].offset1 = dt_array[cnt];
+			(*map)[i][j].lane_ctrl = dt_array[cnt + 1];
+			dev_err(dev, "%s: port %d, uc: %d, offset1:%d, lane: %d\n",
+				__func__, j, i, dt_array[cnt], dt_array[cnt + 1]);
+		}
+		(*map_uc)[i].pp = &(*map)[i][0];
+	}
+	kfree(dt_array);
+	return 0;
+
+err_pdata_fail:
+	kfree(dt_array);
+err_alloc:
+err_port_map:
+	return ret;
+}
+
+static const char * const tx_master_port_text[] = {
+	"ZERO", "SWRM_PCM_OUT", "SWRM_TX1_CH1", "SWRM_TX1_CH2", "SWRM_TX1_CH3",
+	"SWRM_TX1_CH4", "SWRM_TX2_CH1", "SWRM_TX2_CH2", "SWRM_TX2_CH3",
+	"SWRM_TX2_CH4", "SWRM_TX3_CH1", "SWRM_TX3_CH2", "SWRM_TX3_CH3",
+	"SWRM_TX3_CH4", "SWRM_PCM_IN",
+};
+
+static const struct soc_enum tx_master_port_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tx_master_port_text),
+				tx_master_port_text);
+
+static const struct snd_kcontrol_new swr_dmic_snd_controls[] = {
+	SOC_ENUM_EXT("HIFI PortMap", tx_master_port_enum,
+		swr_dmic_tx_master_port_get, swr_dmic_tx_master_port_put),
+	SOC_ENUM_EXT("LP PortMap", tx_master_port_enum,
+		swr_dmic_tx_master_port_get, swr_dmic_tx_master_port_put),
+};
+
+static const struct snd_kcontrol_new dmic_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_kcontrol_new va_dmic_switch[] = {
+	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
+};
+
+static const struct snd_soc_dapm_widget swr_dmic_dapm_widgets[] = {
+	SND_SOC_DAPM_MIXER_E("SWR_DMIC_MIXER", SND_SOC_NOPM,
+			SWR_DMIC_HIFI_PORT, 0,
+			dmic_switch, ARRAY_SIZE(dmic_switch), dmic_swr_ctrl,
+			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_MIXER_E("SWR_DMIC_VA_MIXER", SND_SOC_NOPM,
+			SWR_DMIC_LP_PORT, 0,
+			va_dmic_switch, ARRAY_SIZE(va_dmic_switch), dmic_swr_ctrl,
+			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+
+	SND_SOC_DAPM_INPUT("SWR_DMIC"),
+	SND_SOC_DAPM_INPUT("VA_SWR_DMIC"),
+
+	SND_SOC_DAPM_OUT_DRV_E("SMIC_PORT_EN", SND_SOC_NOPM,
+				SWR_DMIC_HIFI_PORT, 0, NULL, 0,
+				swr_dmic_port_enable,
+				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+	SND_SOC_DAPM_OUT_DRV_E("SMIC_VA_PORT_EN", SND_SOC_NOPM,
+				SWR_DMIC_LP_PORT, 0, NULL, 0,
+				swr_dmic_port_enable,
+				SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+
+	SND_SOC_DAPM_OUTPUT("SWR_DMIC_OUTPUT"),
+	SND_SOC_DAPM_OUTPUT("SWR_DMIC_VA_OUTPUT"),
+};
+
+static const struct snd_soc_dapm_route swr_dmic_audio_map[] = {
+	{"SWR_DMIC_MIXER", "Switch", "SWR_DMIC"},
+	{"SMIC_PORT_EN", NULL, "SWR_DMIC_MIXER"},
+	{"SWR_DMIC_OUTPUT", NULL, "SMIC_PORT_EN"},
+	{"SWR_DMIC_VA_MIXER", "Switch", "VA_SWR_DMIC"},
+	{"SMIC_VA_PORT_EN", NULL, "SWR_DMIC_VA_MIXER"},
+	{"SWR_DMIC_VA_OUTPUT", NULL, "SMIC_VA_PORT_EN"},
+};
+
+static int swr_dmic_codec_probe(struct snd_soc_component *component)
+{
+	struct swr_dmic_priv *swr_dmic =
+			snd_soc_component_get_drvdata(component);
+	struct snd_soc_dapm_context *dapm =
+			snd_soc_component_get_dapm(component);
+	char w_name[MAX_NAME_LEN];
+
+	if (!swr_dmic)
+		return -EINVAL;
+
+	swr_dmic->component = component;
+	if (!component->name_prefix) {
+		dev_err(component->dev, "%s: component prefix is NULL\n", __func__);
+		return -EPROBE_DEFER;
+	}
+
+	memset(w_name, 0, sizeof(w_name));
+	strlcpy(w_name, component->name_prefix, sizeof(w_name));
+	strlcat(w_name, " ", sizeof(w_name));
+	strlcat(w_name, swr_dmic->dai_driver->capture.stream_name,
+				sizeof(w_name));
+	snd_soc_dapm_ignore_suspend(dapm, w_name);
+
+	memset(w_name, 0, sizeof(w_name));
+	strlcpy(w_name, component->name_prefix, sizeof(w_name));
+	strlcat(w_name, " SWR_DMIC", sizeof(w_name));
+	snd_soc_dapm_ignore_suspend(dapm, w_name);
+
+	memset(w_name, 0, sizeof(w_name));
+	strlcpy(w_name, component->name_prefix, sizeof(w_name));
+	strlcat(w_name, " SMIC_PORT_EN", sizeof(w_name));
+	snd_soc_dapm_ignore_suspend(dapm, w_name);
+
+	memset(w_name, 0, sizeof(w_name));
+	strlcpy(w_name, component->name_prefix, sizeof(w_name));
+	strlcat(w_name, " SWR_DMIC_OUTPUT", sizeof(w_name));
+	snd_soc_dapm_ignore_suspend(dapm, w_name);
+
+	memset(w_name, 0, sizeof(w_name));
+	strlcpy(w_name, component->name_prefix, sizeof(w_name));
+	strlcat(w_name, " VA_SWR_DMIC", sizeof(w_name));
+	snd_soc_dapm_ignore_suspend(dapm, w_name);
+
+	memset(w_name, 0, sizeof(w_name));
+	strlcpy(w_name, component->name_prefix, sizeof(w_name));
+	strlcat(w_name, " SMIC_VA_PORT_EN", sizeof(w_name));
+	snd_soc_dapm_ignore_suspend(dapm, w_name);
+
+	memset(w_name, 0, sizeof(w_name));
+	strlcpy(w_name, component->name_prefix, sizeof(w_name));
+	strlcat(w_name, " SWR_DMIC_VA_OUTPUT", sizeof(w_name));
+	snd_soc_dapm_ignore_suspend(dapm, w_name);
+
+	snd_soc_dapm_sync(dapm);
+
+	swr_dmic->nblock.notifier_call = swr_dmic_event_notify;
+#ifdef CONFIG_SND_SOC_WCD939X
+	wcd939x_swr_dmic_register_notifier(swr_dmic->supply_component,
+					&swr_dmic->nblock, true);
+#else
+	wcd938x_swr_dmic_register_notifier(swr_dmic->supply_component,
+					&swr_dmic->nblock, true);
+#endif
+
+	return 0;
+}
+
+static void swr_dmic_codec_remove(struct snd_soc_component *component)
+{
+	struct swr_dmic_priv *swr_dmic =
+			snd_soc_component_get_drvdata(component);
+
+	swr_dmic->component = NULL;
+	return;
+}
+
+static const struct snd_soc_component_driver soc_codec_dev_swr_dmic = {
+	.name = NULL,
+	.probe = swr_dmic_codec_probe,
+	.remove = swr_dmic_codec_remove,
+	.controls = swr_dmic_snd_controls,
+	.num_controls = ARRAY_SIZE(swr_dmic_snd_controls),
+	.dapm_widgets = swr_dmic_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(swr_dmic_dapm_widgets),
+	.dapm_routes = swr_dmic_audio_map,
+	.num_dapm_routes = ARRAY_SIZE(swr_dmic_audio_map),
+};
+
+static int enable_wcd_codec_supply(struct swr_dmic_priv *swr_dmic, bool enable)
+{
+	int rc = 0;
+	int micb_num = swr_dmic->micb_num;
+	struct snd_soc_component *component = swr_dmic->supply_component;
+
+	if (!component) {
+		pr_err_ratelimited("%s: component is NULL\n", __func__);
+		return -EINVAL;
+	}
+	dev_dbg(component->dev, "%s: supply %d micbias: %d enable: %d\n",
+		__func__, swr_dmic->is_en_supply, micb_num, enable);
+
+	if (enable)
+#ifdef CONFIG_SND_SOC_WCD939X
+		rc = wcd939x_codec_force_enable_micbias_v2(component,
+					SND_SOC_DAPM_PRE_PMU, micb_num);
+#else
+		rc = wcd938x_codec_force_enable_micbias_v2(component,
+					SND_SOC_DAPM_PRE_PMU, micb_num);
+#endif
+	else
+#ifdef CONFIG_SND_SOC_WCD939X
+		rc = wcd939x_codec_force_enable_micbias_v2(component,
+					SND_SOC_DAPM_POST_PMD, micb_num);
+#else
+		rc = wcd938x_codec_force_enable_micbias_v2(component,
+					SND_SOC_DAPM_POST_PMD, micb_num);
+#endif
+	return rc;
+}
+
+static int swr_dmic_parse_supply(struct device_node *np,
+				struct swr_dmic_priv *swr_dmic)
+{
+	struct platform_device *pdev = NULL;
+
+	if (!np || !swr_dmic)
+		return -EINVAL;
+
+	pdev = of_find_device_by_node(np);
+	if (!pdev)
+		return -EINVAL;
+
+	swr_dmic->supply_component = snd_soc_lookup_component(&pdev->dev, NULL);
+
+	return 0;
+}
+
+static struct snd_soc_dai_driver swr_dmic_dai[] = {
+	{
+		.name = "",
+		.id = 0,
+		.capture = {
+			.stream_name = "",
+			.rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
+				SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |
+				SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000),
+			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
+				SNDRV_PCM_FMTBIT_S24_LE |
+				SNDRV_PCM_FMTBIT_S32_LE),
+			.rate_max = 192000,
+			.rate_min = 8000,
+			.channels_min = 1,
+			.channels_max = 2,
+		},
+	},
+};
+
+static int swr_dmic_event_notify(struct notifier_block *block,
+				unsigned long val,
+				void *data)
+{
+	u16 event = (val & 0xffff);
+	int ret = 0;
+	struct swr_dmic_priv *swr_dmic = container_of(block,
+					struct swr_dmic_priv,
+					nblock);
+	switch (event) {
+#ifdef CONFIG_SND_SOC_WCD939X
+	case WCD939X_EVT_SSR_DOWN:
+#else
+	case WCD938X_EVT_SSR_DOWN:
+#endif
+		ret = swr_dmic_down(swr_dmic->swr_slave);
+		break;
+#ifdef CONFIG_SND_SOC_WCD939X
+	case WCD939X_EVT_SSR_UP:
+#else
+	case WCD938X_EVT_SSR_UP:
+#endif
+		ret = swr_dmic_up(swr_dmic->swr_slave);
+		if (!ret)
+			ret = swr_dmic_reset(swr_dmic->swr_slave);
+		break;
+	}
+
+	return ret;
+}
+
+static int swr_dmic_probe(struct swr_device *pdev)
+{
+	int ret = 0;
+	int i = 0;
+	u8 swr_devnum = 0;
+	int dev_index = -1;
+	struct swr_dmic_priv *swr_dmic = NULL;
+	const char *swr_dmic_codec_name_of = NULL;
+	struct snd_soc_component *component = NULL;
+	int num_retry = NUM_ATTEMPTS;
+
+	swr_dmic = devm_kzalloc(&pdev->dev, sizeof(struct swr_dmic_priv),
+			    GFP_KERNEL);
+	if (!swr_dmic)
+		return -ENOMEM;
+
+	ret = of_property_read_u32(pdev->dev.of_node, "qcom,swr-dmic-supply",
+				&swr_dmic->micb_num);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
+		__func__, "qcom,swr-dmic-supply",
+		pdev->dev.of_node->full_name);
+		goto err;
+	}
+	swr_dmic->wcd_handle = of_parse_phandle(pdev->dev.of_node,
+						"qcom,wcd-handle", 0);
+	if (!swr_dmic->wcd_handle) {
+		dev_dbg(&pdev->dev, "%s: no wcd handle listed\n",
+			__func__);
+		swr_dmic->is_wcd_supply = false;
+	} else {
+		swr_dmic_parse_supply(swr_dmic->wcd_handle, swr_dmic);
+		swr_dmic->is_wcd_supply = true;
+	}
+
+	if (swr_dmic->is_wcd_supply) {
+		ret = enable_wcd_codec_supply(swr_dmic, true);
+		if (ret) {
+			ret = -EPROBE_DEFER;
+			swr_dmic->is_wcd_supply = false;
+			swr_dmic->wcd_handle = NULL;
+			goto err;
+		}
+		++swr_dmic->is_en_supply;
+	}
+
+	swr_set_dev_data(pdev, swr_dmic);
+
+	swr_dmic->swr_slave = pdev;
+
+	ret = of_property_read_string(pdev->dev.of_node, "qcom,codec-name",
+				&swr_dmic_codec_name_of);
+	if (ret) {
+		dev_dbg(&pdev->dev, "%s: Looking up %s property in node %s failed\n",
+		__func__, "qcom,codec-name",
+		pdev->dev.of_node->full_name);
+		goto dev_err;
+	}
+
+	ret = swr_dmic_parse_port_params(&pdev->dev, "qcom,swr-tx-port-params");
+	if (ret) {
+		dev_err(&pdev->dev, "%s: Parsing %s failed in node %s\n",
+			__func__, "qcom,swr-tx-port-params",
+			pdev->dev.of_node->full_name);
+		goto dev_err;
+	}
+
+	/*
+	 * Add 5msec delay to provide sufficient time for
+	 * soundwire auto enumeration of slave devices as
+	 * as per HW requirement.
+	 */
+	usleep_range(5000, 5010);
+	do {
+		/* Add delay for soundwire enumeration */
+		usleep_range(100, 110);
+		ret = swr_get_logical_dev_num(pdev, pdev->addr, &swr_devnum);
+	} while (ret && --num_retry);
+
+	if (ret) {
+		dev_info(&pdev->dev,
+			"%s get devnum %d for dev addr %llx failed\n",
+			__func__, swr_devnum, pdev->addr);
+		ret = -EPROBE_DEFER;
+
+		if (swr_dmic->is_en_supply == 1) {
+			enable_wcd_codec_supply(swr_dmic, false);
+			--swr_dmic->is_en_supply;
+		}
+		swr_dmic->is_wcd_supply = false;
+		swr_dmic->wcd_handle = NULL;
+		goto err;
+	}
+	pdev->dev_num = swr_devnum;
+	swr_init_port_params(pdev, SWR_DMIC_MAX_PORTS,
+			     swr_dmic->swr_tx_port_params);
+
+	swr_dmic->driver = devm_kzalloc(&pdev->dev,
+			sizeof(struct snd_soc_component_driver), GFP_KERNEL);
+	if (!swr_dmic->driver) {
+		ret = -ENOMEM;
+		goto dev_err;
+	}
+
+	memcpy(swr_dmic->driver, &soc_codec_dev_swr_dmic,
+			sizeof(struct snd_soc_component_driver));
+
+	for (i = 0; i < ARRAY_SIZE(codec_name_list); i++) {
+		if (!strcmp(swr_dmic_codec_name_of, codec_name_list[i])) {
+			dev_index = i;
+			break;
+		}
+	}
+
+	if (dev_index < 0) {
+		ret = -EINVAL;
+		goto dev_err;
+	}
+
+	swr_dmic->driver->name = codec_name_list[dev_index];
+
+	swr_dmic->dai_driver = devm_kzalloc(&pdev->dev,
+			sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
+	if (!swr_dmic->dai_driver) {
+		ret = -ENOMEM;
+		goto dev_err;
+	}
+
+	memcpy(swr_dmic->dai_driver, swr_dmic_dai,
+			sizeof(struct snd_soc_dai_driver));
+	swr_dmic->dai_driver->id = dev_index;
+	swr_dmic->dai_driver->name = dai_name_list[dev_index];
+	swr_dmic->dai_driver->capture.stream_name = aif_name_list[dev_index];
+
+	/* Number of DAI's used is 1 */
+	ret = snd_soc_register_component(&pdev->dev, swr_dmic->driver,
+				swr_dmic->dai_driver, 1);
+	if (ret) {
+		dev_err(&pdev->dev, "%s: Codec registration failed\n",
+			__func__);
+		goto dev_err;
+	}
+
+	component = snd_soc_lookup_component(&pdev->dev,
+						swr_dmic->driver->name);
+	if (!component) {
+		dev_err(&pdev->dev, "%s: could not find swr_dmic component\n",
+			__func__);
+		goto dev_err;
+	}
+	swr_dmic->component = component;
+
+	return 0;
+
+dev_err:
+	if (swr_dmic->is_en_supply == 1) {
+		enable_wcd_codec_supply(swr_dmic, false);
+		--swr_dmic->is_en_supply;
+	}
+	swr_dmic->is_wcd_supply = false;
+	swr_dmic->wcd_handle = NULL;
+	swr_remove_device(pdev);
+err:
+	return ret;
+}
+
+static int swr_dmic_remove(struct swr_device *pdev)
+{
+	struct swr_dmic_priv *swr_dmic;
+
+	swr_dmic = swr_get_dev_data(pdev);
+	if (!swr_dmic) {
+		dev_err(&pdev->dev, "%s: swr_dmic is NULL\n", __func__);
+		return -EINVAL;
+	}
+	if (swr_dmic->is_en_supply == 1) {
+		enable_wcd_codec_supply(swr_dmic, false);
+		--swr_dmic->is_en_supply;
+	}
+	snd_soc_unregister_component(&pdev->dev);
+	swr_set_dev_data(pdev, NULL);
+	return 0;
+}
+
+static int swr_dmic_up(struct swr_device *pdev)
+{
+	int ret = 0;
+	struct swr_dmic_priv *swr_dmic;
+
+	swr_dmic = swr_get_dev_data(pdev);
+	if (!swr_dmic) {
+		dev_err_ratelimited(&pdev->dev, "%s: swr_dmic is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	++swr_dmic->is_en_supply;
+	if (swr_dmic->is_en_supply == 1)
+		ret = enable_wcd_codec_supply(swr_dmic, true);
+
+	return ret;
+}
+
+static int swr_dmic_down(struct swr_device *pdev)
+{
+	struct swr_dmic_priv *swr_dmic;
+	int ret = 0;
+
+	swr_dmic = swr_get_dev_data(pdev);
+	if (!swr_dmic) {
+		dev_err_ratelimited(&pdev->dev, "%s: swr_dmic is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	dev_dbg(&pdev->dev, "%s: is_en_supply: %d\n",
+		__func__, swr_dmic->is_en_supply);
+	--swr_dmic->is_en_supply;
+	if (swr_dmic->is_en_supply < 0) {
+		dev_warn(&pdev->dev, "%s: mismatch in supply count %d\n",
+			__func__, swr_dmic->is_en_supply);
+		swr_dmic->is_en_supply = 0;
+		goto done;
+	}
+	if (!swr_dmic->is_en_supply)
+		enable_wcd_codec_supply(swr_dmic, false);
+
+done:
+	return ret;
+}
+
+static int swr_dmic_reset(struct swr_device *pdev)
+{
+	struct swr_dmic_priv *swr_dmic;
+	u8 retry = NUM_ATTEMPTS;
+	u8 devnum = 0;
+
+	swr_dmic = swr_get_dev_data(pdev);
+	if (!swr_dmic) {
+		dev_err_ratelimited(&pdev->dev, "%s: swr_dmic is NULL\n", __func__);
+		return -EINVAL;
+	}
+
+	while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
+		/* Retry after 1 msec delay */
+		usleep_range(1000, 1100);
+	}
+	pdev->dev_num = devnum;
+	dev_dbg(&pdev->dev, "%s: devnum: %d\n", __func__, devnum);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int swr_dmic_suspend(struct device *dev)
+{
+	dev_dbg(dev, "%s: system suspend\n", __func__);
+	return 0;
+}
+
+static int swr_dmic_resume(struct device *dev)
+{
+	struct swr_dmic_priv *swr_dmic = swr_get_dev_data(to_swr_device(dev));
+
+	if (!swr_dmic) {
+		dev_err_ratelimited(dev, "%s: swr_dmic private data is NULL\n", __func__);
+		return -EINVAL;
+	}
+	dev_dbg(dev, "%s: system resume\n", __func__);
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops swr_dmic_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(swr_dmic_suspend, swr_dmic_resume)
+};
+
+static const struct swr_device_id swr_dmic_id[] = {
+	{"swr-dmic", 0},
+	{}
+};
+
+static const struct of_device_id swr_dmic_dt_match[] = {
+	{
+		.compatible = "qcom,swr-dmic",
+	},
+	{}
+};
+
+static struct swr_driver swr_dmic_driver = {
+	.driver = {
+		.name = "swr-dmic",
+		.owner = THIS_MODULE,
+		.pm = &swr_dmic_pm_ops,
+		.of_match_table = swr_dmic_dt_match,
+	},
+	.probe = swr_dmic_probe,
+	.remove = swr_dmic_remove,
+	.id_table = swr_dmic_id,
+};
+
+static int __init swr_dmic_init(void)
+{
+	return swr_driver_register(&swr_dmic_driver);
+}
+
+static void __exit swr_dmic_exit(void)
+{
+	swr_driver_unregister(&swr_dmic_driver);
+}
+
+module_init(swr_dmic_init);
+module_exit(swr_dmic_exit);
+
+MODULE_DESCRIPTION("SWR DMIC driver");
+MODULE_LICENSE("GPL v2");

qcom/opensource/audio-kernel/asoc/codecs/swr-dmic.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _SWR_DMIC_H
+#define _SWR_DMIC_H
+
+#include <sound/soc.h>
+#include <sound/info.h>
+
+enum {
+	SWR_DMIC_HIFI_PORT = 0,
+	SWR_DMIC_LP_PORT,
+	SWR_DMIC_MAX_PORTS,
+};
+
+#endif /* _SWR_DMIC_H */