msm: camera: isp: Add YUV format support

Add YUV format support in ISP driver. This change is
needed to support the requirement of many OEM who
are trying to bring up YUV sensors.
This commit adds support for YUV 422 8 bit and YUV422 10 bit
format using IPP and RDI path.

CRs-Fixed: 3025233
Change-Id: I61c5881bc655451a6aa6aebe6d6bbf520597a473
Signed-off-by: Gaurav Jindal <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c

@@ -264,6 +264,14 @@ int cam_ife_csid_get_format_rdi(
 		path_format->decode_fmt  = 0xD;
 		path_format->plain_fmt = 0x1;
 		break;
+	case CAM_FORMAT_YUV422:
+		path_format->decode_fmt  = 0x1;
+		path_format->plain_fmt = 0x01;
+		break;
+	case CAM_FORMAT_YUV422_10:
+		path_format->decode_fmt  = 0x2;
+		path_format->plain_fmt = 0x01;
+		break;
 	default:
 		rc = -EINVAL;
 		break;
@@ -342,6 +350,14 @@ int cam_ife_csid_get_format_ipp_ppp(
 		path_format->decode_fmt  = 0xD;
 		path_format->plain_fmt = 0x1;
 		break;
+	case CAM_FORMAT_YUV422:
+		path_format->decode_fmt  = 0x1;
+		path_format->plain_fmt = 0x0;
+		break;
+	case CAM_FORMAT_YUV422_10:
+		path_format->decode_fmt  = 0x2;
+		path_format->plain_fmt = 0x0;
+		break;
 	default:
 		CAM_ERR(CAM_ISP, "Unsupported format %d",
 			in_format);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe580.h

@@ -38,6 +38,9 @@ static struct cam_vfe_camif_ver3_reg_data vfe_580_camif_reg_data = {
 	.pp_camif_cfg_ife_out_en_shift   = 8,
 	.top_debug_cfg_en                = 1,
 	.dual_vfe_sync_mask              = 0x3,
+	.input_bayer_fmt                 = 0,
+	.input_yuv_fmt                   = 1,
+
 };
 
 static struct cam_vfe_camif_lite_ver3_reg_data vfe580_camif_rdi1_reg_data = {

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -868,6 +868,7 @@ static int cam_vfe_bus_ver3_config_rdi_wm(
 		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_8:
+	case CAM_FORMAT_YUV422:
 		if (rsrc_data->default_line_based) {
 			rsrc_data->en_cfg = 0x1;
 			rsrc_data->width =
@@ -968,6 +969,18 @@ static int cam_vfe_bus_ver3_config_rdi_wm(
 			ALIGNUP(rsrc_data->width * 8, 16) / 16;
 		rsrc_data->en_cfg = 0x1;
 		break;
+	case CAM_FORMAT_YUV422_10:
+		if (rsrc_data->default_line_based) {
+			rsrc_data->en_cfg = 0x1;
+			rsrc_data->width =
+				ALIGNUP((rsrc_data->width * 5) / 4, 16) / 16;
+		} else {
+			rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH;
+			rsrc_data->height = 0;
+			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
+			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+		}
+		break;
 	default:
 		CAM_ERR(CAM_ISP, "Unsupported RDI format %d",
 			rsrc_data->format);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c

@@ -169,7 +169,8 @@ static int cam_vfe_camif_ver3_err_irq_top_half(
 	return rc;
 }
 
-static int cam_vfe_camif_ver3_validate_pix_pattern(uint32_t pattern)
+static int cam_vfe_camif_ver3_validate_pix_pattern(uint32_t pattern,
+	struct cam_vfe_mux_camif_ver3_data *camif_data)
 {
 	int rc;
 
@@ -178,11 +179,17 @@ static int cam_vfe_camif_ver3_validate_pix_pattern(uint32_t pattern)
 	case CAM_ISP_PATTERN_BAYER_GRGRGR:
 	case CAM_ISP_PATTERN_BAYER_BGBGBG:
 	case CAM_ISP_PATTERN_BAYER_GBGBGB:
+		camif_data->cam_common_cfg.input_pp_fmt =
+			camif_data->reg_data->input_bayer_fmt;
+		rc = 0;
+		break;
 	case CAM_ISP_PATTERN_YUV_YCBYCR:
 	case CAM_ISP_PATTERN_YUV_YCRYCB:
 	case CAM_ISP_PATTERN_YUV_CBYCRY:
 	case CAM_ISP_PATTERN_YUV_CRYCBY:
 		rc = 0;
+		camif_data->cam_common_cfg.input_pp_fmt =
+			camif_data->reg_data->input_yuv_fmt;
 		break;
 	default:
 		CAM_ERR(CAM_ISP, "Error, Invalid pix pattern:%d", pattern);
@@ -256,7 +263,7 @@ int cam_vfe_camif_ver3_acquire_resource(
 	acquire_data = (struct cam_vfe_acquire_args *)acquire_param;
 
 	rc = cam_vfe_camif_ver3_validate_pix_pattern(
-		acquire_data->vfe_in.in_port->test_pattern);
+		acquire_data->vfe_in.in_port->test_pattern, camif_data);
 
 	if (rc) {
 		CAM_ERR(CAM_ISP, "Validate pix pattern failed, rc = %d", rc);
@@ -445,6 +452,8 @@ static int cam_vfe_camif_ver3_resource_start(
 		CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BHIST;
 	val |= (rsrc_data->cam_common_cfg.input_mux_sel_pp & 0x3) <<
 		CAM_SHIFT_TOP_CORE_CFG_INPUTMUX_PP;
+	val |= (rsrc_data->cam_common_cfg.input_pp_fmt & 0x3) <<
+		CAM_SHIFT_TOP_CORE_CFG_INPUT_PP_FMT;
 
 	if (rsrc_data->is_fe_enabled && !rsrc_data->is_offline)
 		val |= 0x2 << rsrc_data->reg_data->operating_mode_shift;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_VFE_CAMIF_VER3_H_
@@ -60,6 +60,10 @@ struct cam_vfe_camif_ver3_reg_data {
 	uint32_t     pp_camif_cfg_ife_out_en_shift;
 	uint32_t     top_debug_cfg_en;
 	uint32_t     dual_vfe_sync_mask;
+
+	uint32_t     input_bayer_fmt;
+	uint32_t     input_yuv_fmt;
+
 };
 
 struct cam_vfe_camif_ver3_hw_info {

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h

@@ -17,6 +17,7 @@
 #define CAM_SHIFT_TOP_CORE_CFG_DISP_DS16_R2PD    28
 #define CAM_SHIFT_TOP_CORE_CFG_DISP_DS4_R2PD     27
 #define CAM_SHIFT_TOP_CORE_CFG_DSP_STREAMING     25
+#define CAM_SHIFT_TOP_CORE_CFG_INPUT_PP_FMT      14
 #define CAM_SHIFT_TOP_CORE_CFG_STATS_IHIST       10
 #define CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BE       9
 #define CAM_SHIFT_TOP_CORE_CFG_STATS_HDR_BHIST    8
@@ -75,6 +76,7 @@ struct cam_vfe_camif_common_cfg {
 	uint32_t     hdr_bhist_src_sel;
 	uint32_t     input_mux_sel_pdaf;
 	uint32_t     input_mux_sel_pp;
+	uint32_t     input_pp_fmt;
 };
 
 struct cam_vfe_top_ver3_hw_info {

include/uapi/camera/media/cam_defs.h

@@ -179,7 +179,8 @@ struct cam_iommu_handle {
 #define CAM_FORMAT_PLAIN32                      47
 #define CAM_FORMAT_ARGB_16                      48
 #define CAM_FORMAT_PLAIN16_10_LSB               49
-#define CAM_FORMAT_MAX                          50
+#define CAM_FORMAT_YUV422_10                    50
+#define CAM_FORMAT_MAX                          51
 
 /* Pixel Patterns */
 #define PIXEL_PATTERN_RGRGRG                    0x0