msm: camera: isp: Update constraint error debug info for vfe and sfe

Update debug status info for constraint violation in v680 hw.

CRs-Fixed: 2841729
Change-Id: I3576f1fb0d1caf56cbfe2e40c01aa407e6172299
Signed-off-by: Mukund Madhusudan Atre <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h

@@ -923,73 +923,122 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.name          = "STATS_BHIST_2",
 		},
 	},
+	.num_cons_err = 29,
 	.constraint_error_list = {
 		{
-			.bitmask = 0x000001,
-			.error_description = "PPC 1x1 illegal"
+			.bitmask = BIT(0),
+			.error_description = "PPC 1x1 input not supported"
 		},
 		{
-			.bitmask = 0x000002,
-			.error_description = "PPC 1x2 illegal"
+			.bitmask = BIT(1),
+			.error_description = "PPC 1x2 input not supported"
 		},
 		{
-			.bitmask = 0x000004,
-			.error_description = "PPC 2x1 illegal"
+			.bitmask = BIT(2),
+			.error_description = "PPC 2x1 input not supported"
 		},
 		{
-			.bitmask = 0x000008,
-			.error_description = "PPC 2x2 illegal"
+			.bitmask = BIT(3),
+			.error_description = "PPC 2x2 input not supported"
 		},
 		{
-			.bitmask = 0x000010,
-			.error_description = "Pack 8 BPP illegal"
+			.bitmask = BIT(4),
+			.error_description = "Pack 8 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000020,
-			.error_description = "Pack 16 BPP illegal"
+			.bitmask = BIT(5),
+			.error_description = "Pack 16 format not supported"
 		},
 		{
-			.bitmask = 0x000040,
-			.error_description = "Pack 32 BPP illegal"
+			.bitmask = BIT(6),
+			.error_description = "Pack 32 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000080,
-			.error_description = "Pack 64 BPP illegal"
+			.bitmask = BIT(7),
+			.error_description = "Pack 64 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000100,
-			.error_description = "Pack 128 BPP illegal"
+			.bitmask = BIT(8),
+			.error_description = "Pack MIPI 20 format not supported"
 		},
 		{
-			.bitmask = 0x000200,
-			.error_description = "Frame based illegal"
+			.bitmask = BIT(9),
+			.error_description = "Pack MIPI 14 format not supported"
 		},
 		{
-			.bitmask = 0x000400,
-			.error_description = "Index based illegal"
+			.bitmask = BIT(10),
+			.error_description = "Pack MIPI 12 format not supported"
 		},
 		{
-			.bitmask = 0x000800,
+			.bitmask = BIT(11),
+			.error_description = "Pack MIPI 10 format not supported"
+		},
+		{
+			.bitmask = BIT(12),
+			.error_description = "Pack 128 BPP format not supported"
+		},
+		{
+			.bitmask = BIT(13),
+			.error_description = "UBWC NV12 format not supported"
+		},
+		{
+			.bitmask = BIT(14),
+			.error_description = "UBWC NV12 4R format not supported"
+		},
+		{
+			.bitmask = BIT(15),
+			.error_description = "UBWC TP10 format not supported"
+		},
+		{
+			.bitmask = BIT(16),
+			.error_description = "Frame based Mode not supported"
+		},
+		{
+			.bitmask = BIT(17),
+			.error_description = "Index based Mode not supported"
+		},
+		{
+			.bitmask = BIT(18),
+			.error_description = "FIFO image addr unalign"
+		},
+		{
+			.bitmask = BIT(19),
+			.error_description = "FIFO ubwc addr unalign"
+		},
+		{
+			.bitmask = BIT(20),
+			.error_description = "FIFO frmheader addr unalign"
+		},
+		{
+			.bitmask = BIT(21),
 			.error_description = "Image address unalign"
 		},
 		{
-			.bitmask = 0x001000,
+			.bitmask = BIT(22),
+			.error_description = "UBWC address unalign"
+		},
+		{
+			.bitmask = BIT(23),
 			.error_description = "Frame Header address unalign"
 		},
 		{
-			.bitmask = 0x002000,
+			.bitmask = BIT(24),
+			.error_description = "Stride unalign"
+		},
+		{
+			.bitmask = BIT(25),
 			.error_description = "X Initialization unalign"
 		},
 		{
-			.bitmask = 0x004000,
+			.bitmask = BIT(26),
 			.error_description = "Image Width unalign"
 		},
 		{
-			.bitmask = 0x008000,
+			.bitmask = BIT(27),
 			.error_description = "Image Height unalign"
 		},
 		{
-			.bitmask = 0x010000,
+			.bitmask = BIT(28),
 			.error_description = "Meta Stride unalign"
 		},
 	},

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -194,6 +194,7 @@ struct cam_sfe_bus_wr_priv {
 	int                                 bus_irq_handle;
 	int                                 error_irq_handle;
 	void                               *tasklet_info;
+	uint32_t                            num_cons_err;
 	struct cam_sfe_constraint_error_info      *constraint_error_list;
 };
 
@@ -381,10 +382,10 @@ static void cam_sfe_bus_wr_print_constraint_errors(
 	CAM_INFO(CAM_ISP, "Constraint violation bitflags: 0x%X",
 		constraint_errors);
 
-	for (i = 0; i < CAM_SFE_BUS_CONS_ERR_MAX; i++) {
+	for (i = 0; i < bus_priv->num_cons_err; i++) {
 		if (bus_priv->constraint_error_list[i].bitmask &
 			constraint_errors) {
-			CAM_INFO(CAM_ISP, "WM: %s %s programming",
+			CAM_INFO(CAM_ISP, "WM: %s %s",
 				wm_name, bus_priv->constraint_error_list[i]
 				.error_description);
 		}
@@ -2965,6 +2966,7 @@ int cam_sfe_bus_wr_init(
 	bus_priv->common_data.max_bw_counter_limit = hw_info->max_bw_counter_limit;
 	bus_priv->common_data.err_irq_subscribe    = false;
 	bus_priv->common_data.sfe_irq_controller   = sfe_irq_controller;
+	bus_priv->num_cons_err = hw_info->num_cons_err;
 	bus_priv->constraint_error_list = hw_info->constraint_error_list;
 	rc = cam_cpas_get_cpas_hw_version(&bus_priv->common_data.hw_version);
 	if (rc) {

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.h

@@ -11,7 +11,7 @@
 
 #define CAM_SFE_BUS_WR_MAX_CLIENTS     13
 #define CAM_SFE_BUS_WR_MAX_SUB_GRPS    6
-#define CAM_SFE_BUS_CONS_ERR_MAX       21
+#define CAM_SFE_BUS_CONS_ERR_MAX       32
 
 enum cam_sfe_bus_wr_src_grp {
 	CAM_SFE_BUS_WR_SRC_GRP_0,
@@ -145,6 +145,7 @@ struct cam_sfe_bus_sfe_out_hw_info {
  * @num_client:            Total number of write clients
  * @bus_client_reg:        Bus client register info
  * @sfe_out_hw_info:       SFE output capability
+ * @num_cons_err:          Number of contraint errors in list
  * @constraint_error_list: Static list of all constraint errors
  * @num_comp_grp:          Number of composite groups
  * @comp_done_shift:       Mask shift for comp done mask
@@ -160,6 +161,7 @@ struct cam_sfe_bus_wr_hw_info {
 	uint32_t num_out;
 	struct cam_sfe_bus_sfe_out_hw_info
 		sfe_out_hw_info[CAM_SFE_BUS_SFE_OUT_MAX];
+	uint32_t num_cons_err;
 	struct cam_sfe_constraint_error_info
 		constraint_error_list[CAM_SFE_BUS_CONS_ERR_MAX];
 	uint32_t num_comp_grp;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h

@@ -1508,89 +1508,90 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			},
 		},
 	},
+	.num_cons_err = 21,
 	.constraint_error_list = {
 		{
-			.bitmask = 0x000001,
-			.error_description = "PPC 1x1 illegal"
+			.bitmask = BIT(0),
+			.error_description = "PPC 1x1 input not supported"
 		},
 		{
-			.bitmask = 0x000002,
-			.error_description = "PPC 1x2 illegal"
+			.bitmask = BIT(1),
+			.error_description = "PPC 1x2 input not supported"
 		},
 		{
-			.bitmask = 0x000004,
-			.error_description = "PPC 2x1 illegal"
+			.bitmask = BIT(2),
+			.error_description = "PPC 2x1 input not supported"
 		},
 		{
-			.bitmask = 0x000008,
-			.error_description = "PPC 2x2 illegal"
+			.bitmask = BIT(3),
+			.error_description = "PPC 2x2 input not supported"
 		},
 		{
-			.bitmask = 0x000010,
-			.error_description = "Pack 8 BPP illegal"
+			.bitmask = BIT(4),
+			.error_description = "Pack 8 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000020,
-			.error_description = "Pack 16 BPP illegal"
+			.bitmask = BIT(5),
+			.error_description = "Pack 16 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000040,
-			.error_description = "Pack 32 BPP illegal"
+			.bitmask = BIT(6),
+			.error_description = "Pack 32 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000080,
-			.error_description = "Pack 64 BPP illegal"
+			.bitmask = BIT(7),
+			.error_description = "Pack 64 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000100,
-			.error_description = "Pack 128 BPP illegal"
+			.bitmask = BIT(8),
+			.error_description = "Pack 128 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000200,
-			.error_description = "UBWC NV12 illegal"
+			.bitmask = BIT(9),
+			.error_description = "UBWC NV12 format not supported"
 		},
 		{
-			.bitmask = 0x000400,
-			.error_description = "UBWC NV12 4R illegal"
+			.bitmask = BIT(10),
+			.error_description = "UBWC NV12 4R format not supported"
 		},
 		{
-			.bitmask = 0x000800,
-			.error_description = "UBWC TP10 illegal"
+			.bitmask = BIT(11),
+			.error_description = "UBWC TP10 format not supported"
 		},
 		{
-			.bitmask = 0x001000,
-			.error_description = "Frame based illegal"
+			.bitmask = BIT(12),
+			.error_description = "Frame based Mode not supported"
 		},
 		{
-			.bitmask = 0x002000,
-			.error_description = "Index based illegal"
+			.bitmask = BIT(13),
+			.error_description = "Index based Mode not supported"
 		},
 		{
-			.bitmask = 0x004000,
+			.bitmask = BIT(14),
 			.error_description = "Image address unalign"
 		},
 		{
-			.bitmask = 0x008000,
+			.bitmask = BIT(15),
 			.error_description = "UBWC address unalign"
 		},
 		{
-			.bitmask = 0x010000,
+			.bitmask = BIT(16),
 			.error_description = "Frame Header address unalign"
 		},
 		{
-			.bitmask = 0x020000,
+			.bitmask = BIT(17),
 			.error_description = "X Initialization unalign"
 		},
 		{
-			.bitmask = 0x040000,
+			.bitmask = BIT(18),
 			.error_description = "Image Width unalign"
 		},
 		{
-			.bitmask = 0x080000,
+			.bitmask = BIT(19),
 			.error_description = "Image Height unalign"
 		},
 		{
-			.bitmask = 0x100000,
+			.bitmask = BIT(20),
 			.error_description = "Meta Stride unalign"
 		},
 	},

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680.h

@@ -1851,89 +1851,122 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			},
 		},
 	},
+	.num_cons_err = 29,
 	.constraint_error_list = {
 		{
-			.bitmask = 0x000001,
-			.error_description = "PPC 1x1 illegal"
+			.bitmask = BIT(0),
+			.error_description = "PPC 1x1 input not supported"
 		},
 		{
-			.bitmask = 0x000002,
-			.error_description = "PPC 1x2 illegal"
+			.bitmask = BIT(1),
+			.error_description = "PPC 1x2 input not supported"
 		},
 		{
-			.bitmask = 0x000004,
-			.error_description = "PPC 2x1 illegal"
+			.bitmask = BIT(2),
+			.error_description = "PPC 2x1 input not supported"
 		},
 		{
-			.bitmask = 0x000008,
-			.error_description = "PPC 2x2 illegal"
+			.bitmask = BIT(3),
+			.error_description = "PPC 2x2 input not supported"
 		},
 		{
-			.bitmask = 0x000010,
-			.error_description = "Pack 8 BPP illegal"
+			.bitmask = BIT(4),
+			.error_description = "Pack 8 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000020,
-			.error_description = "Pack 16 BPP illegal"
+			.bitmask = BIT(5),
+			.error_description = "Pack 16 format not supported"
 		},
 		{
-			.bitmask = 0x000040,
-			.error_description = "Pack 32 BPP illegal"
+			.bitmask = BIT(6),
+			.error_description = "Pack 32 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000080,
-			.error_description = "Pack 64 BPP illegal"
+			.bitmask = BIT(7),
+			.error_description = "Pack 64 BPP format not supported"
 		},
 		{
-			.bitmask = 0x000100,
-			.error_description = "Pack 128 BPP illegal"
+			.bitmask = BIT(8),
+			.error_description = "Pack MIPI 20 format not supported"
 		},
 		{
-			.bitmask = 0x000200,
-			.error_description = "UBWC NV12 illegal"
+			.bitmask = BIT(9),
+			.error_description = "Pack MIPI 14 format not supported"
 		},
 		{
-			.bitmask = 0x000400,
-			.error_description = "UBWC NV12 4R illegal"
+			.bitmask = BIT(10),
+			.error_description = "Pack MIPI 12 format not supported"
 		},
 		{
-			.bitmask = 0x000800,
-			.error_description = "UBWC TP10 illegal"
+			.bitmask = BIT(11),
+			.error_description = "Pack MIPI 10 format not supported"
 		},
 		{
-			.bitmask = 0x001000,
-			.error_description = "Frame based illegal"
+			.bitmask = BIT(12),
+			.error_description = "Pack 128 BPP format not supported"
 		},
 		{
-			.bitmask = 0x002000,
-			.error_description = "Index based illegal"
+			.bitmask = BIT(13),
+			.error_description = "UBWC NV12 format not supported"
 		},
 		{
-			.bitmask = 0x004000,
+			.bitmask = BIT(14),
+			.error_description = "UBWC NV12 4R format not supported"
+		},
+		{
+			.bitmask = BIT(15),
+			.error_description = "UBWC TP10 format not supported"
+		},
+		{
+			.bitmask = BIT(16),
+			.error_description = "Frame based Mode not supported"
+		},
+		{
+			.bitmask = BIT(17),
+			.error_description = "Index based Mode not supported"
+		},
+		{
+			.bitmask = BIT(18),
+			.error_description = "FIFO image addr unalign"
+		},
+		{
+			.bitmask = BIT(19),
+			.error_description = "FIFO ubwc addr unalign"
+		},
+		{
+			.bitmask = BIT(20),
+			.error_description = "FIFO frmheader addr unalign"
+		},
+		{
+			.bitmask = BIT(21),
 			.error_description = "Image address unalign"
 		},
 		{
-			.bitmask = 0x008000,
+			.bitmask = BIT(22),
 			.error_description = "UBWC address unalign"
 		},
 		{
-			.bitmask = 0x010000,
+			.bitmask = BIT(23),
 			.error_description = "Frame Header address unalign"
 		},
 		{
-			.bitmask = 0x020000,
+			.bitmask = BIT(24),
+			.error_description = "Stride unalign"
+		},
+		{
+			.bitmask = BIT(25),
 			.error_description = "X Initialization unalign"
 		},
 		{
-			.bitmask = 0x040000,
+			.bitmask = BIT(26),
 			.error_description = "Image Width unalign"
 		},
 		{
-			.bitmask = 0x080000,
+			.bitmask = BIT(27),
 			.error_description = "Image Height unalign"
 		},
 		{
-			.bitmask = 0x100000,
+			.bitmask = BIT(28),
 			.error_description = "Meta Stride unalign"
 		},
 	},

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -213,6 +213,7 @@ struct cam_vfe_bus_ver3_priv {
 	int                                 error_irq_handle;
 	void                               *tasklet_info;
 	uint32_t                            max_out_res;
+	uint32_t                            num_cons_err;
 	struct cam_vfe_constraint_error_info      *constraint_error_list;
 };
 
@@ -649,10 +650,10 @@ static void cam_vfe_bus_ver3_print_constraint_errors(
 	CAM_INFO_RATE_LIMIT(CAM_ISP, "Constraint violation bitflags: 0x%X",
 		constraint_errors);
 
-	for (i = 0; i < CAM_VFE_BUS_VER3_CONS_ERR_MAX; i++) {
+	for (i = 0; i < bus_priv->num_cons_err; i++) {
 		if (bus_priv->constraint_error_list[i].bitmask &
 			constraint_errors) {
-			CAM_INFO(CAM_ISP, "WM:%s %s programming",
+			CAM_INFO(CAM_ISP, "WM:%s %s",
 				wm_name, bus_priv->constraint_error_list[i]
 				.error_description);
 		}
@@ -3947,6 +3948,7 @@ int cam_vfe_bus_ver3_init(
 		ver3_hw_info->pack_align_shift;
 	bus_priv->common_data.max_bw_counter_limit =
 		ver3_hw_info->max_bw_counter_limit;
+	bus_priv->num_cons_err = ver3_hw_info->num_cons_err;
 	bus_priv->constraint_error_list = ver3_hw_info->constraint_error_list;
 
 	if (bus_priv->num_out >= CAM_VFE_BUS_VER3_VFE_OUT_MAX) {

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h

@@ -14,7 +14,7 @@
 #define CAM_VFE_BUS_VER3_MAX_MID_PER_PORT 4
 #define CAM_VFE_BUS_VER3_480_MAX_CLIENTS     26
 #define CAM_VFE_BUS_VER3_680_MAX_CLIENTS     28
-#define CAM_VFE_BUS_VER3_CONS_ERR_MAX        21
+#define CAM_VFE_BUS_VER3_CONS_ERR_MAX        32
 
 enum cam_vfe_bus_ver3_vfe_core_id {
 	CAM_VFE_BUS_VER3_VFE_CORE_0,
@@ -204,6 +204,7 @@ struct cam_vfe_bus_ver3_vfe_out_hw_info {
  * @num_client:            Total number of write clients
  * @bus_client_reg:        Bus client register info
  * @vfe_out_hw_info:       VFE output capability
+ * @num_cons_err:          Number of constraint errors in list
  * @constraint_error_list: Static list of all constraint errors
  * @num_comp_grp:          Number of composite groups
  * @comp_done_shift:       Mask shift for comp done mask
@@ -223,6 +224,7 @@ struct cam_vfe_bus_ver3_hw_info {
 	uint32_t num_out;
 	struct cam_vfe_bus_ver3_vfe_out_hw_info
 		vfe_out_hw_info[CAM_VFE_BUS_VER3_VFE_OUT_MAX];
+	uint32_t num_cons_err;
 	struct cam_vfe_constraint_error_info
 		constraint_error_list[CAM_VFE_BUS_VER3_CONS_ERR_MAX];
 	uint32_t num_comp_grp;