qcacmn: Add prefetch_timer config for CE rings
Add prefetch_timer configuration for CE rings. Set prefetch_timer=1 configuration for qca6490 destination CEs, prefetch_timer=0 configuration for other targets CEs. Basically setting to 1us asking CE hw to update ring tail pointer to update within 1us. FW side CE SW sets all rings to 1us already. Idea behind this change is, we have seen pre-silicon issue where SRC ring TP read by SW was not seen updated value when prefetch was set to 8us. Changing prefetch timer value to 1us helps to resolve pre-silicon issue. So host side rings need to update the prefetch timer to 1us. Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741 CRs-Fixed: 2669762
This commit is contained in:

committed by
nshrivas

szülő
7dad533e6c
commit
9043089a40
@@ -835,7 +835,6 @@ extern void hal_detach(void *hal_soc)
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}
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qdf_export_symbol(hal_detach);
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/**
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* hal_ce_dst_setup - Initialize CE destination ring registers
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* @hal_soc: HAL SOC handle
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@@ -859,6 +858,19 @@ static inline void hal_ce_dst_setup(struct hal_soc *hal, struct hal_srng *srng,
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reg_val |= srng->u.dst_ring.max_buffer_length &
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HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK;
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HAL_REG_WRITE(hal, reg_addr, reg_val);
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if (srng->prefetch_timer) {
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reg_addr = HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(
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ring_config->reg_start[R0_INDEX] +
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(ring_num * ring_config->reg_size[R0_INDEX]));
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reg_val = HAL_REG_READ(hal, reg_addr);
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reg_val &= ~HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK;
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reg_val |= srng->prefetch_timer;
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HAL_REG_WRITE(hal, reg_addr, reg_val);
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reg_val = HAL_REG_READ(hal, reg_addr);
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}
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}
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/**
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@@ -1053,6 +1065,7 @@ void *hal_srng_setup(void *hal_soc, int ring_type, int ring_num,
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srng->intr_timer_thres_us = ring_params->intr_timer_thres_us;
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srng->intr_batch_cntr_thres_entries =
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ring_params->intr_batch_cntr_thres_entries;
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srng->prefetch_timer = ring_params->prefetch_timer;
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srng->hal_soc = hal_soc;
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for (i = 0 ; i < MAX_SRNG_REG_GROUPS; i++) {
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