qcacmn: Add prefetch_timer config for CE rings

Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.

Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change  is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.

Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
This commit is contained in:
Vevek Venkatesan
2020-04-21 15:13:49 +05:30
committed by nshrivas
parent 7dad533e6c
commit 9043089a40
5 changed files with 37 additions and 8 deletions

View File

@@ -643,6 +643,12 @@ enum hal_ring_type {
#define HAL_SRNG_MSI_INTR 0x00020000
#define HAL_SRNG_CACHED_DESC 0x00040000
#ifdef QCA_WIFI_QCA6490
#define HAL_SRNG_PREFETCH_TIMER 1
#else
#define HAL_SRNG_PREFETCH_TIMER 0
#endif
#define PN_SIZE_24 0
#define PN_SIZE_48 1
#define PN_SIZE_128 2
@@ -748,6 +754,8 @@ struct hal_srng_params {
uint32_t entry_size;
/* hw register base address */
void *hwreg_base[MAX_SRNG_REG_GROUPS];
/* prefetch timer config - in micro seconds */
uint32_t prefetch_timer;
};
/* hal_construct_shadow_config() - initialize the shadow registers for dp rings