qcacmn: Hal changes for Big endian platform

Hal layer changes to support big endian platform.

Change-Id: I3fa6015ee1915b59c69e593ced57225edcca1c38
CRs-Fixed: 3427031

hal/wifi3.0/be/hal_be_api_mon.h

@@ -2341,8 +2341,8 @@ hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv,
 {
 	struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv;
 
-	ppdu_info->packet_info.sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) |
-					    (addr->buffer_virt_addr_31_0));
+	ppdu_info->packet_info.sw_cookie = (((uint64_t)qdf_le32_to_cpu(addr->buffer_virt_addr_63_32) << 32) |
+					    qdf_le32_to_cpu(addr->buffer_virt_addr_31_0));
 	/* HW DMA length is '-1' of actual DMA length*/
 	ppdu_info->packet_info.dma_length = addr->dma_length + 1;
 	ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation;

hal/wifi3.0/be/hal_be_generic_api.h

@@ -3318,6 +3318,21 @@ static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
 			  reo_qref->rx_reo_queue_desc_addr_39_32);
 }
 
+#ifdef BIG_ENDIAN_HOST
+static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal)
+{
+	HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
+		      HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, GXI_SWAP, 1) |
+		      HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1));
+}
+#else
+static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal)
+{
+	HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
+		      HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1));
+}
+#endif
+
 /**
  * hal_reo_shared_qaddr_setup_be() - Allocate MLO and Non MLO reo queue
  * reference table shared between SW and HW and initialize in Qdesc Base0
@@ -3402,10 +3417,7 @@ static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl,
 	HAL_REG_WRITE(hal,
 		      HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE),
 		      hal->reo_qref.mlo_reo_qref_table_paddr >> 8);
-	HAL_REG_WRITE(hal,
-		      HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
-		      HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE,
-			     1));
+	hal_reo_shared_qaddr_enable(hal);
 	HAL_REG_WRITE(hal,
 		      HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE),
 		      HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED,

hal/wifi3.0/be/hal_be_rx.h

@@ -356,13 +356,12 @@ static inline uintptr_t hal_rx_wbm_get_desc_va(void *hal_desc)
 {
 	uint64_t va_from_desc;
 
-	va_from_desc = HAL_RX_GET(hal_desc,
+	va_from_desc = qdf_le64_to_cpu(HAL_RX_GET(hal_desc,
 				       WBM2SW_COMPLETION_RING_RX,
 				       BUFFER_VIRT_ADDR_31_0) |
 				       (((uint64_t)HAL_RX_GET(hal_desc,
 				       WBM2SW_COMPLETION_RING_RX,
-					       BUFFER_VIRT_ADDR_63_32)) << 32);
-
+				       BUFFER_VIRT_ADDR_63_32)) << 32));
 	return (uintptr_t)va_from_desc;
 }
 
@@ -495,13 +494,12 @@ static inline uintptr_t hal_rx_get_reo_desc_va(void *reo_desc)
 {
 	uint64_t va_from_desc;
 
-	va_from_desc = HAL_RX_GET(reo_desc,
+	va_from_desc = qdf_le64_to_cpu(HAL_RX_GET(reo_desc,
 				       REO_DESTINATION_RING,
 				       BUFFER_VIRT_ADDR_31_0) |
 				       (((uint64_t)HAL_RX_GET(reo_desc,
 				       REO_DESTINATION_RING,
-				       BUFFER_VIRT_ADDR_63_32)) << 32);
-
+				       BUFFER_VIRT_ADDR_63_32)) << 32));
 	return (uintptr_t)va_from_desc;
 }
 

hal/wifi3.0/be/hal_be_tx.h

@@ -620,13 +620,13 @@ static inline uint64_t hal_tx_comp_get_desc_va(void *hal_desc)
 {
 	uint64_t va_from_desc;
 
-	va_from_desc = HAL_TX_DESC_GET(hal_desc,
+	va_from_desc = qdf_le64_to_cpu(HAL_TX_DESC_GET(hal_desc,
 				       WBM2SW_COMPLETION_RING_TX,
 				       BUFFER_VIRT_ADDR_31_0) |
 				       (((uint64_t)HAL_TX_DESC_GET(
 				       hal_desc,
 				       WBM2SW_COMPLETION_RING_TX,
-					BUFFER_VIRT_ADDR_63_32)) << 32);
+				       BUFFER_VIRT_ADDR_63_32)) << 32));
 
 	return va_from_desc;
 }

hal/wifi3.0/hal_api_mon.h

@@ -38,34 +38,34 @@
 #define HAL_RX_TLV32_HDR_SIZE			4
 
 #define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
-		((*((uint32_t *)(rx_status_tlv_ptr)) & \
+		((qdf_le32_to_cpu(*((uint32_t *)(rx_status_tlv_ptr))) & \
 		HAL_RX_USER_TLV32_TYPE_MASK) >> \
 		HAL_RX_USER_TLV32_TYPE_LSB)
 
 #define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
-		((*((uint32_t *)(rx_status_tlv_ptr)) & \
+		((qdf_le32_to_cpu(*((uint32_t *)(rx_status_tlv_ptr))) & \
 		HAL_RX_USER_TLV32_LEN_MASK) >> \
 		HAL_RX_USER_TLV32_LEN_LSB)
 
 #define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
-		((*((uint32_t *)(rx_status_tlv_ptr)) & \
+		((qdf_le32_to_cpu(*((uint32_t *)(rx_status_tlv_ptr))) & \
 		HAL_RX_USER_TLV32_USERID_MASK) >> \
 		HAL_RX_USER_TLV32_USERID_LSB)
 
 #define HAL_RX_TLV64_HDR_SIZE			8
 
 #define HAL_RX_GET_USER_TLV64_TYPE(rx_status_tlv_ptr) \
-		((*((uint64_t *)(rx_status_tlv_ptr)) & \
+		((qdf_le64_to_cpu(*((uint64_t *)(rx_status_tlv_ptr))) & \
 		HAL_RX_USER_TLV64_TYPE_MASK) >> \
 		HAL_RX_USER_TLV64_TYPE_LSB)
 
 #define HAL_RX_GET_USER_TLV64_LEN(rx_status_tlv_ptr) \
-		((*((uint64_t *)(rx_status_tlv_ptr)) & \
+		((qdf_le64_to_cpu(*((uint64_t *)(rx_status_tlv_ptr))) & \
 		HAL_RX_USER_TLV64_LEN_MASK) >> \
 		HAL_RX_USER_TLV64_LEN_LSB)
 
 #define HAL_RX_GET_USER_TLV64_USERID(rx_status_tlv_ptr) \
-		((*((uint64_t *)(rx_status_tlv_ptr)) & \
+		((qdf_le64_to_cpu(*((uint64_t *)(rx_status_tlv_ptr))) & \
 		HAL_RX_USER_TLV64_USERID_MASK) >> \
 		HAL_RX_USER_TLV64_USERID_LSB)