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@@ -40,6 +40,42 @@ qdf_size_t dp_get_context_size_be(enum dp_context_type context_type)
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}
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#ifdef DP_FEATURE_HW_COOKIE_CONVERSION
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+#if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
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+/**
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+ * dp_cc_wbm_sw_en_cfg() - configure HW cookie conversion enablement
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+ per wbm2sw ring
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+ * @cc_cfg: HAL HW cookie conversion configuration structure pointer
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+ *
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+ * Return: None
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+ */
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+static inline
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+void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
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+{
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+ cc_cfg->wbm2sw6_cc_en = 1;
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+ cc_cfg->wbm2sw5_cc_en = 1;
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+ cc_cfg->wbm2sw4_cc_en = 1;
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+ cc_cfg->wbm2sw3_cc_en = 1;
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+ cc_cfg->wbm2sw2_cc_en = 1;
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+ /* disable wbm2sw1 hw cc as it's for FW */
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+ cc_cfg->wbm2sw1_cc_en = 0;
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+ cc_cfg->wbm2sw0_cc_en = 1;
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+ cc_cfg->wbm2fw_cc_en = 0;
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+}
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+#else
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+static inline
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+void dp_cc_wbm_sw_en_cfg(struct hal_hw_cc_config *cc_cfg)
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+{
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+ cc_cfg->wbm2sw6_cc_en = 1;
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+ cc_cfg->wbm2sw5_cc_en = 1;
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+ cc_cfg->wbm2sw4_cc_en = 1;
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+ cc_cfg->wbm2sw3_cc_en = 1;
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+ cc_cfg->wbm2sw2_cc_en = 1;
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+ cc_cfg->wbm2sw1_cc_en = 1;
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+ cc_cfg->wbm2sw0_cc_en = 1;
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+ cc_cfg->wbm2fw_cc_en = 0;
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+}
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+#endif
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+
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/**
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* dp_cc_reg_cfg_init() - initialize and configure HW cookie
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conversion register
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@@ -68,14 +104,7 @@ static void dp_cc_reg_cfg_init(struct dp_soc *soc,
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/* 36th bit should be 1 then HW know this is CMEM address */
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cc_cfg.lut_base_addr_39_32 = 0x10;
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- cc_cfg.wbm2sw6_cc_en = 1;
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- cc_cfg.wbm2sw5_cc_en = 1;
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- cc_cfg.wbm2sw4_cc_en = 1;
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- cc_cfg.wbm2sw3_cc_en = 1;
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- cc_cfg.wbm2sw2_cc_en = 1;
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- cc_cfg.wbm2sw1_cc_en = 1;
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- cc_cfg.wbm2sw0_cc_en = 1;
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- cc_cfg.wbm2fw_cc_en = 0;
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+ dp_cc_wbm_sw_en_cfg(&cc_cfg);
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hal_cookie_conversion_reg_cfg_be(soc->hal_soc, &cc_cfg);
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}
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