disp: msm: sde: Update LUT DMA reg dump ranges and offsets

Update the LUT DMA register range registration to target
specific ranges of valid registers instead of the full
memory region of the LUT DMA module. This ensures that
unused LUT DMA register regions are not dumped.

Change-Id: I3739692ae7fcfd5777bb8774dd34c16ab87c3ae1
Signed-off-by: Christopher Braga <[email protected]>

msm/sde/sde_hw_reg_dma_v1.c

@@ -967,6 +967,7 @@ static int init_reg_dma_vbif(struct sde_hw_reg_dma *cfg)
 	return ret;
 }
 
+#define BASE_REG_SIZE 0x400
 int init_v2(struct sde_hw_reg_dma *cfg)
 {
 	int ret = 0, i = 0;
@@ -989,8 +990,24 @@ int init_v2(struct sde_hw_reg_dma *cfg)
 
 	v1_supported[IGC] = GRP_DSPP_HW_BLK_SELECT | GRP_VIG_HW_BLK_SELECT |
 			GRP_DMA_HW_BLK_SELECT;
-	if (cfg->caps->reg_dma_blks[REG_DMA_TYPE_SB].valid == true)
+	if (cfg->caps->reg_dma_blks[REG_DMA_TYPE_SB].valid == true) {
+		char name[20];
+		uint32_t base = cfg->caps->reg_dma_blks[REG_DMA_TYPE_SB].base;
+
+		snprintf(name, sizeof(name), "REG_DMA_SB");
+		sde_dbg_reg_register_dump_range(LUTDMA_DBG_NAME, name, base,
+				base + BASE_REG_SIZE, cfg->caps->xin_id);
 		reg_dma->ops.last_command_sb = last_cmd_sb_v2;
+	}
+
+	if (cfg->caps->reg_dma_blks[REG_DMA_TYPE_DB].valid == true) {
+		char name[20];
+		uint32_t base = cfg->caps->reg_dma_blks[REG_DMA_TYPE_DB].base;
+
+		snprintf(name, sizeof(name), "REG_DMA_DB");
+		sde_dbg_reg_register_dump_range(LUTDMA_DBG_NAME, name, base,
+				base + BASE_REG_SIZE, cfg->caps->xin_id);
+	}
 
 	if (cfg->caps->split_vbif_supported)
 		ret = init_reg_dma_vbif(cfg);
@@ -998,8 +1015,10 @@ int init_v2(struct sde_hw_reg_dma *cfg)
 	return ret;
 }
 
+#define CTL_REG_SIZE 0x80
 int init_v3(struct sde_hw_reg_dma *cfg)
 {
+	char name[20];
 	int ret = 0, i;
 
 	ret = init_v2(cfg);
@@ -1017,6 +1036,29 @@ int init_v3(struct sde_hw_reg_dma *cfg)
 		reg_dma_ctl_queue1_off[i] = reg_dma_ctl0_queue1_cmd0_offset * i + 8;
 	}
 
+	/* Register DBG DUMP RANGES - CTL paths are 0x80 in size */
+	if (cfg->caps->reg_dma_blks[REG_DMA_TYPE_DB].valid) {
+		for (i = CTL_0; i < ARRAY_SIZE(reg_dma_ctl_queue_off); i++) {
+			u32 base = cfg->caps->reg_dma_blks[REG_DMA_TYPE_DB].base +
+					reg_dma_ctl_queue_off[i];
+
+			snprintf(name, sizeof(name), "REG_DMA_DB_CTL%d", i);
+			sde_dbg_reg_register_dump_range(LUTDMA_DBG_NAME, name, base,
+					base + CTL_REG_SIZE, cfg->caps->xin_id);
+		}
+	}
+
+	if (cfg->caps->reg_dma_blks[REG_DMA_TYPE_SB].valid) {
+		for (i = CTL_0; i < ARRAY_SIZE(reg_dma_ctl_queue_off); i++) {
+			u32 base = cfg->caps->reg_dma_blks[REG_DMA_TYPE_SB].base +
+					reg_dma_ctl_queue_off[i];
+
+			snprintf(name, sizeof(name), "REG_DMA_SB_CTL%d", i);
+			sde_dbg_reg_register_dump_range(LUTDMA_DBG_NAME, name, base,
+					base + CTL_REG_SIZE, cfg->caps->xin_id);
+		}
+	}
+
 	for (i = CTL_0; i < CTL_MAX; i++) {
 		ctl_trigger_done_mask[i][DMA_CTL_QUEUE0] = BIT(3);
 		ctl_trigger_done_mask[i][DMA_CTL_QUEUE1] = BIT(4);

msm/sde/sde_kms.c

@@ -4849,7 +4849,7 @@ static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
 		unsigned long mdp_addr = msm_get_phys_addr(platformdev, "mdp_phys");
 		sde_kms->reg_dma_len = msm_iomap_size(platformdev, "regdma_phys");
 		sde_kms->reg_dma_off = msm_get_phys_addr(platformdev, "regdma_phys") - mdp_addr;
-		rc =  sde_dbg_reg_register_base("reg_dma", sde_kms->reg_dma,
+		rc =  sde_dbg_reg_register_base(LUTDMA_DBG_NAME, sde_kms->reg_dma,
 				sde_kms->reg_dma_len,
 				msm_get_phys_addr(platformdev, "regdma_phys"),
 				SDE_DBG_LUTDMA);

msm/sde/sde_reg_dma.c

@@ -99,6 +99,13 @@ int sde_reg_dma_init(void __iomem *addr, struct sde_mdss_cfg *m,
 	int rc = 0;
 	set_default_dma_ops(&reg_dma);
 
+	/**
+	 * Register dummy range to ensure register dump is only done on
+	 * targeted LUTDMA regions. start = 1, end = 1 so full range isn't used
+	 */
+	sde_dbg_reg_register_dump_range(LUTDMA_DBG_NAME, "DUMMY_LUTDMA", 1, 1,
+			m->dma_cfg.xin_id);
+
 	if (!addr || !m || !dev) {
 		DRM_DEBUG("invalid addr %pK catalog %pK dev %pK\n", addr, m,
 				dev);

msm/sde_dbg.c

@@ -42,8 +42,8 @@
 /* offsets from LUTDMA top address for the debug buses */
 #define LUTDMA_0_DEBUG_BUS_CTRL		0x1e8
 #define LUTDMA_0_DEBUG_BUS_STATUS	0x1ec
-#define LUTDMA_1_DEBUG_BUS_CTRL		0x5e8
-#define LUTDMA_1_DEBUG_BUS_STATUS	0x5ec
+#define LUTDMA_1_DEBUG_BUS_CTRL		0x9e8
+#define LUTDMA_1_DEBUG_BUS_STATUS	0x9ec
 
 /* offsets from sde top address for the debug buses */
 #define DBGBUS_SSPP0		0x188

msm/sde_dbg.h

@@ -34,6 +34,8 @@
 #define SDE_EVTLOG_H32(val) (val >> 32)
 #define SDE_EVTLOG_L32(val) (val & 0xffffffff)
 
+#define LUTDMA_DBG_NAME "reg_dma"
+
 /* flags to enable the HW block dumping */
 #define SDE_DBG_SDE		BIT(0)
 #define SDE_DBG_RSC		BIT(1)