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video: driver: add support for cyclic intra refresh

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Currently driver supports only random intra refresh, extend
it to support cyclic intra refresh too.
Cyclic intra refresh is supported dynamically as well.
- If intra refresh type is set and num of LCU’s to be refreshed
  are non-zero before session start, intra refresh will be enabled
  throughout the session.
  Any further dynamic settings in the number of LCU’s including 0
  will be honored accordingly.
- If intra refresh type is set and num of LCU’s to be refreshed are zero
  before session start, intra refresh will be disabled.
  When client sets it to non-zero value dynamically, driver will set
  HFI_PROP_REQUEST_SYNC_FRAME with
  HFI_SYNC_FRAME_REQUEST_WITH_PREFIX_SEQ_HDR.
  Driver needs to send HFI_PROP_REQUEST_SYNC_FRAME only at time of
  CIR Enable, no need to send at time of disable/enable again.

Change-Id: I10a2fb22d131353721ee658213ed807ce0794009
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
This commit is contained in:
Dikshita Agarwal
2022-01-24 14:26:01 +05:30
parent 0abd877e95
commit 8f0e12cc93
11 changed files with 219 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
driver/platform/kalama/src/msm_vidc_kalama.c
View File

@@ -154,7 +154,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
0, 0,
0,
{0},
{META_ROI_INFO}},
{META_ROI_INFO, IR_PERIOD}},
{PIX_FMTS, ENC, HEVC,
MSM_VIDC_FMT_NV12,
MSM_VIDC_FMT_TP10C,
@@ -174,7 +174,8 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
* META_ROI_INFO -> MIN_QUALITY -> BLUR_TYPES
*/
PROFILE, MIN_FRAME_QP, MAX_FRAME_QP, I_FRAME_QP, P_FRAME_QP,
B_FRAME_QP, META_ROI_INFO, MIN_QUALITY, BLUR_TYPES}},
B_FRAME_QP, META_ROI_INFO, MIN_QUALITY, BLUR_TYPES,
IR_PERIOD}},
{PIX_FMTS, DEC, HEVC|HEIC,
MSM_VIDC_FMT_NV12,
@@ -487,7 +488,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
HFI_PROP_RATE_CONTROL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
{0},
{LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP,
{LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP,
P_FRAME_QP, B_FRAME_QP, ENH_LAYER_COUNT, BIT_RATE,
META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY,
PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING,
@@ -505,7 +506,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
HFI_PROP_RATE_CONTROL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
{0},
{LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP,
{LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP,
P_FRAME_QP, B_FRAME_QP, CONSTANT_QUALITY, ENH_LAYER_COUNT,
BIT_RATE, META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY,
PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING,
@@ -656,13 +657,25 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
HFI_PROP_BASELAYER_PRIORITYID,
CAP_FLAG_OUTPUT_PORT},
{IR_RANDOM, ENC, H264|HEVC,
{IR_TYPE, ENC, H264|HEVC,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC,
BIT(V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM) |
BIT(V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC),
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM,
V4L2_CID_MPEG_VIDEO_VIDC_INTRA_REFRESH_TYPE,
0,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{IR_PERIOD, ENC, H264|HEVC,
0, INT_MAX, 1, 0,
V4L2_CID_MPEG_VIDC_INTRA_REFRESH_PERIOD,
HFI_PROP_IR_RANDOM_PERIOD,
CAP_FLAG_OUTPUT_PORT,
{BITRATE_MODE, ALL_INTRA}, {0},
msm_vidc_adjust_ir_random, msm_vidc_set_u32},
0,
CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT |
CAP_FLAG_DYNAMIC_ALLOWED,
{BITRATE_MODE, ALL_INTRA, META_ROI_INFO, PIX_FMTS},
{0},
msm_vidc_adjust_ir_period, msm_vidc_set_ir_period},
{AU_DELIMITER, ENC, H264|HEVC,
V4L2_MPEG_MSM_VIDC_DISABLE,
@@ -1676,7 +1689,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
0,
CAP_FLAG_OUTPUT_PORT,
{GOP_SIZE, B_FRAME},
{LTR_COUNT, IR_RANDOM, SLICE_MODE},
{LTR_COUNT, IR_PERIOD, SLICE_MODE},
msm_vidc_adjust_all_intra, NULL},
{INPUT_METADATA_FD, ENC|DEC, CODECS_ALL,
@@ -1884,7 +1897,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
HFI_PROP_ROI_INFO,
CAP_FLAG_INPUT_PORT | CAP_FLAG_BITMASK,
{BITRATE_MODE, PIX_FMTS},
{MIN_QUALITY},
{MIN_QUALITY, IR_PERIOD},
msm_vidc_adjust_roi_info, NULL},
{META_SALIENCY_INFO, ENC, H264|HEVC,

34
driver/platform/waipio/src/msm_vidc_waipio.c
View File

@@ -146,7 +146,7 @@ static struct msm_platform_inst_capability instance_data_waipio[] = {
0, 0,
0,
{0},
{META_ROI_INFO}},
{META_ROI_INFO, IR_PERIOD}},
{PIX_FMTS, ENC, HEVC,
MSM_VIDC_FMT_NV12,
MSM_VIDC_FMT_TP10C,
@@ -166,7 +166,8 @@ static struct msm_platform_inst_capability instance_data_waipio[] = {
* META_ROI_INFO -> MIN_QUALITY -> BLUR_TYPES
*/
PROFILE, MIN_FRAME_QP, MAX_FRAME_QP, I_FRAME_QP, P_FRAME_QP,
B_FRAME_QP, META_ROI_INFO, MIN_QUALITY, BLUR_TYPES}},
B_FRAME_QP, META_ROI_INFO, MIN_QUALITY, BLUR_TYPES,
IR_PERIOD}},
{PIX_FMTS, DEC, HEVC|HEIC,
MSM_VIDC_FMT_NV12,
@@ -435,7 +436,7 @@ static struct msm_platform_inst_capability instance_data_waipio[] = {
HFI_PROP_RATE_CONTROL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
{0},
{LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP,
{LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP,
P_FRAME_QP, B_FRAME_QP, ENH_LAYER_COUNT, BIT_RATE,
META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY,
PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING,
@@ -453,7 +454,7 @@ static struct msm_platform_inst_capability instance_data_waipio[] = {
HFI_PROP_RATE_CONTROL,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
{0},
{LTR_COUNT, IR_RANDOM, TIME_DELTA_BASED_RC, I_FRAME_QP,
{LTR_COUNT, IR_PERIOD, TIME_DELTA_BASED_RC, I_FRAME_QP,
P_FRAME_QP, B_FRAME_QP, CONSTANT_QUALITY, ENH_LAYER_COUNT,
BIT_RATE, META_ROI_INFO, MIN_QUALITY, BITRATE_BOOST, VBV_DELAY,
PEAK_BITRATE, SLICE_MODE, CONTENT_ADAPTIVE_CODING,
@@ -604,13 +605,24 @@ static struct msm_platform_inst_capability instance_data_waipio[] = {
HFI_PROP_BASELAYER_PRIORITYID,
CAP_FLAG_OUTPUT_PORT},
{IR_RANDOM, ENC, H264|HEVC,
{IR_TYPE, ENC, H264|HEVC,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM,
BIT(V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM),
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM,
V4L2_CID_MPEG_VIDEO_VIDC_INTRA_REFRESH_TYPE,
0,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{IR_PERIOD, ENC, H264|HEVC,
0, INT_MAX, 1, 0,
V4L2_CID_MPEG_VIDC_INTRA_REFRESH_PERIOD,
HFI_PROP_IR_RANDOM_PERIOD,
CAP_FLAG_OUTPUT_PORT,
{BITRATE_MODE, ALL_INTRA}, {0},
msm_vidc_adjust_ir_random, msm_vidc_set_u32},
0,
CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT |
CAP_FLAG_DYNAMIC_ALLOWED,
{BITRATE_MODE, ALL_INTRA, META_ROI_INFO, PIX_FMTS},
{0},
msm_vidc_adjust_ir_period, msm_vidc_set_ir_period},
{AU_DELIMITER, ENC, H264|HEVC,
V4L2_MPEG_MSM_VIDC_DISABLE,
@@ -1526,7 +1538,7 @@ static struct msm_platform_inst_capability instance_data_waipio[] = {
0,
CAP_FLAG_OUTPUT_PORT,
{GOP_SIZE, B_FRAME},
{LTR_COUNT, IR_RANDOM, SLICE_MODE},
{LTR_COUNT, IR_PERIOD, SLICE_MODE},
msm_vidc_adjust_all_intra, NULL},
{INPUT_METADATA_FD, ENC|DEC, CODECS_ALL,
@@ -1729,7 +1741,7 @@ static struct msm_platform_inst_capability instance_data_waipio[] = {
HFI_PROP_ROI_INFO,
CAP_FLAG_INPUT_PORT | CAP_FLAG_BITMASK,
{BITRATE_MODE, PIX_FMTS},
{MIN_QUALITY},
{MIN_QUALITY, IR_PERIOD},
msm_vidc_adjust_roi_info, NULL},
{META_SALIENCY_INFO, ENC, H264|HEVC,

2
driver/vidc/inc/hfi_property.h
View File

@@ -533,6 +533,8 @@ enum hfi_nal_length_field_type {
#define HFI_PROP_MAINTAIN_MIN_QUALITY 0x0300017D
#define HFI_PROP_IR_CYCLIC_PERIOD 0x0300017E
#define HFI_PROP_AV1_FILM_GRAIN_PRESENT 0x03000180
#define HFI_PROP_AV1_SUPER_BLOCK_ENABLED 0x03000181

7
driver/vidc/inc/msm_vidc_control.h
View File

@@ -23,7 +23,7 @@ int msm_vidc_adjust_profile(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_ltr_count(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_use_ltr(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_mark_ltr(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_ir_random(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_ir_period(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_delta_based_rc(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_output_order(void *instance, struct v4l2_ctrl *ctrl);
int msm_vidc_adjust_input_buf_host_max_count(void *instance, struct v4l2_ctrl *ctrl);
@@ -111,6 +111,8 @@ int msm_vidc_set_csc_custom_matrix(void *instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_session_priority(void* instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_ir_period(void *instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_level(void *instance,
enum msm_vidc_inst_capability_type cap_id);
int msm_vidc_set_s32(void *instance,
@@ -125,4 +127,7 @@ int msm_vidc_update_cap_value(struct msm_vidc_inst *inst, u32 cap,
s32 adjusted_val, const char *func);
int msm_vidc_get_parent_value(struct msm_vidc_inst* inst, u32 cap, u32 parent,
s32 *value, const char *func);
u32 msm_vidc_get_port_info(struct msm_vidc_inst *inst,
enum msm_vidc_inst_capability_type cap_id);
#endif

1
driver/vidc/inc/msm_vidc_inst.h
View File

@@ -172,5 +172,6 @@ struct msm_vidc_inst {
u32 auto_framerate;
u32 max_rate;
bool has_bframe;
bool ir_enabled;
};
#endif // _MSM_VIDC_INST_H_

3
driver/vidc/inc/msm_vidc_internal.h
View File

@@ -434,6 +434,7 @@ enum msm_vidc_inst_capability_type {
USE_LTR,
MARK_LTR,
BASELAYER_PRIORITY,
IR_TYPE,
AU_DELIMITER,
GRID,
I_FRAME_MIN_QP,
@@ -511,7 +512,7 @@ enum msm_vidc_inst_capability_type {
TRANSFORM_8X8,
STAGE,
LTR_COUNT,
IR_RANDOM,
IR_PERIOD,
BITRATE_BOOST,
SLICE_MODE,
BLUR_RESOLUTION,

2
driver/vidc/inc/venus_hfi.h
View File

@@ -61,6 +61,8 @@ int venus_hfi_trigger_stability(struct msm_vidc_inst *inst, u32 type,
u32 client_id, u32 val);
int venus_hfi_scale_clocks(struct msm_vidc_inst* inst, u64 freq);
int venus_hfi_scale_buses(struct msm_vidc_inst* inst, u64 bw_ddr, u64 bw_llcc);
int venus_hfi_set_ir_period(struct msm_vidc_inst *inst, u32 ir_type,
enum msm_vidc_inst_capability_type cap_id);
void venus_hfi_pm_work_handler(struct work_struct *work);
irqreturn_t venus_hfi_isr(int irq, void *data);

93
driver/vidc/src/msm_vidc_control.c
View File

@@ -144,7 +144,13 @@ static const char * const av1_tier[] = {
NULL,
};
static u32 msm_vidc_get_port_info(struct msm_vidc_inst *inst,
static const char *const mpeg_video_vidc_ir_type[] = {
"Random",
"Cyclic",
NULL,
};
u32 msm_vidc_get_port_info(struct msm_vidc_inst *inst,
enum msm_vidc_inst_capability_type cap_id)
{
struct msm_vidc_inst_capability *capability = inst->capabilities;
@@ -185,6 +191,8 @@ static const char * const * msm_vidc_get_qmenu_type(
return av1_level;
case V4L2_CID_MPEG_VIDEO_AV1_TIER:
return av1_tier;
case V4L2_CID_MPEG_VIDEO_VIDC_INTRA_REFRESH_TYPE:
return mpeg_video_vidc_ir_type;
default:
i_vpr_e(inst, "%s: No available qmenu for ctrl %#x\n",
__func__, control_id);
@@ -1413,10 +1421,11 @@ int msm_vidc_adjust_mark_ltr(void *instance, struct v4l2_ctrl *ctrl)
return 0;
}
int msm_vidc_adjust_ir_random(void *instance, struct v4l2_ctrl *ctrl)
int msm_vidc_adjust_ir_period(void *instance, struct v4l2_ctrl *ctrl)
{
struct msm_vidc_inst_capability *capability;
s32 adjusted_value, all_intra = 0;
s32 adjusted_value, all_intra = 0, roi_enable = 0,
pix_fmts = MSM_VIDC_FMT_NONE;
struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
if (!inst || !inst->capabilities) {
@@ -1425,30 +1434,54 @@ int msm_vidc_adjust_ir_random(void *instance, struct v4l2_ctrl *ctrl)
}
capability = inst->capabilities;
adjusted_value = ctrl ? ctrl->val : capability->cap[IR_RANDOM].value;
adjusted_value = ctrl ? ctrl->val : capability->cap[IR_PERIOD].value;
if (msm_vidc_get_parent_value(inst, IR_RANDOM, ALL_INTRA,
&all_intra, __func__))
if (msm_vidc_get_parent_value(inst, IR_PERIOD, ALL_INTRA,
&all_intra, __func__) ||
msm_vidc_get_parent_value(inst, IR_PERIOD, META_ROI_INFO,
&roi_enable, __func__))
return -EINVAL;
if (all_intra) {
adjusted_value = 0;
i_vpr_h(inst, "%s: IR unsupported, all intra: %d\n",
i_vpr_h(inst, "%s: intra refresh unsupported, all intra: %d\n",
__func__, all_intra);
goto exit;
}
if (roi_enable) {
i_vpr_h(inst,
"%s: intra refresh unsupported with roi metadata\n",
__func__);
adjusted_value = 0;
goto exit;
}
if (inst->codec == MSM_VIDC_HEVC) {
if (msm_vidc_get_parent_value(inst, IR_PERIOD,
PIX_FMTS, &pix_fmts, __func__))
return -EINVAL;
if (is_10bit_colorformat(pix_fmts)) {
i_vpr_h(inst,
"%s: intra refresh is supported only for 8 bit\n",
__func__);
adjusted_value = 0;
goto exit;
}
}
/*
* BITRATE_MODE dependency is NOT common across all chipsets.
* Hence, do not return error if not specified as one of the parent.
*/
if (is_parent_available(inst, IR_RANDOM, BITRATE_MODE, __func__) &&
if (is_parent_available(inst, IR_PERIOD, BITRATE_MODE, __func__) &&
inst->hfi_rc_type != HFI_RC_CBR_CFR &&
inst->hfi_rc_type != HFI_RC_CBR_VFR)
adjusted_value = 0;
exit:
msm_vidc_update_cap_value(inst, IR_RANDOM,
msm_vidc_update_cap_value(inst, IR_PERIOD,
adjusted_value, __func__);
return 0;
@@ -4030,6 +4063,48 @@ int msm_vidc_set_level(void *instance,
return rc;
}
int msm_vidc_set_ir_period(void *instance,
enum msm_vidc_inst_capability_type cap_id)
{
int rc = 0;
struct msm_vidc_inst *inst = (struct msm_vidc_inst *)instance;
u32 ir_type = 0;
struct msm_vidc_core *core;
if (!inst || !inst->capabilities) {
d_vpr_e("%s: invalid params\n", __func__);
return -EINVAL;
}
core = inst->core;
if (inst->capabilities->cap[IR_TYPE].value ==
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM) {
if (inst->bufq[OUTPUT_PORT].vb2q->streaming) {
i_vpr_h(inst, "%s: dynamic random intra refresh not allowed\n",
__func__);
return 0;
}
ir_type = HFI_PROP_IR_RANDOM_PERIOD;
} else if (inst->capabilities->cap[IR_TYPE].value ==
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC) {
ir_type = HFI_PROP_IR_CYCLIC_PERIOD;
} else {
i_vpr_e(inst, "%s: invalid ir_type %d\n",
__func__, inst->capabilities->cap[IR_TYPE]);
return -EINVAL;
}
rc = venus_hfi_set_ir_period(inst, ir_type, cap_id);
if (rc) {
i_vpr_e(inst, "%s: failed to set ir period %d\n",
__func__, inst->capabilities->cap[IR_PERIOD].value);
return rc;
}
return rc;
}
int msm_vidc_set_q16(void *instance,
enum msm_vidc_inst_capability_type cap_id)
{

4
driver/vidc/src/msm_vidc_driver.c
View File

@@ -133,6 +133,7 @@ static const struct msm_vidc_cap_name cap_name_arr[] = {
{USE_LTR, "USE_LTR" },
{MARK_LTR, "MARK_LTR" },
{BASELAYER_PRIORITY, "BASELAYER_PRIORITY" },
{IR_TYPE, "IR_TYPE" },
{AU_DELIMITER, "AU_DELIMITER" },
{GRID, "GRID" },
{I_FRAME_MIN_QP, "I_FRAME_MIN_QP" },
@@ -206,7 +207,7 @@ static const struct msm_vidc_cap_name cap_name_arr[] = {
{TRANSFORM_8X8, "TRANSFORM_8X8" },
{STAGE, "STAGE" },
{LTR_COUNT, "LTR_COUNT" },
{IR_RANDOM, "IR_RANDOM" },
{IR_PERIOD, "IR_PERIOD" },
{BITRATE_BOOST, "BITRATE_BOOST" },
{SLICE_MODE, "SLICE_MODE" },
{BLUR_RESOLUTION, "BLUR_RESOLUTION" },
@@ -1370,6 +1371,7 @@ bool msm_vidc_allow_s_ctrl(struct msm_vidc_inst *inst, u32 id)
case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK:
case V4L2_CID_MPEG_VIDC_PRIORITY:
case V4L2_CID_MPEG_VIDC_INPUT_METADATA_FD:
case V4L2_CID_MPEG_VIDC_INTRA_REFRESH_PERIOD:
allow = true;
break;
default:

65
driver/vidc/src/venus_hfi.c
View File

@@ -17,6 +17,7 @@
#include "venus_hfi.h"
#include "msm_vidc_core.h"
#include "msm_vidc_control.h"
#include "msm_vidc_power.h"
#include "msm_vidc_platform.h"
#include "msm_vidc_memory.h"
@@ -3662,3 +3663,67 @@ exit:
return rc;
}
int venus_hfi_set_ir_period(struct msm_vidc_inst *inst, u32 ir_type,
enum msm_vidc_inst_capability_type cap_id)
{
int rc = 0;
struct msm_vidc_core *core;
u32 ir_period, sync_frame_req = 0;
if (!inst || !inst->core) {
d_vpr_e("%s: invalid params\n", __func__);
return -EINVAL;
}
core = inst->core;
core_lock(core, __func__);
ir_period = inst->capabilities->cap[cap_id].value;
rc = hfi_create_header(inst->packet, inst->packet_size,
inst->session_id, core->header_id++);
if (rc)
goto exit;
/* Request sync frame if ir period enabled dynamically */
if (!inst->ir_enabled) {
inst->ir_enabled = ((ir_period > 0) ? true : false);
if (inst->ir_enabled && inst->bufq[OUTPUT_PORT].vb2q->streaming) {
sync_frame_req = HFI_SYNC_FRAME_REQUEST_WITH_PREFIX_SEQ_HDR;
rc = hfi_create_packet(inst->packet, inst->packet_size,
HFI_PROP_REQUEST_SYNC_FRAME,
HFI_HOST_FLAGS_NONE,
HFI_PAYLOAD_U32_ENUM,
msm_vidc_get_port_info(inst, REQUEST_I_FRAME),
core->packet_id++,
&sync_frame_req,
sizeof(u32));
if (rc)
goto exit;
}
}
rc = hfi_create_packet(inst->packet, inst->packet_size,
ir_type,
HFI_HOST_FLAGS_NONE,
HFI_PAYLOAD_U32,
msm_vidc_get_port_info(inst, cap_id),
core->packet_id++,
&ir_period,
sizeof(u32));
if (rc)
goto exit;
rc = __iface_cmdq_write(inst->core, inst->packet);
if (rc) {
i_vpr_e(inst, "%s: failed to set cap[%d] %s to fw\n",
__func__, cap_id, cap_name(cap_id));
goto exit;
}
exit:
core_unlock(core, __func__);
return rc;
}

7
include/uapi/vidc/media/v4l2_vidc_extensions.h
View File

@@ -71,6 +71,13 @@
/* Encoder Intra refresh period */
#define V4L2_CID_MPEG_VIDC_INTRA_REFRESH_PERIOD (V4L2_CID_MPEG_VIDC_BASE + 0xB)
/* Encoder Intra refresh type */
#define V4L2_CID_MPEG_VIDEO_VIDC_INTRA_REFRESH_TYPE \
(V4L2_CID_MPEG_VIDC_BASE + 0xC)
enum v4l2_mpeg_vidc_ir_type {
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM = 0x0,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC = 0x1,
};
#define V4L2_CID_MPEG_VIDC_TIME_DELTA_BASED_RC (V4L2_CID_MPEG_VIDC_BASE + 0xD)
/* Encoder quality controls */
#define V4L2_CID_MPEG_VIDC_CONTENT_ADAPTIVE_CODING \