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Merge "disp: msm: dsi: Fix DSI lane swapping"

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This commit is contained in:
qctecmdr
2023-04-29 23:02:10 -07:00
committed by Gerrit - the friendly Code Review server
parent f993f4d8e0 f59a9af17c
commit 8ef80f7cf4
2 changed files with 21 additions and 10 deletions
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20
msm/dsi/dsi_ctrl_hw_2_2.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include <linux/iopoll.h> #include <linux/iopoll.h>
#include "dsi_ctrl_hw.h" #include "dsi_ctrl_hw.h"
@@ -24,18 +24,26 @@
#define DSI_MDP_MISR_CTRL 0x364 #define DSI_MDP_MISR_CTRL 0x364
#define DSI_MDP_MISR_SIGNATURE 0x368 #define DSI_MDP_MISR_SIGNATURE 0x368
void dsi_ctrl_hw_22_setup_lane_map(struct dsi_ctrl_hw *ctrl, void dsi_ctrl_hw_22_setup_lane_map(struct dsi_ctrl_hw *ctrl_hw,
struct dsi_lane_map *lane_map) struct dsi_lane_map *lane_map)
{ {
u32 reg_value = lane_map->lane_map_v2[DSI_LOGICAL_LANE_0] | struct dsi_ctrl *ctrl = container_of(ctrl_hw, struct dsi_ctrl, hw);
u32 reg_value;
/* Lane swap is performed through PHY for controller version 2.2/PHY versions 3.0 and above */
if (ctrl->version >= DSI_CTRL_VERSION_2_2) {
DSI_CTRL_HW_DBG(ctrl_hw, "DSI controller version is >=2.2, lane swap is performed through PHY");
return;
}
reg_value = lane_map->lane_map_v2[DSI_LOGICAL_LANE_0] |
(lane_map->lane_map_v2[DSI_LOGICAL_LANE_1] << 4) | (lane_map->lane_map_v2[DSI_LOGICAL_LANE_1] << 4) |
(lane_map->lane_map_v2[DSI_LOGICAL_LANE_2] << 8) | (lane_map->lane_map_v2[DSI_LOGICAL_LANE_2] << 8) |
(lane_map->lane_map_v2[DSI_LOGICAL_LANE_3] << 12); (lane_map->lane_map_v2[DSI_LOGICAL_LANE_3] << 12);
DSI_W32(ctrl, DSI_LANE_SWAP_CTRL, reg_value); DSI_W32(ctrl_hw, DSI_LOGICAL_LANE_SWAP_CTRL, reg_value);
DSI_CTRL_HW_DBG(ctrl, "[DSI_%d] Lane swap setup complete\n", DSI_CTRL_HW_DBG(ctrl_hw, "[DSI_%d] Lane swap setup complete\n",
ctrl->index); ctrl_hw->index);
} }
int dsi_ctrl_hw_22_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, int dsi_ctrl_hw_22_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl,

11
msm/dsi/dsi_display.c
View File

@@ -3964,22 +3964,25 @@ static int dsi_display_parse_lane_map(struct dsi_display *display)
{ {
int rc = 0, i = 0; int rc = 0, i = 0;
const char *data; const char *data;
u8 temp[DSI_LANE_MAX - 1]; u32 temp[DSI_LANE_MAX - 1];
struct dsi_parser_utils *utils;
if (!display) { if (!display) {
DSI_ERR("invalid params\n"); DSI_ERR("invalid params\n");
return -EINVAL; return -EINVAL;
} }
utils = &display->panel->utils;
/* lane-map-v2 supersedes lane-map-v1 setting */ /* lane-map-v2 supersedes lane-map-v1 setting */
rc = of_property_read_u8_array(display->pdev->dev.of_node, rc = utils->read_u32_array(display->pdev->dev.of_node,
"qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1)); "qcom,lane-map-v2", temp, (DSI_LANE_MAX - 1));
if (!rc) { if (!rc) {
for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++) for (i = DSI_LOGICAL_LANE_0; i < (DSI_LANE_MAX - 1); i++)
display->lane_map.lane_map_v2[i] = BIT(temp[i]); display->lane_map.lane_map_v2[i] = BIT(temp[i]);
return 0; return 0;
} else if (rc != EINVAL) { } else if (rc != -EINVAL) {
DSI_DEBUG("Incorrect mapping, configure default\n"); DSI_DEBUG("Incorrect mapping, configuring default\n");
goto set_default; goto set_default;
} }