asoc: bolero: reset all clks after SSR/PDR

After SSR/PDR, the lpass clocks will be in off state. Force restart
clocks after SSR/PDR, if enabled before SSR/PDR, to reenable the clocks.

Change-Id: I3d850d92bdc6324aa7a64a83a9066f388a85c7f7
Signed-off-by: Meng Wang <mengw@codeaurora.org>
这个提交包含在:
Meng Wang
2019-05-08 15:12:56 +08:00
父节点 988afa4fca
当前提交 8ef0cc2ed4
修改 8 个文件,包含 70 行新增6 行删除

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@@ -234,6 +234,9 @@ static int va_macro_event_handler(struct snd_soc_component *component,
"%s: va_mclk_users is non-zero still, audio SSR fail!!\n",
__func__);
break;
case BOLERO_MACRO_EVT_CLK_RESET:
bolero_rsc_clk_reset(va_dev, VA_CORE_CLK);
break;
default:
break;
}