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@@ -23023,6 +23023,48 @@ typedef enum {
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WMI_WOW_RESUME_FLAG_TX_DATA = 0x00000001, /* TX data pending to be sent in resume */
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} WMI_WOW_RESUME_FLAG_ENUM;
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+/* wow nack reason codes */
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+typedef enum {
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+ /* WoW error due to unnkown reason */
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+ WMI_WOW_NON_ACK_REASON_UNKNOWN = 0,
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+
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+ /* WoW error due to TX failure */
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+ WMI_WOW_NON_ACK_REASON_TX = 1,
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+
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+ /* WoW error due to some data blocked */
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+ WMI_WOW_NON_ACK_REASON_IS_BLOCK = 2,
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+
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+ /* WoW error in WFA mode */
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+ WMI_WOW_NON_ACK_REASON_NOT_ALLOW = 3,
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+
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+ /* WoW error mac operation fail */
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+ WMI_WOW_NON_ACK_REASON_HW_FAIL = 4,
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+
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+ /* WoW error due to timeout */
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+ WMI_WOW_NON_ACK_REASON_TIMEOUT = 5,
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+
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+ /* WoW error due to RTT or CFR capture active */
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+ WMI_WOW_NON_ACK_REASON_RTT_DMA = 6,
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+
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+ /* WoW error due to roam module holding lock */
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+ WMI_WOW_NON_ACK_REASON_ROAM = 7,
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+
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+ /* WoW error remote peer not sleeping */
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+ WMI_WOW_NON_ACK_REASON_PEER_ACTIVE = 8,
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+
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+ /* WoW error due to WoW entry defer failed */
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+ WMI_WOW_NON_ACK_REASON_DEFER_FAILURE = 9,
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+
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+ /* WoW error due to WoW entry defer timeout */
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+ WMI_WOW_NON_ACK_REASON_DEFER_TIMEOUT = 10,
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+
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+ /* WoW error due to FATAL event */
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+ WMI_WOW_NON_ACK_REASON_FATAL_EVENT = 11,
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+
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+ /* WoW error if close to TBTT */
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+ WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12,
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+} WMI_WOW_NACK_STATUS;
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+
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typedef struct {
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A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param */
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/* reserved0:
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@@ -41432,16 +41474,16 @@ typedef struct {
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#define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 1, 1, value)
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/* Bit 66: 20Mhz-only limited capabilities support */
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-#define WMI_EHTCAP_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1)
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-#define WMI_EHTCAP_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value)
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+#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1)
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+#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value)
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/* Bit 67: 20Mhz-only triggered MU beamforming full BW feedback and DL MU-MIMO */
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-#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1)
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-#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value)
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+#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1)
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+#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value)
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/* Bit 68: 20Mhz-only M-RU support */
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-#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1)
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-#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value)
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+#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1)
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+#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value)
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/* Bits 69-71: reserved */
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