msm: camera: sensor: Add Trace logs for CCI BURST WRITE

Add Trace logs for each threshold irq and corresponding
Error cases for BURST WRITE usecases.

CRs-Fixed: 3562709
Change-Id: I9e91fc0b9ae0eda20063c8150c8c4694b583355f
Signed-off-by: Lokesh Kumar Aakulu <[email protected]>
(cherry picked from commit 9326d397a2ec90696ce37a5d5966cdc671d657e3)

drivers/cam_sensor_module/cam_cci/cam_cci_core.c

@@ -798,6 +798,12 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev,
 		return -EINVAL;
 	}
 
+	trace_cam_cci_burst(cci_dev->soc_info.index, master, queue,
+		"cci burst write START for sid",
+		c_ctrl->cci_info->sid);
+	CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d : START for sid: 0x%x size: %d",
+		cci_dev->soc_info.index, master, queue, c_ctrl->cci_info->sid, i2c_msg->size);
+
 	addr_len = cam_cci_convert_type_to_num_bytes(i2c_msg->addr_type);
 	data_len = cam_cci_convert_type_to_num_bytes(i2c_msg->data_type);
 	len = (cmd_size * data_len + addr_len);
@@ -1005,6 +1011,10 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev,
 		cci_dev->soc_info.index, master, queue, num_word_written_to_queue,
 		cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]);
 
+	trace_cam_cci_burst(cci_dev->soc_info.index, master, queue,
+		"thirq_cnt",
+		cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]);
+
 	index = 0;
 	queue_start_threshold = half_queue_mark * MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_WORDS;
 	num_words_in_queue = cam_io_r_mb(base +
@@ -1043,6 +1053,9 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev,
 					"wait for Threshold_IRQ, th_irq_ref_cnt[%d]:%d",
 					cci_dev->soc_info.index, master, queue, queue,
 					cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]);
+				trace_cam_cci_burst(cci_dev->soc_info.index, master, queue,
+					"Q_START thirq_cnt",
+					cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]);
 
 				if (!cam_common_wait_for_completion_timeout(
 					&cci_dev->cci_master_info[master].th_burst_complete[queue],
@@ -1064,6 +1077,9 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev,
 					goto ERROR;
 				}
 				cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]--;
+				trace_cam_cci_burst(cci_dev->soc_info.index, master, queue,
+					"thirq raised Buflvl",
+					cci_dev->cci_master_info[master].th_irq_ref_cnt[queue]);
 				CAM_DBG(CAM_CCI,
 					"CCI%d_I2C_M%d_Q%d Threshold IRQ Raised, BufferLevel: %d",
 					cci_dev->soc_info.index, master, queue,
@@ -1132,6 +1148,12 @@ static int32_t cam_cci_data_queue_burst(struct cci_device *cci_dev,
 			cci_dev->soc_info.index, master, queue, (c_ctrl->cci_info->sid << 1), rc);
 		goto ERROR;
 	}
+	trace_cam_cci_burst(cci_dev->soc_info.index, master, queue,
+		"cci burst write Done for sid",
+		c_ctrl->cci_info->sid);
+	CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d : completed ....for sid: 0x%x size: %d",
+		cci_dev->soc_info.index, master, queue, c_ctrl->cci_info->sid, i2c_msg->size);
+
 ERROR:
 	kfree(data_queue);
 	return rc;

drivers/cam_sensor_module/cam_cci/cam_cci_dev.c

@@ -188,6 +188,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
 		spin_lock_irqsave(
 			&cci_master_info->lock_q[QUEUE_0],
 			flags);
+		trace_cam_cci_burst(cci_dev->soc_info.index, 1, 0,
+			"th_irq honoured irq1", irq_status1);
 		complete(&cci_master_info->th_burst_complete[QUEUE_0]);
 		spin_unlock_irqrestore(
 			&cci_master_info->lock_q[QUEUE_0],
@@ -199,6 +201,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
 		spin_lock_irqsave(
 			&cci_master_info->lock_q[QUEUE_1],
 			flags);
+		trace_cam_cci_burst(cci_dev->soc_info.index, 1, 1,
+			"th_irq honoured irq1", irq_status1);
 		complete(&cci_master_info->th_burst_complete[QUEUE_1]);
 		spin_unlock_irqrestore(
 			&cci_master_info->lock_q[QUEUE_1],
@@ -210,6 +214,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
 		spin_lock_irqsave(
 			&cci_master_info->lock_q[QUEUE_0],
 			flags);
+		trace_cam_cci_burst(cci_dev->soc_info.index, 0, 0,
+			"th_irq honoured irq1", irq_status1);
 		complete(&cci_master_info->th_burst_complete[QUEUE_0]);
 		spin_unlock_irqrestore(
 			&cci_master_info->lock_q[QUEUE_0],
@@ -221,6 +227,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
 		spin_lock_irqsave(
 			&cci_master_info->lock_q[QUEUE_1],
 			flags);
+		trace_cam_cci_burst(cci_dev->soc_info.index, 0, 1,
+			"th_irq honoured irq1", irq_status1);
 		complete(&cci_master_info->th_burst_complete[QUEUE_1]);
 		spin_unlock_irqrestore(
 			&cci_master_info->lock_q[QUEUE_1],
@@ -335,28 +343,34 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
 	if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_ERROR_BMSK) {
 		cci_dev->cci_master_info[MASTER_0].status = -EINVAL;
 		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK) {
-			if (cci_dev->is_probing)
+			if (cci_dev->is_probing) {
 				CAM_INFO(CAM_CCI,
 					"Base:%pK,cci: %d, M0_Q0 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
-			else
+			} else {
 				CAM_ERR(CAM_CCI,
 					"Base:%pK,cci: %d, M0_Q0 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
+				trace_cam_cci_burst(cci_dev->soc_info.index, 0, 0,
+					"NACK_ERROR irq0", irq_status0);
+			}
 			cam_cci_dump_registers(cci_dev, MASTER_0,
 					QUEUE_0);
 			complete_all(&cci_dev->cci_master_info[MASTER_0]
 				.report_q[QUEUE_0]);
 		}
 		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK) {
-			if (cci_dev->is_probing)
+			if (cci_dev->is_probing) {
 				CAM_INFO(CAM_CCI,
 					"Base:%pK,cci: %d, M0_Q1 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
-			else
+			} else {
 				CAM_ERR(CAM_CCI,
 					"Base:%pK,cci: %d, M0_Q1 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
+				trace_cam_cci_burst(cci_dev->soc_info.index, 0, 1,
+					"NACK_ERROR irq0", irq_status0);
+			}
 			cam_cci_dump_registers(cci_dev, MASTER_0,
 					QUEUE_1);
 			complete_all(&cci_dev->cci_master_info[MASTER_0]
@@ -377,28 +391,34 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
 	if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK) {
 		cci_dev->cci_master_info[MASTER_1].status = -EINVAL;
 		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK) {
-			if (cci_dev->is_probing)
+			if (cci_dev->is_probing) {
 				CAM_INFO(CAM_CCI,
 					"Base:%pK, cci: %d, M1_Q0 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
-			else
+			} else {
 				CAM_ERR(CAM_CCI,
 					"Base:%pK, cci: %d, M1_Q0 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
+				trace_cam_cci_burst(cci_dev->soc_info.index, 1, 0,
+					"NACK_ERROR irq0", irq_status0);
+			}
 			cam_cci_dump_registers(cci_dev, MASTER_1,
 					QUEUE_0);
 			complete_all(&cci_dev->cci_master_info[MASTER_1]
 			.report_q[QUEUE_0]);
 		}
 		if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK) {
-			if (cci_dev->is_probing)
+			if (cci_dev->is_probing) {
 				CAM_INFO(CAM_CCI,
 					"Base:%pK, cci: %d, M1_Q1 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
-			else
+			} else {
 				CAM_ERR(CAM_CCI,
 					"Base:%pK, cci: %d, M1_Q1 NACK ERROR: 0x%x",
 					base, cci_dev->soc_info.index, irq_status0);
+				trace_cam_cci_burst(cci_dev->soc_info.index, 1, 1,
+					"NACK_ERROR irq0", irq_status0);
+			}
 			cam_cci_dump_registers(cci_dev, MASTER_1,
 				QUEUE_1);
 			complete_all(&cci_dev->cci_master_info[MASTER_1]

drivers/cam_utils/cam_trace.h

@@ -405,6 +405,31 @@ TRACE_EVENT(cam_cdm_cb,
 	)
 );
 
+TRACE_EVENT(cam_cci_burst,
+	TP_PROTO(const int32_t idx, int32_t m,
+		int32_t q, const char *msg,
+		uint32_t val),
+	TP_ARGS(idx, m, q, msg, val),
+	TP_STRUCT__entry(
+		__field(int32_t, index)
+		__field(int32_t, master)
+		__field(int32_t, queue)
+		__string(msg, msg)
+		__field(uint32_t, value)
+	),
+	TP_fast_assign(
+		__entry->index = idx;
+		__entry->master = m;
+		__entry->queue = q;
+		__assign_str(msg, msg);
+		__entry->value = val;
+	),
+	TP_printk(
+		"CCI%d_M%d_Q%d %s : 0x%x",
+		__entry->index, __entry->master, __entry->queue, __get_str(msg), __entry->value
+	)
+);
+
 #endif /* _CAM_TRACE_H */
 
 /* This part must be outside protection */