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disp: msm: sde: reset mixers in crtc when ctl datapath switches

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This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.

Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
   CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
   the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
   allocates new resources and CTL_1 is allocated.

sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.

Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This commit is contained in:
Jayaprakash Madisetty
2021-12-03 13:17:08 +05:30
parent 2a867bb340
commit 8b01e6124e
7 changed files with 41 additions and 8 deletions
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6
msm/sde/sde_encoder.c
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@@ -1,4 +1,5 @@
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
@@ -2487,6 +2488,7 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
struct drm_connector *conn;
struct sde_connector_state *c_state;
struct msm_display_mode *msm_mode;
struct sde_crtc *sde_crtc;
int i = 0, ret;
int num_lm, num_intf, num_pp_per_intf;
@@ -2518,6 +2520,7 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
}
sde_enc->crtc = drm_enc->crtc;
sde_crtc = to_sde_crtc(drm_enc->crtc);
sde_crtc_set_qos_dirty(drm_enc->crtc);
/* get and store the mode_info */
@@ -2577,7 +2580,8 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
phys->hw_pp = sde_enc->hw_pp[i * num_pp_per_intf];
phys->connector = conn;
if (phys->ops.mode_set)
phys->ops.mode_set(phys, mode, adj_mode);
phys->ops.mode_set(phys, mode, adj_mode,
&sde_crtc->reinit_crtc_mixers);
}
}