|
@@ -1,6 +1,6 @@
|
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
|
|
/*
|
|
|
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
|
|
|
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
|
|
|
*/
|
|
|
|
|
|
#include <linux/of.h>
|
|
@@ -273,6 +273,7 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
|
|
|
uint32_t status = 0, retry_cnt = 0;
|
|
|
bool reset_ipe_cdm_fail = false;
|
|
|
bool reset_ipe_top_fail = false;
|
|
|
+ struct cam_ipe_device_hw_info *hw_info = NULL;
|
|
|
|
|
|
CAM_DBG(CAM_ICP, "CAM_ICP_IPE_CMD_RESET");
|
|
|
if (!core_info->clk_enable || !core_info->cpas_start) {
|
|
@@ -281,12 +282,14 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
|
|
|
+ hw_info = core_info->ipe_hw_info;
|
|
|
+
|
|
|
/* IPE CDM core reset*/
|
|
|
- cam_io_w_mb((uint32_t)0xF,
|
|
|
- soc_info->reg_map[0].mem_base + IPE_CDM_RST_CMD);
|
|
|
+ cam_io_w_mb(hw_info->cdm_rst_val,
|
|
|
+ soc_info->reg_map[0].mem_base + hw_info->cdm_rst_cmd);
|
|
|
while (retry_cnt < HFI_MAX_POLL_TRY) {
|
|
|
readw_poll_timeout((soc_info->reg_map[0].mem_base +
|
|
|
- IPE_CDM_IRQ_STATUS),
|
|
|
+ hw_info->cdm_irq_status),
|
|
|
status, ((status & IPE_RST_DONE_IRQ_STATUS_BIT) == 0x1),
|
|
|
100, 10000);
|
|
|
|
|
@@ -297,7 +300,7 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
|
|
|
retry_cnt++;
|
|
|
}
|
|
|
status = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
|
- IPE_CDM_IRQ_STATUS);
|
|
|
+ hw_info->cdm_irq_status);
|
|
|
if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) != 0x1) {
|
|
|
CAM_ERR(CAM_ICP, "IPE CDM rst failed status 0x%x", status);
|
|
|
reset_ipe_cdm_fail = true;
|
|
@@ -306,10 +309,10 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
|
|
|
/* IPE reset*/
|
|
|
status = 0;
|
|
|
cam_io_w_mb((uint32_t)0x3,
|
|
|
- soc_info->reg_map[0].mem_base + IPE_TOP_RST_CMD);
|
|
|
+ soc_info->reg_map[0].mem_base + hw_info->top_rst_cmd);
|
|
|
while (retry_cnt < HFI_MAX_POLL_TRY) {
|
|
|
readw_poll_timeout((soc_info->reg_map[0].mem_base +
|
|
|
- IPE_TOP_IRQ_STATUS),
|
|
|
+ hw_info->top_irq_status),
|
|
|
status, ((status & IPE_RST_DONE_IRQ_STATUS_BIT) == 0x1),
|
|
|
100, 10000);
|
|
|
|
|
@@ -321,13 +324,12 @@ static int cam_ipe_cmd_reset(struct cam_hw_soc_info *soc_info,
|
|
|
retry_cnt++;
|
|
|
}
|
|
|
status = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
|
- IPE_TOP_IRQ_STATUS);
|
|
|
+ hw_info->top_irq_status);
|
|
|
if ((status & IPE_RST_DONE_IRQ_STATUS_BIT) != 0x1) {
|
|
|
CAM_ERR(CAM_ICP, "IPE top rst failed status 0x%x", status);
|
|
|
reset_ipe_top_fail = true;
|
|
|
}
|
|
|
|
|
|
- cam_ipe_get_gdsc_control(soc_info);
|
|
|
cam_cpas_reg_read(core_info->cpas_handle,
|
|
|
CAM_CPAS_REG_CPASTOP, core_info->ipe_hw_info->pwr_ctrl,
|
|
|
true, &pwr_ctrl);
|