msm: camera: isp: Dump imp CSID regs during timeout
This change dumps important csid registers and clock info during sw reset timeout. CRs-Fixed: 3583444 Change-Id: Iac8f45343058766012c19b8d61fa9e541e8a2b76 Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
This commit is contained in:
@@ -2436,6 +2436,59 @@ int cam_ife_csid_ver2_get_hw_caps(void *hw_priv,
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return rc;
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return rc;
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}
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}
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static void cam_ife_csid_ver2_dump_imp_regs(
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struct cam_ife_csid_ver2_hw *csid_hw)
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{
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void __iomem *mem_base;
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int top_irq_val[4] = {0};
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int reset_cfg = 0;
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int dual_csid_cfg = 0;
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uint32_t clk_lvl;
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uint32_t hw_idx;
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struct cam_ife_csid_ver2_reg_info *csid_reg;
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struct cam_hw_soc_info *soc_info;
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csid_reg = (struct cam_ife_csid_ver2_reg_info *)
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csid_hw->core_info->csid_reg;
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soc_info = &csid_hw->hw_info->soc_info;
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mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
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hw_idx = csid_hw->hw_intf->hw_idx;
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/* Dumping CSID top irq registers */
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top_irq_val[0] = cam_io_r_mb(mem_base +
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csid_reg->cmn_reg->top_irq_status_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
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top_irq_val[1] = cam_io_r_mb(mem_base +
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csid_reg->cmn_reg->top_irq_mask_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
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top_irq_val[2] = cam_io_r_mb(mem_base +
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csid_reg->cmn_reg->top_irq_clear_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
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top_irq_val[3] = cam_io_r_mb(mem_base +
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csid_reg->cmn_reg->top_irq_set_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
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CAM_INFO(CAM_ISP,
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"CSID[%d] csid top status 0x%x, mask 0x%x, clr 0x%x, set 0x%x",
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hw_idx, top_irq_val[0], top_irq_val[1],
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top_irq_val[2], top_irq_val[3]);
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/* Dumping CSID reset cfg and dual csid cfg */
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reset_cfg = cam_io_r_mb(mem_base + csid_reg->cmn_reg->reset_cfg_addr);
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dual_csid_cfg = cam_io_r_mb(
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soc_info->reg_map[CAM_IFE_CSID_TOP_MEM_BASE_ID].mem_base +
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csid_reg->top_reg->dual_csid_cfg0_addr[hw_idx]);
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CAM_INFO(CAM_ISP,
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"CSID[%d] csid reset_cfg 0x%x, dual_csid_cfg 0x%x, is_dual_en %d",
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hw_idx, reset_cfg, dual_csid_cfg, csid_hw->top_cfg.dual_en);
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/* Dumping CSID Clock */
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cam_soc_util_get_clk_level(soc_info, csid_hw->clk_rate,
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soc_info->src_clk_idx, &clk_lvl);
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CAM_INFO(CAM_ISP,
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"CSID[%d] clk lvl %u received clk_rate %u applied clk_rate sw_client:%lu hw_client:[%lu %lu]",
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hw_idx, clk_lvl, csid_hw->clk_rate,
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soc_info->applied_src_clk_rates.sw_client,
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soc_info->applied_src_clk_rates.hw_client[hw_idx].high,
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soc_info->applied_src_clk_rates.hw_client[hw_idx].low);
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}
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static int cam_ife_csid_ver2_wait_for_reset(
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static int cam_ife_csid_ver2_wait_for_reset(
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struct cam_ife_csid_ver2_hw *csid_hw)
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struct cam_ife_csid_ver2_hw *csid_hw)
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{
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{
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@@ -2459,16 +2512,16 @@ static int cam_ife_csid_ver2_wait_for_reset(
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cam_io_r_mb(
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cam_io_r_mb(
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soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base +
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soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base +
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csid_reg->cmn_reg->test_bus_debug));
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csid_reg->cmn_reg->test_bus_debug));
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} else {
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} else
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CAM_ERR(CAM_ISP, "CSID[%u], sync-mode[%d] reset timed out",
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CAM_ERR(CAM_ISP, "CSID[%u], sync-mode[%d] reset timed out",
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csid_hw->hw_intf->hw_idx, csid_hw->sync_mode);
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csid_hw->hw_intf->hw_idx, csid_hw->sync_mode);
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}
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} else {
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cam_ife_csid_ver2_dump_imp_regs(csid_hw);
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} else
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CAM_DBG(CAM_ISP,
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CAM_DBG(CAM_ISP,
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"CSID[%u], sync-mode[%d] reset success",
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"CSID[%u], sync-mode[%d] reset success",
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csid_hw->hw_intf->hw_idx,
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csid_hw->hw_intf->hw_idx,
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csid_hw->sync_mode);
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csid_hw->sync_mode);
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}
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return rc;
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return rc;
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}
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}
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@@ -2482,6 +2535,7 @@ static int cam_ife_csid_ver2_reset_irq_top_half(uint32_t evt_id,
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CAM_DBG(CAM_ISP, "CSID[%u] TOP_IRQ_STATUS_0 = 0x%x", csid_hw->hw_intf->hw_idx,
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CAM_DBG(CAM_ISP, "CSID[%u] TOP_IRQ_STATUS_0 = 0x%x", csid_hw->hw_intf->hw_idx,
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th_payload->evt_status_arr[0]);
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th_payload->evt_status_arr[0]);
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complete(&csid_hw->hw_info->hw_complete);
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complete(&csid_hw->hw_info->hw_complete);
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return 0;
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return 0;
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