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@@ -116,9 +116,9 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
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} else {
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base_cycles = 0;
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vsp_cycles = div_u64(vsp_cycles, 2);
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- /* VSP FW Overhead 1.05 */
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- vsp_cycles = div_u64(vsp_cycles * 21, 20);
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}
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+ /* VSP FW Overhead 1.05 */
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+ vsp_cycles = div_u64(vsp_cycles * 21, 20);
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if (inst->capabilities->cap[STAGE].value == MSM_VIDC_STAGE_1)
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vsp_cycles = vsp_cycles * 3;
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@@ -148,9 +148,9 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
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} else {
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base_cycles = 0;
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vsp_cycles = div_u64(vsp_cycles, 2);
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- /* VSP FW overhead 1.05 */
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- vsp_cycles = div_u64(vsp_cycles * 21, 20);
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}
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+ /* VSP FW overhead 1.05 */
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+ vsp_cycles = div_u64(vsp_cycles * 21, 20);
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if (inst->capabilities->cap[STAGE].value == MSM_VIDC_STAGE_1)
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vsp_cycles = vsp_cycles * 3;
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