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@@ -16,51 +16,53 @@
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#define CAM_VFE_88X_NUM_DBG_REG 5
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+/* Offsets might not match due to csid secure regs at beginning of reg space */
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+
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static struct cam_irq_register_set vfe_lite88x_top_irq_reg_set[2] = {
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{
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- .mask_reg_offset = 0x00002024,
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- .clear_reg_offset = 0x0000202C,
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- .status_reg_offset = 0x0000201C,
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- .set_reg_offset = 0x00002034,
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+ .mask_reg_offset = 0x00001024,
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+ .clear_reg_offset = 0x0000102C,
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+ .status_reg_offset = 0x0000101C,
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+ .set_reg_offset = 0x00001034,
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.test_set_val = BIT(0),
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.test_sub_val = BIT(0),
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},
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{
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- .mask_reg_offset = 0x00002028,
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- .clear_reg_offset = 0x00002030,
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- .status_reg_offset = 0x00002020,
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+ .mask_reg_offset = 0x00001028,
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+ .clear_reg_offset = 0x00001030,
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+ .status_reg_offset = 0x00001020,
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},
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};
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static struct cam_irq_controller_reg_info vfe_lite88x_top_irq_reg_info = {
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.num_registers = 2,
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.irq_reg_set = vfe_lite88x_top_irq_reg_set,
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- .global_irq_cmd_offset = 0x00002038,
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+ .global_irq_cmd_offset = 0x00001038,
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.global_clear_bitmask = 0x00000001,
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.global_set_bitmask = 0x00000010,
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.clear_all_bitmask = 0xFFFFFFFF,
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};
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static struct cam_vfe_top_ver4_reg_offset_common vfe_lite88x_top_common_reg = {
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- .hw_version = 0x00002000,
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- .hw_capability = 0x00002004,
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- .core_cgc_ovd_0 = 0x00002014,
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- .ahb_cgc_ovd = 0x00002018,
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- .core_cfg_0 = 0x0000203C,
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- .diag_config = 0x00002040,
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- .diag_sensor_status_0 = 0x00002044,
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- .diag_sensor_status_1 = 0x00002048,
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- .ipp_violation_status = 0x00002054,
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- .bus_violation_status = 0x00002264,
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- .bus_overflow_status = 0x00002268,
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- .top_debug_cfg = 0x00002074,
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+ .hw_version = 0x00001000,
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+ .hw_capability = 0x00001004,
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+ .core_cgc_ovd_0 = 0x00001014,
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+ .ahb_cgc_ovd = 0x00001018,
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+ .core_cfg_0 = 0x0000103C,
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+ .diag_config = 0x00001040,
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+ .diag_sensor_status_0 = 0x00001044,
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+ .diag_sensor_status_1 = 0x00001048,
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+ .ipp_violation_status = 0x00001054,
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+ .bus_violation_status = 0x00001264,
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+ .bus_overflow_status = 0x00001268,
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+ .top_debug_cfg = 0x00001074,
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.num_top_debug_reg = CAM_VFE_88X_NUM_DBG_REG,
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.top_debug = {
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- 0x0000205C,
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- 0x00002060,
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- 0x00002064,
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- 0x00002068,
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- 0x0000206C,
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+ 0x0000105C,
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+ 0x00001060,
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+ 0x00001064,
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+ 0x00001068,
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+ 0x0000106C,
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},
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};
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@@ -150,35 +152,35 @@ static struct cam_vfe_top_ver4_hw_info vfe_lite88x_top_hw_info = {
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static struct cam_irq_register_set vfe_lite88x_bus_irq_reg[1] = {
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{
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- .mask_reg_offset = 0x00002218,
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- .clear_reg_offset = 0x00002220,
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- .status_reg_offset = 0x00002228,
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+ .mask_reg_offset = 0x00001218,
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+ .clear_reg_offset = 0x00001220,
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+ .status_reg_offset = 0x00001228,
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},
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};
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static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
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.common_reg = {
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- .hw_version = 0x00002200,
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- .cgc_ovd = 0x00002208,
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+ .hw_version = 0x00001200,
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+ .cgc_ovd = 0x00001208,
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.if_frameheader_cfg = {
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- 0x00002234,
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- 0x00002238,
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- 0x0000223C,
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- 0x00002240,
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- 0x00002244,
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+ 0x00001234,
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+ 0x00001238,
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+ 0x0000123C,
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+ 0x00001240,
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+ 0x00001244,
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},
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- .pwr_iso_cfg = 0x0000225C,
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- .overflow_status_clear = 0x00002260,
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- .ccif_violation_status = 0x00002264,
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- .overflow_status = 0x00002268,
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- .image_size_violation_status = 0x00002270,
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- .debug_status_top_cfg = 0x000022F0,
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- .debug_status_top = 0x000022F4,
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- .test_bus_ctrl = 0x00002394,
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+ .pwr_iso_cfg = 0x0000125C,
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+ .overflow_status_clear = 0x00001260,
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+ .ccif_violation_status = 0x00001264,
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+ .overflow_status = 0x00001268,
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+ .image_size_violation_status = 0x00001270,
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+ .debug_status_top_cfg = 0x000012F0,
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+ .debug_status_top = 0x000012F4,
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+ .test_bus_ctrl = 0x00001394,
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.irq_reg_info = {
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.num_registers = 1,
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.irq_reg_set = vfe_lite88x_bus_irq_reg,
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- .global_irq_cmd_offset = 0x00002230,
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+ .global_irq_cmd_offset = 0x00001230,
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.global_clear_bitmask = 0x00000001,
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},
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},
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@@ -186,175 +188,175 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
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.bus_client_reg = {
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/* BUS Client 0 RDI0 */
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{
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- .cfg = 0x00002400,
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- .image_addr = 0x00002404,
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- .frame_incr = 0x00002408,
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- .image_cfg_0 = 0x0000240C,
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- .image_cfg_1 = 0x00002410,
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- .image_cfg_2 = 0x00002414,
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- .packer_cfg = 0x00002418,
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- .frame_header_addr = 0x00002420,
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- .frame_header_incr = 0x00002424,
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- .frame_header_cfg = 0x00002428,
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- .line_done_cfg = 0x0000242C,
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- .irq_subsample_period = 0x00002430,
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- .irq_subsample_pattern = 0x00002434,
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- .mmu_prefetch_cfg = 0x00002460,
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- .mmu_prefetch_max_offset = 0x00002464,
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- .system_cache_cfg = 0x00002468,
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- .addr_cfg = 0x00002470,
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- .addr_status_0 = 0x00002478,
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- .addr_status_1 = 0x0000247C,
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- .addr_status_2 = 0x00002480,
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- .addr_status_3 = 0x00002484,
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- .debug_status_cfg = 0x00002488,
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- .debug_status_0 = 0x0000248C,
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- .debug_status_1 = 0x00002490,
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+ .cfg = 0x00001400,
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+ .image_addr = 0x00001404,
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+ .frame_incr = 0x00001408,
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+ .image_cfg_0 = 0x0000140C,
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+ .image_cfg_1 = 0x00001410,
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+ .image_cfg_2 = 0x00001414,
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+ .packer_cfg = 0x00001418,
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+ .frame_header_addr = 0x00001420,
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+ .frame_header_incr = 0x00001424,
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+ .frame_header_cfg = 0x00001428,
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+ .line_done_cfg = 0x0000142C,
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+ .irq_subsample_period = 0x00001430,
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+ .irq_subsample_pattern = 0x00001434,
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+ .mmu_prefetch_cfg = 0x00001460,
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+ .mmu_prefetch_max_offset = 0x00001464,
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+ .system_cache_cfg = 0x00001468,
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+ .addr_cfg = 0x00001470,
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+ .addr_status_0 = 0x00001478,
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+ .addr_status_1 = 0x0000147C,
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+ .addr_status_2 = 0x00001480,
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+ .addr_status_3 = 0x00001484,
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+ .debug_status_cfg = 0x00001488,
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+ .debug_status_0 = 0x0000148C,
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+ .debug_status_1 = 0x00001490,
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.comp_group = CAM_VFE_BUS_VER3_COMP_GRP_1,
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.ubwc_regs = NULL,
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},
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/* BUS Client 1 RDI1 */
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{
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- .cfg = 0x00002500,
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- .image_addr = 0x00002504,
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- .frame_incr = 0x00002508,
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- .image_cfg_0 = 0x0000250C,
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- .image_cfg_1 = 0x00002510,
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- .image_cfg_2 = 0x00002514,
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- .packer_cfg = 0x00002518,
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- .frame_header_addr = 0x00002520,
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- .frame_header_incr = 0x00002524,
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- .frame_header_cfg = 0x00002528,
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- .line_done_cfg = 0x0000252C,
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- .irq_subsample_period = 0x00002530,
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- .irq_subsample_pattern = 0x00002534,
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- .mmu_prefetch_cfg = 0x00002560,
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- .mmu_prefetch_max_offset = 0x00002564,
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- .system_cache_cfg = 0x00002568,
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- .addr_cfg = 0x00002570,
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- .addr_status_0 = 0x00002578,
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- .addr_status_1 = 0x0000257C,
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- .addr_status_2 = 0x00002580,
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- .addr_status_3 = 0x00002584,
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- .debug_status_cfg = 0x00002588,
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- .debug_status_0 = 0x0000258C,
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- .debug_status_1 = 0x00002590,
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+ .cfg = 0x00001500,
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+ .image_addr = 0x00001504,
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+ .frame_incr = 0x00001508,
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+ .image_cfg_0 = 0x0000150C,
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+ .image_cfg_1 = 0x00001510,
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+ .image_cfg_2 = 0x00001514,
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+ .packer_cfg = 0x00001518,
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+ .frame_header_addr = 0x00001520,
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+ .frame_header_incr = 0x00001524,
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+ .frame_header_cfg = 0x00001528,
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+ .line_done_cfg = 0x0000152C,
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+ .irq_subsample_period = 0x00001530,
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+ .irq_subsample_pattern = 0x00001534,
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+ .mmu_prefetch_cfg = 0x00001560,
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+ .mmu_prefetch_max_offset = 0x00001564,
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+ .system_cache_cfg = 0x00001568,
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+ .addr_cfg = 0x00001570,
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+ .addr_status_0 = 0x00001578,
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+ .addr_status_1 = 0x0000157C,
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+ .addr_status_2 = 0x00001580,
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+ .addr_status_3 = 0x00001584,
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+ .debug_status_cfg = 0x00001588,
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+ .debug_status_0 = 0x0000158C,
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+ .debug_status_1 = 0x00001590,
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.comp_group = CAM_VFE_BUS_VER3_COMP_GRP_2,
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.ubwc_regs = NULL,
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},
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/* BUS Client 2 RDI2 */
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{
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- .cfg = 0x00002600,
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- .image_addr = 0x00002604,
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- .frame_incr = 0x00002608,
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- .image_cfg_0 = 0x0000260C,
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- .image_cfg_1 = 0x00002610,
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- .image_cfg_2 = 0x00002614,
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- .packer_cfg = 0x00002618,
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- .frame_header_addr = 0x00002620,
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- .frame_header_incr = 0x00002624,
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- .frame_header_cfg = 0x00002628,
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- .line_done_cfg = 0x0000262C,
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- .irq_subsample_period = 0x00002630,
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- .irq_subsample_pattern = 0x00002634,
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- .mmu_prefetch_cfg = 0x00002660,
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- .mmu_prefetch_max_offset = 0x00002664,
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- .system_cache_cfg = 0x00002668,
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- .addr_cfg = 0x00002670,
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- .addr_status_0 = 0x00002678,
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- .addr_status_1 = 0x0000267C,
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- .addr_status_2 = 0x00002680,
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- .addr_status_3 = 0x00002684,
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- .debug_status_cfg = 0x00002688,
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- .debug_status_0 = 0x0000268C,
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- .debug_status_1 = 0x00002690,
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+ .cfg = 0x00001600,
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+ .image_addr = 0x00001604,
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+ .frame_incr = 0x00001608,
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+ .image_cfg_0 = 0x0000160C,
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+ .image_cfg_1 = 0x00001610,
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+ .image_cfg_2 = 0x00001614,
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+ .packer_cfg = 0x00001618,
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+ .frame_header_addr = 0x00001620,
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+ .frame_header_incr = 0x00001624,
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+ .frame_header_cfg = 0x00001628,
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+ .line_done_cfg = 0x0000162C,
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+ .irq_subsample_period = 0x00001630,
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+ .irq_subsample_pattern = 0x00001634,
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+ .mmu_prefetch_cfg = 0x00001660,
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+ .mmu_prefetch_max_offset = 0x00001664,
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+ .system_cache_cfg = 0x00001668,
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+ .addr_cfg = 0x00001670,
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+ .addr_status_0 = 0x00001678,
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+ .addr_status_1 = 0x0000167C,
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+ .addr_status_2 = 0x00001680,
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+ .addr_status_3 = 0x00001684,
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+ .debug_status_cfg = 0x00001688,
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+ .debug_status_0 = 0x0000168C,
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+ .debug_status_1 = 0x00001690,
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.comp_group = CAM_VFE_BUS_VER3_COMP_GRP_3,
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.ubwc_regs = NULL,
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},
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/* BUS Client 3 RDI3 */
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{
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- .cfg = 0x00002700,
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- .image_addr = 0x00002704,
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- .frame_incr = 0x00002708,
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- .image_cfg_0 = 0x0000270C,
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- .image_cfg_1 = 0x00002710,
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- .image_cfg_2 = 0x00002714,
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- .packer_cfg = 0x00002718,
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- .frame_header_addr = 0x00002720,
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- .frame_header_incr = 0x00002724,
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- .frame_header_cfg = 0x00002728,
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- .line_done_cfg = 0x0000272C,
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- .irq_subsample_period = 0x00002730,
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- .irq_subsample_pattern = 0x00002734,
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- .mmu_prefetch_cfg = 0x00002760,
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- .mmu_prefetch_max_offset = 0x00002764,
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- .system_cache_cfg = 0x00002768,
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- .addr_cfg = 0x00002770,
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- .addr_status_0 = 0x00002778,
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- .addr_status_1 = 0x0000277C,
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- .addr_status_2 = 0x00002780,
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- .addr_status_3 = 0x00002784,
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- .debug_status_cfg = 0x00002788,
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- .debug_status_0 = 0x0000278C,
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- .debug_status_1 = 0x00002790,
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+ .cfg = 0x00001700,
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+ .image_addr = 0x00001704,
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+ .frame_incr = 0x00001708,
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+ .image_cfg_0 = 0x0000170C,
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+ .image_cfg_1 = 0x00001710,
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+ .image_cfg_2 = 0x00001714,
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+ .packer_cfg = 0x00001718,
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+ .frame_header_addr = 0x00001720,
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+ .frame_header_incr = 0x00001724,
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+ .frame_header_cfg = 0x00001728,
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+ .line_done_cfg = 0x0000172C,
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+ .irq_subsample_period = 0x00001730,
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+ .irq_subsample_pattern = 0x00001734,
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+ .mmu_prefetch_cfg = 0x00001760,
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+ .mmu_prefetch_max_offset = 0x00001764,
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+ .system_cache_cfg = 0x00001768,
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+ .addr_cfg = 0x00001770,
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+ .addr_status_0 = 0x00001778,
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+ .addr_status_1 = 0x0000177C,
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+ .addr_status_2 = 0x00001780,
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+ .addr_status_3 = 0x00001784,
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+ .debug_status_cfg = 0x00001788,
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+ .debug_status_0 = 0x0000178C,
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+ .debug_status_1 = 0x00001790,
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.comp_group = CAM_VFE_BUS_VER3_COMP_GRP_4,
|
|
|
.ubwc_regs = NULL,
|
|
|
},
|
|
|
/* BUS Client 4 Gamma */
|
|
|
{
|
|
|
- .cfg = 0x00002800,
|
|
|
- .image_addr = 0x00002804,
|
|
|
- .frame_incr = 0x00002808,
|
|
|
- .image_cfg_0 = 0x0000280C,
|
|
|
- .image_cfg_1 = 0x00002810,
|
|
|
- .image_cfg_2 = 0x00002814,
|
|
|
- .packer_cfg = 0x00002818,
|
|
|
- .frame_header_addr = 0x00002820,
|
|
|
- .frame_header_incr = 0x00002824,
|
|
|
- .frame_header_cfg = 0x00002828,
|
|
|
- .line_done_cfg = 0x0000282C,
|
|
|
- .irq_subsample_period = 0x00002830,
|
|
|
- .irq_subsample_pattern = 0x00002834,
|
|
|
- .mmu_prefetch_cfg = 0x00002860,
|
|
|
- .mmu_prefetch_max_offset = 0x00002864,
|
|
|
- .system_cache_cfg = 0x00002868,
|
|
|
- .addr_cfg = 0x00002870,
|
|
|
- .addr_status_0 = 0x00002878,
|
|
|
- .addr_status_1 = 0x0000287C,
|
|
|
- .addr_status_2 = 0x00002880,
|
|
|
- .addr_status_3 = 0x00002884,
|
|
|
- .debug_status_cfg = 0x00002888,
|
|
|
- .debug_status_0 = 0x0000288C,
|
|
|
- .debug_status_1 = 0x00002890,
|
|
|
+ .cfg = 0x00001800,
|
|
|
+ .image_addr = 0x00001804,
|
|
|
+ .frame_incr = 0x00001808,
|
|
|
+ .image_cfg_0 = 0x0000180C,
|
|
|
+ .image_cfg_1 = 0x00001810,
|
|
|
+ .image_cfg_2 = 0x00001814,
|
|
|
+ .packer_cfg = 0x00001818,
|
|
|
+ .frame_header_addr = 0x00001820,
|
|
|
+ .frame_header_incr = 0x00001824,
|
|
|
+ .frame_header_cfg = 0x00001828,
|
|
|
+ .line_done_cfg = 0x0000182C,
|
|
|
+ .irq_subsample_period = 0x00001830,
|
|
|
+ .irq_subsample_pattern = 0x00001834,
|
|
|
+ .mmu_prefetch_cfg = 0x00001860,
|
|
|
+ .mmu_prefetch_max_offset = 0x00001864,
|
|
|
+ .system_cache_cfg = 0x00001868,
|
|
|
+ .addr_cfg = 0x00001870,
|
|
|
+ .addr_status_0 = 0x00001878,
|
|
|
+ .addr_status_1 = 0x0000187C,
|
|
|
+ .addr_status_2 = 0x00001880,
|
|
|
+ .addr_status_3 = 0x00001884,
|
|
|
+ .debug_status_cfg = 0x00001888,
|
|
|
+ .debug_status_0 = 0x0000188C,
|
|
|
+ .debug_status_1 = 0x00001890,
|
|
|
.comp_group = CAM_VFE_BUS_VER3_COMP_GRP_0,
|
|
|
.ubwc_regs = NULL,
|
|
|
},
|
|
|
/* BUS Client 5 Stats BE */
|
|
|
{
|
|
|
- .cfg = 0x00002900,
|
|
|
- .image_addr = 0x00002904,
|
|
|
- .frame_incr = 0x00002908,
|
|
|
- .image_cfg_0 = 0x0000290C,
|
|
|
- .image_cfg_1 = 0x00002910,
|
|
|
- .image_cfg_2 = 0x00002914,
|
|
|
- .packer_cfg = 0x00002918,
|
|
|
- .frame_header_addr = 0x00002920,
|
|
|
- .frame_header_incr = 0x00002924,
|
|
|
- .frame_header_cfg = 0x00002928,
|
|
|
- .line_done_cfg = 0x0000292C,
|
|
|
- .irq_subsample_period = 0x00002930,
|
|
|
- .irq_subsample_pattern = 0x00002934,
|
|
|
- .mmu_prefetch_cfg = 0x00002960,
|
|
|
- .mmu_prefetch_max_offset = 0x00002964,
|
|
|
- .system_cache_cfg = 0x00002968,
|
|
|
- .addr_cfg = 0x00002970,
|
|
|
- .addr_status_0 = 0x00002978,
|
|
|
- .addr_status_1 = 0x0000297C,
|
|
|
- .addr_status_2 = 0x00002980,
|
|
|
- .addr_status_3 = 0x00002984,
|
|
|
- .debug_status_cfg = 0x00002988,
|
|
|
- .debug_status_0 = 0x0000298C,
|
|
|
- .debug_status_1 = 0x00002990,
|
|
|
+ .cfg = 0x00001900,
|
|
|
+ .image_addr = 0x00001904,
|
|
|
+ .frame_incr = 0x00001908,
|
|
|
+ .image_cfg_0 = 0x0000190C,
|
|
|
+ .image_cfg_1 = 0x00001910,
|
|
|
+ .image_cfg_2 = 0x00001914,
|
|
|
+ .packer_cfg = 0x00001918,
|
|
|
+ .frame_header_addr = 0x00001920,
|
|
|
+ .frame_header_incr = 0x00001924,
|
|
|
+ .frame_header_cfg = 0x00001928,
|
|
|
+ .line_done_cfg = 0x0000192C,
|
|
|
+ .irq_subsample_period = 0x00001930,
|
|
|
+ .irq_subsample_pattern = 0x00001934,
|
|
|
+ .mmu_prefetch_cfg = 0x00001960,
|
|
|
+ .mmu_prefetch_max_offset = 0x00001964,
|
|
|
+ .system_cache_cfg = 0x00001968,
|
|
|
+ .addr_cfg = 0x00001970,
|
|
|
+ .addr_status_0 = 0x00001978,
|
|
|
+ .addr_status_1 = 0x0000197C,
|
|
|
+ .addr_status_2 = 0x00001980,
|
|
|
+ .addr_status_3 = 0x00001984,
|
|
|
+ .debug_status_cfg = 0x00001988,
|
|
|
+ .debug_status_0 = 0x0000198C,
|
|
|
+ .debug_status_1 = 0x00001990,
|
|
|
.comp_group = CAM_VFE_BUS_VER3_COMP_GRP_0,
|
|
|
.ubwc_regs = NULL,
|
|
|
},
|
zhuo