disp: msm: sde: add hardware catalog support for VDC-m block
Add hardware catalog support for VDC-m block to parse the register offsets and feature capabilities. Change-Id: I1bfbc4b6e7e9f34738d49fecdef4b427a0ccded7 Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Cette révision appartient à :
Abhinav Kumar
révisé par
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
Parent
3e0f65f882
révision
88a43f2441
@@ -318,6 +318,15 @@ enum {
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DSC_PROP_MAX,
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};
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enum {
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VDC_OFF,
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VDC_LEN,
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VDC_REV,
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VDC_ENC,
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VDC_CTL,
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VDC_PROP_MAX,
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};
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enum {
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DS_TOP_OFF,
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DS_TOP_LEN,
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@@ -710,6 +719,14 @@ static struct sde_prop_type dsc_prop[] = {
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{DSC_422, "qcom,sde-dsc-native422-supp", false, PROP_TYPE_U32_ARRAY}
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};
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static struct sde_prop_type vdc_prop[] = {
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{VDC_OFF, "qcom,sde-vdc-off", false, PROP_TYPE_U32_ARRAY},
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{VDC_LEN, "qcom,sde-vdc-size", false, PROP_TYPE_U32},
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{VDC_REV, "qcom,sde-vdc-hw-rev", false, PROP_TYPE_STRING},
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{VDC_ENC, "qcom,sde-vdc-enc", false, PROP_TYPE_U32_ARRAY},
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{VDC_CTL, "qcom,sde-vdc-ctl", false, PROP_TYPE_U32_ARRAY},
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};
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static struct sde_prop_type cdm_prop[] = {
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{HW_OFF, "qcom,sde-cdm-off", false, PROP_TYPE_U32_ARRAY},
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{HW_LEN, "qcom,sde-cdm-size", false, PROP_TYPE_U32},
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@@ -2784,6 +2801,85 @@ end:
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return rc;
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};
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static int sde_vdc_parse_dt(struct device_node *np,
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struct sde_mdss_cfg *sde_cfg)
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{
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int rc, prop_count[MAX_BLOCKS], i;
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struct sde_prop_value *prop_value = NULL;
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bool prop_exists[VDC_PROP_MAX];
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u32 off_count, vdc_rev;
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const char *rev;
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struct sde_vdc_cfg *vdc;
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struct sde_vdc_sub_blks *sblk;
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if (!sde_cfg) {
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SDE_ERROR("invalid argument\n");
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rc = -EINVAL;
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goto end;
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}
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prop_value = kzalloc(VDC_PROP_MAX *
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sizeof(struct sde_prop_value), GFP_KERNEL);
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if (!prop_value) {
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rc = -ENOMEM;
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goto end;
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}
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rc = _validate_dt_entry(np, vdc_prop, ARRAY_SIZE(vdc_prop), prop_count,
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&off_count);
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if (rc)
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goto end;
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sde_cfg->vdc_count = off_count;
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rc = of_property_read_string(np, vdc_prop[VDC_REV].prop_name, &rev);
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if ((rc == -EINVAL) || (rc == -ENODATA)) {
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vdc_rev = SDE_VDC_HW_REV_1_1;
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rc = 0;
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} else if (!rc && !strcmp(rev, "vdc_1_1")) {
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vdc_rev = SDE_VDC_HW_REV_1_1;
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rc = 0;
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} else {
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SDE_ERROR("invalid vdc configuration\n");
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}
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rc = _read_dt_entry(np, vdc_prop, ARRAY_SIZE(vdc_prop), prop_count,
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prop_exists, prop_value);
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if (rc)
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goto end;
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for (i = 0; i < off_count; i++) {
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vdc = sde_cfg->vdc + i;
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sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);
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if (!sblk) {
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rc = -ENOMEM;
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/* catalog deinit will release the allocated blocks */
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goto end;
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}
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vdc->sblk = sblk;
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vdc->base = PROP_VALUE_ACCESS(prop_value, VDC_OFF, i);
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vdc->id = VDC_0 + i;
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vdc->len = PROP_VALUE_ACCESS(prop_value, VDC_LEN, 0);
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snprintf(vdc->name, SDE_HW_BLK_NAME_LEN, "vdc_%u",
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vdc->id - VDC_0);
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if (!prop_exists[VDC_LEN])
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vdc->len = DEFAULT_SDE_HW_BLOCK_LEN;
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sblk->enc.base = PROP_VALUE_ACCESS(prop_value,
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VDC_ENC, i);
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sblk->ctl.base = PROP_VALUE_ACCESS(prop_value,
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VDC_CTL, i);
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set_bit(SDE_VDC_HW_REV_1_1, &vdc->features);
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}
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end:
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kfree(prop_value);
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return rc;
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};
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static int sde_cdm_parse_dt(struct device_node *np,
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struct sde_mdss_cfg *sde_cfg)
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{
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@@ -4542,6 +4638,9 @@ void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
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for (i = 0; i < sde_cfg->pingpong_count; i++)
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kfree(sde_cfg->pingpong[i].sblk);
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for (i = 0; i < sde_cfg->vdc_count; i++)
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kfree(sde_cfg->vdc[i].sblk);
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for (i = 0; i < sde_cfg->vbif_count; i++) {
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kfree(sde_cfg->vbif[i].dynamic_ot_rd_tbl.cfg);
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kfree(sde_cfg->vbif[i].dynamic_ot_wr_tbl.cfg);
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@@ -4634,6 +4733,10 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev)
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if (rc)
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goto end;
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rc = sde_vdc_parse_dt(np, sde_cfg);
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if (rc)
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goto end;
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rc = sde_pp_parse_dt(np, sde_cfg);
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if (rc)
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goto end;
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@@ -404,6 +404,19 @@ enum {
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SDE_DSC_MAX
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};
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/** VDC sub-blocks/features
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* @SDE_VDC_HW_REV_1_1 vdc block supports vdc 1.1 only
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* @SDE_VDC_ENC vdc encoder sub block
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* @SDE_VDC_CTL vdc ctl sub block
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* @SDE_VDC_MAX
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*/
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enum {
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SDE_VDC_HW_REV_1_1,
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SDE_VDC_ENC,
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SDE_VDC_CTL,
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SDE_VDC_MAX
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};
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/**
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* CTL sub-blocks
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* @SDE_CTL_SPLIT_DISPLAY CTL supports video mode split display
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@@ -594,6 +607,14 @@ struct sde_dsc_blk {
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SDE_HW_SUBBLK_INFO;
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};
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/**
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* struct sde_vdc_blk : VDC Encoder sub-blk information
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* @info: HW register and features supported by this sub-blk
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*/
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struct sde_vdc_blk {
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SDE_HW_SUBBLK_INFO;
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};
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/**
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* struct sde_format_extended - define sde specific pixel format+modifier
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* @fourcc_format: Base FOURCC pixel format code
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@@ -760,6 +781,15 @@ struct sde_dsc_sub_blks {
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struct sde_dsc_blk ctl;
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};
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/**
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* struct sde_vdc_sub_blks : VDC sub-blks
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*
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*/
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struct sde_vdc_sub_blks {
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struct sde_vdc_blk enc;
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struct sde_vdc_blk ctl;
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};
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struct sde_wb_sub_blocks {
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u32 maxlinewidth;
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};
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@@ -993,6 +1023,20 @@ struct sde_dsc_cfg {
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struct sde_dsc_sub_blks *sblk;
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};
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/**
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* struct sde_vdc_cfg - information of VDC blocks
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* @id enum identifying this block
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* @base register offset of this block
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* @len: length of hardware block
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* @features bit mask identifying sub-blocks/features
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* @enc VDC encoder register offset(relative to VDC base)
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* @ctl VDC Control register offset(relative to VDC base)
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*/
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struct sde_vdc_cfg {
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SDE_HW_BLK_INFO;
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struct sde_vdc_sub_blks *sblk;
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};
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/**
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* struct sde_cdm_cfg - information of chroma down blocks
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* @id enum identifying this block
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@@ -1442,6 +1486,9 @@ struct sde_mdss_cfg {
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u32 dsc_count;
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struct sde_dsc_cfg dsc[MAX_BLOCKS];
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u32 vdc_count;
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struct sde_vdc_cfg vdc[MAX_BLOCKS];
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u32 cdm_count;
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struct sde_cdm_cfg cdm[MAX_BLOCKS];
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_MDSS_H
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@@ -230,6 +230,13 @@ enum sde_dsc {
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DSC_MAX
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};
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enum sde_vdc {
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VDC_NONE = 0,
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VDC_0,
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VDC_1,
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VDC_MAX
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};
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enum sde_intf {
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INTF_0 = 1,
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INTF_1,
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