Add 'qcom/opensource/graphics-kernel/' from commit 'b4fdc4c04295ac59109ae19d64747522740c3f14'
git-subtree-dir: qcom/opensource/graphics-kernel git-subtree-mainline:992813d9c1git-subtree-split:b4fdc4c042Change-Id: repo: https://git.codelinaro.org/clo/la/platform/vendor/qcom/opensource/graphics-kernel tag: GRAPHICS.LA.14.0.r1-07700-lanai.0
This commit is contained in:
David Wronek
548
qcom/opensource/graphics-kernel/adreno_a5xx_preempt.c
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548
qcom/opensource/graphics-kernel/adreno_a5xx_preempt.c
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@@ -0,0 +1,548 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014-2017,2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include "adreno.h"
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#include "adreno_a5xx.h"
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#include "adreno_pm4types.h"
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#include "adreno_trace.h"
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#define PREEMPT_RECORD(_field) \
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offsetof(struct a5xx_cp_preemption_record, _field)
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#define PREEMPT_SMMU_RECORD(_field) \
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offsetof(struct a5xx_cp_smmu_info, _field)
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static void _update_wptr(struct adreno_device *adreno_dev, bool reset_timer)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct adreno_ringbuffer *rb = adreno_dev->cur_rb;
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unsigned int wptr;
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unsigned long flags;
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spin_lock_irqsave(&rb->preempt_lock, flags);
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kgsl_regread(device, A5XX_CP_RB_WPTR, &wptr);
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if (wptr != rb->wptr) {
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kgsl_regwrite(device, A5XX_CP_RB_WPTR, rb->wptr);
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/*
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* In case something got submitted while preemption was on
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* going, reset the timer.
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*/
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reset_timer = true;
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}
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if (reset_timer)
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rb->dispatch_q.expires = jiffies +
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msecs_to_jiffies(adreno_drawobj_timeout);
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spin_unlock_irqrestore(&rb->preempt_lock, flags);
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}
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static void _a5xx_preemption_done(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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unsigned int status;
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/*
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* In the very unlikely case that the power is off, do nothing - the
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* state will be reset on power up and everybody will be happy
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*/
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if (!kgsl_state_is_awake(device))
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return;
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kgsl_regread(device, A5XX_CP_CONTEXT_SWITCH_CNTL, &status);
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if (status != 0) {
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dev_err(device->dev,
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"Preemption not complete: status=%X cur=%d R/W=%X/%X next=%d R/W=%X/%X\n",
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status, adreno_dev->cur_rb->id,
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adreno_get_rptr(adreno_dev->cur_rb),
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adreno_dev->cur_rb->wptr,
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adreno_dev->next_rb->id,
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adreno_get_rptr(adreno_dev->next_rb),
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adreno_dev->next_rb->wptr);
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/* Set a fault and restart */
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adreno_dispatcher_fault(adreno_dev, ADRENO_PREEMPT_FAULT);
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return;
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}
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del_timer_sync(&adreno_dev->preempt.timer);
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trace_adreno_preempt_done(adreno_dev->cur_rb->id, adreno_dev->next_rb->id, 0, 0);
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/* Clean up all the bits */
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adreno_dev->prev_rb = adreno_dev->cur_rb;
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adreno_dev->cur_rb = adreno_dev->next_rb;
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adreno_dev->next_rb = NULL;
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/* Update the wptr for the new command queue */
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_update_wptr(adreno_dev, true);
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/* Update the dispatcher timer for the new command queue */
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mod_timer(&adreno_dev->dispatcher.timer,
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adreno_dev->cur_rb->dispatch_q.expires);
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/* Clear the preempt state */
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adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
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}
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static void _a5xx_preemption_fault(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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unsigned int status;
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/*
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* If the power is on check the preemption status one more time - if it
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* was successful then just transition to the complete state
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*/
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if (kgsl_state_is_awake(device)) {
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kgsl_regread(device, A5XX_CP_CONTEXT_SWITCH_CNTL, &status);
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if (status == 0) {
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adreno_set_preempt_state(adreno_dev,
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ADRENO_PREEMPT_COMPLETE);
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adreno_dispatcher_schedule(device);
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return;
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}
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}
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dev_err(device->dev,
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"Preemption timed out: cur=%d R/W=%X/%X, next=%d R/W=%X/%X\n",
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adreno_dev->cur_rb->id,
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adreno_get_rptr(adreno_dev->cur_rb),
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adreno_dev->cur_rb->wptr,
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adreno_dev->next_rb->id,
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adreno_get_rptr(adreno_dev->next_rb),
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adreno_dev->next_rb->wptr);
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adreno_dispatcher_fault(adreno_dev, ADRENO_PREEMPT_FAULT);
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}
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static void _a5xx_preemption_worker(struct work_struct *work)
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{
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struct adreno_preemption *preempt = container_of(work,
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struct adreno_preemption, work);
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struct adreno_device *adreno_dev = container_of(preempt,
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struct adreno_device, preempt);
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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/* Need to take the mutex to make sure that the power stays on */
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mutex_lock(&device->mutex);
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if (adreno_in_preempt_state(adreno_dev, ADRENO_PREEMPT_FAULTED))
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_a5xx_preemption_fault(adreno_dev);
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mutex_unlock(&device->mutex);
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}
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/* Find the highest priority active ringbuffer */
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static struct adreno_ringbuffer *a5xx_next_ringbuffer(
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struct adreno_device *adreno_dev)
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{
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struct adreno_ringbuffer *rb;
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unsigned long flags;
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unsigned int i;
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FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
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bool empty;
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spin_lock_irqsave(&rb->preempt_lock, flags);
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empty = adreno_rb_empty(rb);
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spin_unlock_irqrestore(&rb->preempt_lock, flags);
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if (!empty)
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return rb;
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}
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return NULL;
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}
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void a5xx_preemption_trigger(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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struct kgsl_iommu *iommu = KGSL_IOMMU(device);
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struct adreno_ringbuffer *next;
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uint64_t ttbr0;
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unsigned int contextidr;
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unsigned long flags;
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/* Put ourselves into a possible trigger state */
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if (!adreno_move_preempt_state(adreno_dev,
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ADRENO_PREEMPT_NONE, ADRENO_PREEMPT_START))
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return;
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/* Get the next ringbuffer to preempt in */
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next = a5xx_next_ringbuffer(adreno_dev);
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/*
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* Nothing to do if every ringbuffer is empty or if the current
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* ringbuffer is the only active one
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*/
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if (next == NULL || next == adreno_dev->cur_rb) {
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/*
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* Update any critical things that might have been skipped while
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* we were looking for a new ringbuffer
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*/
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if (next != NULL) {
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_update_wptr(adreno_dev, false);
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mod_timer(&adreno_dev->dispatcher.timer,
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adreno_dev->cur_rb->dispatch_q.expires);
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}
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adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
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return;
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}
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/* Turn off the dispatcher timer */
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del_timer(&adreno_dev->dispatcher.timer);
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/*
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* This is the most critical section - we need to take care not to race
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* until we have programmed the CP for the switch
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*/
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spin_lock_irqsave(&next->preempt_lock, flags);
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/* Get the pagetable from the pagetable info. */
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kgsl_sharedmem_readq(device->scratch, &ttbr0,
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SCRATCH_RB_OFFSET(next->id, ttbr0));
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kgsl_sharedmem_readl(device->scratch, &contextidr,
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SCRATCH_RB_OFFSET(next->id, contextidr));
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kgsl_sharedmem_writel(next->preemption_desc,
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PREEMPT_RECORD(wptr), next->wptr);
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spin_unlock_irqrestore(&next->preempt_lock, flags);
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/* And write it to the smmu info */
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if (kgsl_mmu_is_perprocess(&device->mmu)) {
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kgsl_sharedmem_writeq(iommu->smmu_info,
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PREEMPT_SMMU_RECORD(ttbr0), ttbr0);
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kgsl_sharedmem_writel(iommu->smmu_info,
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PREEMPT_SMMU_RECORD(context_idr), contextidr);
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}
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kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,
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lower_32_bits(next->preemption_desc->gpuaddr));
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kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI,
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upper_32_bits(next->preemption_desc->gpuaddr));
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adreno_dev->next_rb = next;
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/* Start the timer to detect a stuck preemption */
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mod_timer(&adreno_dev->preempt.timer,
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jiffies + msecs_to_jiffies(ADRENO_PREEMPT_TIMEOUT));
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trace_adreno_preempt_trigger(adreno_dev->cur_rb->id, adreno_dev->next_rb->id,
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1, 0);
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adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_TRIGGERED);
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/* Trigger the preemption */
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kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_CNTL, 1);
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}
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void a5xx_preempt_callback(struct adreno_device *adreno_dev, int bit)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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unsigned int status;
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if (!adreno_move_preempt_state(adreno_dev,
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ADRENO_PREEMPT_TRIGGERED, ADRENO_PREEMPT_PENDING))
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return;
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kgsl_regread(device, A5XX_CP_CONTEXT_SWITCH_CNTL, &status);
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if (status != 0) {
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dev_err(KGSL_DEVICE(adreno_dev)->dev,
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"preempt interrupt with non-zero status: %X\n",
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status);
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/*
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* Under the assumption that this is a race between the
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* interrupt and the register, schedule the worker to clean up.
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* If the status still hasn't resolved itself by the time we get
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* there then we have to assume something bad happened
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*/
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adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_COMPLETE);
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adreno_dispatcher_schedule(device);
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return;
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}
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del_timer(&adreno_dev->preempt.timer);
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trace_adreno_preempt_done(adreno_dev->cur_rb->id, adreno_dev->next_rb->id, 0, 0);
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adreno_dev->prev_rb = adreno_dev->cur_rb;
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adreno_dev->cur_rb = adreno_dev->next_rb;
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adreno_dev->next_rb = NULL;
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/* Update the wptr if it changed while preemption was ongoing */
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_update_wptr(adreno_dev, true);
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/* Update the dispatcher timer for the new command queue */
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mod_timer(&adreno_dev->dispatcher.timer,
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adreno_dev->cur_rb->dispatch_q.expires);
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adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
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a5xx_preemption_trigger(adreno_dev);
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}
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void a5xx_preemption_schedule(struct adreno_device *adreno_dev)
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{
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struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
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if (!adreno_is_preemption_enabled(adreno_dev))
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return;
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mutex_lock(&device->mutex);
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if (adreno_in_preempt_state(adreno_dev, ADRENO_PREEMPT_COMPLETE))
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_a5xx_preemption_done(adreno_dev);
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a5xx_preemption_trigger(adreno_dev);
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mutex_unlock(&device->mutex);
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}
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u32 a5xx_preemption_pre_ibsubmit(struct adreno_device *adreno_dev,
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struct adreno_ringbuffer *rb,
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struct adreno_context *drawctxt, u32 *cmds)
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{
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unsigned int *cmds_orig = cmds;
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uint64_t gpuaddr = rb->preemption_desc->gpuaddr;
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unsigned int preempt_style = 0;
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if (!adreno_is_preemption_enabled(adreno_dev))
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return 0;
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if (drawctxt) {
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/*
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* Preemption from secure to unsecure needs Zap shader to be
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* run to clear all secure content. CP does not know during
|
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* preemption if it is switching between secure and unsecure
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* contexts so restrict Secure contexts to be preempted at
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* ringbuffer level.
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*/
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if (drawctxt->base.flags & KGSL_CONTEXT_SECURE)
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preempt_style = KGSL_CONTEXT_PREEMPT_STYLE_RINGBUFFER;
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else
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preempt_style = FIELD_GET(KGSL_CONTEXT_PREEMPT_STYLE_MASK,
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drawctxt->base.flags);
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}
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/*
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* CP_PREEMPT_ENABLE_GLOBAL(global preemption) can only be set by KMD
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* in ringbuffer.
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* 1) set global preemption to 0x0 to disable global preemption.
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* Only RB level preemption is allowed in this mode
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* 2) Set global preemption to defer(0x2) for finegrain preemption.
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* when global preemption is set to defer(0x2),
|
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* CP_PREEMPT_ENABLE_LOCAL(local preemption) determines the
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* preemption point. Local preemption
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* can be enabled by both UMD(within IB) and KMD.
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*/
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*cmds++ = cp_type7_packet(CP_PREEMPT_ENABLE_GLOBAL, 1);
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*cmds++ = ((preempt_style == KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN)
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? 2 : 0);
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/* Turn CP protection OFF */
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cmds += cp_protected_mode(adreno_dev, cmds, 0);
|
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|
||||
/*
|
||||
* CP during context switch will save context switch info to
|
||||
* a5xx_cp_preemption_record pointed by CONTEXT_SWITCH_SAVE_ADDR
|
||||
*/
|
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*cmds++ = cp_type4_packet(A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO, 1);
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*cmds++ = lower_32_bits(gpuaddr);
|
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*cmds++ = cp_type4_packet(A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI, 1);
|
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*cmds++ = upper_32_bits(gpuaddr);
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||||
/* Turn CP protection ON */
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cmds += cp_protected_mode(adreno_dev, cmds, 1);
|
||||
|
||||
/*
|
||||
* Enable local preemption for finegrain preemption in case of
|
||||
* a misbehaving IB
|
||||
*/
|
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if (preempt_style == KGSL_CONTEXT_PREEMPT_STYLE_FINEGRAIN) {
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*cmds++ = cp_type7_packet(CP_PREEMPT_ENABLE_LOCAL, 1);
|
||||
*cmds++ = 1;
|
||||
} else {
|
||||
*cmds++ = cp_type7_packet(CP_PREEMPT_ENABLE_LOCAL, 1);
|
||||
*cmds++ = 0;
|
||||
}
|
||||
|
||||
/* Enable CP_CONTEXT_SWITCH_YIELD packets in the IB2s */
|
||||
*cmds++ = cp_type7_packet(CP_YIELD_ENABLE, 1);
|
||||
*cmds++ = 2;
|
||||
|
||||
return (unsigned int) (cmds - cmds_orig);
|
||||
}
|
||||
|
||||
unsigned int a5xx_preemption_post_ibsubmit(struct adreno_device *adreno_dev,
|
||||
unsigned int *cmds)
|
||||
{
|
||||
int dwords = 0;
|
||||
|
||||
if (!adreno_is_preemption_enabled(adreno_dev))
|
||||
return 0;
|
||||
|
||||
cmds[dwords++] = cp_type7_packet(CP_CONTEXT_SWITCH_YIELD, 4);
|
||||
/* Write NULL to the address to skip the data write */
|
||||
dwords += cp_gpuaddr(adreno_dev, &cmds[dwords], 0x0);
|
||||
cmds[dwords++] = 1;
|
||||
/* generate interrupt on preemption completion */
|
||||
cmds[dwords++] = 1;
|
||||
|
||||
return dwords;
|
||||
}
|
||||
|
||||
void a5xx_preemption_start(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
struct kgsl_iommu *iommu = KGSL_IOMMU(device);
|
||||
struct adreno_ringbuffer *rb;
|
||||
unsigned int i;
|
||||
|
||||
if (!adreno_is_preemption_enabled(adreno_dev))
|
||||
return;
|
||||
|
||||
/* Force the state to be clear */
|
||||
adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE);
|
||||
|
||||
/* Only set up smmu info when per-process pagetables are enabled */
|
||||
|
||||
if (kgsl_mmu_is_perprocess(&device->mmu)) {
|
||||
/* smmu_info is allocated and mapped in a5xx_preemption_iommu_init */
|
||||
kgsl_sharedmem_writel(iommu->smmu_info,
|
||||
PREEMPT_SMMU_RECORD(magic), A5XX_CP_SMMU_INFO_MAGIC_REF);
|
||||
kgsl_sharedmem_writeq(iommu->smmu_info,
|
||||
PREEMPT_SMMU_RECORD(ttbr0), MMU_DEFAULT_TTBR0(device));
|
||||
|
||||
/* The CP doesn't use the asid record, so poison it */
|
||||
kgsl_sharedmem_writel(iommu->smmu_info,
|
||||
PREEMPT_SMMU_RECORD(asid), 0xDECAFBAD);
|
||||
kgsl_sharedmem_writel(iommu->smmu_info,
|
||||
PREEMPT_SMMU_RECORD(context_idr), 0);
|
||||
|
||||
kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO,
|
||||
lower_32_bits(iommu->smmu_info->gpuaddr));
|
||||
|
||||
kgsl_regwrite(device, A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI,
|
||||
upper_32_bits(iommu->smmu_info->gpuaddr));
|
||||
}
|
||||
|
||||
FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
|
||||
/*
|
||||
* preemption_desc is allocated and mapped at init time,
|
||||
* so no need to check sharedmem_writel return value
|
||||
*/
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(rptr), 0);
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(wptr), 0);
|
||||
|
||||
adreno_ringbuffer_set_pagetable(device, rb,
|
||||
device->mmu.defaultpagetable);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static int a5xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev,
|
||||
struct adreno_ringbuffer *rb, uint64_t counteraddr)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
|
||||
if (IS_ERR_OR_NULL(rb->preemption_desc))
|
||||
rb->preemption_desc = kgsl_allocate_global(device,
|
||||
A5XX_CP_CTXRECORD_SIZE_IN_BYTES, SZ_16K, 0,
|
||||
KGSL_MEMDESC_PRIVILEGED, "preemption_desc");
|
||||
|
||||
if (IS_ERR(rb->preemption_desc))
|
||||
return PTR_ERR(rb->preemption_desc);
|
||||
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(magic), A5XX_CP_CTXRECORD_MAGIC_REF);
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(info), 0);
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(data), 0);
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(cntl), A5XX_CP_RB_CNTL_DEFAULT);
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(rptr), 0);
|
||||
kgsl_sharedmem_writel(rb->preemption_desc,
|
||||
PREEMPT_RECORD(wptr), 0);
|
||||
kgsl_sharedmem_writeq(rb->preemption_desc,
|
||||
PREEMPT_RECORD(rptr_addr), SCRATCH_RB_GPU_ADDR(device,
|
||||
rb->id, rptr));
|
||||
kgsl_sharedmem_writeq(rb->preemption_desc,
|
||||
PREEMPT_RECORD(rbase), rb->buffer_desc->gpuaddr);
|
||||
kgsl_sharedmem_writeq(rb->preemption_desc,
|
||||
PREEMPT_RECORD(counter), counteraddr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int a5xx_preemption_init(struct adreno_device *adreno_dev)
|
||||
{
|
||||
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
|
||||
struct kgsl_iommu *iommu = KGSL_IOMMU(device);
|
||||
struct adreno_preemption *preempt = &adreno_dev->preempt;
|
||||
struct adreno_ringbuffer *rb;
|
||||
int ret;
|
||||
unsigned int i;
|
||||
uint64_t addr;
|
||||
|
||||
/* We are dependent on IOMMU to make preemption go on the CP side */
|
||||
if (kgsl_mmu_get_mmutype(device) != KGSL_MMU_TYPE_IOMMU)
|
||||
return -ENODEV;
|
||||
|
||||
INIT_WORK(&preempt->work, _a5xx_preemption_worker);
|
||||
|
||||
/* Allocate mem for storing preemption counters */
|
||||
if (IS_ERR_OR_NULL(preempt->scratch))
|
||||
preempt->scratch = kgsl_allocate_global(device,
|
||||
adreno_dev->num_ringbuffers *
|
||||
A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE, 0, 0, 0,
|
||||
"preemption_counters");
|
||||
|
||||
ret = PTR_ERR_OR_ZERO(preempt->scratch);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
addr = preempt->scratch->gpuaddr;
|
||||
|
||||
/* Allocate mem for storing preemption switch record */
|
||||
FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
|
||||
ret = a5xx_preemption_ringbuffer_init(adreno_dev, rb, addr);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
addr += A5XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE;
|
||||
}
|
||||
|
||||
/* Allocate mem for storing preemption smmu record */
|
||||
if (kgsl_mmu_is_perprocess(&device->mmu) && IS_ERR_OR_NULL(iommu->smmu_info))
|
||||
iommu->smmu_info = kgsl_allocate_global(device, PAGE_SIZE, 0,
|
||||
KGSL_MEMFLAGS_GPUREADONLY, KGSL_MEMDESC_PRIVILEGED,
|
||||
"smmu_info");
|
||||
|
||||
if (IS_ERR(iommu->smmu_info))
|
||||
return PTR_ERR(iommu->smmu_info);
|
||||
|
||||
set_bit(ADRENO_DEVICE_PREEMPTION, &adreno_dev->priv);
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user