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disp: msm: sde: update HFC layer checks

Update HFC layer checks to handle partial update. Layer checks
should compare against ROI when partial update is enabled.
Layer checks should compare against full panel height when
destination scaler is enabled. Destination scaler and PU
concurrency is not supported.

Change-Id: I3435370a81f05a492411433054ae09f2125c6bf7
Signed-off-by: Anjaneya Prasad Musunuri <[email protected]>
Anjaneya Prasad Musunuri 3 years ago
parent
commit
87332208c3
3 changed files with 11 additions and 1 deletions
  1. 8 0
      msm/sde/sde_color_processing.c
  2. 2 0
      msm/sde/sde_hw_mdss.h
  3. 1 1
      msm/sde/sde_hw_reg_dma_v1_color_proc.c

+ 8 - 0
msm/sde/sde_color_processing.c

@@ -1650,6 +1650,7 @@ static void _sde_cp_crtc_commit_feature(struct sde_cp_node *prop_node,
 	int i = 0, ret = 0;
 	bool feature_enabled = false;
 	struct sde_mdss_cfg *catalog = NULL;
+	struct sde_crtc_state *sde_crtc_state;
 
 	memset(&hw_cfg, 0, sizeof(hw_cfg));
 	_sde_cp_get_cached_payload(prop_node, &hw_cfg, &feature_enabled);
@@ -1662,6 +1663,13 @@ static void _sde_cp_crtc_commit_feature(struct sde_cp_node *prop_node,
 	hw_cfg.skip_blend_plane_h = sde_crtc->skip_blend_plane_h;
 	hw_cfg.skip_blend_plane_w = sde_crtc->skip_blend_plane_w;
 
+	sde_crtc_state = to_sde_crtc_state(sde_crtc->base.state);
+	if (!sde_crtc_state) {
+		DRM_ERROR("invalid sde_crtc_state %pK\n", sde_crtc_state);
+		return;
+	}
+	hw_cfg.num_ds_enabled = sde_crtc_state->num_ds_enabled;
+
 	SDE_EVT32(hw_cfg.panel_width, hw_cfg.panel_height);
 
 	for (i = 0; i < num_mixers; i++) {

+ 2 - 0
msm/sde/sde_hw_mdss.h

@@ -643,6 +643,7 @@ struct sde_mdss_color {
  * @skip_blend_plane: plane which has been skipped staging into layer mixer
  * @skip_blend_plane_w: skip plane width
  * @skip_blend_plane_h: skip plane height
+ * @num_ds_enabled: Number of destination scalers enabled
  */
 struct sde_hw_cp_cfg {
 	void *payload;
@@ -661,6 +662,7 @@ struct sde_hw_cp_cfg {
 	enum sde_sspp skip_blend_plane;
 	u32 skip_blend_plane_w;
 	u32 skip_blend_plane_h;
+	u32 num_ds_enabled;
 };
 
 /**

+ 1 - 1
msm/sde/sde_hw_reg_dma_v1_color_proc.c

@@ -5597,7 +5597,7 @@ static bool __reg_dmav1_valid_hfc_en_cfg(struct drm_msm_dem_cfg *dcfg,
 		return false;
 	}
 
-	h = hw_cfg->panel_height;
+	h = hw_cfg->num_ds_enabled ? hw_cfg->panel_height : hw_cfg->displayv;
 	w = hw_cfg->panel_width;
 	temp = hw_cfg->panel_width / 2;
 	if (dcfg->pentile) {