disp: msm: sde: update unmult offsets

Unmult feature is currently using offsets from previous targets.
This leads to unexpected alpha transparency errors on screen.
This change updates the new offsets based on hw version and
retains the original offsets for backward compatibility.

Change-Id: Icdba050371a583f1a20b91a451be3324de12c2cf
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This commit is contained in:
Nilaan Gunabalachandran
2021-08-10 15:47:44 -04:00
parent 6bf96605eb
commit 8724924e6e
3 changed files with 24 additions and 9 deletions

View File

@@ -160,6 +160,11 @@
#define SDE_UIDLE_MAX_FPS_120 120 #define SDE_UIDLE_MAX_FPS_120 120
#define SDE_UIDLE_MAX_FPS_240 240 #define SDE_UIDLE_MAX_FPS_240 240
/* Unmult Offsets */
#define SDE_VIG_UNMULT 0x1EA0
#define SDE_DGM_UNMULT 0x804
#define SDE_DGM_UNMULT_2 0xE04
#define SSPP_GET_REGDMA_BASE(blk_base, top_off) ((blk_base) >= (top_off) ?\ #define SSPP_GET_REGDMA_BASE(blk_base, top_off) ((blk_base) >= (top_off) ?\
(blk_base) - (top_off) : (blk_base)) (blk_base) - (top_off) : (blk_base))
@@ -1431,8 +1436,10 @@ static void _sde_sspp_setup_vigs_pp(struct sde_dt_props *props,
_sde_sspp_setup_vcm(sspp, props, "sspp_vig_igc", &sblk->igc_blk[0], _sde_sspp_setup_vcm(sspp, props, "sspp_vig_igc", &sblk->igc_blk[0],
SDE_SSPP_VIG_IGC, VIG_IGC_PROP, true); SDE_SSPP_VIG_IGC, VIG_IGC_PROP, true);
if (props->exists[VIG_INVERSE_PMA]) if (props->exists[VIG_INVERSE_PMA]) {
set_bit(SDE_SSPP_INVERSE_PMA, &sspp->features); set_bit(SDE_SSPP_INVERSE_PMA, &sspp->features);
sblk->unmult_offset[0] = SDE_VIG_UNMULT;
}
} }
static int _sde_sspp_setup_vigs(struct device_node *np, static int _sde_sspp_setup_vigs(struct device_node *np,
@@ -1829,9 +1836,14 @@ static int _sde_sspp_setup_dmas(struct device_node *np,
SDE_SSPP_DMA_GC, DMA_GC_PROP, true); SDE_SSPP_DMA_GC, DMA_GC_PROP, true);
if (PROP_VALUE_ACCESS(props[j]->values, if (PROP_VALUE_ACCESS(props[j]->values,
DMA_DGM_INVERSE_PMA, 0)) DMA_DGM_INVERSE_PMA, 0)) {
set_bit(SDE_SSPP_DGM_INVERSE_PMA, set_bit(SDE_SSPP_DGM_INVERSE_PMA,
&sspp->features); &sspp->features);
if (sde_cfg->hwversion >= SDE_HW_VER_810)
sblk->unmult_offset[j] = SDE_DGM_UNMULT_2 + j*0x1000;
else
sblk->unmult_offset[j] = SDE_DGM_UNMULT + j*0x1000;
}
if (props[j]->exists[DMA_CSC_OFF]) if (props[j]->exists[DMA_CSC_OFF])
_sde_sspp_setup_dgm(sspp, props[j], _sde_sspp_setup_dgm(sspp, props[j],

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@@ -778,6 +778,7 @@ enum sde_creq_lut_types {
* @fp16_csc_blk: FP16 CSC block array * @fp16_csc_blk: FP16 CSC block array
* @num_fp16_unmult_blk: number of FP16 UNMULT blocks * @num_fp16_unmult_blk: number of FP16 UNMULT blocks
* @fp16_unmult_blk: FP16 UNMULT block array * @fp16_unmult_blk: FP16 UNMULT block array
* @unmult_offset: Unmult register offset
* @format_list: Pointer to list of supported formats * @format_list: Pointer to list of supported formats
* @virt_format_list: Pointer to list of supported formats for virtual planes * @virt_format_list: Pointer to list of supported formats for virtual planes
* @in_rot_format_list: Pointer to list of supported formats for inline rotation * @in_rot_format_list: Pointer to list of supported formats for inline rotation
@@ -829,6 +830,7 @@ struct sde_sspp_sub_blks {
struct sde_pp_blk fp16_csc_blk[SSPP_SUBBLK_COUNT_MAX]; struct sde_pp_blk fp16_csc_blk[SSPP_SUBBLK_COUNT_MAX];
u32 num_fp16_unmult_blk; u32 num_fp16_unmult_blk;
struct sde_pp_blk fp16_unmult_blk[SSPP_SUBBLK_COUNT_MAX]; struct sde_pp_blk fp16_unmult_blk[SSPP_SUBBLK_COUNT_MAX];
u32 unmult_offset[SSPP_SUBBLK_COUNT_MAX];
const struct sde_format_extended *format_list; const struct sde_format_extended *format_list;
const struct sde_format_extended *virt_format_list; const struct sde_format_extended *virt_format_list;

View File

@@ -46,10 +46,6 @@
#define SSPP_UIDLE_CTRL_VALUE_REC1 0x1f4 #define SSPP_UIDLE_CTRL_VALUE_REC1 0x1f4
/* SSPP_DGM */ /* SSPP_DGM */
#define SSPP_DGM_OP_MODE 0x804
#define SSPP_DGM_OP_MODE_REC1 0x1804
#define SSPP_GAMUT_UNMULT_MODE 0x1EA0
#define SSPP_DGM_0 0x9F0 #define SSPP_DGM_0 0x9F0
#define SSPP_DGM_1 0x19F0 #define SSPP_DGM_1 0x19F0
#define SSPP_DGM_SIZE 0x420 #define SSPP_DGM_SIZE 0x420
@@ -1325,27 +1321,32 @@ static void sde_hw_sspp_setup_inverse_pma(struct sde_hw_pipe *ctx,
enum sde_sspp_multirect_index index, u32 enable) enum sde_sspp_multirect_index index, u32 enable)
{ {
u32 op_mode = 0; u32 op_mode = 0;
u32 offset;
if (!ctx || (index == SDE_SSPP_RECT_1)) if (!ctx || (index == SDE_SSPP_RECT_1))
return; return;
offset = ctx->cap->sblk->unmult_offset[0];
if (enable) if (enable)
op_mode |= BIT(0); op_mode |= BIT(0);
SDE_REG_WRITE(&ctx->hw, SSPP_GAMUT_UNMULT_MODE, op_mode); SDE_REG_WRITE(&ctx->hw, offset, op_mode);
} }
static void sde_hw_sspp_setup_dgm_inverse_pma(struct sde_hw_pipe *ctx, static void sde_hw_sspp_setup_dgm_inverse_pma(struct sde_hw_pipe *ctx,
enum sde_sspp_multirect_index index, u32 enable) enum sde_sspp_multirect_index index, u32 enable)
{ {
u32 offset = SSPP_DGM_OP_MODE; u32 offset;
u32 op_mode = 0; u32 op_mode = 0;
if (!ctx) if (!ctx)
return; return;
if (index == SDE_SSPP_RECT_1) if (index == SDE_SSPP_RECT_1)
offset = SSPP_DGM_OP_MODE_REC1; offset = ctx->cap->sblk->unmult_offset[1];
else
offset = ctx->cap->sblk->unmult_offset[0];
op_mode = SDE_REG_READ(&ctx->hw, offset); op_mode = SDE_REG_READ(&ctx->hw, offset);