msm: camera: isp: Add header for TFE980

Add target header for TFE 980.

CRs-Fixed: 3321317
Change-Id: I30853defafd39b8d4738364223f9780c5a3b6c7e
Signed-off-by: Li Sha Lim <[email protected]>
Signed-off-by: Mukund Madhusudan Atre <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h

@@ -25,7 +25,7 @@
 
 #define CAM_VFE_MAX_UBWC_PORTS        4
 
-#define CAM_VFE_PERF_CNT_MAX          2
+#define CAM_VFE_PERF_CNT_MAX          8
 
 enum cam_isp_hw_vfe_in_mux {
 	CAM_ISP_HW_VFE_IN_CAMIF       = 0,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_tfe980.h

@@ -0,0 +1,2473 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CAM_TFE980_H_
+#define _CAM_TFE980_H_
+#include "cam_vfe_top_ver4.h"
+#include "cam_vfe_core.h"
+#include "cam_vfe_bus_ver3.h"
+#include "cam_irq_controller.h"
+
+#define CAM_TFE_980_NUM_DBG_REG              35
+#define CAM_TFE_BUS_VER3_980_MAX_CLIENTS     28
+
+static struct cam_vfe_top_ver4_module_desc tfe980_ipp_mod_desc[] = {
+	{
+		.id = 0,
+		.desc = "CLC_STATS_AWB_BG_TINTLESS",
+	},
+	{
+		.id  = 1,
+		.desc = "CLC_STATS_AWB_BG_AE",
+	},
+	{
+		.id = 2,
+		.desc = "CLC_STATS_BHIST_AEC",
+	},
+	{
+		.id = 3,
+		.desc = "CLC_STATS_RS",
+	},
+	{
+		.id = 4,
+		.desc = "CLC_STATS_BFW_AWB",
+	},
+	{
+		.id = 5,
+		.desc = "CLC_STATS_AWB_BG_AWB",
+	},
+	{
+		.id = 6,
+		.desc = "CLC_STATS_BHIST_AF",
+	},
+	{
+		.id = 7,
+		.desc = "CLC_STATS_AWB_BG_ALSC",
+	},
+	{
+		.id = 8,
+		.desc = "CLC_STATS_BHIST_TMC",
+	},
+	{
+		.id = 9,
+		.desc = "CLC_COMPDECOMP_FD",
+	},
+	{
+		.id = 10,
+		.desc = "CLC_COLOR_CORRECT",
+	},
+	{
+		.id = 11,
+		.desc = "CLC_GTM",
+	},
+	{
+		.id = 12,
+		.desc = "CLC_GLUT",
+	},
+	{
+		.id = 13,
+		.desc = "CLC_COLOR_XFORM",
+	},
+	{
+		.id = 14,
+		.desc = "CLC_DOWNSCALE_MN_Y",
+	},
+	{
+		.id  = 15,
+		.desc = "CLC_DOWNSCALE_MN_C",
+	},
+	{
+		.id = 16,
+		.desc = "CLC_CROP_RND_CLAMP_FD_Y",
+	},
+	{
+		.id = 17,
+		.desc = "CLC_CROP_RND_CLAMP_FD_C",
+	},
+	{
+		.id = 18,
+		.desc = "CLC_BDS2_DEMO",
+	},
+	{
+		.id = 19,
+		.desc = "CLC_PUNCH_BDS2",
+	},
+	{
+		.id = 20,
+		.desc = "CLC_PUNCH_DS4_MUX",
+	},
+	{
+		.id = 21,
+		.desc = "CLC_BAYER_DS_4_DS4",
+	},
+	{
+		.id = 22,
+		.desc = "CLC_CROP_RND_CLAMP_DS4"
+	},
+	{
+		.id = 23,
+		.desc = "CLC_PUNCH_DS16"
+	},
+	{
+		.id = 24,
+		.desc = "CLC_BAYER_DS_4_DS16",
+	},
+	{
+		.id = 25,
+		.desc = "CLC_CROP_RND_CLAMP_DS16",
+	},
+	{
+		.id = 26,
+		.desc = "CLC_CROP_RND_CLAMP_DS2",
+	},
+	{
+		.id = 27,
+		.desc = "CLC_RCS_DS2",
+	},
+	{
+		.id = 28,
+		.desc = "CLC_CROP_RND_CLAMP_FULL_OUT",
+	},
+	{
+		.id = 29,
+		.desc = "CLC_COMPDECOMP_BYPASS",
+	},
+	{
+		.id = 30,
+		.desc = "CLC_CROP_RND_CLAMP_BYPASS",
+	},
+	{
+		.id = 31,
+		.desc = "CLC_RCS_FULL_OUT",
+	},
+};
+
+struct cam_vfe_bayer_ver4_module_desc tfe980_bayer_mod_desc[] = {
+	{
+		.id = 0,
+		.desc = "CLC_DEMUX",
+	},
+	{
+		.id = 1,
+		.desc = "CLC_BPC_PDPC_GIC",
+	},
+	{
+		.id = 2,
+		.desc = "CLC_PDPC_BPC_1D",
+	},
+	{
+		.id = 3,
+		.desc = "CLC_ABF_BINC",
+	},
+	{
+		.id = 4,
+		.desc = "CLC_CHANNEL_GAINS",
+	},
+	{
+		.id = 5,
+		.desc = "CLC_LSC",
+	},
+	{
+		.id = 6,
+		.desc = "CLC_FCG",
+	},
+	{
+		.id = 7,
+		.desc = "CLC_WB_GAIN",
+	},
+	{
+		.id = 8,
+		.desc = "CLC_COMPDECOMP_BAYER",
+	},
+	{
+		.id = 9,
+		.desc = "CLC_CROP_RND_CLAMP_WIRC",
+	},
+};
+
+static struct cam_vfe_top_ver4_wr_client_desc tfe980_wr_client_desc[] = {
+	{
+		.wm_id = 0,
+		.desc = "VIDEO",
+	},
+	{
+		.wm_id = 1,
+		.desc = "DS4_Y",
+	},
+	{
+		.wm_id = 2,
+		.desc = "DS4_C",
+	},
+	{
+		.wm_id = 3,
+		.desc  = "DS16_Y",
+	},
+	{
+		.wm_id = 4,
+		.desc = "DS16_C",
+	},
+	{
+		.wm_id = 5,
+		.desc = "DS2_Y",
+	},
+	{
+		.wm_id = 6,
+		.desc = "DS2_C",
+	},
+	{
+		.wm_id = 7,
+		.desc = "FD_Y",
+	},
+	{
+		.wm_id = 8,
+		.desc = "FD_C",
+	},
+	{
+		.wm_id = 9,
+		.desc = "IR_OUT",
+	},
+	{
+		.wm_id = 10,
+		.desc = "STATS_AEC_BG",
+	},
+	{
+		.wm_id = 11,
+		.desc = "STATS_AEC_BHIST",
+	},
+	{
+		.wm_id = 12,
+		.desc = "STATS_TINTLESS_BG",
+	},
+	{
+		.wm_id = 13,
+		.desc = "STATS_AWB_BG",
+	},
+	{
+		.wm_id = 14,
+		.desc = "STATS_AWB_BFW",
+	},
+	{
+		.wm_id = 15,
+		.desc = "STATS_AF_BHIST",
+	},
+	{
+		.wm_id = 16,
+		.desc = "STATS_ALSC_BG",
+	},
+	{
+		.wm_id = 17,
+		.desc = "STATS_FLICKER",
+	},
+	{
+		.wm_id = 18,
+		.desc = "STATS_TMC_BHIST",
+	},
+	{
+		.wm_id = 19,
+		.desc = "PDAF_0_STATS",
+	},
+	{
+		.wm_id = 20,
+		.desc = "PDAF_1_PREPROCESS_2PD",
+	},
+	{
+		.wm_id = 21,
+		.desc = "PDAF_2_PARSED_DATA",
+	},
+	{
+		.wm_id = 22,
+		.desc = "PDAF_3_CAF",
+	},
+	{
+		.wm_id = 23,
+		.desc = "RDI0",
+	},
+	{
+		.wm_id = 24,
+		.desc = "RDI1",
+	},
+	{
+		.wm_id = 25,
+		.desc = "RDI2",
+	},
+	{
+		.wm_id = 26,
+		.desc = "RDI3",
+	},
+	{
+		.wm_id = 27,
+		.desc = "RDI4",
+	},
+};
+
+static struct cam_vfe_top_ver4_top_err_irq_desc tfe980_top_irq_err_desc[] = {
+	{
+		.bitmask = BIT(2),
+		.err_name = "BAYER_HM violation",
+		.desc = "",
+	},
+	{
+		.bitmask = BIT(24),
+		.err_name = "DYNAMIC PDAF SWITCH VIOLATION",
+		.desc = "PD exposure changes dynamically and the sensor gap is not large enough",
+	},
+	{
+		.bitmask = BIT(25),
+		.err_name  = "HAF violation",
+		.desc = "",
+	},
+	{
+		.bitmask = BIT(26),
+		.err_name = "PP VIOLATION",
+		.desc = "",
+	},
+	{
+		.bitmask  = BIT(27),
+		.err_name = "DIAG VIOLATION",
+		.desc = "HBI is less than the minimum required HBI",
+	},
+};
+
+static struct cam_vfe_top_ver4_pdaf_violation_desc tfe980_haf_violation_desc[] = {
+	{
+		.bitmask = BIT(0),
+		.desc = "Sim monitor 1 violation - SAD output",
+	},
+	{
+		.bitmask = BIT(1),
+		.desc = "Sim monitor 2 violation - pre-proc output",
+	},
+	{
+		.bitmask = BIT(2),
+		.desc = "Sim monitor 3 violation - parsed output",
+	},
+	{
+		.bitmask = BIT(3),
+		.desc = "Sim monitor 4 violation - CAF output",
+	},
+	{
+		.bitmask  = BIT(4),
+		.desc = "PDAF constraint violation",
+	},
+	{
+		.bitmask = BIT(5),
+		.desc = "CAF constraint violation",
+	},
+};
+
+static struct cam_vfe_top_ver4_pdaf_lcr_res_info tfe980_pdaf_haf_res_mask[] = {
+	{
+		.res_id = CAM_ISP_HW_VFE_IN_RDI0,
+		.val = 0,
+	},
+	{
+		.res_id = CAM_ISP_HW_VFE_IN_RDI1,
+		.val = 1,
+	},
+	{
+		.res_id = CAM_ISP_HW_VFE_IN_RDI2,
+		.val = 2,
+	},
+};
+
+static struct cam_irq_register_set tfe980_top_irq_reg_set = {
+	.mask_reg_offset   = 0x00000080,
+	.clear_reg_offset  = 0x00000084,
+	.status_reg_offset = 0x00000088,
+	.set_reg_offset    = 0x0000008C,
+	.test_set_val      = BIT(1),
+	.test_sub_val      = BIT(0),
+};
+
+static struct cam_irq_controller_reg_info tfe980_top_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &tfe980_top_irq_reg_set,
+	.global_irq_cmd_offset = 0x0000007C,
+	.global_clear_bitmask  = 0x00000001,
+	.global_set_bitmask    = 0x00000010,
+	.clear_all_bitmask     = 0xFFFFFFFF,
+};
+
+static uint32_t tfe980_top_debug_reg[] = {
+	0x00000190,
+	0x00000194,
+	0x00000198,
+	0x0000019C,
+	0x000001A0,
+	0x000001A4,
+	0x000001AB,
+	0x000001AC,
+	0x000001B0,
+	0x000001B4,
+	0x000001B8,
+	0x000001BC,
+	0x000001C0,
+	0x000001C4,
+	0x000001C8,
+	0x000001CC,
+	0x000001D0,
+	0x000001D4,
+	0x000001D8,
+	0x000001DC,
+	0x000001E0,
+	0x000001E4,
+	0x000001E8,
+	0x0000C1BC, /*  Bayer debug registers from here onwards */
+	0x0000C1C0,
+	0x0000C1C4,
+	0x0000C1C8,
+	0x0000C1CC,
+	0x0000C1D0,
+	0x0000C1D4,
+	0x0000C1D8,
+	0x0000C1DC,
+	0x0000C1E0,
+	0x0000C1E4,
+	0x0000C1E8,
+};
+
+static struct cam_vfe_top_ver4_reg_offset_common tfe980_top_common_reg = {
+	.hw_version               = 0x00000000,
+	.hw_capability            = 0x00000004,
+	.main_feature             = 0x00000008,
+	.bayer_feature            = 0x0000000C,
+	.stats_feature            = 0x00000010,
+	.fd_feature               = 0x00000014,
+	.core_cgc_ovd_0           = 0x00000018,
+	.ahb_cgc_ovd              = 0x00000020,
+	.core_mux_cfg             = 0x00000024,
+	.pdaf_input_cfg_0         = 0x00000028,
+	.pdaf_input_cfg_1         = 0x0000002C,
+	.stats_throttle_cfg_0     = 0x00000030,
+	.stats_throttle_cfg_1     = 0x00000034,
+	.stats_throttle_cfg_2     = 0x00000038,
+	.core_cfg_4               = 0x0000003C,
+	.pdaf_parsed_throttle_cfg = 0x00000040,
+	.wirc_throttle_cfg        = 0x00000044,
+	.fd_y_throttle_cfg        = 0x00000048,
+	.fd_c_throttle_cfg        = 0x0000004C,
+	.ds16_g_throttle_cfg      = 0x00000050,
+	.ds16_br_throttle_cfg     = 0x00000054,
+	.ds4_g_throttle_cfg       = 0x00000058,
+	.ds4_br_throttle_cfg      = 0x0000005C,
+	.ds2_g_throttle_cfg       = 0x00000060,
+	.ds2_br_throttle_cfg      = 0x00000064,
+	.full_out_throttle_cfg    = 0x00000068,
+	.diag_config              = 0x00000094,
+	.global_reset_cmd         = 0x0000007C,
+	.diag_sensor_status_0     = 0x00000098,
+	.diag_sensor_status_1     = 0x0000009C,
+	.diag_frm_cnt_status_0    = 0x000000A0,
+	.diag_frm_cnt_status_1    = 0x000000A4,
+	.diag_frm_cnt_status_2    = 0x000000A8,
+	.ipp_violation_status     = 0x00000090,
+	.bayer_violation_status   = 0x0000DA24,
+	.pdaf_violation_status    = 0x00009304,
+	.dsp_status               = 0x0000006C,
+	.bus_violation_status     = 0x00000864,
+	.bus_overflow_status      = 0x00000868,
+	.num_perf_counters        = 8,
+	.perf_count_reg = {
+		{
+			.perf_count_cfg    = 0x000000AC,
+			.perf_count_cfg_mc = 0x000000B0,
+			.perf_pix_count    = 0x000000B4,
+			.perf_line_count   = 0x000000B8,
+			.perf_stall_count  = 0x000000BC,
+			.perf_always_count = 0x000000C0,
+			.perf_count_status = 0x000000C4,
+		},
+		{
+			.perf_count_cfg    = 0x000000C8,
+			.perf_count_cfg_mc = 0x000000CC,
+			.perf_pix_count    = 0x000000D0,
+			.perf_line_count   = 0x000000D4,
+			.perf_stall_count  = 0x000000D8,
+			.perf_always_count = 0x000000DC,
+			.perf_count_status = 0x000000E0,
+		},
+		{
+			.perf_count_cfg    = 0x000000E4,
+			.perf_count_cfg_mc = 0x000000E8,
+			.perf_pix_count    = 0x000000EC,
+			.perf_line_count   = 0x000000F0,
+			.perf_stall_count  = 0x000000F4,
+			.perf_always_count = 0x000000F8,
+			.perf_count_status = 0x000000FC,
+		},
+		{
+			.perf_count_cfg    = 0x00000100,
+			.perf_count_cfg_mc = 0x00000104,
+			.perf_pix_count    = 0x00000108,
+			.perf_line_count   = 0x0000010C,
+			.perf_stall_count  = 0x00000110,
+			.perf_always_count = 0x00000114,
+			.perf_count_status = 0x00000118,
+		},
+		/*  Bayer per count regs from here onwards */
+		{
+			.perf_count_cfg    = 0x0000C028,
+			.perf_count_cfg_mc = 0x0000C02C,
+			.perf_pix_count    = 0x0000C030,
+			.perf_line_count   = 0x0000C034,
+			.perf_stall_count  = 0x0000C038,
+			.perf_always_count = 0x0000C03C,
+			.perf_count_status = 0x0000C040,
+		},
+		{
+			.perf_count_cfg    = 0x0000C044,
+			.perf_count_cfg_mc = 0x0000C048,
+			.perf_pix_count    = 0x0000C04C,
+			.perf_line_count   = 0x0000C050,
+			.perf_stall_count  = 0x0000C054,
+			.perf_always_count = 0x0000C058,
+			.perf_count_status = 0x0000C05C,
+		},
+		{
+			.perf_count_cfg    = 0x0000C060,
+			.perf_count_cfg_mc = 0x0000C064,
+			.perf_pix_count    = 0x0000C068,
+			.perf_line_count   = 0x0000C06C,
+			.perf_stall_count  = 0x0000C070,
+			.perf_always_count = 0x0000C074,
+			.perf_count_status = 0x0000C078,
+		},
+		{
+			.perf_count_cfg    = 0x0000C07C,
+			.perf_count_cfg_mc = 0x0000C080,
+			.perf_pix_count    = 0x0000C084,
+			.perf_line_count   = 0x0000C088,
+			.perf_stall_count  = 0x0000C08C,
+			.perf_always_count = 0x0000C090,
+			.perf_count_status = 0x0000C094,
+		},
+	},
+	.top_debug_cfg            = 0x000001EC,
+	.bayer_debug_cfg          = 0x0000C1EC,
+	.num_top_debug_reg        = 35,
+	.top_debug = tfe980_top_debug_reg,
+};
+
+static struct cam_vfe_ver4_path_reg_data tfe980_ipp_common_reg_data = {
+	.sof_irq_mask                    = 0x150,
+	.eof_irq_mask                    = 0x2A0,
+	.error_irq_mask                  = 0xF000005,
+	.ipp_violation_mask              = 0x4000000,
+	.bayer_violation_mask            = 0x4,
+	.pdaf_violation_mask             = 0x2000000,
+	.enable_diagnostic_hw            = 0x1,
+	.top_debug_cfg_en                = 3,
+};
+
+static struct cam_vfe_ver4_path_reg_data tfe980_pdlib_reg_data = {
+	.sof_irq_mask                    = 0x400,
+	.eof_irq_mask                    = 0x800,
+	.enable_diagnostic_hw            = 0x1,
+	.top_debug_cfg_en                = 3,
+};
+
+static struct cam_vfe_ver4_path_reg_data tfe980_vfe_full_rdi_reg_data[5] = {
+	{
+		.sof_irq_mask                    = 0x1000,
+		.eof_irq_mask                    = 0x2000,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 3,
+	},
+	{
+		.sof_irq_mask                    = 0x4000,
+		.eof_irq_mask                    = 0x8000,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 3,
+	},
+	{
+		.sof_irq_mask                    = 0x10000,
+		.eof_irq_mask                    = 0x20000,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 3,
+	},
+	{
+		.sof_irq_mask                    = 0x40000,
+		.eof_irq_mask                    = 0x80000,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 3,
+	},
+	{
+		.sof_irq_mask                    = 0x100000,
+		.eof_irq_mask                    = 0x200000,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 3,
+	},
+};
+
+struct cam_vfe_ver4_path_hw_info
+	tfe980_rdi_hw_info_arr[] = {
+	{
+		.common_reg     = &tfe980_top_common_reg,
+		.reg_data       = &tfe980_vfe_full_rdi_reg_data[0],
+	},
+	{
+		.common_reg     = &tfe980_top_common_reg,
+		.reg_data       = &tfe980_vfe_full_rdi_reg_data[1],
+	},
+	{
+		.common_reg     = &tfe980_top_common_reg,
+		.reg_data       = &tfe980_vfe_full_rdi_reg_data[2],
+	},
+	{
+		.common_reg     = &tfe980_top_common_reg,
+		.reg_data       = &tfe980_vfe_full_rdi_reg_data[3],
+	},
+	{
+		.common_reg     = &tfe980_top_common_reg,
+		.reg_data       = &tfe980_vfe_full_rdi_reg_data[4],
+	},
+};
+
+static struct cam_vfe_top_ver4_debug_reg_info tfe980_dbg_reg_info[CAM_TFE_980_NUM_DBG_REG][8] = {
+	VFE_DBG_INFO_ARRAY_4bit("test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"STATS_AWB_BG_TINTLESS",
+		"STATS_AWB_BG_AE",
+		"STATS_BHIST_AEC",
+		"STATS_RS",
+		"STATS_BFW_AWB",
+		"STATS_AWB_BG_AWB",
+		"STATS_BHIST_AF",
+		"STATS_AWB_BG_ALSC"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"STATS_BHIST_TMC",
+		"compdecomp_fd",
+		"color_correct",
+		"gtm",
+		"glut",
+		"color_xform",
+		"downscale_mn_y",
+		"downscale_mn_c"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"crop_rnd_clamp_fd_y",
+		"crop_rnd_clamp_fd_c",
+		"bds2_demo",
+		"punch_bds2",
+		"punch_ds4_mux",
+		"bayer_ds_4_ds4",
+		"crop_rnd_clamp_ds4",
+		"punch_ds16"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"bayer_ds_4_ds16",
+		"crop_rnd_clamp_ds16",
+		"crop_rnd_clamp_ds2",
+		"clc_haf",
+		"clc_rcs_ds2",
+		"clc_crop_rnd_clamp_full_out",
+		"clc_compdecomp_bypass",
+		"clc_crop_rnd_clamp_bypass"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"clc_rcs_full_out",
+		"clc_haf",
+		"csid_tfe_ipp",
+		"ppp_repeater",
+		"stats_awb_bg_tintless",
+		"stats_awb_bg_ae",
+		"stats_ae_bhist",
+		"stats_bayer_rs"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"stats_bayer_bfw",
+		"stats_awb_bg_awb",
+		"stats_bhist_af",
+		"full_out",
+		"ds4_out_y",
+		"ds4_out_c",
+		"ds16_out_y",
+		"ds16_out_c"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"ds2_out_y",
+		"ds2_out_c",
+		"w_ir",
+		"fd_out_y",
+		"fd_out_c",
+		"haf_sad_stats",
+		"haf_caf_stats",
+		"haf_parsed"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"haf_pre_processed",
+		"full_out",
+		"ubwc_stats",
+		"ds4_out_y",
+		"ds4_out_c",
+		"ds16_out_y",
+		"ds16_out_c",
+		"ds2_out_y"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"ubwc_stats",
+		"ds2_out_c",
+		"fd_out_y",
+		"fd_out_c",
+		"w_ir",
+		"stats_awb_bg_ae",
+		"stats_ae_bhist",
+		"stats_awb_bg_tintless"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"stats_awb_bg_alsc",
+		"stats_throttle_to_bus_awb_bg_awb",
+		"stats_throttle_to_bus_bayer_bfw",
+		"stats_throttle_to_bus_bhist_af",
+		"stats_throttle_to_bus_awb_bg_alsc",
+		"stats_throttle_to_bus_bayer_rs",
+		"stats_throttle_to_bus_bhist_tmc",
+		"stats_throttle_to_bus_sad"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"tfe_haf_processed_to_bus",
+		"tfe_haf_parsed_to_bus",
+		"tfe_stats_throttle_to_bus",
+		"rdi0_splitter_to_bus_wr",
+		"rdi1_splitter_to_bus_wr",
+		"rdi2_splitter_to_bus_wr",
+		"rdi3_splitter_to_bus_wr",
+		"rdi4_splitter_to_bus_wr"
+	),
+	VFE_DBG_INFO_ARRAY_4bit(
+		"stats_bhist_tmc_to_bus_wr",
+		"reserved",
+		"reserved",
+		"reserved",
+		"reserved",
+		"reserved",
+		"reserved",
+		"reserved"
+	),
+	{
+		/* needs to be parsed separately, doesn't conform to I, V, R */
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+		VFE_DBG_INFO(32, "lcr_pd_monitor"),
+	},
+	{
+		/* needs to be parsed separately, doesn't conform to I, V, R */
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+		VFE_DBG_INFO(32, "bus_wr_src_idle"),
+	},
+};
+
+static struct cam_vfe_top_ver4_hw_info tfe980_top_hw_info = {
+	.common_reg = &tfe980_top_common_reg,
+	.vfe_full_hw_info = {
+		.common_reg     = &tfe980_top_common_reg,
+		.reg_data       = &tfe980_ipp_common_reg_data,
+	},
+	.pdlib_hw_info = {
+		.common_reg     = &tfe980_top_common_reg,
+		.reg_data       = &tfe980_pdlib_reg_data,
+	},
+	.rdi_hw_info            = tfe980_rdi_hw_info_arr,
+	.wr_client_desc         = tfe980_wr_client_desc,
+	.ipp_module_desc        = tfe980_ipp_mod_desc,
+	.bayer_module_desc      = tfe980_bayer_mod_desc,
+	.num_mux = 7,
+	.mux_type = {
+		CAM_VFE_CAMIF_VER_4_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_PDLIB_VER_1_0,
+	},
+	.num_path_port_map = 3,
+	.path_port_map = {
+		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_2PD},
+		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PREPROCESS_2PD},
+		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PDAF_PARSED_DATA},
+	},
+	.num_rdi                         = ARRAY_SIZE(tfe980_rdi_hw_info_arr),
+	.num_top_errors                  = ARRAY_SIZE(tfe980_top_irq_err_desc),
+	.top_err_desc                    = tfe980_top_irq_err_desc,
+	.num_pdaf_violation_errors       = ARRAY_SIZE(tfe980_haf_violation_desc),
+	.pdaf_violation_desc             = tfe980_haf_violation_desc,
+	.debug_reg_info                  = &tfe980_dbg_reg_info,
+	.pdaf_lcr_res_mask               = tfe980_pdaf_haf_res_mask,
+	.num_pdaf_lcr_res                = ARRAY_SIZE(tfe980_pdaf_haf_res_mask),
+};
+
+static struct cam_irq_register_set tfe980_bus_irq_reg[2] = {
+	{
+		.mask_reg_offset   = 0x00000818,
+		.clear_reg_offset  = 0x00000820,
+		.status_reg_offset = 0x00000828,
+	},
+	{
+		.mask_reg_offset   = 0x0000081C,
+		.clear_reg_offset  = 0x00000824,
+		.status_reg_offset = 0x0000082C,
+	},
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_0 = {
+	.meta_addr        = 0x00000D40,
+	.meta_cfg         = 0x00000D44,
+	.mode_cfg         = 0x00000D48,
+	.stats_ctrl       = 0x00000D4C,
+	.ctrl_2           = 0x00000D50,
+	.lossy_thresh0    = 0x00000D54,
+	.lossy_thresh1    = 0x00000D58,
+	.off_lossy_var    = 0x00000D5C,
+	.bw_limit         = 0x00000D1C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_1 = {
+	.meta_addr        = 0x00000E40,
+	.meta_cfg         = 0x00000E44,
+	.mode_cfg         = 0x00000E48,
+	.stats_ctrl       = 0x00000E4C,
+	.ctrl_2           = 0x00000E50,
+	.lossy_thresh0    = 0x00000E54,
+	.lossy_thresh1    = 0x00000E58,
+	.off_lossy_var    = 0x00000E5C,
+	.bw_limit         = 0x00000E1C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_2 = {
+	.meta_addr        = 0x00000F40,
+	.meta_cfg         = 0x00000F44,
+	.mode_cfg         = 0x00000F48,
+	.stats_ctrl       = 0x00000F4C,
+	.ctrl_2           = 0x00000F50,
+	.lossy_thresh0    = 0x00000F54,
+	.lossy_thresh1    = 0x00000F58,
+	.off_lossy_var    = 0x00000F5C,
+	.bw_limit         = 0x00000F1C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_3 = {
+	.meta_addr        = 0x00001040,
+	.meta_cfg         = 0x00001044,
+	.mode_cfg         = 0x00001048,
+	.stats_ctrl       = 0x0000104C,
+	.ctrl_2           = 0x00001050,
+	.lossy_thresh0    = 0x00001054,
+	.lossy_thresh1    = 0x00001058,
+	.off_lossy_var    = 0x0000105C,
+	.bw_limit         = 0x0000101C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_4 = {
+	.meta_addr        = 0x00001140,
+	.meta_cfg         = 0x00001144,
+	.mode_cfg         = 0x00001148,
+	.stats_ctrl       = 0x0000114C,
+	.ctrl_2           = 0x00001150,
+	.lossy_thresh0    = 0x00001154,
+	.lossy_thresh1    = 0x00001158,
+	.off_lossy_var    = 0x0000115C,
+	.bw_limit         = 0x0000111C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_5 = {
+	.meta_addr        = 0x00001240,
+	.meta_cfg         = 0x00001244,
+	.mode_cfg         = 0x00001248,
+	.stats_ctrl       = 0x0000124C,
+	.ctrl_2           = 0x00001250,
+	.lossy_thresh0    = 0x00001254,
+	.lossy_thresh1    = 0x00001258,
+	.off_lossy_var    = 0x0000125C,
+	.bw_limit         = 0x0000121C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_6 = {
+	.meta_addr        = 0x00001340,
+	.meta_cfg         = 0x00001344,
+	.mode_cfg         = 0x00001348,
+	.stats_ctrl       = 0x0000134C,
+	.ctrl_2           = 0x00001350,
+	.lossy_thresh0    = 0x00001354,
+	.lossy_thresh1    = 0x00001358,
+	.off_lossy_var    = 0x0000135C,
+	.bw_limit         = 0x0000131C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
+	tfe980_ubwc_regs_client_20 = {
+	.meta_addr        = 0x00002140,
+	.meta_cfg         = 0x00002144,
+	.mode_cfg         = 0x00002148,
+	.stats_ctrl       = 0x0000214C,
+	.ctrl_2           = 0x00002150,
+	.lossy_thresh0    = 0x00002154,
+	.lossy_thresh1    = 0x00002158,
+	.off_lossy_var    = 0x0000215C,
+	.bw_limit         = 0x0000211C,
+	.ubwc_comp_en_bit = BIT(1),
+};
+
+static uint32_t tfe980_out_port_mid[][12] = {
+	{58},
+	{59},
+	{60},
+	{61},
+	{62},
+	{32, 34, 36, 33, 35, 37},
+	{32, 34, 36, 33, 35, 37, 38, 40, 42, 39, 41, 43},
+	{44, 46, 48, 45, 47, 49, 50, 52, 54, 51, 53, 55},
+	{38, 40, 42, 39, 41, 43, 44, 46, 48, 45, 47, 49},
+	{8, 9, 10},
+	{56, 57},
+	{32, 33, 34},
+	{35, 36, 37},
+	{38, 39, 40},
+	{41, 42, 43},
+	{44, 45, 46},
+	{47, 48, 49},
+	{50, 51, 52},
+	{53, 54, 55},
+	{56, 57, 58},
+	{11},
+	{50, 51},
+	{12},
+	{13},
+};
+
+static struct cam_vfe_bus_ver3_hw_info tfe980_bus_hw_info = {
+	.common_reg = {
+		.hw_version                       = 0x00000800,
+		.cgc_ovd                          = 0x00000808,
+		.ctxt_sel                         = 0x00000924,
+		.ubwc_static_ctrl                 = 0x00000858,
+		.pwr_iso_cfg                      = 0x0000085C,
+		.overflow_status_clear            = 0x00000860,
+		.ccif_violation_status            = 0x00000864,
+		.overflow_status                  = 0x00000868,
+		.image_size_violation_status      = 0x00000870,
+		.debug_status_top_cfg             = 0x000008F0,
+		.debug_status_top                 = 0x000008F4,
+		.test_bus_ctrl                    = 0x00000928,
+		.mc_read_sel_shift                = 0x5,
+		.mc_write_sel_shift               = 0x0,
+		.mc_ctxt_mask                     = 0x7,
+		.irq_reg_info = {
+			.num_registers            = 2,
+			.irq_reg_set              = tfe980_bus_irq_reg,
+			.global_irq_cmd_offset    = 0x00000830,
+			.global_clear_bitmask     = 0x00000001,
+		},
+	},
+	.num_client = CAM_TFE_BUS_VER3_980_MAX_CLIENTS,
+	.bus_client_reg = {
+		/* BUS Client 0 FULL */
+		{
+			.cfg                      = 0x00000D00,
+			.image_addr               = 0x00000D04,
+			.frame_incr               = 0x00000D08,
+			.image_cfg_0              = 0x00000D0C,
+			.image_cfg_1              = 0x00000D10,
+			.image_cfg_2              = 0x00000D14,
+			.packer_cfg               = 0x00000D18,
+			.frame_header_addr        = 0x00000D20,
+			.frame_header_incr        = 0x00000D24,
+			.frame_header_cfg         = 0x00000D28,
+			.irq_subsample_period     = 0x00000D30,
+			.irq_subsample_pattern    = 0x00000D34,
+			.framedrop_period         = 0x00000D38,
+			.framedrop_pattern        = 0x00000D3C,
+			.mmu_prefetch_cfg         = 0x00000D60,
+			.mmu_prefetch_max_offset  = 0x00000D64,
+			.system_cache_cfg         = 0x00000D68,
+			.addr_cfg                 = 0x00000D70,
+			.ctxt_cfg                 = 0x00000D78,
+			.addr_status_0            = 0x00000D90,
+			.addr_status_1            = 0x00000D94,
+			.addr_status_2            = 0x00000D98,
+			.addr_status_3            = 0x00000D9C,
+			.debug_status_cfg         = 0x00000D7C,
+			.debug_status_0           = 0x00000D80,
+			.debug_status_1           = 0x00000D84,
+			.bw_limiter_addr          = 0x00000D1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_0,
+		},
+		/* BUS Client 1 DS4_Y */
+		{
+			.cfg                      = 0x00000E00,
+			.image_addr               = 0x00000E04,
+			.frame_incr               = 0x00000E08,
+			.image_cfg_0              = 0x00000E0C,
+			.image_cfg_1              = 0x00000E10,
+			.image_cfg_2              = 0x00000E14,
+			.packer_cfg               = 0x00000E18,
+			.frame_header_addr        = 0x00000E20,
+			.frame_header_incr        = 0x00000E24,
+			.frame_header_cfg         = 0x00000E28,
+			.irq_subsample_period     = 0x00000E30,
+			.irq_subsample_pattern    = 0x00000E34,
+			.framedrop_period         = 0x00000E38,
+			.framedrop_pattern        = 0x00000E3C,
+			.mmu_prefetch_cfg         = 0x00000E60,
+			.mmu_prefetch_max_offset  = 0x00000E64,
+			.system_cache_cfg         = 0x00000E68,
+			.addr_cfg                 = 0x00000E70,
+			.ctxt_cfg                 = 0x00000E78,
+			.addr_status_0            = 0x00000E90,
+			.addr_status_1            = 0x00000E94,
+			.addr_status_2            = 0x00000E98,
+			.addr_status_3            = 0x00000E9C,
+			.debug_status_cfg         = 0x00000E7C,
+			.debug_status_0           = 0x00000E80,
+			.debug_status_1           = 0x00000E84,
+			.bw_limiter_addr          = 0x00000E1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_1,
+		},
+		/* BUS Client 2 DS4_C */
+		{
+			.cfg                      = 0x00000F00,
+			.image_addr               = 0x00000F04,
+			.frame_incr               = 0x00000F08,
+			.image_cfg_0              = 0x00000F0C,
+			.image_cfg_1              = 0x00000F10,
+			.image_cfg_2              = 0x00000F14,
+			.packer_cfg               = 0x00000F18,
+			.frame_header_addr        = 0x00000F20,
+			.frame_header_incr        = 0x00000F24,
+			.frame_header_cfg         = 0x00000F28,
+			.irq_subsample_period     = 0x00000F30,
+			.irq_subsample_pattern    = 0x00000F34,
+			.framedrop_period         = 0x00000F38,
+			.framedrop_pattern        = 0x00000F3C,
+			.mmu_prefetch_cfg         = 0x00000F60,
+			.mmu_prefetch_max_offset  = 0x00000F64,
+			.system_cache_cfg         = 0x00000F68,
+			.addr_cfg                 = 0x00000F70,
+			.ctxt_cfg                 = 0x00000F78,
+			.addr_status_0            = 0x00000F90,
+			.addr_status_1            = 0x00000F94,
+			.addr_status_2            = 0x00000F98,
+			.addr_status_3            = 0x00000F9C,
+			.debug_status_cfg         = 0x00000F7C,
+			.debug_status_0           = 0x00000F80,
+			.debug_status_1           = 0x00000F84,
+			.bw_limiter_addr          = 0x00000F1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_2,
+		},
+		/* BUS Client 3 DS16_Y */
+		{
+			.cfg                      = 0x00001000,
+			.image_addr               = 0x00001004,
+			.frame_incr               = 0x00001008,
+			.image_cfg_0              = 0x0000100C,
+			.image_cfg_1              = 0x00001010,
+			.image_cfg_2              = 0x00001014,
+			.packer_cfg               = 0x00001018,
+			.frame_header_addr        = 0x00001020,
+			.frame_header_incr        = 0x00001024,
+			.frame_header_cfg         = 0x00001028,
+			.irq_subsample_period     = 0x00001030,
+			.irq_subsample_pattern    = 0x00001034,
+			.framedrop_period         = 0x00001038,
+			.framedrop_pattern        = 0x0000103C,
+			.mmu_prefetch_cfg         = 0x00001060,
+			.mmu_prefetch_max_offset  = 0x00001064,
+			.system_cache_cfg         = 0x00001068,
+			.addr_cfg                 = 0x00001070,
+			.ctxt_cfg                 = 0x00001078,
+			.addr_status_0            = 0x00001090,
+			.addr_status_1            = 0x00001094,
+			.addr_status_2            = 0x00001098,
+			.addr_status_3            = 0x0000109C,
+			.debug_status_cfg         = 0x0000107C,
+			.debug_status_0           = 0x00001080,
+			.debug_status_1           = 0x00001084,
+			.bw_limiter_addr          = 0x0000101C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_3,
+		},
+		/* BUS Client 4 DS16_C */
+		{
+			.cfg                      = 0x00001100,
+			.image_addr               = 0x00001104,
+			.frame_incr               = 0x00001108,
+			.image_cfg_0              = 0x0000110C,
+			.image_cfg_1              = 0x00001110,
+			.image_cfg_2              = 0x00001114,
+			.packer_cfg               = 0x00001118,
+			.frame_header_addr        = 0x00001120,
+			.frame_header_incr        = 0x00001124,
+			.frame_header_cfg         = 0x00001128,
+			.irq_subsample_period     = 0x00001130,
+			.irq_subsample_pattern    = 0x00001134,
+			.framedrop_period         = 0x00001138,
+			.framedrop_pattern        = 0x0000113C,
+			.mmu_prefetch_cfg         = 0x00001160,
+			.mmu_prefetch_max_offset  = 0x00001164,
+			.system_cache_cfg         = 0x00001168,
+			.addr_cfg                 = 0x00001170,
+			.ctxt_cfg                 = 0x00001178,
+			.addr_status_0            = 0x00001190,
+			.addr_status_1            = 0x00001194,
+			.addr_status_2            = 0x00001198,
+			.addr_status_3            = 0x0000119C,
+			.debug_status_cfg         = 0x0000117C,
+			.debug_status_0           = 0x00001180,
+			.debug_status_1           = 0x00001184,
+			.bw_limiter_addr          = 0x0000111C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_4,
+		},
+		/* BUS Client 5 DS2_Y */
+		{
+			.cfg                      = 0x00001200,
+			.image_addr               = 0x00001204,
+			.frame_incr               = 0x00001208,
+			.image_cfg_0              = 0x0000120C,
+			.image_cfg_1              = 0x00001210,
+			.image_cfg_2              = 0x00001214,
+			.packer_cfg               = 0x00001218,
+			.frame_header_addr        = 0x00001220,
+			.frame_header_incr        = 0x00001224,
+			.frame_header_cfg         = 0x00001228,
+			.irq_subsample_period     = 0x00001230,
+			.irq_subsample_pattern    = 0x00001234,
+			.framedrop_period         = 0x00001238,
+			.framedrop_pattern        = 0x0000123C,
+			.mmu_prefetch_cfg         = 0x00001260,
+			.mmu_prefetch_max_offset  = 0x00001264,
+			.system_cache_cfg         = 0x00001268,
+			.addr_cfg                 = 0x00001270,
+			.ctxt_cfg                 = 0x00001278,
+			.addr_status_0            = 0x00001290,
+			.addr_status_1            = 0x00001294,
+			.addr_status_2            = 0x00001298,
+			.addr_status_3            = 0x0000129C,
+			.debug_status_cfg         = 0x0000127C,
+			.debug_status_0           = 0x00001280,
+			.debug_status_1           = 0x00001284,
+			.bw_limiter_addr          = 0x0000121C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_5,
+		},
+		/* BUS Client 6 DS2_C */
+		{
+			.cfg                      = 0x00001300,
+			.image_addr               = 0x00001304,
+			.frame_incr               = 0x00001308,
+			.image_cfg_0              = 0x0000130C,
+			.image_cfg_1              = 0x00001310,
+			.image_cfg_2              = 0x00001314,
+			.packer_cfg               = 0x00001318,
+			.frame_header_addr        = 0x00001320,
+			.frame_header_incr        = 0x00001324,
+			.frame_header_cfg         = 0x00001328,
+			.irq_subsample_period     = 0x00001330,
+			.irq_subsample_pattern    = 0x00001334,
+			.framedrop_period         = 0x00001338,
+			.framedrop_pattern        = 0x0000133C,
+			.mmu_prefetch_cfg         = 0x00001360,
+			.mmu_prefetch_max_offset  = 0x00001364,
+			.system_cache_cfg         = 0x00001368,
+			.addr_cfg                 = 0x00001370,
+			.ctxt_cfg                 = 0x00001378,
+			.addr_status_0            = 0x00001390,
+			.addr_status_1            = 0x00001394,
+			.addr_status_2            = 0x00001398,
+			.addr_status_3            = 0x0000139C,
+			.debug_status_cfg         = 0x0000137C,
+			.debug_status_0           = 0x00001380,
+			.debug_status_1           = 0x00001384,
+			.bw_limiter_addr          = 0x0000131C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_6,
+		},
+		/* BUS Client 7 FD_Y */
+		{
+			.cfg                      = 0x00001400,
+			.image_addr               = 0x00001404,
+			.frame_incr               = 0x00001408,
+			.image_cfg_0              = 0x0000140C,
+			.image_cfg_1              = 0x00001410,
+			.image_cfg_2              = 0x00001414,
+			.packer_cfg               = 0x00001418,
+			.frame_header_addr        = 0x00001420,
+			.frame_header_incr        = 0x00001424,
+			.frame_header_cfg         = 0x00001428,
+			.irq_subsample_period     = 0x00001430,
+			.irq_subsample_pattern    = 0x00001434,
+			.framedrop_period         = 0x00001438,
+			.framedrop_pattern        = 0x0000143C,
+			.mmu_prefetch_cfg         = 0x00001460,
+			.mmu_prefetch_max_offset  = 0x00001464,
+			.system_cache_cfg         = 0x00001468,
+			.addr_cfg                 = 0x00001470,
+			.ctxt_cfg                 = 0x00001478,
+			.addr_status_0            = 0x00001490,
+			.addr_status_1            = 0x00001494,
+			.addr_status_2            = 0x00001498,
+			.addr_status_3            = 0x0000149C,
+			.debug_status_cfg         = 0x0000147C,
+			.debug_status_0           = 0x00001480,
+			.debug_status_1           = 0x00001484,
+			.bw_limiter_addr          = 0x0000141C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_1,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 8 FD_C */
+		{
+			.cfg                      = 0x00001500,
+			.image_addr               = 0x00001504,
+			.frame_incr               = 0x00001508,
+			.image_cfg_0              = 0x0000150C,
+			.image_cfg_1              = 0x00001510,
+			.image_cfg_2              = 0x00001514,
+			.packer_cfg               = 0x00001518,
+			.frame_header_addr        = 0x00001520,
+			.frame_header_incr        = 0x00001524,
+			.frame_header_cfg         = 0x00001528,
+			.irq_subsample_period     = 0x00001530,
+			.irq_subsample_pattern    = 0x00001534,
+			.framedrop_period         = 0x00001538,
+			.framedrop_pattern        = 0x0000153C,
+			.mmu_prefetch_cfg         = 0x00001560,
+			.mmu_prefetch_max_offset  = 0x00001564,
+			.system_cache_cfg         = 0x00001568,
+			.addr_cfg                 = 0x00001570,
+			.ctxt_cfg                 = 0x00001578,
+			.addr_status_0            = 0x00001590,
+			.addr_status_1            = 0x00001594,
+			.addr_status_2            = 0x00001598,
+			.addr_status_3            = 0x0000159C,
+			.debug_status_cfg         = 0x0000157C,
+			.debug_status_0           = 0x00001580,
+			.debug_status_1           = 0x00001584,
+			.bw_limiter_addr          = 0x0000151C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_1,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 9 IR */
+		{
+			.cfg                      = 0x00001600,
+			.image_addr               = 0x00001604,
+			.frame_incr               = 0x00001608,
+			.image_cfg_0              = 0x0000160C,
+			.image_cfg_1              = 0x00001610,
+			.image_cfg_2              = 0x00001614,
+			.packer_cfg               = 0x00001618,
+			.frame_header_addr        = 0x00001620,
+			.frame_header_incr        = 0x00001624,
+			.frame_header_cfg         = 0x00001628,
+			.irq_subsample_period     = 0x00001630,
+			.irq_subsample_pattern    = 0x00001634,
+			.framedrop_period         = 0x00001638,
+			.framedrop_pattern        = 0x0000163C,
+			.mmu_prefetch_cfg         = 0x00001660,
+			.mmu_prefetch_max_offset  = 0x00001664,
+			.system_cache_cfg         = 0x00001668,
+			.addr_cfg                 = 0x00001670,
+			.ctxt_cfg                 = 0x00001678,
+			.addr_status_0            = 0x00001690,
+			.addr_status_1            = 0x00001694,
+			.addr_status_2            = 0x00001698,
+			.addr_status_3            = 0x0000169C,
+			.debug_status_cfg         = 0x0000167C,
+			.debug_status_0           = 0x00001680,
+			.debug_status_1           = 0x00001684,
+			.bw_limiter_addr          = 0x0000161C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 10 STATS_AEC_BG */
+		{
+			.cfg                      = 0x00001700,
+			.image_addr               = 0x00001704,
+			.frame_incr               = 0x00001708,
+			.image_cfg_0              = 0x0000170C,
+			.image_cfg_1              = 0x00001710,
+			.image_cfg_2              = 0x00001714,
+			.packer_cfg               = 0x00001718,
+			.frame_header_addr        = 0x00001720,
+			.frame_header_incr        = 0x00001724,
+			.frame_header_cfg         = 0x00001728,
+			.irq_subsample_period     = 0x00001730,
+			.irq_subsample_pattern    = 0x00001734,
+			.framedrop_period         = 0x00001738,
+			.framedrop_pattern        = 0x0000173C,
+			.mmu_prefetch_cfg         = 0x00001760,
+			.mmu_prefetch_max_offset  = 0x00001764,
+			.system_cache_cfg         = 0x00001768,
+			.addr_cfg                 = 0x00001770,
+			.ctxt_cfg                 = 0x00001778,
+			.addr_status_0            = 0x00001790,
+			.addr_status_1            = 0x00001794,
+			.addr_status_2            = 0x00001798,
+			.addr_status_3            = 0x0000179C,
+			.debug_status_cfg         = 0x0000177C,
+			.debug_status_0           = 0x00001780,
+			.debug_status_1           = 0x00001784,
+			.bw_limiter_addr          = 0x0000171C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 11 STATS_AEC_BHIST */
+		{
+			.cfg                      = 0x00001800,
+			.image_addr               = 0x00001804,
+			.frame_incr               = 0x00001808,
+			.image_cfg_0              = 0x0000180C,
+			.image_cfg_1              = 0x00001810,
+			.image_cfg_2              = 0x00001814,
+			.packer_cfg               = 0x00001818,
+			.frame_header_addr        = 0x00001820,
+			.frame_header_incr        = 0x00001824,
+			.frame_header_cfg         = 0x00001828,
+			.irq_subsample_period     = 0x00001830,
+			.irq_subsample_pattern    = 0x00001834,
+			.framedrop_period         = 0x00001838,
+			.framedrop_pattern        = 0x0000183C,
+			.mmu_prefetch_cfg         = 0x00001860,
+			.mmu_prefetch_max_offset  = 0x00001864,
+			.system_cache_cfg         = 0x00001868,
+			.addr_cfg                 = 0x00001870,
+			.ctxt_cfg                 = 0x00001878,
+			.addr_status_0            = 0x00001890,
+			.addr_status_1            = 0x00001894,
+			.addr_status_2            = 0x00001898,
+			.addr_status_3            = 0x0000189C,
+			.debug_status_cfg         = 0x0000187C,
+			.debug_status_0           = 0x00001880,
+			.debug_status_1           = 0x00001884,
+			.bw_limiter_addr          = 0x0000181C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 12 STATS_TINTELESS_BG */
+		{
+			.cfg                      = 0x00001900,
+			.image_addr               = 0x00001904,
+			.frame_incr               = 0x00001908,
+			.image_cfg_0              = 0x0000190C,
+			.image_cfg_1              = 0x00001910,
+			.image_cfg_2              = 0x00001914,
+			.packer_cfg               = 0x00001918,
+			.frame_header_addr        = 0x00001920,
+			.frame_header_incr        = 0x00001924,
+			.frame_header_cfg         = 0x00001928,
+			.irq_subsample_period     = 0x00001930,
+			.irq_subsample_pattern    = 0x00001934,
+			.framedrop_period         = 0x00001938,
+			.framedrop_pattern        = 0x0000193C,
+			.mmu_prefetch_cfg         = 0x00001960,
+			.mmu_prefetch_max_offset  = 0x00001964,
+			.system_cache_cfg         = 0x00001968,
+			.addr_cfg                 = 0x00001970,
+			.ctxt_cfg                 = 0x00001978,
+			.addr_status_0            = 0x00001990,
+			.addr_status_1            = 0x00001994,
+			.addr_status_2            = 0x00001998,
+			.addr_status_3            = 0x0000199C,
+			.debug_status_cfg         = 0x0000197C,
+			.debug_status_0           = 0x00001980,
+			.debug_status_1           = 0x00001984,
+			.bw_limiter_addr          = 0x0000191C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 13 STATS_AWB_BG */
+		{
+			.cfg                      = 0x00001A00,
+			.image_addr               = 0x00001A04,
+			.frame_incr               = 0x00001A08,
+			.image_cfg_0              = 0x00001A0C,
+			.image_cfg_1              = 0x00001A10,
+			.image_cfg_2              = 0x00001A14,
+			.packer_cfg               = 0x00001A18,
+			.frame_header_addr        = 0x00001A20,
+			.frame_header_incr        = 0x00001A24,
+			.frame_header_cfg         = 0x00001A28,
+			.irq_subsample_period     = 0x00001A30,
+			.irq_subsample_pattern    = 0x00001A34,
+			.framedrop_period         = 0x00001A38,
+			.framedrop_pattern        = 0x00001A3C,
+			.mmu_prefetch_cfg         = 0x00001A60,
+			.mmu_prefetch_max_offset  = 0x00001A64,
+			.system_cache_cfg         = 0x00001A68,
+			.addr_cfg                 = 0x00001A70,
+			.ctxt_cfg                 = 0x00001A78,
+			.addr_status_0            = 0x00001A90,
+			.addr_status_1            = 0x00001A94,
+			.addr_status_2            = 0x00001A98,
+			.addr_status_3            = 0x00001A9C,
+			.debug_status_cfg         = 0x00001A7C,
+			.debug_status_0           = 0x00001A80,
+			.debug_status_1           = 0x00001A84,
+			.bw_limiter_addr          = 0x00001A1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 14 STATS_AWB_BFW */
+		{
+			.cfg                      = 0x00001B00,
+			.image_addr               = 0x00001B04,
+			.frame_incr               = 0x00001B08,
+			.image_cfg_0              = 0x00001B0C,
+			.image_cfg_1              = 0x00001B10,
+			.image_cfg_2              = 0x00001B14,
+			.packer_cfg               = 0x00001B18,
+			.frame_header_addr        = 0x00001B20,
+			.frame_header_incr        = 0x00001B24,
+			.frame_header_cfg         = 0x00001B28,
+			.irq_subsample_period     = 0x00001B30,
+			.irq_subsample_pattern    = 0x00001B34,
+			.framedrop_period         = 0x00001B38,
+			.framedrop_pattern        = 0x00001B3C,
+			.mmu_prefetch_cfg         = 0x00001B60,
+			.mmu_prefetch_max_offset  = 0x00001B64,
+			.system_cache_cfg         = 0x00001B68,
+			.addr_cfg                 = 0x00001B70,
+			.ctxt_cfg                 = 0x00001B78,
+			.addr_status_0            = 0x00001B90,
+			.addr_status_1            = 0x00001B94,
+			.addr_status_2            = 0x00001B98,
+			.addr_status_3            = 0x00001B9C,
+			.debug_status_cfg         = 0x00001B7C,
+			.debug_status_0           = 0x00001B80,
+			.debug_status_1           = 0x00001B84,
+			.bw_limiter_addr          = 0x00001B1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 15 STATS_AF_BHIST */
+		{
+			.cfg                      = 0x00001C00,
+			.image_addr               = 0x00001C04,
+			.frame_incr               = 0x00001C08,
+			.image_cfg_0              = 0x00001C0C,
+			.image_cfg_1              = 0x00001C10,
+			.image_cfg_2              = 0x00001C14,
+			.packer_cfg               = 0x00001C18,
+			.frame_header_addr        = 0x00001C20,
+			.frame_header_incr        = 0x00001C24,
+			.frame_header_cfg         = 0x00001C28,
+			.irq_subsample_period     = 0x00001C30,
+			.irq_subsample_pattern    = 0x00001C34,
+			.framedrop_period         = 0x00001C38,
+			.framedrop_pattern        = 0x00001C3C,
+			.mmu_prefetch_cfg         = 0x00001C60,
+			.mmu_prefetch_max_offset  = 0x00001C64,
+			.system_cache_cfg         = 0x00001C68,
+			.addr_cfg                 = 0x00001C70,
+			.ctxt_cfg                 = 0x00001C78,
+			.addr_status_0            = 0x00001C90,
+			.addr_status_1            = 0x00001C94,
+			.addr_status_2            = 0x00001C98,
+			.addr_status_3            = 0x00001C9C,
+			.debug_status_cfg         = 0x00001C7C,
+			.debug_status_0           = 0x00001C80,
+			.debug_status_1           = 0x00001C84,
+			.bw_limiter_addr          = 0x00001C1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 16 STATS_ALSC_BG */ /* Or ALSC_BHIST? */
+		{
+			.cfg                      = 0x00001D00,
+			.image_addr               = 0x00001D04,
+			.frame_incr               = 0x00001D08,
+			.image_cfg_0              = 0x00001D0C,
+			.image_cfg_1              = 0x00001D10,
+			.image_cfg_2              = 0x00001D14,
+			.packer_cfg               = 0x00001D18,
+			.frame_header_addr        = 0x00001D20,
+			.frame_header_incr        = 0x00001D24,
+			.frame_header_cfg         = 0x00001D28,
+			.irq_subsample_period     = 0x00001D30,
+			.irq_subsample_pattern    = 0x00001D34,
+			.framedrop_period         = 0x00001D38,
+			.framedrop_pattern        = 0x00001D3C,
+			.mmu_prefetch_cfg         = 0x00001D60,
+			.mmu_prefetch_max_offset  = 0x00001D64,
+			.system_cache_cfg         = 0x00001D68,
+			.addr_cfg                 = 0x00001D70,
+			.ctxt_cfg                 = 0x00001D78,
+			.addr_status_0            = 0x00001D90,
+			.addr_status_1            = 0x00001D94,
+			.addr_status_2            = 0x00001D98,
+			.addr_status_3            = 0x00001D9C,
+			.debug_status_cfg         = 0x00001D7C,
+			.debug_status_0           = 0x00001D80,
+			.debug_status_1           = 0x00001D84,
+			.bw_limiter_addr          = 0x00001D1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 17 STATS_FLICKER_BAYERS */
+		{
+			.cfg                      = 0x00001E00,
+			.image_addr               = 0x00001E04,
+			.frame_incr               = 0x00001E08,
+			.image_cfg_0              = 0x00001E0C,
+			.image_cfg_1              = 0x00001E10,
+			.image_cfg_2              = 0x00001E14,
+			.packer_cfg               = 0x00001E18,
+			.frame_header_addr        = 0x00001E20,
+			.frame_header_incr        = 0x00001E24,
+			.frame_header_cfg         = 0x00001E28,
+			.irq_subsample_period     = 0x00001E30,
+			.irq_subsample_pattern    = 0x00001E34,
+			.framedrop_period         = 0x00001E38,
+			.framedrop_pattern        = 0x00001E3C,
+			.mmu_prefetch_cfg         = 0x00001E60,
+			.mmu_prefetch_max_offset  = 0x00001E64,
+			.system_cache_cfg         = 0x00001E68,
+			.addr_cfg                 = 0x00001E70,
+			.ctxt_cfg                 = 0x00001E78,
+			.addr_status_0            = 0x00001E90,
+			.addr_status_1            = 0x00001E94,
+			.addr_status_2            = 0x00001E98,
+			.addr_status_3            = 0x00001E9C,
+			.debug_status_cfg         = 0x00001E7C,
+			.debug_status_0           = 0x00001E80,
+			.debug_status_1           = 0x00001E84,
+			.bw_limiter_addr          = 0x00001E1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 18 STATS_TMC_BHIST */
+		{
+			.cfg                      = 0x00001F00,
+			.image_addr               = 0x00001F04,
+			.frame_incr               = 0x00001F08,
+			.image_cfg_0              = 0x00001F0C,
+			.image_cfg_1              = 0x00001F10,
+			.image_cfg_2              = 0x00001F14,
+			.packer_cfg               = 0x00001F18,
+			.frame_header_addr        = 0x00001F20,
+			.frame_header_incr        = 0x00001F24,
+			.frame_header_cfg         = 0x00001F28,
+			.irq_subsample_period     = 0x00001F30,
+			.irq_subsample_pattern    = 0x00001F34,
+			.framedrop_period         = 0x00001F38,
+			.framedrop_pattern        = 0x00001F3C,
+			.mmu_prefetch_cfg         = 0x00001F60,
+			.mmu_prefetch_max_offset  = 0x00001F64,
+			.system_cache_cfg         = 0x00001F68,
+			.addr_cfg                 = 0x00001F70,
+			.ctxt_cfg                 = 0x00001F78,
+			.addr_status_0            = 0x00001F90,
+			.addr_status_1            = 0x00001F94,
+			.addr_status_2            = 0x00001F98,
+			.addr_status_3            = 0x00001F9C,
+			.debug_status_cfg         = 0x00001F7C,
+			.debug_status_0           = 0x00001F80,
+			.debug_status_1           = 0x00001F84,
+			.bw_limiter_addr          = 0x00001F1C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 19 PDAF_0 */
+		{
+			.cfg                      = 0x00002000,
+			.image_addr               = 0x00002004,
+			.frame_incr               = 0x00002008,
+			.image_cfg_0              = 0x0000200C,
+			.image_cfg_1              = 0x00002010,
+			.image_cfg_2              = 0x00002014,
+			.packer_cfg               = 0x00002018,
+			.frame_header_addr        = 0x00002020,
+			.frame_header_incr        = 0x00002024,
+			.frame_header_cfg         = 0x00002028,
+			.irq_subsample_period     = 0x00002030,
+			.irq_subsample_pattern    = 0x00002034,
+			.framedrop_period         = 0x00002038,
+			.framedrop_pattern        = 0x0000203C,
+			.mmu_prefetch_cfg         = 0x00002060,
+			.mmu_prefetch_max_offset  = 0x00002064,
+			.system_cache_cfg         = 0x00002068,
+			.addr_cfg                 = 0x00002070,
+			.ctxt_cfg                 = 0x00002078,
+			.addr_status_0            = 0x00002090,
+			.addr_status_1            = 0x00002094,
+			.addr_status_2            = 0x00002098,
+			.addr_status_3            = 0x0000209C,
+			.debug_status_cfg         = 0x0000207C,
+			.debug_status_0           = 0x00002080,
+			.debug_status_1           = 0x00002084,
+			.bw_limiter_addr          = 0x0000201C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_3,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 20 PDAF_1 */
+		{
+			.cfg                      = 0x00002100,
+			.image_addr               = 0x00002104,
+			.frame_incr               = 0x00002108,
+			.image_cfg_0              = 0x0000210C,
+			.image_cfg_1              = 0x00002110,
+			.image_cfg_2              = 0x00002114,
+			.packer_cfg               = 0x00002118,
+			.frame_header_addr        = 0x00002120,
+			.frame_header_incr        = 0x00002124,
+			.frame_header_cfg         = 0x00002128,
+			.irq_subsample_period     = 0x00002130,
+			.irq_subsample_pattern    = 0x00002134,
+			.framedrop_period         = 0x00002138,
+			.framedrop_pattern        = 0x0000213C,
+			.mmu_prefetch_cfg         = 0x00002160,
+			.mmu_prefetch_max_offset  = 0x00002164,
+			.system_cache_cfg         = 0x00002168,
+			.addr_cfg                 = 0x00002170,
+			.ctxt_cfg                 = 0x00002178,
+			.addr_status_0            = 0x00002190,
+			.addr_status_1            = 0x00002194,
+			.addr_status_2            = 0x00002198,
+			.addr_status_3            = 0x0000219C,
+			.debug_status_cfg         = 0x0000217C,
+			.debug_status_0           = 0x00002180,
+			.debug_status_1           = 0x00002184,
+			.bw_limiter_addr          = 0x0000211C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_3,
+			.ubwc_regs                = &tfe980_ubwc_regs_client_20,
+		},
+		/* BUS Client 21 PDAF_2 */
+		{
+			.cfg                      = 0x00002200,
+			.image_addr               = 0x00002204,
+			.frame_incr               = 0x00002208,
+			.image_cfg_0              = 0x0000220C,
+			.image_cfg_1              = 0x00002210,
+			.image_cfg_2              = 0x00002214,
+			.packer_cfg               = 0x00002218,
+			.frame_header_addr        = 0x00002220,
+			.frame_header_incr        = 0x00002224,
+			.frame_header_cfg         = 0x00002228,
+			.irq_subsample_period     = 0x00002230,
+			.irq_subsample_pattern    = 0x00002234,
+			.framedrop_period         = 0x00002238,
+			.framedrop_pattern        = 0x0000223C,
+			.mmu_prefetch_cfg         = 0x00002260,
+			.mmu_prefetch_max_offset  = 0x00002264,
+			.system_cache_cfg         = 0x00002268,
+			.addr_cfg                 = 0x00002270,
+			.ctxt_cfg                 = 0x00002278,
+			.addr_status_0            = 0x00002290,
+			.addr_status_1            = 0x00002294,
+			.addr_status_2            = 0x00002298,
+			.addr_status_3            = 0x0000229C,
+			.debug_status_cfg         = 0x0000227C,
+			.debug_status_0           = 0x00002280,
+			.debug_status_1           = 0x00002284,
+			.bw_limiter_addr          = 0x0000221C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_3,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 22 PDAF_3 */
+		{
+			.cfg                      = 0x00002300,
+			.image_addr               = 0x00002304,
+			.frame_incr               = 0x00002308,
+			.image_cfg_0              = 0x0000230C,
+			.image_cfg_1              = 0x00002310,
+			.image_cfg_2              = 0x00002314,
+			.packer_cfg               = 0x00002318,
+			.frame_header_addr        = 0x00002320,
+			.frame_header_incr        = 0x00002324,
+			.frame_header_cfg         = 0x00002328,
+			.irq_subsample_period     = 0x00002330,
+			.irq_subsample_pattern    = 0x00002334,
+			.framedrop_period         = 0x00002338,
+			.framedrop_pattern        = 0x0000233C,
+			.mmu_prefetch_cfg         = 0x00002360,
+			.mmu_prefetch_max_offset  = 0x00002364,
+			.system_cache_cfg         = 0x00002368,
+			.addr_cfg                 = 0x00002370,
+			.ctxt_cfg                 = 0x00002378,
+			.addr_status_0            = 0x00002390,
+			.addr_status_1            = 0x00002394,
+			.addr_status_2            = 0x00002398,
+			.addr_status_3            = 0x0000239C,
+			.debug_status_cfg         = 0x0000237C,
+			.debug_status_0           = 0x00002380,
+			.debug_status_1           = 0x00002384,
+			.bw_limiter_addr          = 0x0000231C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_4,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 23 RDI_0 */
+		{
+			.cfg                      = 0x00002400,
+			.image_addr               = 0x00002404,
+			.frame_incr               = 0x00002408,
+			.image_cfg_0              = 0x0000240C,
+			.image_cfg_1              = 0x00002410,
+			.image_cfg_2              = 0x00002414,
+			.packer_cfg               = 0x00002418,
+			.frame_header_addr        = 0x00002420,
+			.frame_header_incr        = 0x00002424,
+			.frame_header_cfg         = 0x00002428,
+			.irq_subsample_period     = 0x00002430,
+			.irq_subsample_pattern    = 0x00002434,
+			.framedrop_period         = 0x00002438,
+			.framedrop_pattern        = 0x0000243C,
+			.mmu_prefetch_cfg         = 0x00002460,
+			.mmu_prefetch_max_offset  = 0x00002464,
+			.system_cache_cfg         = 0x00002468,
+			.addr_cfg                 = 0x00002470,
+			.ctxt_cfg                 = 0x00002478,
+			.addr_status_0            = 0x00002490,
+			.addr_status_1            = 0x00002494,
+			.addr_status_2            = 0x00002498,
+			.addr_status_3            = 0x0000249C,
+			.debug_status_cfg         = 0x0000247C,
+			.debug_status_0           = 0x00002480,
+			.debug_status_1           = 0x00002484,
+			.bw_limiter_addr          = 0x0000241C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_5,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 24 RDI_1 */
+		{
+			.cfg                      = 0x00002500,
+			.image_addr               = 0x00002504,
+			.frame_incr               = 0x00002508,
+			.image_cfg_0              = 0x0000250C,
+			.image_cfg_1              = 0x00002510,
+			.image_cfg_2              = 0x00002514,
+			.packer_cfg               = 0x00002518,
+			.frame_header_addr        = 0x00002520,
+			.frame_header_incr        = 0x00002524,
+			.frame_header_cfg         = 0x00002528,
+			.irq_subsample_period     = 0x00002530,
+			.irq_subsample_pattern    = 0x00002534,
+			.framedrop_period         = 0x00002538,
+			.framedrop_pattern        = 0x0000253C,
+			.mmu_prefetch_cfg         = 0x00002560,
+			.mmu_prefetch_max_offset  = 0x00002564,
+			.system_cache_cfg         = 0x00002568,
+			.addr_cfg                 = 0x00002570,
+			.ctxt_cfg                 = 0x00002578,
+			.addr_status_0            = 0x00002590,
+			.addr_status_1            = 0x00002594,
+			.addr_status_2            = 0x00002598,
+			.addr_status_3            = 0x0000259C,
+			.debug_status_cfg         = 0x0000257C,
+			.debug_status_0           = 0x00002580,
+			.debug_status_1           = 0x00002584,
+			.bw_limiter_addr          = 0x0000251C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_6,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 25 RDI_2 */
+		{
+			.cfg                      = 0x00002600,
+			.image_addr               = 0x00002604,
+			.frame_incr               = 0x00002608,
+			.image_cfg_0              = 0x0000260C,
+			.image_cfg_1              = 0x00002610,
+			.image_cfg_2              = 0x00002614,
+			.packer_cfg               = 0x00002618,
+			.frame_header_addr        = 0x00002620,
+			.frame_header_incr        = 0x00002624,
+			.frame_header_cfg         = 0x00002628,
+			.irq_subsample_period     = 0x00002630,
+			.irq_subsample_pattern    = 0x00002634,
+			.framedrop_period         = 0x00002638,
+			.framedrop_pattern        = 0x0000263C,
+			.mmu_prefetch_cfg         = 0x00002660,
+			.mmu_prefetch_max_offset  = 0x00002664,
+			.system_cache_cfg         = 0x00002668,
+			.addr_cfg                 = 0x00002670,
+			.ctxt_cfg                 = 0x00002678,
+			.addr_status_0            = 0x00002690,
+			.addr_status_1            = 0x00002694,
+			.addr_status_2            = 0x00002698,
+			.addr_status_3            = 0x0000269C,
+			.debug_status_cfg         = 0x0000267C,
+			.debug_status_0           = 0x00002680,
+			.debug_status_1           = 0x00002684,
+			.bw_limiter_addr          = 0x0000261C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_7,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 26 RDI_3 */
+		{
+			.cfg                      = 0x00002700,
+			.image_addr               = 0x00002704,
+			.frame_incr               = 0x00002708,
+			.image_cfg_0              = 0x0000270C,
+			.image_cfg_1              = 0x00002710,
+			.image_cfg_2              = 0x00002714,
+			.packer_cfg               = 0x00002718,
+			.frame_header_addr        = 0x00002720,
+			.frame_header_incr        = 0x00002724,
+			.frame_header_cfg         = 0x00002728,
+			.irq_subsample_period     = 0x00002730,
+			.irq_subsample_pattern    = 0x00002734,
+			.framedrop_period         = 0x00002738,
+			.framedrop_pattern        = 0x0000273C,
+			.mmu_prefetch_cfg         = 0x00002760,
+			.mmu_prefetch_max_offset  = 0x00002764,
+			.system_cache_cfg         = 0x00002768,
+			.addr_cfg                 = 0x00002770,
+			.ctxt_cfg                 = 0x00002778,
+			.addr_status_0            = 0x00002790,
+			.addr_status_1            = 0x00002794,
+			.addr_status_2            = 0x00002798,
+			.addr_status_3            = 0x0000279C,
+			.debug_status_cfg         = 0x0000277C,
+			.debug_status_0           = 0x00002780,
+			.debug_status_1           = 0x00002784,
+			.bw_limiter_addr          = 0x0000271C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_8,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 27 RDI_4 */
+		{
+			.cfg                      = 0x00002800,
+			.image_addr               = 0x00002804,
+			.frame_incr               = 0x00002808,
+			.image_cfg_0              = 0x0000280C,
+			.image_cfg_1              = 0x00002810,
+			.image_cfg_2              = 0x00002814,
+			.packer_cfg               = 0x00002818,
+			.frame_header_addr        = 0x00002820,
+			.frame_header_incr        = 0x00002824,
+			.frame_header_cfg         = 0x00002828,
+			.irq_subsample_period     = 0x00002830,
+			.irq_subsample_pattern    = 0x00002834,
+			.framedrop_period         = 0x00002838,
+			.framedrop_pattern        = 0x0000283C,
+			.mmu_prefetch_cfg         = 0x00002860,
+			.mmu_prefetch_max_offset  = 0x00002864,
+			.system_cache_cfg         = 0x00002868,
+			.addr_cfg                 = 0x00002870,
+			.ctxt_cfg                 = 0x00002878,
+			.addr_status_0            = 0x00002890,
+			.addr_status_1            = 0x00002894,
+			.addr_status_2            = 0x00002898,
+			.addr_status_3            = 0x0000289C,
+			.debug_status_cfg         = 0x0000287C,
+			.debug_status_0           = 0x00002880,
+			.debug_status_1           = 0x00002884,
+			.bw_limiter_addr          = 0x0000281C,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_9,
+			.ubwc_regs                = NULL,
+		},
+	},
+	.num_out = 24,
+	.vfe_out_hw_info = {
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI0,
+			.max_width     = 16384,
+			.max_height    = 16384,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
+			.mid           = tfe980_out_port_mid[0],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				23,
+			},
+			.name          = {
+				"RDI_0",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI1,
+			.max_width     = 16384,
+			.max_height    = 16384,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
+			.mid           = tfe980_out_port_mid[1],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				24,
+			},
+			.name          = {
+				"RDI_1",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI2,
+			.max_width     = 16384,
+			.max_height    = 16384,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
+			.mid           = tfe980_out_port_mid[2],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				25,
+			},
+			.name          = {
+				"RDI_2",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI3,
+			.max_width     = 16384,
+			.max_height    = 16384,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_5,
+			.mid           = tfe980_out_port_mid[3],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				26,
+			},
+			.name          = {
+				"RDI_3",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI4,
+			.max_width     = 16384,
+			.max_height    = 16384,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_5,
+			.mid           = tfe980_out_port_mid[4],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				27,
+			},
+			.name          = {
+				"RDI_4",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_FULL,
+			.max_width     = 4672,
+			.max_height    = 16384,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[5],
+			.num_mid       = 6,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 0,
+			.wm_idx        = {
+				0,
+			},
+			.name          = {
+				"FULL",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_DS4,
+			.max_width     = 1168,
+			.max_height    = 4096,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[6],
+			.num_mid       = 12,
+			.num_wm        = 2,
+			.line_based    = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 0,
+			.wm_idx        = {
+				1,
+				2,
+			},
+			.name          = {
+				"DS4_Y",
+				"DS4_UV"
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_DS16,
+			.max_width     = 292,
+			.max_height    = 1024,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[7],
+			.num_mid       = 12,
+			.num_wm        = 2,
+			.line_based    = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 0,
+			.wm_idx        = {
+				3,
+				4,
+			},
+			.name          = {
+				"DS16_Y",
+				"DS16_UV",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_DS2,
+			.max_width     = 4672,
+			.max_height    = 8192,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[8],
+			.num_mid       = 12,
+			.num_wm        = 2,
+			.line_based    = 1,
+			.mc_based      = true,
+			.wm_idx        = {
+				5,
+				6,
+			},
+			.name          = {
+				"DS2_Y",
+				"DS2_UV",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_FD,
+			.max_width     = 9312,
+			.max_height    = 16384,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[9],
+			.num_mid       = 3,
+			.num_wm        = 2,
+			.line_based    = 1,
+			.wm_idx        = {
+				7,
+				8,
+			},
+			.name          = {
+				"FD_Y",
+				"FD_C",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_IR,
+			.max_width     = 9312,
+			.max_height    = 8192,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[10],
+			.num_mid       = 2,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				9,
+			},
+			.name          = {
+				"IR",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AEC_BE,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[11],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				10,
+			},
+			.name          = {
+				"STATS_AEC_BG",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AEC_BHIST,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[12],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				11,
+			},
+			.name          = {
+				"STATS_BHIST",
+			},
+		},
+		{
+			.vfe_out_type  =
+				CAM_VFE_BUS_VER3_VFE_OUT_STATS_TL_BG,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[13],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				12,
+			},
+			.name          = {
+				"STATS_TL_BG",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AWB_BG,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[14],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				13,
+			},
+			.name          = {
+				"STATS_AWB_BG",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_AWB_BFW,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[15],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				14,
+			},
+			.name          = {
+				"AWB_BFW",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_AF_BHIST,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[16],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				15,
+			},
+			.name          = {
+				"AF_BHIST",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_ALSC,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[17],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				16,
+			},
+			.name          = {
+				"ALSC_BG",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BAYER_RS,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[18],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				17,
+			},
+			.name          = {
+				"STATS_RS",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_TMC_BHIST,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.mid           = tfe980_out_port_mid[19],
+			.num_mid       = 3,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				18,
+			},
+			.name          = {
+				"STATS_TMC_BHIST",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_2PD,
+			.max_width     = 14592,
+			.max_height    = 4096,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
+			.mid           = tfe980_out_port_mid[20],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				19,
+			},
+			.name          = {
+				"PDAF_0_2PD",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_PREPROCESS_2PD,
+			.max_width     = 1920,
+			.max_height    = 1080,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
+			.mid           = tfe980_out_port_mid[21],
+			.num_mid       = 2,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				20,
+			},
+			.name          = {
+				"PDAF_1_PREPROCESS_2PD",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_PDAF_PARSED,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
+			.mid           = tfe980_out_port_mid[22],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.wm_idx        = {
+				21,
+			},
+			.name          = {
+				"PDAF_2_PARSED_DATA",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_CAF,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
+			.mid           = tfe980_out_port_mid[23],
+			.num_mid       = 1,
+			.num_wm        = 1,
+			.mc_based      = true,
+			.mc_grp_shift  = 4,
+			.wm_idx        = {
+				22,
+			},
+			.name          = {
+				"STATS_BAF",
+			},
+		},
+	},
+	.num_cons_err = 32,
+	.constraint_error_list = {
+		{
+			.bitmask = BIT(0),
+			.error_description = "PPC 1x1 input Not Supported"
+		},
+		{
+			.bitmask = BIT(1),
+			.error_description = "PPC 1x2 input Not Supported"
+		},
+		{
+			.bitmask = BIT(2),
+			.error_description = "PPC 2x1 input Not Supported"
+		},
+		{
+			.bitmask = BIT(3),
+			.error_description = "PPC 2x2 input Not Supported"
+		},
+		{
+			.bitmask = BIT(4),
+			.error_description = "Pack 8 BPP format Not Supported"
+		},
+		{
+			.bitmask = BIT(5),
+			.error_description = "Pack 16 BPP format Not Supported"
+		},
+		{
+			.bitmask = BIT(6),
+			.error_description = "Pack 24 BPP format Not Supported"
+		},
+		{
+			.bitmask = BIT(7),
+			.error_description = "Pack 32 BPP format Not Supported"
+		},
+		{
+			.bitmask = BIT(8),
+			.error_description = "Pack 64 BPP format Not Supported"
+		},
+		{
+			.bitmask = BIT(9),
+			.error_description = "Pack MIPI 20 format Not Supported"
+		},
+		{
+			.bitmask = BIT(10),
+			.error_description = "Pack MIPI 14 format Not Supported"
+		},
+		{
+			.bitmask = BIT(11),
+			.error_description = "Pack MIPI 12 format Not Supported"
+		},
+		{
+			.bitmask = BIT(12),
+			.error_description = "Pack MIPI 10 format Not Supported"
+		},
+		{
+			.bitmask = BIT(13),
+			.error_description = "Pack 128 BPP format Not Supported"
+		},
+		{
+			.bitmask = BIT(14),
+			.error_description = "UBWC P016 format Not Supported"
+		},
+		{
+			.bitmask = BIT(15),
+			.error_description = "UBWC P010 format Not Supported"
+		},
+		{
+			.bitmask = BIT(16),
+			.error_description = "UBWC NV12 format Not Supported"
+		},
+		{
+			.bitmask = BIT(17),
+			.error_description = "UBWC NV12 4R format Not Supported"
+		},
+		{
+			.bitmask = BIT(18),
+			.error_description = "UBWC TP10 format Not Supported"
+		},
+		{
+			.bitmask = BIT(19),
+			.error_description = "Frame based Mode Not Supported"
+		},
+		{
+			.bitmask = BIT(20),
+			.error_description = "Index based Mode Not Supported"
+		},
+		{
+			.bitmask = BIT(21),
+			.error_description = "FIFO image addr unalign"
+		},
+		{
+			.bitmask = BIT(22),
+			.error_description = "FIFO ubwc addr unalign"
+		},
+		{
+			.bitmask = BIT(23),
+			.error_description = "FIFO framehdr addr unalign"
+		},
+		{
+			.bitmask = BIT(24),
+			.error_description = "Image address unalign"
+		},
+		{
+			.bitmask = BIT(25),
+			.error_description = "UBWC address unalign"
+		},
+		{
+			.bitmask = BIT(26),
+			.error_description = "Frame Header address unalign"
+		},
+		{
+			.bitmask = BIT(27),
+			.error_description = "Stride unalign"
+		},
+		{
+			.bitmask = BIT(28),
+			.error_description = "X Initialization unalign"
+		},
+		{
+			.bitmask = BIT(29),
+			.error_description = "Image Width unalign",
+		},
+		{
+			.bitmask = BIT(30),
+			.error_description = "Image Height unalign",
+		},
+		{
+			.bitmask = BIT(31),
+			.error_description = "Meta Stride unalign",
+		},
+	},
+	.num_comp_grp          = 10,
+	.support_consumed_addr = true,
+	.comp_done_mask = {
+		0x7, BIT(3), 0x70, BIT(7), BIT(8), BIT(16),
+		BIT(17), BIT(18), BIT(19), BIT(20),
+	},
+	.top_irq_shift         = 0,
+	.max_out_res           = CAM_ISP_IFE_OUT_RES_BASE + 42,
+	.pack_align_shift      = 5,
+	.max_bw_counter_limit  = 0xFF,
+};
+
+static struct cam_vfe_irq_hw_info tfe980_irq_hw_info = {
+	.reset_mask    = 0,
+	.supported_irq = CAM_VFE_HW_IRQ_CAP_EXT_CSID,
+	.top_irq_reg   = &tfe980_top_irq_reg_info,
+};
+
+static struct cam_vfe_hw_info cam_tfe980_hw_info = {
+	.irq_hw_info                  = &tfe980_irq_hw_info,
+
+	.bus_version                   = CAM_VFE_BUS_VER_3_0,
+	.bus_hw_info                   = &tfe980_bus_hw_info,
+
+	.top_version                   = CAM_VFE_TOP_VER_4_0,
+	.top_hw_info                   = &tfe980_top_hw_info,
+};
+#endif /* _CAM_TFE980_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -16,11 +16,13 @@
 #include "cam_vfe680_110.h"
 #include "cam_vfe780.h"
 #include "cam_vfe880.h"
+#include "cam_tfe980.h"
 #include "cam_vfe_lite17x.h"
 #include "cam_vfe_lite48x.h"
 #include "cam_vfe_lite68x.h"
 #include "cam_vfe_lite78x.h"
 #include "cam_vfe_lite88x.h"
+#include "cam_vfe_lite98x.h"
 #include "cam_vfe_hw_intf.h"
 #include "cam_vfe_core.h"
 #include "cam_vfe_dev.h"
@@ -71,6 +73,10 @@ static const struct of_device_id cam_vfe_dt_match[] = {
 		.compatible = "qcom,vfe880",
 		.data = &cam_vfe880_hw_info,
 	},
+	{
+		.compatible = "qcom,tfe980",
+		.data  = &cam_tfe980_hw_info,
+	},
 	{
 		.compatible = "qcom,vfe-lite170",
 		.data = &cam_vfe_lite17x_hw_info,
@@ -107,6 +113,10 @@ static const struct of_device_id cam_vfe_dt_match[] = {
 		.compatible = "qcom,vfe-lite880",
 		.data = &cam_vfe_lite88x_hw_info,
 	},
+	{
+		.compatible = "qcom,vfe-lite980",
+		.data = &cam_vfe_lite98x_hw_info,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cam_vfe_dt_match);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 
@@ -397,6 +397,32 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
 	.ubwc_comp_en_bit = BIT(1),
 };
 
+static uint32_t vfe480_out_port_mid[][4] = {
+	{8, 0, 0, 0},
+	{9, 0, 0, 0},
+	{10, 0, 0, 0},
+	{32, 33, 34, 35},
+	{16, 0, 0, 0},
+	{17, 0, 0, 0},
+	{11, 12, 0, 0},
+	{20, 21, 22, 0},
+	{25, 26, 0, 0},
+	{40, 0, 0, 0},
+	{41, 0, 0, 0},
+	{42, 0, 0, 0},
+	{43, 0, 0, 0},
+	{44, 0, 0, 0},
+	{45, 0, 0, 0},
+	{46, 0, 0, 0},
+	{47, 0, 0, 0},
+	{48, 0, 0, 0},
+	{36, 37, 38, 39},
+	{18, 0, 0, 0},
+	{19, 0, 0, 0},
+	{23, 24, 0, 0},
+	{27, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x0000AA00,
@@ -1177,7 +1203,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
-			.mid[0]        = 8,
+			.mid           = vfe480_out_port_mid[0],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				23,
@@ -1191,7 +1218,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
-			.mid[0]        = 9,
+			.mid           = vfe480_out_port_mid[1],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				24,
@@ -1205,7 +1233,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_5,
-			.mid[0]        = 10,
+			.mid           = vfe480_out_port_mid[2],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				25,
@@ -1219,10 +1248,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 4096,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 32,
-			.mid[1]        = 33,
-			.mid[2]        = 34,
-			.mid[3]        = 35,
+			.mid           = vfe480_out_port_mid[3],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				0,
@@ -1238,7 +1265,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 16,
+			.mid           = vfe480_out_port_mid[4],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				2,
@@ -1252,7 +1280,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 17,
+			.mid           = vfe480_out_port_mid[5],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				3,
@@ -1266,8 +1295,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 11,
-			.mid[1]        = 12,
+			.mid           = vfe480_out_port_mid[6],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				10,
@@ -1281,9 +1310,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 20,
-			.mid[1]        = 21,
-			.mid[2]        = 22,
+			.mid           = vfe480_out_port_mid[7],
+			.num_mid       = 3,
 			.num_wm        = 2,
 			.wm_idx        = {
 				8,
@@ -1299,8 +1327,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 25,
-			.mid[1]        = 26,
+			.mid           = vfe480_out_port_mid[8],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				11,
@@ -1314,7 +1342,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 40,
+			.mid           = vfe480_out_port_mid[9],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				12,
@@ -1329,7 +1358,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 41,
+			.mid           = vfe480_out_port_mid[10],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				13,
@@ -1345,7 +1375,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 42,
+			.mid           = vfe480_out_port_mid[11],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				14,
@@ -1359,7 +1390,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 43,
+			.mid           = vfe480_out_port_mid[12],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				20,
@@ -1373,7 +1405,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]         = 44,
+			.mid           = vfe480_out_port_mid[13],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				15,
@@ -1387,7 +1420,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 45,
+			.mid           = vfe480_out_port_mid[14],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				16,
@@ -1401,7 +1435,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 46,
+			.mid           = vfe480_out_port_mid[15],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				17,
@@ -1415,7 +1450,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 47,
+			.mid           = vfe480_out_port_mid[16],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				18,
@@ -1429,7 +1465,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 48,
+			.mid           = vfe480_out_port_mid[17],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				19,
@@ -1443,10 +1480,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 4096,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 36,
-			.mid[1]        = 37,
-			.mid[2]        = 38,
-			.mid[3]        = 39,
+			.mid           = vfe480_out_port_mid[18],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				4,
@@ -1462,7 +1497,9 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 18,
+
+			.mid           = vfe480_out_port_mid[19],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				6,
@@ -1476,7 +1513,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 19,
+			.mid           = vfe480_out_port_mid[20],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				7,
@@ -1490,8 +1528,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 23,
-			.mid[1]        = 24,
+			.mid           = vfe480_out_port_mid[21],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				21,
@@ -1505,7 +1543,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
-			.mid[0]        = 27,
+			.mid           = vfe480_out_port_mid[22],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				22,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_VFE680_H_
@@ -472,6 +472,26 @@ static struct cam_irq_controller_reg_info vfe680_top_irq_reg_info = {
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static uint32_t vfe680_top_debug_reg[] = {
+	0x000000A0,
+	0x000000A4,
+	0x000000A8,
+	0x000000AC,
+	0x000000B0,
+	0x000000B4,
+	0x000000B8,
+	0x000000BC,
+	0x000000C0,
+	0x000000C4,
+	0x000000C8,
+	0x000000CC,
+	0x000000D0,
+	0x000000D4,
+	0x000000D8,
+	0x000000DC,
+	0x000000E0,
+};
+
 static struct cam_vfe_top_ver4_reg_offset_common vfe680_top_common_reg = {
 	.hw_version               = 0x00000000,
 	.hw_capability            = 0x00000004,
@@ -529,25 +549,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe680_top_common_reg = {
 	},
 	.top_debug_cfg            = 0x000000FC,
 	.num_top_debug_reg        = CAM_VFE_680_NUM_DBG_REG,
-	.top_debug = {
-		0x000000A0,
-		0x000000A4,
-		0x000000A8,
-		0x000000AC,
-		0x000000B0,
-		0x000000B4,
-		0x000000B8,
-		0x000000BC,
-		0x000000C0,
-		0x000000C4,
-		0x000000C8,
-		0x000000CC,
-		0x000000D0,
-		0x000000D4,
-		0x000000D8,
-		0x000000DC,
-		0x000000E0,
-	},
+	.top_debug = vfe680_top_debug_reg,
 };
 
 static struct cam_vfe_ver4_path_reg_data vfe_pp_common_reg_data = {
@@ -595,7 +597,7 @@ static struct cam_vfe_ver4_path_reg_data vfe680_pdlib_reg_data = {
 };
 
 struct cam_vfe_ver4_path_hw_info
-	vfe680_rdi_hw_info_arr[CAM_VFE_RDI_VER2_MAX] = {
+	vfe680_rdi_hw_info_arr[] = {
 	{
 		.common_reg     = &vfe680_top_common_reg,
 		.reg_data       = &vfe680_vfe_full_rdi_reg_data[0],
@@ -792,24 +794,23 @@ static struct cam_vfe_top_ver4_hw_info vfe680_top_hw_info = {
 		.common_reg     = &vfe680_top_common_reg,
 		.reg_data       = &vfe680_pdlib_reg_data,
 	},
-	.rdi_hw_info[0] = &vfe680_rdi_hw_info_arr[0],
-	.rdi_hw_info[1] = &vfe680_rdi_hw_info_arr[1],
-	.rdi_hw_info[2] = &vfe680_rdi_hw_info_arr[2],
+	.rdi_hw_info            = vfe680_rdi_hw_info_arr,
 	.wr_client_desc         = vfe680_wr_client_desc,
 	.ipp_module_desc        = vfe680_ipp_mod_desc,
 	.num_mux = 5,
 	.mux_type = {
 		CAM_VFE_CAMIF_VER_4_0,
+		CAM_VFE_PDLIB_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
-		CAM_VFE_PDLIB_VER_1_0,
 	},
 	.num_path_port_map = 2,
 	.path_port_map = {
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_2PD},
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PREPROCESS_2PD}
 	},
+	.num_rdi                         = ARRAY_SIZE(vfe680_rdi_hw_info_arr),
 	.num_top_errors                  = ARRAY_SIZE(vfe680_top_irq_err_desc),
 	.top_err_desc                    = vfe680_top_irq_err_desc,
 	.num_pdaf_violation_errors       = ARRAY_SIZE(vfe680_pdaf_violation_desc),
@@ -886,6 +887,34 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
 	.ubwc_comp_en_bit = BIT(1),
 };
 
+static uint32_t vfe680_out_port_mid[][4] = {
+	{18, 0, 0, 0},
+	{19, 0, 0, 0},
+	{20, 0, 0, 0},
+	{8, 9, 10, 11},
+	{32, 0, 0, 0},
+	{33, 0, 0, 0},
+	{16, 17, 0, 0},
+	{36, 37, 38, 0},
+	{4, 0, 0, 0},
+	{41, 0, 0, 0},
+	{44, 0, 0, 0},
+	{42, 0, 0, 0},
+	{40, 0, 0, 0},
+	{46, 0, 0, 0},
+	{47, 0, 0, 0},
+	{12, 13, 14, 15},
+	{34, 0, 0, 0},
+	{35, 0, 0, 0},
+	{5, 6, 0, 0},
+	{48, 0, 0, 0},
+	{43, 0, 0, 0},
+	{7, 0, 0, 0},
+	{39, 0, 0, 0},
+	{49, 50, 0, 0},
+	{45, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x00000C00,
@@ -1748,7 +1777,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
-			.mid[0]        = 18,
+			.mid           = vfe680_out_port_mid[0],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1763,7 +1793,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
-			.mid[0]        = 19,
+			.mid           = vfe680_out_port_mid[1],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1778,7 +1809,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
-			.mid[0]        = 20,
+			.mid           = vfe680_out_port_mid[2],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1793,10 +1825,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 4096,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 8,
-			.mid[1]        = 9,
-			.mid[2]        = 10,
-			.mid[3]        = 11,
+			.mid           = vfe680_out_port_mid[3],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				0,
@@ -1812,7 +1842,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 32,
+			.mid           = vfe680_out_port_mid[4],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				2,
@@ -1826,7 +1857,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 33,
+			.mid           = vfe680_out_port_mid[5],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				3,
@@ -1840,8 +1872,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 16,
-			.mid[1]        = 17,
+			.mid           = vfe680_out_port_mid[6],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				10,
@@ -1855,9 +1887,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 36,
-			.mid[1]        = 37,
-			.mid[2]        = 38,
+			.mid           = vfe680_out_port_mid[7],
+			.num_mid       = 3,
 			.num_wm        = 2,
 			.wm_idx        = {
 				8,
@@ -1873,7 +1904,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 4,
+			.mid           = vfe680_out_port_mid[8],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				20,
@@ -1888,7 +1920,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 41,
+			.mid           = vfe680_out_port_mid[9],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				13,
@@ -1902,7 +1935,9 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 44,
+
+			.mid           = vfe680_out_port_mid[10],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				16,
@@ -1916,7 +1951,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 42,
+			.mid           = vfe680_out_port_mid[11],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				14,
@@ -1930,7 +1966,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 40,
+			.mid           = vfe680_out_port_mid[12],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				12,
@@ -1944,7 +1981,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 46,
+			.mid           = vfe680_out_port_mid[13],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				18,
@@ -1958,7 +1996,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 47,
+			.mid           = vfe680_out_port_mid[14],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				19,
@@ -1972,10 +2011,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 4096,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 12,
-			.mid[1]        = 13,
-			.mid[2]        = 14,
-			.mid[3]        = 15,
+			.mid           = vfe680_out_port_mid[15],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				4,
@@ -1991,7 +2028,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 34,
+			.mid           = vfe680_out_port_mid[16],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				6,
@@ -2005,7 +2043,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 35,
+			.mid           = vfe680_out_port_mid[17],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				7,
@@ -2019,8 +2058,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 5,
-			.mid[1]        = 6,
+			.mid           = vfe680_out_port_mid[18],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				21,
@@ -2034,7 +2073,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 48,
+			.mid           = vfe680_out_port_mid[19],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				23,
@@ -2048,7 +2088,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 43,
+			.mid           = vfe680_out_port_mid[20],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				15,
@@ -2062,7 +2103,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 7,
+			.mid           = vfe680_out_port_mid[21],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				22,
@@ -2076,7 +2118,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 39,
+			.mid           = vfe680_out_port_mid[22],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				11,
@@ -2090,8 +2133,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 49,
-			.mid[1]        = 50,
+			.mid           = vfe680_out_port_mid[23],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				27,
@@ -2106,7 +2149,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 45,
+			.mid           = vfe680_out_port_mid[24],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				17,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680_110.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_VFE680_110_H_
@@ -12,6 +13,26 @@
 
 #define CAM_VFE_680_110_NUM_DBG_REG              17
 
+static uint32_t vfe680_110_top_debug_reg[] = {
+	0x000000A0,
+	0x000000A4,
+	0x000000A8,
+	0x000000AC,
+	0x000000B0,
+	0x000000B4,
+	0x000000B8,
+	0x000000BC,
+	0x000000C0,
+	0x000000C4,
+	0x000000C8,
+	0x000000CC,
+	0x000000D0,
+	0x000000D4,
+	0x000000D8,
+	0x000000DC,
+	0x000000E0,
+};
+
 static struct cam_vfe_top_ver4_reg_offset_common vfe680_110_top_common_reg = {
 	.hw_version               = 0x00000000,
 	.hw_capability            = 0x00000004,
@@ -50,29 +71,11 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe680_110_top_common_reg = {
 	.bus_overflow_status      = 0x00000C68,
 	.top_debug_cfg            = 0x000000FC,
 	.num_top_debug_reg        = CAM_VFE_680_110_NUM_DBG_REG,
-	.top_debug = {
-		0x000000A0,
-		0x000000A4,
-		0x000000A8,
-		0x000000AC,
-		0x000000B0,
-		0x000000B4,
-		0x000000B8,
-		0x000000BC,
-		0x000000C0,
-		0x000000C4,
-		0x000000C8,
-		0x000000CC,
-		0x000000D0,
-		0x000000D4,
-		0x000000D8,
-		0x000000DC,
-		0x000000E0,
-	},
+	.top_debug = vfe680_110_top_debug_reg,
 };
 
 struct cam_vfe_ver4_path_hw_info
-	vfe680_110_rdi_hw_info_arr[CAM_VFE_RDI_VER2_MAX] = {
+	vfe680_110_rdi_hw_info_arr[] = {
 	{
 		.common_reg     = &vfe680_110_top_common_reg,
 		.reg_data       = &vfe680_vfe_full_rdi_reg_data[0],
@@ -97,24 +100,23 @@ static struct cam_vfe_top_ver4_hw_info vfe680_110_top_hw_info = {
 		.common_reg     = &vfe680_110_top_common_reg,
 		.reg_data       = &vfe680_pdlib_reg_data,
 	},
-	.rdi_hw_info[0] = &vfe680_110_rdi_hw_info_arr[0],
-	.rdi_hw_info[1] = &vfe680_110_rdi_hw_info_arr[1],
-	.rdi_hw_info[2] = &vfe680_110_rdi_hw_info_arr[2],
+	.rdi_hw_info            = vfe680_110_rdi_hw_info_arr,
 	.wr_client_desc         = vfe680_wr_client_desc,
 	.ipp_module_desc        = vfe680_ipp_mod_desc,
 	.num_mux = 5,
 	.mux_type = {
 		CAM_VFE_CAMIF_VER_4_0,
+		CAM_VFE_PDLIB_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
-		CAM_VFE_PDLIB_VER_1_0,
 	},
 	.num_path_port_map = 2,
 	.path_port_map = {
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_2PD},
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PREPROCESS_2PD}
 	},
+	.num_rdi                         = ARRAY_SIZE(vfe680_110_rdi_hw_info_arr),
 	.num_top_errors                  = ARRAY_SIZE(vfe680_top_irq_err_desc),
 	.top_err_desc                    = vfe680_top_irq_err_desc,
 	.num_pdaf_violation_errors       = ARRAY_SIZE(vfe680_pdaf_violation_desc),

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_VFE780_H_
@@ -513,6 +513,26 @@ static struct cam_irq_controller_reg_info vfe780_top_irq_reg_info = {
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static uint32_t vfe780_top_debug_reg[] = {
+	0x000000A0,
+	0x000000A4,
+	0x000000A8,
+	0x000000AC,
+	0x000000B0,
+	0x000000B4,
+	0x000000B8,
+	0x000000BC,
+	0x000000C0,
+	0x000000C4,
+	0x000000C8,
+	0x000000CC,
+	0x000000D0,
+	0x000000D4,
+	0x000000D8,
+	0x000000DC,
+	0x000000E0,
+};
+
 static struct cam_vfe_top_ver4_reg_offset_common vfe780_top_common_reg = {
 	.hw_version               = 0x00000000,
 	.hw_capability            = 0x00000004,
@@ -571,25 +591,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe780_top_common_reg = {
 	.num_top_debug_reg        = CAM_VFE_780_NUM_DBG_REG,
 	.pdaf_input_cfg_0         = 0x00000130,
 	.pdaf_input_cfg_1         = 0x00000134,
-	.top_debug = {
-		0x000000A0,
-		0x000000A4,
-		0x000000A8,
-		0x000000AC,
-		0x000000B0,
-		0x000000B4,
-		0x000000B8,
-		0x000000BC,
-		0x000000C0,
-		0x000000C4,
-		0x000000C8,
-		0x000000CC,
-		0x000000D0,
-		0x000000D4,
-		0x000000D8,
-		0x000000DC,
-		0x000000E0,
-	},
+	.top_debug = vfe780_top_debug_reg,
 };
 
 static struct cam_vfe_ver4_path_reg_data vfe780_pp_common_reg_data = {
@@ -637,7 +639,7 @@ static struct cam_vfe_ver4_path_reg_data vfe780_pdlib_reg_data = {
 };
 
 struct cam_vfe_ver4_path_hw_info
-	vfe780_rdi_hw_info_arr[CAM_VFE_RDI_VER2_MAX] = {
+	vfe780_rdi_hw_info_arr[] = {
 	{
 		.common_reg     = &vfe780_top_common_reg,
 		.reg_data       = &vfe780_vfe_full_rdi_reg_data[0],
@@ -835,18 +837,16 @@ static struct cam_vfe_top_ver4_hw_info vfe780_top_hw_info = {
 		.common_reg     = &vfe780_top_common_reg,
 		.reg_data       = &vfe780_pdlib_reg_data,
 	},
-	.rdi_hw_info[0] = &vfe780_rdi_hw_info_arr[0],
-	.rdi_hw_info[1] = &vfe780_rdi_hw_info_arr[1],
-	.rdi_hw_info[2] = &vfe780_rdi_hw_info_arr[2],
+	.rdi_hw_info            = vfe780_rdi_hw_info_arr,
 	.wr_client_desc         = vfe780_wr_client_desc,
 	.ipp_module_desc        = vfe780_ipp_mod_desc,
 	.num_mux = 5,
 	.mux_type = {
 		CAM_VFE_CAMIF_VER_4_0,
+		CAM_VFE_PDLIB_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
-		CAM_VFE_PDLIB_VER_1_0,
 	},
 	.num_path_port_map = 3,
 	.path_port_map = {
@@ -854,6 +854,7 @@ static struct cam_vfe_top_ver4_hw_info vfe780_top_hw_info = {
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PREPROCESS_2PD},
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PDAF_PARSED_DATA},
 	},
+	.num_rdi                         = ARRAY_SIZE(vfe780_rdi_hw_info_arr),
 	.num_top_errors                  = ARRAY_SIZE(vfe780_top_irq_err_desc),
 	.top_err_desc                    = vfe780_top_irq_err_desc,
 	.num_pdaf_violation_errors       = ARRAY_SIZE(vfe780_pdaf_violation_desc),
@@ -932,6 +933,33 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
 	.ubwc_comp_en_bit = BIT(1),
 };
 
+static uint32_t vfe780_out_port_mid[][4] = {
+	{34, 0, 0, 0},
+	{35, 0, 0, 0},
+	{36, 0, 0, 0},
+	{16, 17, 18, 19},
+	{20, 0, 0, 0},
+	{21, 0, 0, 0},
+	{32, 33, 0, 0},
+	{28, 29, 30},
+	{8, 0, 0, 0},
+	{18, 0, 0, 0},
+	{21, 0, 0, 0},
+	{19, 0, 0, 0},
+	{17, 0, 0, 0},
+	{23, 0, 0, 0},
+	{24, 0, 0, 0},
+	{22, 23, 24, 25},
+	{26, 0, 0, 0},
+	{27, 0, 0, 0},
+	{9, 0, 0, 0},
+	{20, 0, 0, 0},
+	{10, 0, 0, 0},
+	{16, 0, 0, 0},
+	{25, 26, 0, 0},
+	{22, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x00000C00,
@@ -1794,7 +1822,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 16384,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
-			.mid[0]        = 34,
+			.mid           = vfe780_out_port_mid[0],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1809,7 +1838,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 16384,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
-			.mid[0]        = 35,
+			.mid           = vfe780_out_port_mid[1],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1824,7 +1854,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 16384,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
-			.mid[0]        = 36,
+			.mid           = vfe780_out_port_mid[2],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1839,10 +1870,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 4928,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 16,
-			.mid[1]        = 17,
-			.mid[2]        = 18,
-			.mid[3]        = 19,
+			.mid           = vfe780_out_port_mid[3],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				0,
@@ -1858,7 +1887,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 1696,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 20,
+			.mid           = vfe780_out_port_mid[4],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				2,
@@ -1872,7 +1902,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 424,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 21,
+			.mid           = vfe780_out_port_mid[5],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				3,
@@ -1886,8 +1917,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 7296,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 32,
-			.mid[1]        = 33,
+			.mid           = vfe780_out_port_mid[6],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				10,
@@ -1901,9 +1932,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 2304,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 28,
-			.mid[1]        = 29,
-			.mid[2]        = 30,
+			.mid           = vfe780_out_port_mid[7],
+			.num_mid       = 3,
 			.num_wm        = 2,
 			.wm_idx        = {
 				8,
@@ -1919,7 +1949,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 14592,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 8,
+			.mid           = vfe780_out_port_mid[8],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				20,
@@ -1934,7 +1965,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 18,
+			.mid           = vfe780_out_port_mid[9],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				13,
@@ -1948,7 +1980,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 21,
+			.mid           = vfe780_out_port_mid[10],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				16,
@@ -1962,7 +1995,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 19,
+			.mid           = vfe780_out_port_mid[11],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				14,
@@ -1976,7 +2010,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 17,
+			.mid           = vfe780_out_port_mid[12],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				12,
@@ -1990,7 +2025,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 23,
+			.mid           = vfe780_out_port_mid[13],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				18,
@@ -2004,7 +2040,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 24,
+			.mid           = vfe780_out_port_mid[14],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				19,
@@ -2018,10 +2055,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 4928,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 22,
-			.mid[1]        = 23,
-			.mid[2]        = 24,
-			.mid[3]        = 25,
+			.mid           = vfe780_out_port_mid[15],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				4,
@@ -2037,7 +2072,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 1232,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 26,
+			.mid           = vfe780_out_port_mid[16],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				6,
@@ -2051,7 +2087,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 308,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 27,
+			.mid           = vfe780_out_port_mid[17],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				7,
@@ -2065,7 +2102,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 9,
+			.mid           = vfe780_out_port_mid[18],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				21,
@@ -2079,7 +2117,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 20,
+			.mid           = vfe780_out_port_mid[19],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				15,
@@ -2093,7 +2132,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 10,
+			.mid           = vfe780_out_port_mid[20],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				22,
@@ -2107,7 +2147,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 16,
+			.mid           = vfe780_out_port_mid[21],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				11,
@@ -2121,8 +2162,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 25,
-			.mid[1]        = 26,
+			.mid           = vfe780_out_port_mid[22],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				26,
@@ -2137,7 +2178,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe780_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 22,
+			.mid           = vfe780_out_port_mid[23],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				17,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe880.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_VFE880_H_
@@ -533,6 +533,28 @@ static struct cam_irq_controller_reg_info vfe880_top_irq_reg_info = {
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static uint32_t vfe880_top_debug_reg[] = {
+	0x000000A0,
+	0x000000A4,
+	0x000000A8,
+	0x000000AC,
+	0x000000B0,
+	0x000000B4,
+	0x000000B8,
+	0x000000BC,
+	0x000000C0,
+	0x000000C4,
+	0x000000C8,
+	0x000000CC,
+	0x000000D0,
+	0x000000D4,
+	0x000000D8,
+	0x000000DC,
+	0x000000E0,
+	0x000000E4,
+	0x000000E8,
+};
+
 static struct cam_vfe_top_ver4_reg_offset_common vfe880_top_common_reg = {
 	.hw_version               = 0x00000000,
 	.hw_capability            = 0x00000004,
@@ -591,27 +613,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe880_top_common_reg = {
 	.num_top_debug_reg        = CAM_VFE_880_NUM_DBG_REG,
 	.pdaf_input_cfg_0         = 0x00000130,
 	.pdaf_input_cfg_1         = 0x00000134,
-	.top_debug = {
-		0x000000A0,
-		0x000000A4,
-		0x000000A8,
-		0x000000AC,
-		0x000000B0,
-		0x000000B4,
-		0x000000B8,
-		0x000000BC,
-		0x000000C0,
-		0x000000C4,
-		0x000000C8,
-		0x000000CC,
-		0x000000D0,
-		0x000000D4,
-		0x000000D8,
-		0x000000DC,
-		0x000000E0,
-		0x000000E4,
-		0x000000E8,
-	},
+	.top_debug = vfe880_top_debug_reg,
 };
 
 static struct cam_vfe_ver4_path_reg_data vfe880_pp_common_reg_data = {
@@ -659,7 +661,7 @@ static struct cam_vfe_ver4_path_reg_data vfe880_pdlib_reg_data = {
 };
 
 struct cam_vfe_ver4_path_hw_info
-	vfe880_rdi_hw_info_arr[CAM_VFE_RDI_VER2_MAX] = {
+	vfe880_rdi_hw_info_arr[] = {
 	{
 		.common_reg     = &vfe880_top_common_reg,
 		.reg_data       = &vfe880_vfe_full_rdi_reg_data[0],
@@ -879,18 +881,16 @@ static struct cam_vfe_top_ver4_hw_info vfe880_top_hw_info = {
 		.common_reg     = &vfe880_top_common_reg,
 		.reg_data       = &vfe880_pdlib_reg_data,
 	},
-	.rdi_hw_info[0] = &vfe880_rdi_hw_info_arr[0],
-	.rdi_hw_info[1] = &vfe880_rdi_hw_info_arr[1],
-	.rdi_hw_info[2] = &vfe880_rdi_hw_info_arr[2],
+	.rdi_hw_info            = vfe880_rdi_hw_info_arr,
 	.wr_client_desc         = vfe880_wr_client_desc,
 	.ipp_module_desc        = vfe880_ipp_mod_desc,
 	.num_mux = 5,
 	.mux_type = {
 		CAM_VFE_CAMIF_VER_4_0,
+		CAM_VFE_PDLIB_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
-		CAM_VFE_PDLIB_VER_1_0,
 	},
 	.num_path_port_map = 3,
 	.path_port_map = {
@@ -898,6 +898,7 @@ static struct cam_vfe_top_ver4_hw_info vfe880_top_hw_info = {
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PREPROCESS_2PD},
 		{CAM_ISP_HW_VFE_IN_PDLIB, CAM_ISP_IFE_OUT_RES_PDAF_PARSED_DATA},
 	},
+	.num_rdi                         = ARRAY_SIZE(vfe880_rdi_hw_info_arr),
 	.num_top_errors                  = ARRAY_SIZE(vfe880_top_irq_err_desc),
 	.top_err_desc                    = vfe880_top_irq_err_desc,
 	.num_pdaf_violation_errors       = ARRAY_SIZE(vfe880_pdaf_violation_desc),
@@ -976,6 +977,34 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
 	.ubwc_comp_en_bit = BIT(1),
 };
 
+static uint32_t vfe880_out_port_mid[][4] = {
+	{34, 0, 0, 0},
+	{35, 0, 0, 0},
+	{36, 0, 0, 0},
+	{16, 17, 18, 19},
+	{20, 0, 0, 0},
+	{21, 0, 0, 0},
+	{32, 33, 0, 0},
+	{28, 29, 30, 0},
+	{8, 0, 0, 0},
+	{18, 0, 0, 0},
+	{21, 0, 0, 0},
+	{19, 0, 0, 0},
+	{17, 0, 0, 0},
+	{23, 0, 0, 0},
+	{24, 0, 0, 0},
+	{22, 23, 24, 25},
+	{26, 0, 0, 0},
+	{27, 0, 0, 0},
+	{9, 0, 0, 0},
+	{20, 0, 0, 0},
+	{10, 0, 0, 0},
+	{16, 0, 0, 0},
+	{25, 26, 0, 0},
+	{22, 0, 0, 0},
+	{30, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x00000C00,
@@ -1869,7 +1898,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 16384,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
-			.mid[0]        = 34,
+			.mid           = vfe880_out_port_mid[0],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1884,7 +1914,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 16384,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
-			.mid[0]        = 35,
+			.mid           = vfe880_out_port_mid[1],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1899,7 +1930,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 16384,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
-			.mid[0]        = 36,
+			.mid           = vfe880_out_port_mid[2],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.line_based    = 1,
 			.wm_idx        = {
@@ -1914,10 +1946,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 4928,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 16,
-			.mid[1]        = 17,
-			.mid[2]        = 18,
-			.mid[3]        = 19,
+			.mid           = vfe880_out_port_mid[3],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				0,
@@ -1933,7 +1963,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 1696,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 20,
+			.mid           = vfe880_out_port_mid[4],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				2,
@@ -1947,7 +1978,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 424,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 21,
+			.mid           = vfe880_out_port_mid[5],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				3,
@@ -1961,8 +1993,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 7296,
 			.max_height    = 16384,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 32,
-			.mid[1]        = 33,
+			.mid           = vfe880_out_port_mid[6],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				10,
@@ -1976,9 +2008,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 2304,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 28,
-			.mid[1]        = 29,
-			.mid[2]        = 30,
+			.mid           = vfe880_out_port_mid[7],
+			.num_mid       = 3,
 			.num_wm        = 2,
 			.wm_idx        = {
 				8,
@@ -1994,7 +2025,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 14592,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 8,
+			.mid           = vfe880_out_port_mid[8],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				20,
@@ -2009,7 +2041,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 18,
+			.mid           = vfe880_out_port_mid[9],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				13,
@@ -2023,7 +2056,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 21,
+			.mid           = vfe880_out_port_mid[10],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				16,
@@ -2037,7 +2071,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 19,
+			.mid           = vfe880_out_port_mid[11],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				14,
@@ -2051,7 +2086,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 17,
+			.mid           = vfe880_out_port_mid[12],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				12,
@@ -2065,7 +2101,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 23,
+			.mid           = vfe880_out_port_mid[13],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				18,
@@ -2079,7 +2116,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 24,
+			.mid           = vfe880_out_port_mid[14],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				19,
@@ -2093,10 +2131,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 4928,
 			.max_height    = 4096,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 22,
-			.mid[1]        = 23,
-			.mid[2]        = 24,
-			.mid[3]        = 25,
+			.mid           = vfe880_out_port_mid[15],
+			.num_mid       = 4,
 			.num_wm        = 2,
 			.wm_idx        = {
 				4,
@@ -2112,7 +2148,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 1232,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 26,
+			.mid           = vfe880_out_port_mid[16],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				6,
@@ -2126,7 +2163,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 308,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 27,
+			.mid           = vfe880_out_port_mid[17],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				7,
@@ -2140,7 +2178,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = 1920,
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 9,
+			.mid           = vfe880_out_port_mid[18],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				21,
@@ -2154,7 +2193,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 20,
+			.mid           = vfe880_out_port_mid[19],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				15,
@@ -2168,7 +2208,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 10,
+			.mid           = vfe880_out_port_mid[20],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				22,
@@ -2182,7 +2223,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 16,
+			.mid           = vfe880_out_port_mid[21],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				11,
@@ -2196,8 +2238,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 25,
-			.mid[1]        = 26,
+			.mid           = vfe880_out_port_mid[22],
+			.num_mid       = 2,
 			.num_wm        = 1,
 			.wm_idx        = {
 				26,
@@ -2212,7 +2254,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 22,
+			.mid           = vfe880_out_port_mid[23],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				17,
@@ -2227,7 +2270,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe880_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 30,
+			.mid           = vfe880_out_port_mid[24],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				27,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite48x.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_VFE_LITE48x_H_
@@ -223,6 +223,13 @@ static struct cam_irq_register_set vfe48x_bus_irq_reg[2] = {
 	},
 };
 
+static uint32_t vfe48x_out_port_mid[][4] = {
+	{16, 0, 0, 0},
+	{17, 0, 0, 0},
+	{18, 0, 0, 0},
+	{19, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe48x_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x00001A00,
@@ -375,7 +382,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe48x_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
-			.mid[0]        = 16,
+			.mid           = vfe48x_out_port_mid[0],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				0,
@@ -389,7 +397,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe48x_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
-			.mid[0]        = 17,
+			.mid           = vfe48x_out_port_mid[1],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				1,
@@ -403,7 +412,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe48x_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
-			.mid[0]        = 18,
+			.mid           = vfe48x_out_port_mid[2],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				2,
@@ -417,7 +427,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe48x_bus_hw_info = {
 			.max_width     = -1,
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
-			.mid[0]        = 19,
+			.mid           = vfe48x_out_port_mid[3],
+			.num_mid       = 1,
 			.num_wm        = 1,
 			.wm_idx        = {
 				3,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite68x.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.​
  */
 
 
@@ -82,6 +82,14 @@ static struct cam_irq_controller_reg_info vfe68x_top_irq_reg_info = {
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static uint32_t vfe68x_top_debug_reg[] = {
+	0x0000105C,
+	0x00001060,
+	0x00001064,
+	0x00001068,
+	0x0000106C,
+};
+
 static struct cam_vfe_top_ver4_reg_offset_common vfe68x_top_common_reg = {
 	.hw_version               = 0x00001000,
 	.hw_capability            = 0x00001004,
@@ -96,13 +104,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe68x_top_common_reg = {
 	.bus_overflow_status      = 0x00001268,
 	.top_debug_cfg            = 0x00001074,
 	.num_top_debug_reg        = CAM_VFE_68X_NUM_DBG_REG,
-	.top_debug                = {
-		0x0000105C,
-		0x00001060,
-		0x00001064,
-		0x00001068,
-		0x0000106C,
-	},
+	.top_debug                = vfe68x_top_debug_reg,
 };
 
 static struct cam_vfe_ver4_path_reg_data vfe68x_ipp_reg_data =
@@ -148,7 +150,7 @@ static struct cam_vfe_ver4_path_reg_data vfe68x_rdi_reg_data[4] = {
 };
 
 static struct cam_vfe_ver4_path_hw_info
-	vfe68x_rdi_hw_info[CAM_VFE_RDI_VER2_MAX] = {
+	vfe68x_rdi_hw_info[] = {
 	{
 		.common_reg     = &vfe68x_top_common_reg,
 		.reg_data       = &vfe68x_rdi_reg_data[0],
@@ -222,10 +224,7 @@ static struct cam_vfe_top_ver4_debug_reg_info vfe68x_dbg_reg_info[CAM_VFE_68X_NU
 
 static struct cam_vfe_top_ver4_hw_info vfe68x_top_hw_info = {
 	.common_reg = &vfe68x_top_common_reg,
-	.rdi_hw_info[0] = &vfe68x_rdi_hw_info[0],
-	.rdi_hw_info[1] = &vfe68x_rdi_hw_info[1],
-	.rdi_hw_info[2] = &vfe68x_rdi_hw_info[2],
-	.rdi_hw_info[3] = &vfe68x_rdi_hw_info[3],
+	.rdi_hw_info =   vfe68x_rdi_hw_info,
 	.vfe_full_hw_info = {
 		.common_reg     = &vfe68x_top_common_reg,
 		.reg_data       = &vfe68x_ipp_reg_data,
@@ -240,6 +239,7 @@ static struct cam_vfe_top_ver4_hw_info vfe68x_top_hw_info = {
 		CAM_VFE_RDI_VER_1_0,
 		CAM_VFE_RDI_VER_1_0,
 	},
+	.num_rdi        = ARRAY_SIZE(vfe68x_rdi_hw_info),
 	.debug_reg_info = &vfe68x_dbg_reg_info,
 };
 
@@ -256,6 +256,15 @@ static struct cam_irq_register_set vfe680x_bus_irq_reg[2] = {
 		},
 };
 
+static uint32_t vfe680x_out_port_mid[][4] = {
+	{8, 0, 0, 0},
+	{9, 0, 0, 0},
+	{10, 0, 0, 0},
+	{11, 0, 0, 0},
+	{12, 0, 0, 0},
+	{13, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x00001200,
@@ -467,7 +476,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
 			.num_wm        = 1,
-			.mid[0]        = 8,
+			.mid           = vfe680x_out_port_mid[0],
+			.num_mid       = 1,
 			.line_based    = 1,
 			.wm_idx        = {
 				0,
@@ -482,7 +492,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
 			.num_wm        = 1,
-			.mid[0]        = 9,
+			.mid           = vfe680x_out_port_mid[1],
+			.num_mid       = 1,
 			.line_based    = 1,
 			.wm_idx        = {
 				1,
@@ -497,7 +508,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
 			.num_wm        = 1,
-			.mid[0]        = 10,
+			.mid           = vfe680x_out_port_mid[2],
+			.num_mid       = 1,
 			.line_based    = 1,
 			.wm_idx        = {
 				2,
@@ -512,7 +524,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
 			.num_wm        = 1,
-			.mid[0]        = 11,
+			.mid           = vfe680x_out_port_mid[3],
+			.num_mid       = 1,
 			.line_based    = 1,
 			.wm_idx        = {
 				3,
@@ -528,7 +541,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
 			.num_wm        = 1,
-			.mid[0]        = 12,
+			.mid           = vfe680x_out_port_mid[4],
+			.num_mid       = 1,
 			.wm_idx        = {
 				4,
 			},
@@ -542,7 +556,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe680x_bus_hw_info = {
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
 			.num_wm        = 1,
-			.mid[0]        = 13,
+			.mid           = vfe680x_out_port_mid[5],
+			.num_mid       = 1,
 			.wm_idx        = {
 				5,
 			},

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite78x.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 
@@ -82,6 +82,14 @@ static struct cam_irq_controller_reg_info vfe_lite78x_top_irq_reg_info = {
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static uint32_t vfe_lite78x_top_debug_reg[] = {
+	0x0000105C,
+	0x00001060,
+	0x00001064,
+	0x00001068,
+	0x0000106C,
+};
+
 static struct cam_vfe_top_ver4_reg_offset_common vfe_lite78x_top_common_reg = {
 	.hw_version               = 0x00001000,
 	.hw_capability            = 0x00001004,
@@ -96,13 +104,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe_lite78x_top_common_reg = {
 	.bus_overflow_status      = 0x00001268,
 	.top_debug_cfg            = 0x00001074,
 	.num_top_debug_reg        = CAM_VFE_78X_NUM_DBG_REG,
-	.top_debug                = {
-		0x0000105C,
-		0x00001060,
-		0x00001064,
-		0x00001068,
-		0x0000106C,
-	},
+	.top_debug                = vfe_lite78x_top_debug_reg,
 };
 
 static struct cam_vfe_ver4_path_reg_data vfe_lite78x_ipp_reg_data =
@@ -148,7 +150,7 @@ static struct cam_vfe_ver4_path_reg_data vfe_lite78x_rdi_reg_data[4] = {
 };
 
 static struct cam_vfe_ver4_path_hw_info
-	vfe_lite78x_rdi_hw_info[CAM_VFE_RDI_VER2_MAX] = {
+	vfe_lite78x_rdi_hw_info[] = {
 	{
 		.common_reg     = &vfe_lite78x_top_common_reg,
 		.reg_data       = &vfe_lite78x_rdi_reg_data[0],
@@ -222,10 +224,7 @@ static struct cam_vfe_top_ver4_debug_reg_info vfe78x_dbg_reg_info[CAM_VFE_78X_NU
 
 static struct cam_vfe_top_ver4_hw_info vfe_lite78x_top_hw_info = {
 	.common_reg = &vfe_lite78x_top_common_reg,
-	.rdi_hw_info[0] = &vfe_lite78x_rdi_hw_info[0],
-	.rdi_hw_info[1] = &vfe_lite78x_rdi_hw_info[1],
-	.rdi_hw_info[2] = &vfe_lite78x_rdi_hw_info[2],
-	.rdi_hw_info[3] = &vfe_lite78x_rdi_hw_info[3],
+	.rdi_hw_info = vfe_lite78x_rdi_hw_info,
 	.vfe_full_hw_info = {
 		.common_reg     = &vfe_lite78x_top_common_reg,
 		.reg_data       = &vfe_lite78x_ipp_reg_data,
@@ -241,6 +240,7 @@ static struct cam_vfe_top_ver4_hw_info vfe_lite78x_top_hw_info = {
 		CAM_VFE_RDI_VER_1_0,
 	},
 	.debug_reg_info = &vfe78x_dbg_reg_info,
+	.num_rdi        = ARRAY_SIZE(vfe_lite78x_rdi_hw_info),
 };
 
 static struct cam_irq_register_set vfe_lite78x_bus_irq_reg[1] = {
@@ -251,6 +251,15 @@ static struct cam_irq_register_set vfe_lite78x_bus_irq_reg[1] = {
 	},
 };
 
+static uint32_t vfe_lite78x_out_port_mid[][4] = {
+	{8, 0, 0, 0},
+	{9, 0, 0, 0},
+	{10, 0, 0, 0},
+	{11, 0, 0, 0},
+	{12, 0, 0, 0},
+	{13, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe_lite78x_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x00001200,
@@ -463,7 +472,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite78x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 8,
+			.mid           = vfe_lite78x_out_port_mid[0],
+			.num_mid       = 1,
 			.wm_idx        = {
 				0,
 			},
@@ -478,7 +488,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite78x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 9,
+			.mid           = vfe_lite78x_out_port_mid[1],
+			.num_mid       = 1,
 			.wm_idx        = {
 				1,
 			},
@@ -493,7 +504,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite78x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 10,
+			.mid           = vfe_lite78x_out_port_mid[2],
+			.num_mid       = 1,
 			.wm_idx        = {
 				2,
 			},
@@ -508,7 +520,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite78x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 11,
+			.mid           = vfe_lite78x_out_port_mid[3],
+			.num_mid       = 1,
 			.wm_idx        = {
 				3,
 			},
@@ -523,7 +536,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite78x_bus_hw_info = {
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
 			.num_wm        = 1,
-			.mid[0]        = 12,
+			.mid           = vfe_lite78x_out_port_mid[4],
+			.num_mid       = 1,
 			.wm_idx        = {
 				4,
 			},
@@ -537,7 +551,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite78x_bus_hw_info = {
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
 			.num_wm        = 1,
-			.mid[0]        = 13,
+			.mid           = vfe_lite78x_out_port_mid[5],
+			.num_mid       = 1,
 			.wm_idx        = {
 				5,
 			},

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite88x.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 
@@ -43,6 +43,14 @@ static struct cam_irq_controller_reg_info vfe_lite88x_top_irq_reg_info = {
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static uint32_t vfe_lite88x_top_debug_reg[] = {
+	0x0000105C,
+	0x00001060,
+	0x00001064,
+	0x00001068,
+	0x0000106C,
+};
+
 static struct cam_vfe_top_ver4_reg_offset_common vfe_lite88x_top_common_reg = {
 	.hw_version               = 0x00001000,
 	.hw_capability            = 0x00001004,
@@ -57,13 +65,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe_lite88x_top_common_reg = {
 	.bus_overflow_status      = 0x00001268,
 	.top_debug_cfg            = 0x00001074,
 	.num_top_debug_reg        = CAM_VFE_88X_NUM_DBG_REG,
-	.top_debug                = {
-		0x0000105C,
-		0x00001060,
-		0x00001064,
-		0x00001068,
-		0x0000106C,
-	},
+	.top_debug                = vfe_lite88x_top_debug_reg,
 };
 
 static struct cam_vfe_ver4_path_reg_data vfe_lite88x_ipp_reg_data = {
@@ -108,7 +110,7 @@ static struct cam_vfe_ver4_path_reg_data vfe_lite88x_rdi_reg_data[4] = {
 };
 
 static struct cam_vfe_ver4_path_hw_info
-	vfe_lite88x_rdi_hw_info[CAM_VFE_RDI_VER2_MAX] = {
+	vfe_lite88x_rdi_hw_info[] = {
 	{
 		.common_reg     = &vfe_lite88x_top_common_reg,
 		.reg_data       = &vfe_lite88x_rdi_reg_data[0],
@@ -129,10 +131,7 @@ static struct cam_vfe_ver4_path_hw_info
 
 static struct cam_vfe_top_ver4_hw_info vfe_lite88x_top_hw_info = {
 	.common_reg = &vfe_lite88x_top_common_reg,
-	.rdi_hw_info[0] = &vfe_lite88x_rdi_hw_info[0],
-	.rdi_hw_info[1] = &vfe_lite88x_rdi_hw_info[1],
-	.rdi_hw_info[2] = &vfe_lite88x_rdi_hw_info[2],
-	.rdi_hw_info[3] = &vfe_lite88x_rdi_hw_info[3],
+	.rdi_hw_info = vfe_lite88x_rdi_hw_info,
 	.vfe_full_hw_info = {
 		.common_reg     = &vfe_lite88x_top_common_reg,
 		.reg_data       = &vfe_lite88x_ipp_reg_data,
@@ -148,6 +147,7 @@ static struct cam_vfe_top_ver4_hw_info vfe_lite88x_top_hw_info = {
 		CAM_VFE_RDI_VER_1_0,
 	},
 	.debug_reg_info = &vfe78x_dbg_reg_info,
+	.num_rdi        = ARRAY_SIZE(vfe_lite88x_rdi_hw_info),
 };
 
 static struct cam_irq_register_set vfe_lite88x_bus_irq_reg[1] = {
@@ -158,6 +158,15 @@ static struct cam_irq_register_set vfe_lite88x_bus_irq_reg[1] = {
 	},
 };
 
+static uint32_t vfe_lite88x_out_port_mid[][4] = {
+	{8, 0, 0, 0},
+	{9, 0, 0, 0},
+	{10, 0, 0, 0},
+	{11, 0, 0, 0},
+	{12, 0, 0, 0},
+	{13, 0, 0, 0},
+};
+
 static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
 	.common_reg = {
 		.hw_version                       = 0x00001200,
@@ -370,7 +379,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 8,
+			.mid           = vfe_lite88x_out_port_mid[0],
+			.num_mid       = 1,
 			.wm_idx        = {
 				0,
 			},
@@ -385,7 +395,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 9,
+			.mid           = vfe_lite88x_out_port_mid[1],
+			.num_mid       = 1,
 			.wm_idx        = {
 				1,
 			},
@@ -400,7 +411,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 10,
+			.mid           = vfe_lite88x_out_port_mid[2],
+			.num_mid       = 1,
 			.wm_idx        = {
 				2,
 			},
@@ -415,7 +427,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
 			.num_wm        = 1,
 			.line_based    = 1,
-			.mid[0]        = 11,
+			.mid           = vfe_lite88x_out_port_mid[3],
+			.num_mid       = 1,
 			.wm_idx        = {
 				3,
 			},
@@ -430,7 +443,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
 			.max_height    = 1080,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
 			.num_wm        = 1,
-			.mid[0]        = 12,
+			.mid           = vfe_lite88x_out_port_mid[4],
+			.num_mid       = 1,
 			.wm_idx        = {
 				4,
 			},
@@ -444,7 +458,8 @@ static struct cam_vfe_bus_ver3_hw_info vfe_lite88x_bus_hw_info = {
 			.max_height    = -1,
 			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
 			.num_wm        = 1,
-			.mid[0]        = 13,
+			.mid           = vfe_lite88x_out_port_mid[5],
+			.num_mid       = 1,
 			.wm_idx        = {
 				5,
 			},

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite98x.h

@@ -0,0 +1,495 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+
+#ifndef _CAM_VFE_LITE98X_H_
+#define _CAM_VFE_LITE98X_H_
+#include "cam_vfe_camif_ver3.h"
+#include "cam_vfe_top_ver4.h"
+#include "cam_vfe_core.h"
+#include "cam_vfe_bus_ver3.h"
+#include "cam_irq_controller.h"
+#include "cam_vfe_lite78x.h"
+
+#define CAM_VFE_98X_NUM_DBG_REG 5
+
+/* Offsets might not match due to csid secure regs at beginning of reg space */
+
+static struct cam_irq_register_set vfe_lite98x_top_irq_reg_set[2] = {
+	{
+		.mask_reg_offset   = 0x00001024,
+		.clear_reg_offset  = 0x0000102C,
+		.status_reg_offset = 0x0000101C,
+		.set_reg_offset    = 0x00001034,
+		.test_set_val      = BIT(0),
+		.test_sub_val      = BIT(0),
+	},
+	{
+		.mask_reg_offset   = 0x00001028,
+		.clear_reg_offset  = 0x00001030,
+		.status_reg_offset = 0x00001020,
+	},
+};
+
+static struct cam_irq_controller_reg_info vfe_lite98x_top_irq_reg_info = {
+	.num_registers = 2,
+	.irq_reg_set = vfe_lite98x_top_irq_reg_set,
+	.global_irq_cmd_offset = 0x00001038,
+	.global_clear_bitmask  = 0x00000001,
+	.global_set_bitmask    = 0x00000010,
+	.clear_all_bitmask     = 0xFFFFFFFF,
+};
+
+static uint32_t vfe_lite98x_top_debug_reg[] = {
+	0x0000105C,
+	0x00001060,
+	0x00001064,
+	0x00001068,
+	0x0000106C,
+};
+
+static struct cam_vfe_top_ver4_reg_offset_common vfe_lite98x_top_common_reg = {
+	.hw_version               = 0x00001000,
+	.hw_capability            = 0x00001004,
+	.core_cgc_ovd_0           = 0x00001014,
+	.ahb_cgc_ovd              = 0x00001018,
+	.core_cfg_0               = 0x0000103C,
+	.diag_config              = 0x00001040,
+	.diag_sensor_status_0     = 0x00001044,
+	.diag_sensor_status_1     = 0x00001048,
+	.ipp_violation_status     = 0x00001054,
+	.bus_violation_status     = 0x00001264,
+	.bus_overflow_status      = 0x00001268,
+	.top_debug_cfg            = 0x00001074,
+	.num_top_debug_reg        = CAM_VFE_98X_NUM_DBG_REG,
+	.top_debug                = vfe_lite98x_top_debug_reg,
+};
+
+static struct cam_vfe_ver4_path_reg_data vfe_lite98x_ipp_reg_data = {
+	.sof_irq_mask                    = 0x1,
+	.eof_irq_mask                    = 0x2,
+	.error_irq_mask                  = 0x2,
+	.enable_diagnostic_hw            = 0x1,
+	.top_debug_cfg_en                = 0x3,
+	.ipp_violation_mask              = 0x10,
+};
+
+static struct cam_vfe_ver4_path_reg_data vfe_lite98x_rdi_reg_data[4] = {
+
+	{
+		.sof_irq_mask                    = 0x4,
+		.eof_irq_mask                    = 0x8,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 0x3,
+	},
+	{
+		.sof_irq_mask                    = 0x10,
+		.eof_irq_mask                    = 0x20,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 0x3,
+	},
+	{
+		.sof_irq_mask                    = 0x40,
+		.eof_irq_mask                    = 0x80,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 0x3,
+	},
+	{
+		.sof_irq_mask                    = 0x100,
+		.eof_irq_mask                    = 0x200,
+		.error_irq_mask                  = 0x0,
+		.enable_diagnostic_hw            = 0x1,
+		.top_debug_cfg_en                = 0x3,
+	},
+};
+
+static struct cam_vfe_ver4_path_hw_info
+	vfe_lite98x_rdi_hw_info[] = {
+	{
+		.common_reg     = &vfe_lite98x_top_common_reg,
+		.reg_data       = &vfe_lite98x_rdi_reg_data[0],
+	},
+	{
+		.common_reg     = &vfe_lite98x_top_common_reg,
+		.reg_data       = &vfe_lite98x_rdi_reg_data[1],
+	},
+	{
+		.common_reg     = &vfe_lite98x_top_common_reg,
+		.reg_data       = &vfe_lite98x_rdi_reg_data[2],
+	},
+	{
+		.common_reg     = &vfe_lite98x_top_common_reg,
+		.reg_data       = &vfe_lite98x_rdi_reg_data[3],
+	},
+};
+
+static struct cam_vfe_top_ver4_hw_info vfe_lite98x_top_hw_info = {
+	.common_reg = &vfe_lite98x_top_common_reg,
+	.rdi_hw_info = vfe_lite98x_rdi_hw_info,
+	.vfe_full_hw_info = {
+		.common_reg     = &vfe_lite98x_top_common_reg,
+		.reg_data       = &vfe_lite98x_ipp_reg_data,
+	},
+	.ipp_module_desc        = vfe_lite78x_ipp_mod_desc,
+	.wr_client_desc         = vfe_lite78x_wr_client_desc,
+	.num_mux = 5,
+	.mux_type = {
+		CAM_VFE_CAMIF_VER_4_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+		CAM_VFE_RDI_VER_1_0,
+	},
+	.debug_reg_info = &vfe78x_dbg_reg_info,
+	.num_rdi        = ARRAY_SIZE(vfe_lite98x_rdi_hw_info),
+};
+
+static struct cam_irq_register_set vfe_lite98x_bus_irq_reg[1] = {
+	{
+		.mask_reg_offset   = 0x00001218,
+		.clear_reg_offset  = 0x00001220,
+		.status_reg_offset = 0x00001228,
+	},
+};
+
+static uint32_t vfe_lite98x_out_port_mid[][4] = {
+	{8, 0, 0, 0},
+	{9, 0, 0, 0},
+	{10, 0, 0, 0},
+	{11, 0, 0, 0},
+	{12, 0, 0, 0},
+	{13, 0, 0, 0},
+};
+
+static struct cam_vfe_bus_ver3_hw_info vfe_lite98x_bus_hw_info = {
+	.common_reg = {
+		.hw_version                       = 0x00001200,
+		.cgc_ovd                          = 0x00001208,
+		.if_frameheader_cfg               = {
+			0x00001234,
+			0x00001238,
+			0x0000123C,
+			0x00001240,
+			0x00001244,
+		},
+		.pwr_iso_cfg                      = 0x0000125C,
+		.overflow_status_clear            = 0x00001260,
+		.ccif_violation_status            = 0x00001264,
+		.overflow_status                  = 0x00001268,
+		.image_size_violation_status      = 0x00001270,
+		.debug_status_top_cfg             = 0x000012F0,
+		.debug_status_top                 = 0x000012F4,
+		.test_bus_ctrl                    = 0x00001328,
+		.irq_reg_info = {
+			.num_registers            = 1,
+			.irq_reg_set              = vfe_lite98x_bus_irq_reg,
+			.global_irq_cmd_offset    = 0x00001230,
+			.global_clear_bitmask     = 0x00000001,
+		},
+	},
+	.num_client = 6,
+	.bus_client_reg = {
+		/* BUS Client 0 RDI0 */
+		{
+			.cfg                      = 0x00001700,
+			.image_addr               = 0x00001704,
+			.frame_incr               = 0x00001708,
+			.image_cfg_0              = 0x0000170C,
+			.image_cfg_1              = 0x00001710,
+			.image_cfg_2              = 0x00001714,
+			.packer_cfg               = 0x00001718,
+			.frame_header_addr        = 0x00001720,
+			.frame_header_incr        = 0x00001724,
+			.frame_header_cfg         = 0x00001728,
+			.line_done_cfg            = 0x0000172C,
+			.irq_subsample_period     = 0x00001730,
+			.irq_subsample_pattern    = 0x00001734,
+			.mmu_prefetch_cfg         = 0x00001760,
+			.mmu_prefetch_max_offset  = 0x00001764,
+			.system_cache_cfg         = 0x00001768,
+			.addr_cfg                 = 0x00001770,
+			.addr_status_0            = 0x00001790,
+			.addr_status_1            = 0x00001794,
+			.addr_status_2            = 0x00001798,
+			.addr_status_3            = 0x0000179C,
+			.debug_status_cfg         = 0x0000177C,
+			.debug_status_0           = 0x00001780,
+			.debug_status_1           = 0x00001784,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_1,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 1 RDI1 */
+		{
+			.cfg                      = 0x00001800,
+			.image_addr               = 0x00001804,
+			.frame_incr               = 0x00001808,
+			.image_cfg_0              = 0x0000180C,
+			.image_cfg_1              = 0x00001810,
+			.image_cfg_2              = 0x00001814,
+			.packer_cfg               = 0x00001818,
+			.frame_header_addr        = 0x00001820,
+			.frame_header_incr        = 0x00001824,
+			.frame_header_cfg         = 0x00001828,
+			.line_done_cfg            = 0x0000182C,
+			.irq_subsample_period     = 0x00001830,
+			.irq_subsample_pattern    = 0x00001834,
+			.mmu_prefetch_cfg         = 0x00001860,
+			.mmu_prefetch_max_offset  = 0x00001864,
+			.system_cache_cfg         = 0x00001868,
+			.addr_cfg                 = 0x00001870,
+			.addr_status_0            = 0x00001890,
+			.addr_status_1            = 0x00001894,
+			.addr_status_2            = 0x00001898,
+			.addr_status_3            = 0x0000189C,
+			.debug_status_cfg         = 0x0000187C,
+			.debug_status_0           = 0x00001880,
+			.debug_status_1           = 0x00001884,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_2,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 2 RDI2 */
+		{
+			.cfg                      = 0x00001900,
+			.image_addr               = 0x00001904,
+			.frame_incr               = 0x00001908,
+			.image_cfg_0              = 0x0000190C,
+			.image_cfg_1              = 0x00001910,
+			.image_cfg_2              = 0x00001914,
+			.packer_cfg               = 0x00001918,
+			.frame_header_addr        = 0x00001920,
+			.frame_header_incr        = 0x00001924,
+			.frame_header_cfg         = 0x00001928,
+			.line_done_cfg            = 0x0000192C,
+			.irq_subsample_period     = 0x00001930,
+			.irq_subsample_pattern    = 0x00001934,
+			.mmu_prefetch_cfg         = 0x00001960,
+			.mmu_prefetch_max_offset  = 0x00001964,
+			.system_cache_cfg         = 0x00001968,
+			.addr_cfg                 = 0x00001970,
+			.addr_status_0            = 0x00001990,
+			.addr_status_1            = 0x00001994,
+			.addr_status_2            = 0x00001998,
+			.addr_status_3            = 0x0000199C,
+			.debug_status_cfg         = 0x0000197C,
+			.debug_status_0           = 0x00001980,
+			.debug_status_1           = 0x00001984,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_3,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 3 RDI3 */
+		{
+			.cfg                      = 0x00001A00,
+			.image_addr               = 0x00001A04,
+			.frame_incr               = 0x00001A08,
+			.image_cfg_0              = 0x00001A0C,
+			.image_cfg_1              = 0x00001A10,
+			.image_cfg_2              = 0x00001A14,
+			.packer_cfg               = 0x00001A18,
+			.frame_header_addr        = 0x00001A20,
+			.frame_header_incr        = 0x00001A24,
+			.frame_header_cfg         = 0x00001A28,
+			.line_done_cfg            = 0x00001A2C,
+			.irq_subsample_period     = 0x00001A30,
+			.irq_subsample_pattern    = 0x00001A34,
+			.mmu_prefetch_cfg         = 0x00001A60,
+			.mmu_prefetch_max_offset  = 0x00001A64,
+			.system_cache_cfg         = 0x00001A68,
+			.addr_cfg                 = 0x00001A70,
+			.addr_status_0            = 0x00001A90,
+			.addr_status_1            = 0x00001A94,
+			.addr_status_2            = 0x00001A98,
+			.addr_status_3            = 0x00001A9C,
+			.debug_status_cfg         = 0x00001A7C,
+			.debug_status_0           = 0x00001A80,
+			.debug_status_1           = 0x00001A84,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_4,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 4 Gamma */
+		{
+			.cfg                      = 0x00001B00,
+			.image_addr               = 0x00001B04,
+			.frame_incr               = 0x00001B08,
+			.image_cfg_0              = 0x00001B0C,
+			.image_cfg_1              = 0x00001B10,
+			.image_cfg_2              = 0x00001B14,
+			.packer_cfg               = 0x00001B18,
+			.frame_header_addr        = 0x00001B20,
+			.frame_header_incr        = 0x00001B24,
+			.frame_header_cfg         = 0x00001B28,
+			.line_done_cfg            = 0x00001B2C,
+			.irq_subsample_period     = 0x00001B30,
+			.irq_subsample_pattern    = 0x00001B34,
+			.mmu_prefetch_cfg         = 0x00001B60,
+			.mmu_prefetch_max_offset  = 0x00001B64,
+			.system_cache_cfg         = 0x00001B68,
+			.addr_cfg                 = 0x00001B70,
+			.addr_status_0            = 0x00001B90,
+			.addr_status_1            = 0x00001B94,
+			.addr_status_2            = 0x00001B98,
+			.addr_status_3            = 0x00001B9C,
+			.debug_status_cfg         = 0x00001B7C,
+			.debug_status_0           = 0x00001B80,
+			.debug_status_1           = 0x00001B84,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = NULL,
+		},
+		/* BUS Client 5 Stats BE */
+		{
+			.cfg                      = 0x00001C00,
+			.image_addr               = 0x00001C04,
+			.frame_incr               = 0x00001C08,
+			.image_cfg_0              = 0x00001C0C,
+			.image_cfg_1              = 0x00001C10,
+			.image_cfg_2              = 0x00001C14,
+			.packer_cfg               = 0x00001C18,
+			.frame_header_addr        = 0x00001C20,
+			.frame_header_incr        = 0x00001C24,
+			.frame_header_cfg         = 0x00001C28,
+			.line_done_cfg            = 0x00001C2C,
+			.irq_subsample_period     = 0x00001C30,
+			.irq_subsample_pattern    = 0x00001C34,
+			.mmu_prefetch_cfg         = 0x00001C60,
+			.mmu_prefetch_max_offset  = 0x00001C64,
+			.system_cache_cfg         = 0x00001C68,
+			.addr_cfg                 = 0x00001C70,
+			.addr_status_0            = 0x00001C90,
+			.addr_status_1            = 0x00001C94,
+			.addr_status_2            = 0x00001C98,
+			.addr_status_3            = 0x00001C9C,
+			.debug_status_cfg         = 0x00001C7C,
+			.debug_status_0           = 0x00001C80,
+			.debug_status_1           = 0x00001C84,
+			.comp_group               = CAM_VFE_BUS_VER3_COMP_GRP_0,
+			.ubwc_regs                = NULL,
+		},
+	},
+	.num_out = 6,
+	.vfe_out_hw_info = {
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI0,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_1,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.mid           = vfe_lite98x_out_port_mid[0],
+			.num_mid       = 1,
+			.wm_idx        = {
+				0,
+			},
+			.name          = {
+				"LITE_0",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI1,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_2,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.mid           = vfe_lite98x_out_port_mid[1],
+			.num_mid       = 1,
+			.wm_idx        = {
+				1,
+			},
+			.name          = {
+				"LITE_1",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI2,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_3,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.mid           = vfe_lite98x_out_port_mid[2],
+			.num_mid       = 1,
+			.wm_idx        = {
+				2,
+			},
+			.name          = {
+				"LITE_2",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_RDI3,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_4,
+			.num_wm        = 1,
+			.line_based    = 1,
+			.mid           = vfe_lite98x_out_port_mid[3],
+			.num_mid       = 1,
+			.wm_idx        = {
+				3,
+			},
+			.name          = {
+				"LITE_3",
+			},
+		},
+		{
+			.vfe_out_type  =
+				CAM_VFE_BUS_VER3_VFE_OUT_PREPROCESS_RAW,
+			.max_width     = 1920,
+			.max_height    = 1080,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.num_wm        = 1,
+			.mid           = vfe_lite98x_out_port_mid[4],
+			.num_mid       = 1,
+			.wm_idx        = {
+				4,
+			},
+			.name          = {
+				"PREPROCESS_RAW",
+			},
+		},
+		{
+			.vfe_out_type  = CAM_VFE_BUS_VER3_VFE_OUT_STATS_BG,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_VFE_BUS_VER3_SRC_GRP_0,
+			.num_wm        = 1,
+			.mid           = vfe_lite98x_out_port_mid[5],
+			.num_mid       = 1,
+			.wm_idx        = {
+				5,
+			},
+			.name          = {
+				"STATS_BG",
+			},
+		},
+	},
+	.num_comp_grp    = 5,
+	.support_consumed_addr = true,
+	.comp_done_mask = {
+		BIT(0), BIT(1), BIT(2), BIT(3), BIT(4),
+	},
+	.top_irq_shift   = 0,
+	.max_out_res = CAM_ISP_IFE_OUT_RES_BASE + 34,
+};
+
+static struct cam_vfe_irq_hw_info vfe_lite98x_irq_hw_info = {
+	.reset_mask    = 0,
+	.supported_irq = CAM_VFE_HW_IRQ_CAP_LITE_EXT_CSID,
+	.top_irq_reg   = &vfe_lite98x_top_irq_reg_info,
+};
+
+static struct cam_vfe_hw_info cam_vfe_lite98x_hw_info = {
+	.irq_hw_info                   = &vfe_lite98x_irq_hw_info,
+
+	.bus_version                   = CAM_VFE_BUS_VER_3_0,
+	.bus_hw_info                   = &vfe_lite98x_bus_hw_info,
+
+	.top_version                   = CAM_VFE_TOP_VER_4_0,
+	.top_hw_info                   = &vfe_lite98x_top_hw_info,
+};
+
+#endif /* _CAM_VFE_LITE98X_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -196,7 +196,8 @@ struct cam_vfe_bus_ver3_vfe_out_data {
 	struct cam_cdm_utils_ops        *cdm_util_ops;
 	uint32_t                         secure_mode;
 	void                            *priv;
-	uint32_t                         mid[CAM_VFE_BUS_VER3_MAX_MID_PER_PORT];
+	uint32_t                        *mid;
+	uint32_t                         num_mid;
 	bool                             limiter_enabled;
 };
 
@@ -2384,9 +2385,8 @@ static int cam_vfe_bus_ver3_init_vfe_out_resource(uint32_t  index,
 	vfe_out->hw_intf = ver3_bus_priv->common_data.hw_intf;
 	vfe_out->irq_handle = 0;
 
-	for (i = 0; i < CAM_VFE_BUS_VER3_MAX_MID_PER_PORT; i++)
-		rsrc_data->mid[i] = ver3_hw_info->vfe_out_hw_info[index].mid[i];
-
+	rsrc_data->num_mid = ver3_hw_info->vfe_out_hw_info->num_mid;
+	rsrc_data->mid = ver3_hw_info->vfe_out_hw_info[index].mid;
 
 	return 0;
 }
@@ -4145,7 +4145,7 @@ static int cam_vfe_bus_get_res_for_mid(
 		if (!out_data)
 			continue;
 
-		for (j = 0; j < CAM_VFE_BUS_VER3_MAX_MID_PER_PORT; j++) {
+		for (j = 0; j < out_data->num_mid; j++) {
 			if (out_data->mid[j] == get_res->mid)
 				goto end;
 		}

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 
@@ -58,9 +58,12 @@ enum cam_vfe_bus_ver3_vfe_out_type {
 	CAM_VFE_BUS_VER3_VFE_OUT_RDI1,
 	CAM_VFE_BUS_VER3_VFE_OUT_RDI2,
 	CAM_VFE_BUS_VER3_VFE_OUT_RDI3,
+	CAM_VFE_BUS_VER3_VFE_OUT_RDI4,
 	CAM_VFE_BUS_VER3_VFE_OUT_FULL,
+	CAM_VFE_BUS_VER3_VFE_OUT_DS2,
 	CAM_VFE_BUS_VER3_VFE_OUT_DS4,
 	CAM_VFE_BUS_VER3_VFE_OUT_DS16,
+	CAM_VFE_BUS_VER3_VFE_OUT_IR,
 	CAM_VFE_BUS_VER3_VFE_OUT_RAW_DUMP,
 	CAM_VFE_BUS_VER3_VFE_OUT_FD,
 	CAM_VFE_BUS_VER3_VFE_OUT_PDAF,
@@ -82,6 +85,7 @@ enum cam_vfe_bus_ver3_vfe_out_type {
 	CAM_VFE_BUS_VER3_VFE_OUT_AWB_BFW,
 	CAM_VFE_BUS_VER3_VFE_OUT_PREPROCESS_2PD,
 	CAM_VFE_BUS_VER3_VFE_OUT_STATS_AEC_BE,
+	CAM_VFE_BUS_VER3_VFE_OUT_STATS_AEC_BHIST,
 	CAM_VFE_BUS_VER3_VFE_OUT_LTM_STATS,
 	CAM_VFE_BUS_VER3_VFE_OUT_STATS_GTM_BHIST,
 	CAM_VFE_BUS_VER3_VFE_OUT_STATS_BG,
@@ -90,6 +94,8 @@ enum cam_vfe_bus_ver3_vfe_out_type {
 	CAM_VFE_BUS_VER3_VFE_OUT_STATS_BAYER_RS,
 	CAM_VFE_BUS_VER3_VFE_OUT_PDAF_PARSED,
 	CAM_VFE_BUS_VER3_VFE_OUT_STATS_ALSC,
+	CAM_VFE_BUS_VER3_VFE_OUT_STATS_AF_BHIST,
+	CAM_VFE_BUS_VER3_VFE_OUT_STATS_TMC_BHIST,
 	CAM_VFE_BUS_VER3_VFE_OUT_MAX,
 };
 
@@ -113,6 +119,7 @@ struct cam_vfe_bus_ver3_reg_offset_common {
 	uint32_t cgc_ovd;
 	uint32_t comp_cfg_0;
 	uint32_t comp_cfg_1;
+	uint32_t ctxt_sel;
 	uint32_t if_frameheader_cfg[CAM_VFE_BUS_VER3_MAX_SUB_GRPS];
 	uint32_t ubwc_static_ctrl;
 	uint32_t pwr_iso_cfg;
@@ -123,6 +130,9 @@ struct cam_vfe_bus_ver3_reg_offset_common {
 	uint32_t debug_status_top_cfg;
 	uint32_t debug_status_top;
 	uint32_t test_bus_ctrl;
+	uint32_t mc_read_sel_shift;
+	uint32_t mc_write_sel_shift;
+	uint32_t mc_ctxt_mask;
 	uint32_t top_irq_mask_0;
 	struct cam_irq_controller_reg_info irq_reg_info;
 };
@@ -169,6 +179,7 @@ struct cam_vfe_bus_ver3_reg_offset_bus_client {
 	uint32_t mmu_prefetch_cfg;
 	uint32_t mmu_prefetch_max_offset;
 	uint32_t addr_cfg;
+	uint32_t ctxt_cfg;
 	uint32_t burst_limit;
 	uint32_t system_cache_cfg;
 	void    *ubwc_regs;
@@ -179,6 +190,8 @@ struct cam_vfe_bus_ver3_reg_offset_bus_client {
 	uint32_t debug_status_cfg;
 	uint32_t debug_status_0;
 	uint32_t debug_status_1;
+	uint32_t debug_status_ctxt;
+	uint32_t hw_ctxt_cfg;
 	uint32_t bw_limiter_addr;
 	uint32_t comp_group;
 };
@@ -193,11 +206,14 @@ struct cam_vfe_bus_ver3_vfe_out_hw_info {
 	uint32_t                            max_width;
 	uint32_t                            max_height;
 	uint32_t                            source_group;
-	uint32_t                            mid[CAM_VFE_BUS_VER3_MAX_MID_PER_PORT];
+	uint32_t                           *mid;
+	uint32_t                            num_mid;
 	uint32_t                            num_wm;
 	uint32_t                            line_based;
 	uint32_t                            wm_idx[PLANE_MAX];
+	uint32_t                            mc_grp_shift;
 	uint8_t                            *name[PLANE_MAX];
+	bool                                mc_based;
 };
 
 /*
@@ -212,7 +228,7 @@ struct cam_vfe_bus_ver3_vfe_out_hw_info {
  * @num_cons_err:          Number of constraint errors in list
  * @constraint_error_list: Static list of all constraint errors
  * @num_comp_grp:          Number of composite groups
- * @comp_done_mask:       Mask shift for comp done mask
+ * @comp_done_mask:        Mask shift for comp done mask
  * @top_irq_shift:         Mask shift for top level BUS WR irq
  * @support_consumed_addr: Indicate if bus support consumed address
  * @max_out_res:           Max vfe out resource value supported for hw

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h

@@ -1,13 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_VFE_TOP_COMMON_H_
 #define _CAM_VFE_TOP_COMMON_H_
 
-#define CAM_VFE_TOP_MUX_MAX 6
+#define CAM_VFE_TOP_MUX_MAX 7
 
 #include "cam_cpas_api.h"
 #include "cam_vfe_hw_intf.h"

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c

@@ -39,7 +39,7 @@ struct cam_vfe_top_ver4_priv {
 	atomic_t                                 overflow_pending;
 	uint8_t                                  log_buf[CAM_VFE_LEN_LOG_BUF];
 	uint32_t                                 sof_cnt;
-	struct cam_vfe_top_ver4_perf_counter_cfg perf_counters[CAM_VFE_PERF_COUNTER_MAX];
+	struct cam_vfe_top_ver4_perf_counter_cfg perf_counters[CAM_VFE_PERF_CNT_MAX];
 };
 
 enum cam_vfe_top_ver4_fsm_state {
@@ -1956,7 +1956,7 @@ int cam_vfe_top_ver4_init(
 	top_priv->top_common.num_mux = hw_info->num_mux;
 
 	for (i = 0, j = 0; i < top_priv->top_common.num_mux &&
-		j < CAM_VFE_RDI_VER2_MAX; i++) {
+		j < hw_info->num_rdi; i++) {
 		top_priv->top_common.mux_rsrc[i].res_type =
 			CAM_ISP_RESOURCE_VFE_IN;
 		top_priv->top_common.mux_rsrc[i].hw_intf = hw_intf;
@@ -1998,7 +1998,7 @@ int cam_vfe_top_ver4_init(
 				CAM_ISP_RES_NAME_LEN, "RDI_%d", j);
 			rc = cam_vfe_res_mux_init(top_priv,
 				hw_intf, soc_info,
-				hw_info->rdi_hw_info[j++],
+				&hw_info->rdi_hw_info[j++],
 				&top_priv->top_common.mux_rsrc[i],
 				vfe_irq_controller);
 		} else {
@@ -2028,6 +2028,14 @@ int cam_vfe_top_ver4_init(
 	top_priv->top_common.hw_idx        = hw_intf->hw_idx;
 	top_priv->common_data.common_reg   = hw_info->common_reg;
 
+	if (top_priv->common_data.common_reg->num_perf_counters > CAM_VFE_PERF_CNT_MAX) {
+		CAM_ERR(CAM_ISP, "Invalid number of perf counters: %d max: %d",
+			top_priv->common_data.common_reg->num_perf_counters,
+			CAM_VFE_PERF_CNT_MAX);
+		rc = -EINVAL;
+		goto deinit_resources;
+	}
+
 	return rc;
 
 deinit_resources:

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_VFE_TOP_VER4_H_
@@ -13,11 +13,11 @@
 
 #define CAM_VFE_RDI_VER2_MAX                           4
 #define CAM_VFE_CAMIF_LITE_EVT_MAX                     256
-#define CAM_VFE_TOP_DBG_REG_MAX                        19
-#define CAM_VFE_PERF_COUNTER_MAX                       2
+#define CAM_VFE_TOP_DBG_REG_MAX                        35
 
 struct cam_vfe_top_ver4_perf_count_reg_offset {
 	uint32_t perf_count_cfg;
+	uint32_t perf_count_cfg_mc;
 	uint32_t perf_pix_count;
 	uint32_t perf_line_count;
 	uint32_t perf_stall_count;
@@ -29,10 +29,13 @@ struct cam_vfe_top_ver4_reg_offset_common {
 	uint32_t hw_version;
 	uint32_t titan_version;
 	uint32_t hw_capability;
+	uint32_t main_feature;
+	uint32_t bayer_feature;
 	uint32_t lens_feature;
 	uint32_t stats_feature;
 	uint32_t color_feature;
 	uint32_t zoom_feature;
+	uint32_t fd_feature;
 	uint32_t global_reset_cmd;
 	uint32_t core_cgc_ovd_0;
 	uint32_t core_cgc_ovd_1;
@@ -46,10 +49,12 @@ struct cam_vfe_top_ver4_reg_offset_common {
 	uint32_t core_cfg_4;
 	uint32_t core_cfg_5;
 	uint32_t core_cfg_6;
+	uint32_t core_mux_cfg;
 	uint32_t period_cfg;
 	uint32_t reg_update_cmd;
 	uint32_t trigger_cdm_events;
 	uint32_t ipp_violation_status;
+	uint32_t bayer_violation_status;
 	uint32_t pdaf_violation_status;
 	uint32_t custom_frame_idx;
 	uint32_t dsp_status;
@@ -58,9 +63,21 @@ struct cam_vfe_top_ver4_reg_offset_common {
 	uint32_t diag_sensor_status_1;
 	uint32_t diag_frm_cnt_status_0;
 	uint32_t diag_frm_cnt_status_1;
+	uint32_t diag_frm_cnt_status_2;
 	uint32_t stats_throttle_cfg_0;
 	uint32_t stats_throttle_cfg_1;
 	uint32_t stats_throttle_cfg_2;
+	uint32_t pdaf_parsed_throttle_cfg;
+	uint32_t wirc_throttle_cfg;
+	uint32_t fd_y_throttle_cfg;
+	uint32_t fd_c_throttle_cfg;
+	uint32_t ds16_g_throttle_cfg;
+	uint32_t ds16_br_throttle_cfg;
+	uint32_t ds4_g_throttle_cfg;
+	uint32_t ds4_br_throttle_cfg;
+	uint32_t ds2_g_throttle_cfg;
+	uint32_t ds2_br_throttle_cfg;
+	uint32_t full_out_throttle_cfg;
 	uint32_t bus_violation_status;
 	uint32_t bus_overflow_status;
 	uint32_t irq_sub_pattern_cfg;
@@ -69,12 +86,13 @@ struct cam_vfe_top_ver4_reg_offset_common {
 	uint32_t epoch_height_cfg;
 	uint32_t num_perf_counters;
 	struct cam_vfe_top_ver4_perf_count_reg_offset
-		perf_count_reg[CAM_VFE_PERF_COUNTER_MAX];
+		perf_count_reg[CAM_VFE_PERF_CNT_MAX];
 	uint32_t top_debug_cfg;
+	uint32_t bayer_debug_cfg;
 	uint32_t pdaf_input_cfg_0;
 	uint32_t pdaf_input_cfg_1;
 	uint32_t num_top_debug_reg;
-	uint32_t top_debug[CAM_VFE_TOP_DBG_REG_MAX];
+	uint32_t *top_debug;
 };
 
 struct cam_vfe_top_common_cfg {
@@ -93,6 +111,11 @@ struct cam_vfe_top_ver4_module_desc {
 	uint8_t *desc;
 };
 
+struct cam_vfe_bayer_ver4_module_desc {
+	uint32_t id;
+	uint8_t *desc;
+};
+
 struct cam_vfe_top_ver4_wr_client_desc {
 	uint32_t  wm_id;
 	uint8_t  *desc;
@@ -109,6 +132,11 @@ struct cam_vfe_top_ver4_pdaf_violation_desc {
 	char     *desc;
 };
 
+struct cam_vfe_top_ver4_bayer_violation_desc {
+	uint32_t bitmask;
+	char     *desc;
+};
+
 struct cam_vfe_top_ver4_pdaf_lcr_res_info {
 	uint32_t  res_id;
 	uint32_t  val;
@@ -128,16 +156,18 @@ struct cam_vfe_top_ver4_hw_info {
 	struct cam_vfe_top_ver4_reg_offset_common  *common_reg;
 	struct cam_vfe_ver4_path_hw_info            vfe_full_hw_info;
 	struct cam_vfe_ver4_path_hw_info            pdlib_hw_info;
-	struct cam_vfe_ver4_path_hw_info           *rdi_hw_info[CAM_VFE_RDI_VER2_MAX];
+	struct cam_vfe_ver4_path_hw_info           *rdi_hw_info;
 	struct cam_vfe_ver4_path_reg_data          *reg_data;
 	struct cam_vfe_top_ver4_wr_client_desc     *wr_client_desc;
 	struct cam_vfe_top_ver4_module_desc        *ipp_module_desc;
+	struct cam_vfe_bayer_ver4_module_desc      *bayer_module_desc;
 	uint32_t                                    num_reg;
 	struct cam_vfe_top_ver4_debug_reg_info     (*debug_reg_info)[][8];
 	uint32_t                                    num_mux;
 	uint32_t                                    num_path_port_map;
 	uint32_t mux_type[CAM_VFE_TOP_MUX_MAX];
 	uint32_t path_port_map[CAM_ISP_HW_PATH_PORT_MAP_MAX][2];
+	uint32_t                                     num_rdi;
 	uint32_t                                     num_top_errors;
 	struct cam_vfe_top_ver4_top_err_irq_desc    *top_err_desc;
 	uint32_t                                     num_pdaf_violation_errors;
@@ -156,6 +186,7 @@ struct cam_vfe_ver4_path_reg_data {
 	uint32_t                                     enable_diagnostic_hw;
 	uint32_t                                     top_debug_cfg_en;
 	uint32_t                                     ipp_violation_mask;
+	uint32_t                                     bayer_violation_mask;
 	uint32_t                                     pdaf_violation_mask;
 };